// SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; };