/* $NetBSD: ata_wdc.c,v 1.1.2.5 1998/06/09 12:56:54 bouyer Exp $ */ /* * Copyright (c) 1998 Manuel Bouyer. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /* * Copyright (c) 1994, 1995, 1998 Charles M. Hannum. All rights reserved. * * DMA and multi-sector PIO handling are derived from code contributed by * Onno van der Linden. * * Bus_space-ified by Christopher G. Demetriou. * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Charles M. Hannum. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #define WDCDEBUG #include #include #include #include #include #include #include #include #include #include #include #include #include #ifndef __BUS_SPACE_HAS_STREAM_METHODS #define bus_space_write_multi_stream_2 bus_space_write_multi_2 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ #include #include #include #include #include #define DEBUG_INTR 0x01 #define DEBUG_XFERS 0x02 #define DEBUG_STATUS 0x04 #define DEBUG_FUNCS 0x08 #define DEBUG_PROBE 0x10 #ifdef WDCDEBUG int wdcdebug_wd_mask = DEBUG_PROBE; #define WDCDEBUG_PRINT(args, level) \ if (wdcdebug_wd_mask & (level)) \ printf args #else #define WDCDEBUG_PRINT(args, level) #endif int wdprint __P((void *, const char *)); void wdc_ata_bio_start __P((struct channel_softc *,struct wdc_xfer *)); int wdc_ata_bio_intr __P((struct channel_softc *, struct wdc_xfer *)); void wdc_ata_bio_done __P((struct channel_softc *, struct wdc_xfer *)); int wdc_ata_ctrl_intr __P((struct channel_softc *, struct wdc_xfer *)); int wdprint(aux, pnp) void *aux; const char *pnp; { struct ata_atapi_attach *aa_link = aux; if (pnp) printf("drive at %s", pnp); printf(" channel %d drive %d", aa_link->aa_channel, aa_link->aa_drv_data->drive); return (UNCONF); } void wdc_ata_attach(chp) struct channel_softc *chp; { struct wdc_softc *wdc = chp->wdc; int channel = chp->channel; struct ata_atapi_attach aa_link; int drive; WDCDEBUG_PRINT(("wdc_ata_attach\n"), DEBUG_FUNCS | DEBUG_PROBE); bzero(&aa_link,sizeof(struct ata_atapi_attach)); aa_link.aa_type = T_ATA; aa_link.aa_channel = channel; aa_link.aa_openings = 1; for (drive = 0; drive < 2; drive++) { if ((chp->ch_drive[drive].drive_flags & DRIVE_ATA) == 0) { continue; } aa_link.aa_drv_data = &chp->ch_drive[drive]; if (config_found(&wdc->sc_dev, (void *)&aa_link, wdprint)) wdc_probe_caps(&chp->ch_drive[drive]); } } /* * Handle block I/O operation. Return WDC_COMPLETE, WDC_QUEUED, or * WDC_TRY_AGAIN. Must be called at splio(). */ int wdc_ata_bio(drvp, ata_bio) struct ata_drive_datas *drvp; struct ata_bio *ata_bio; { struct wdc_xfer *xfer; struct channel_softc *chp = drvp->chnl_softc; xfer = wdc_get_xfer((ata_bio->flags & ATA_POLL) ? WDC_NOSLEEP : WDC_CANSLEEP); if (xfer == NULL) return WDC_TRY_AGAIN; xfer->drive = drvp->drive; xfer->cmd = ata_bio; xfer->databuf = ata_bio->databuf; xfer->c_bcount = ata_bio->bcount; xfer->c_start = wdc_ata_bio_start; xfer->c_intr = wdc_ata_bio_intr; wdc_exec_xfer(chp, xfer); return (ata_bio->flags & ATA_ITSDONE) ? WDC_COMPLETE : WDC_QUEUED; } void wdc_ata_bio_start(chp, xfer) struct channel_softc *chp; struct wdc_xfer *xfer; { struct ata_bio *ata_bio = xfer->cmd; struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; u_int16_t cyl; u_int8_t head, sect, cmd = 0; int nblks; WDCDEBUG_PRINT(("wdc_ata_bio_start\n"), DEBUG_FUNCS | DEBUG_XFERS); /* Do control operations specially. */ if (drvp->state < READY) { /* * Actually, we want to be careful not to mess with the control * state if the device is currently busy, but we can assume * that we never get to this point if that's the case. */ /* at this point, we should only be in RECAL state */ if (drvp->state != RECAL) { printf("%s:%d:%d: bad state %d in wdc_ata_bio_start\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, drvp->state); panic("wdc_ata_bio_start: bad state"); } xfer->c_intr = wdc_ata_ctrl_intr; bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, WDSD_IBM | (xfer->drive << 4)); if (wdcwait(chp, WDCS_DRDY) != 0) goto timeout; wdccommandshort(chp, xfer->drive, WDCC_RECAL); drvp->state = RECAL_WAIT; if ((ata_bio->flags & ATA_POLL) == 0) { chp->ch_flags |= WDCF_IRQ_WAIT; timeout(wdctimeout, chp, WAITTIME); } else { /* Wait for at last 400ns for status bit to be valid */ delay(1); wdc_ata_ctrl_intr(chp, xfer); } return; } again: /* * * When starting a multi-sector transfer, or doing single-sector * transfers... */ if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0 || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) != 0) { if (ata_bio->flags & ATA_SINGLE) nblks = 1; else nblks = xfer->c_bcount / ata_bio->lp->d_secsize; /* Check for bad sectors and adjust transfer, if necessary. */ if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { long blkdiff; int i; for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; i++) { blkdiff -= ata_bio->blkno; if (blkdiff < 0) continue; if (blkdiff == 0) { /* Replace current block of transfer. */ ata_bio->blkno = ata_bio->lp->d_secperunit - ata_bio->lp->d_nsectors - i - 1; } if (blkdiff < nblks) { /* Bad block inside transfer. */ ata_bio->flags |= ATA_SINGLE; nblks = 1; } break; } /* Transfer is okay now. */ } if (ata_bio->flags & ATA_LBA) { sect = (ata_bio->blkno >> 0) & 0xff; cyl = (ata_bio->blkno >> 8) & 0xffff; head = (ata_bio->blkno >> 24) & 0x0f; head |= WDSD_LBA; } else { int blkno = ata_bio->blkno; sect = blkno % ata_bio->lp->d_nsectors; sect++; /* Sectors begin with 1, not 0. */ blkno /= ata_bio->lp->d_nsectors; head = blkno % ata_bio->lp->d_ntracks; blkno /= ata_bio->lp->d_ntracks; cyl = blkno; head |= WDSD_CHS; } if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && (ata_bio->flags & ATA_SINGLE) == 0) { ata_bio->nblks = nblks; ata_bio->nbytes = xfer->c_bcount; cmd = (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; nblks = ata_bio->nblks; /* Init the DMA channel. */ if ((*chp->wdc->dma_init)(chp->wdc->dma_arg, chp->channel, xfer->drive, xfer->databuf + xfer->c_skip, ata_bio->nbytes, ata_bio->flags & ATA_READ) != 0) { ata_bio->error = ERROR; ata_bio->r_error = 0; wdc_ata_bio_done(chp, xfer); return; } /* Initiate command */ bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, WDSD_IBM | (xfer->drive << 4)); if (wait_for_ready(chp) < 0) goto timeout; wdccommand(chp, xfer->drive, cmd, cyl, head, sect, nblks, 0); /* start the DMA channel */ (*chp->wdc->dma_start)(chp->wdc->dma_arg, chp->channel, xfer->drive, ata_bio->flags & ATA_READ); /* wait for irq */ goto intr; } /* else not DMA */ ata_bio->nblks = min(nblks, ata_bio->multi); ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; if (ata_bio->nblks > 1 && (ata_bio->flags & ATA_SINGLE) == 0) { cmd = (ata_bio->flags & ATA_READ) ? WDCC_READMULTI : WDCC_WRITEMULTI; } else { cmd = (ata_bio->flags & ATA_READ) ? WDCC_READ : WDCC_WRITE; } /* Initiate command! */ bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, WDSD_IBM | (xfer->drive << 4)); if (wait_for_ready(chp) < 0) goto timeout; wdccommand(chp, xfer->drive, cmd, cyl, head, sect, nblks, (ata_bio->lp->d_type == DTYPE_ST506) ? ata_bio->lp->d_precompcyl / 4 : 0); } else if (ata_bio->nblks > 1) { /* The number of blocks in the last stretch may be smaller. */ nblks = xfer->c_bcount / ata_bio->lp->d_secsize; if (ata_bio->nblks > nblks) { ata_bio->nblks = nblks; ata_bio->nbytes = xfer->c_bcount; } } /* If this was a write and not using DMA, push the data. */ if ((ata_bio->flags & ATA_READ) == 0) { /* Wait for at last 400ns for status bit to be valid */ delay(1); if (wait_for_drq(chp) != 0) { printf("%s:%d:%d: timeout waiting for DRQ, " "st=0x%02x, err=0x%02x\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, chp->ch_status, chp->ch_error); if ((chp->ch_status & WDCS_BSY) == 0 && (chp->ch_status & WDCS_ERR) != 0) { ata_bio->r_error = chp->ch_error; ata_bio->error = ERROR; } else { ata_bio->error = TIMEOUT; } wdc_ata_bio_done(chp, xfer); return; } if (drvp->drive_flags & DRIVE_CAP32) { bus_space_write_multi_stream_4(chp->cmd_iot, chp->cmd_ioh, wd_data, xfer->databuf + xfer->c_skip, ata_bio->nbytes >> 2); } else { bus_space_write_multi_stream_2(chp->cmd_iot, chp->cmd_ioh, wd_data, xfer->databuf + xfer->c_skip, ata_bio->nbytes >> 1); } } intr: /* Wait for IRQ (either real or polled */ if ((ata_bio->flags & ATA_POLL) == 0) { chp->ch_flags |= WDCF_IRQ_WAIT; timeout(wdctimeout, chp, WAITTIME); } else { /* Wait for at last 400ns for status bit to be valid */ delay(1); wdc_ata_bio_intr(chp, xfer); if ((ata_bio->flags & ATA_ITSDONE) == 0) goto again; } return; timeout: printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, chp->ch_status, chp->ch_error); if (chp->ch_status & WDCS_BSY) ata_bio->error = TIMEOUT; else { if ((chp->ch_status & WDCS_ERR) != 0) { ata_bio->r_error = chp->ch_error; ata_bio->error = ERROR; } else if (chp->ch_status & WDCS_DWF) ata_bio->error = ERR_DF; else ata_bio->error = TIMEOUT; } wdc_ata_bio_done(chp, xfer); return; } int wdc_ata_bio_intr(chp, xfer) struct channel_softc *chp; struct wdc_xfer *xfer; { struct ata_bio *ata_bio = xfer->cmd; struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; int dma_err; WDCDEBUG_PRINT(("wdc_ata_bio_intr\n"), DEBUG_INTR); /* Is it not a transfer, but a control operation? */ if (drvp->state < READY) { printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, drvp->state); panic("wdc_ata_bio_intr: bad state\n"); } /* Ack interrupt done by wait_for_unbusy */ if (wait_for_unbusy(chp) < 0) { printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, xfer->c_bcount, xfer->c_skip); /* if we were using DMA, turn off DMA channel */ if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && (ata_bio->flags & ATA_SINGLE) == 0) (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, xfer->drive, ata_bio->flags & ATA_READ); ata_bio->error = TIMEOUT; wdc_ata_bio_done(chp, xfer); return 1; } if (chp->ch_status & WDCS_CORR) ata_bio->flags |= ATA_CORR; /* If we were using DMA, Turn off the DMA channel and check for error */ if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && (ata_bio->flags & ATA_SINGLE) == 0) { if (chp->ch_status & WDCS_DRQ) { printf("%s:%d:%d: intr with DRQ\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive); ata_bio->error = TIMEOUT; wdc_ata_bio_done(chp, xfer); return 1; } dma_err = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, xfer->drive, ata_bio->flags & ATA_READ); /* Error here only if command aborted (DMA or drive ) */ if ((chp->ch_status & WDCS_ERR) != 0 && (chp->ch_error & WDCE_ABRT) != 0) { ata_bio->error = ERROR; ata_bio->r_error = chp->ch_error; wdc_ata_bio_done(chp, xfer); } else if ((chp->ch_status & WDCS_DWF) != 0) { ata_bio->error = ERR_DF; wdc_ata_bio_done(chp, xfer); } else if (dma_err != 0) { ata_bio->error = ERR_DMA; ata_bio->r_error = 0; wdc_ata_bio_done(chp, xfer); } else /* transfert ok, end it */ goto end; } /* If this was a read and not using DMA, fetch the data. */ if ((ata_bio->flags & ATA_READ) != 0) { if ((chp->ch_status & (WDCS_DRDY | WDCS_DSC | WDCS_DRQ)) != (WDCS_DRDY | WDCS_DSC | WDCS_DRQ)) { if ((chp->ch_status & WDCS_ERR) != 0) { ata_bio->error = ERROR; ata_bio->r_error = chp->ch_error; } else { printf("%s:%d:%d: read intr before drq\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive); ata_bio->error = TIMEOUT; } wdc_ata_bio_done(chp, xfer); return 1; } if (drvp->drive_flags & DRIVE_CAP32) { bus_space_read_multi_stream_4(chp->cmd_iot, chp->cmd_ioh, wd_data, xfer->databuf + xfer->c_skip, ata_bio->nbytes >> 2); } else { bus_space_read_multi_stream_2(chp->cmd_iot, chp->cmd_ioh, wd_data, xfer->databuf + xfer->c_skip, ata_bio->nbytes >> 1); } } end: ata_bio->blkno += ata_bio->nblks; xfer->c_skip += ata_bio->nbytes; xfer->c_bcount -= ata_bio->nbytes; /* See if this transfer is complete. */ if (xfer->c_bcount > 0) { if ((ata_bio->flags & ATA_POLL) == 0) { /* Start the next operation */ wdc_ata_bio_start(chp, xfer); } else { /* Let wdc_ata_bio_start do the loop */ return 1; } } else { /* Done with this transfer */ ata_bio->error = NOERROR; wdc_ata_bio_done(chp, xfer); } return 1; } void wdc_ata_bio_done(chp, xfer) struct channel_softc *chp; struct wdc_xfer *xfer; { struct ata_bio *ata_bio = xfer->cmd; int need_done = xfer->c_flags & C_NEEDDONE; int drive = xfer->drive; WDCDEBUG_PRINT(("wdc_ata_bio_done: flags 0x%x\n", (u_int)xfer->c_flags), DEBUG_FUNCS); ata_bio->nbytes = xfer->c_bcount; /* remove this command from xfer queue */ wdc_free_xfer(chp, xfer); ata_bio->flags |= ATA_ITSDONE; if (need_done) { WDCDEBUG_PRINT(("wdc_ata_done: wddone\n"), DEBUG_FUNCS); wddone(chp->ch_drive[drive].drv_softc); } WDCDEBUG_PRINT(("wdcstart from wdc_ata_done, flags 0x%x\n", chp->ch_flags), DEBUG_FUNCS); wdcstart(chp->wdc, chp->channel); } /* * Implement operations needed before read/write. */ int wdc_ata_ctrl_intr(chp, xfer) struct channel_softc *chp; struct wdc_xfer *xfer; { struct ata_bio *ata_bio = xfer->cmd; struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; char *errstring = NULL; WDCDEBUG_PRINT(("wdc_ata_ctrl_intr: state %d\n", drvp->state), DEBUG_FUNCS); again: switch (drvp->state) { case RECAL: /* Should not be in this state here */ panic("wdc_ata_ctrl_intr: state==RECAL"); break; case RECAL_WAIT: errstring = "recal"; if (wdcwait(chp, WDCS_DRDY)) goto timeout; if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) goto error; /* fall through */ case PIOMODE: /* Don't try to set mode if controller can't be adjusted */ if ((chp->wdc->cap & WDC_CAPABILITY_PIO) == 0) goto dmamode; /* * if mode is < 3, it is unknown. Assume the defaults are * good. */ if (drvp->PIO_mode < 3) goto dmamode; wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 0x08 | drvp->PIO_mode, WDSF_SET_MODE); drvp->state = PIOMODE_WAIT; break; case PIOMODE_WAIT: errstring = "piomode"; if (wdcwait(chp, WDCS_DRDY)) goto timeout; if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) goto error; /* fall through */ case DMAMODE: dmamode: if (drvp->drive_flags & DRIVE_UDMA) { wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); } else if (drvp->drive_flags & DRIVE_DMA) { wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 0x20 | drvp->DMA_mode, WDSF_SET_MODE); } else { goto geometry; } drvp->state = DMAMODE_WAIT; break; case DMAMODE_WAIT: errstring = "dmamode"; if (wdcwait(chp, WDCS_DRDY)) goto timeout; if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) goto error; /* fall through */ case GEOMETRY: geometry: if (ata_bio->flags & ATA_LBA) goto multimode; wdccommand(chp, xfer->drive, WDCC_IDP, ata_bio->lp->d_ncylinders, ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, (ata_bio->lp->d_type == DTYPE_ST506) ? ata_bio->lp->d_precompcyl / 4 : 0); drvp->state = GEOMETRY_WAIT; break; case GEOMETRY_WAIT: errstring = "geometry"; if (wdcwait(chp, WDCS_DRDY)) goto timeout; if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) goto error; /* fall through */ case MULTIMODE: multimode: if (ata_bio->multi == 1) goto ready; wdccommand(chp, xfer->drive, WDCC_SETMULTI, 0, 0, 0, ata_bio->multi, 0); drvp->state = MULTIMODE_WAIT; break; case MULTIMODE_WAIT: errstring = "setmulti"; if (wdcwait(chp, WDCS_DRDY)) goto timeout; if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) goto error; /* fall through */ case READY: ready: drvp->state = READY; /* * The drive is usable now */ xfer->c_intr = wdc_ata_bio_intr; wdc_ata_bio_start(chp, xfer); return 1; } if ((ata_bio->flags & ATA_POLL) == 0) { chp->ch_flags |= WDCF_IRQ_WAIT; timeout(wdctimeout, chp, WAITTIME); } else { goto again; } return 1; timeout: if ((xfer->c_flags & C_TIMEOU) == 0 ) { return 0; /* IRQ was not for us */ } printf("%s:%d:%d: %s timed out\n", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring); ata_bio->error = TIMEOUT; wdc_ata_bio_done(chp, xfer); return 0; error: printf("%s:%d:%d: %s ", chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring); if (chp->ch_status & WDCS_DWF) { printf("drive fault\n"); ata_bio->error = ERR_DF; } else { printf("error (%x)\n", chp->ch_error); ata_bio->r_error = chp->ch_error; ata_bio->error = ERROR; } wdc_ata_bio_done(chp, xfer); return 1; }