The NetBSD Project

CVS log for src/usr.sbin/cpuctl/arch/i386.c

[BACK] Up to [cvs.NetBSD.org] / src / usr.sbin / cpuctl / arch

Request diff between arbitrary revisions


Default branch: MAIN


Revision 1.143 / (download) - annotate - [select for diffs], Sat Feb 10 18:43:53 2024 UTC (2 weeks, 1 day ago) by andvar
Branch: MAIN
CVS Tags: HEAD
Changes since 1.142: +4 -4 lines
Diff to previous 1.142 (colored)

Fix various typos in comments, log messages and documentation.

Revision 1.142 / (download) - annotate - [select for diffs], Thu Jan 18 03:19:26 2024 UTC (5 weeks, 3 days ago) by msaitoh
Branch: MAIN
Changes since 1.141: +4 -2 lines
Diff to previous 1.141 (colored)

Add Meteor Lake and Emerald Rapids.

Revision 1.141 / (download) - annotate - [select for diffs], Wed Sep 13 06:53:23 2023 UTC (5 months, 1 week ago) by wiz
Branch: MAIN
Changes since 1.140: +4 -4 lines
Diff to previous 1.140 (colored)

tabify

Revision 1.140 / (download) - annotate - [select for diffs], Tue Sep 12 20:43:38 2023 UTC (5 months, 2 weeks ago) by wiz
Branch: MAIN
Changes since 1.139: +4 -4 lines
Diff to previous 1.139 (colored)

cpuctl: be more verbose about problems and diagnosing them

Revision 1.74.6.18 / (download) - annotate - [select for diffs], Sat Jul 29 10:23:07 2023 UTC (6 months, 4 weeks ago) by martin
Branch: netbsd-8
Changes since 1.74.6.17: +5 -4 lines
Diff to previous 1.74.6.17 (colored) to branchpoint 1.74 (colored) next main 1.75 (colored)

Pull up the following revisions, via patch, requested by msaitoh
in ticket #1854:

	usr.sbin/cpuctl/arch/i386.c                     1.137-1.139

- CPU model 0x5a is not Atom E3500 but Atom Z3500.
- Add Alder Lake-N.

Revision 1.104.2.14 / (download) - annotate - [select for diffs], Sat Jul 29 10:14:09 2023 UTC (6 months, 4 weeks ago) by martin
Branch: netbsd-9
Changes since 1.104.2.13: +5 -4 lines
Diff to previous 1.104.2.13 (colored) to branchpoint 1.104 (colored) next main 1.105 (colored)

Pull up the following revisions, via patch, requested by msaitoh
in ticket #1670:

	usr.sbin/cpuctl/arch/i386.c                     1.137-1.139

- CPU model 0x5a is not Atom E3500 but Atom Z3500.
- Add Alder Lake-N.

Revision 1.133.2.3 / (download) - annotate - [select for diffs], Sat Jul 29 10:07:59 2023 UTC (6 months, 4 weeks ago) by martin
Branch: netbsd-10
CVS Tags: netbsd-10-0-RC4, netbsd-10-0-RC3, netbsd-10-0-RC2, netbsd-10-0-RC1
Changes since 1.133.2.2: +5 -4 lines
Diff to previous 1.133.2.2 (colored) to branchpoint 1.133 (colored) next main 1.134 (colored)

Pull up the following revisions, via patch, requested by msaitoh in
ticket #251:

	usr.sbin/cpuctl/arch/i386.c                     1.137-1.139

- CPU model 0x5a is not Atom E3500 but Atom Z3500.
- Add Alder Lake-N.

Revision 1.139 / (download) - annotate - [select for diffs], Fri Jul 21 10:26:36 2023 UTC (7 months ago) by msaitoh
Branch: MAIN
Changes since 1.138: +3 -3 lines
Diff to previous 1.138 (colored)

Sort by number. No functional change.

Revision 1.138 / (download) - annotate - [select for diffs], Thu Jul 6 02:43:44 2023 UTC (7 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.137: +3 -2 lines
Diff to previous 1.137 (colored)

Add Alder Lake-N.

Revision 1.137 / (download) - annotate - [select for diffs], Wed Jul 5 02:54:37 2023 UTC (7 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.136: +3 -3 lines
Diff to previous 1.136 (colored)

CPU model 0x5a is not Atom E3500 but Atom Z3500.

Revision 1.74.6.17 / (download) - annotate - [select for diffs], Wed Jun 21 19:06:15 2023 UTC (8 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.16: +6 -5 lines
Diff to previous 1.74.6.16 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1827):

	sys/arch/x86/include/specialreg.h: revision 1.202
	sys/arch/x86/include/specialreg.h: revision 1.203
	usr.sbin/cpuctl/arch/i386.c: revision 1.136

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.

Revision 1.104.2.13 / (download) - annotate - [select for diffs], Wed Jun 21 19:04:19 2023 UTC (8 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.12: +6 -5 lines
Diff to previous 1.104.2.12 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1646):

	sys/arch/x86/include/specialreg.h: revision 1.202
	sys/arch/x86/include/specialreg.h: revision 1.203
	usr.sbin/cpuctl/arch/i386.c: revision 1.136

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.

Revision 1.133.2.2 / (download) - annotate - [select for diffs], Wed Jun 21 19:02:18 2023 UTC (8 months ago) by martin
Branch: netbsd-10
Changes since 1.133.2.1: +6 -5 lines
Diff to previous 1.133.2.1 (colored) to branchpoint 1.133 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #200):

	sys/arch/x86/include/specialreg.h: revision 1.202
	sys/arch/x86/include/specialreg.h: revision 1.203
	usr.sbin/cpuctl/arch/i386.c: revision 1.136

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.

Revision 1.136 / (download) - annotate - [select for diffs], Tue Feb 14 15:46:06 2023 UTC (12 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.135: +6 -5 lines
Diff to previous 1.135 (colored)

Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.

Revision 1.74.6.16 / (download) - annotate - [select for diffs], Mon Jan 23 13:13:08 2023 UTC (13 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.15: +52 -6 lines
Diff to previous 1.74.6.15 (colored) to branchpoint 1.74 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1792:

	usr.sbin/cpuctl/arch/i386.c                     1.129-1.135

- Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
- Add Raptor Lake and Sapphire Rapids.
- Modify messages a little.

Revision 1.104.2.12 / (download) - annotate - [select for diffs], Mon Jan 23 13:04:11 2023 UTC (13 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.11: +52 -6 lines
Diff to previous 1.104.2.11 (colored) to branchpoint 1.104 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1575:

	usr.sbin/cpuctl/arch/i386.c			1.129-1.135 (via patch)

- Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
- Add Raptor Lake and Sapphire Rapids.
- Modify messages a little.

Revision 1.133.2.1 / (download) - annotate - [select for diffs], Mon Jan 23 12:54:14 2023 UTC (13 months ago) by martin
Branch: netbsd-10
Changes since 1.133: +20 -6 lines
Diff to previous 1.133 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #57):

	usr.sbin/cpuctl/arch/i386.c: revision 1.134
	usr.sbin/cpuctl/arch/i386.c: revision 1.135

Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.

Add Raptor Lake and Sapphire Rapids.

Revision 1.135 / (download) - annotate - [select for diffs], Fri Dec 30 13:32:46 2022 UTC (13 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.134: +6 -4 lines
Diff to previous 1.134 (colored)

Add Raptor Lake and Sapphire Rapids.

Revision 1.134 / (download) - annotate - [select for diffs], Fri Dec 30 12:21:07 2022 UTC (13 months, 3 weeks ago) by msaitoh
Branch: MAIN
Changes since 1.133: +16 -4 lines
Diff to previous 1.133 (colored)

Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.

Revision 1.133 / (download) - annotate - [select for diffs], Thu Nov 17 15:21:31 2022 UTC (15 months, 1 week ago) by msaitoh
Branch: MAIN
CVS Tags: netbsd-10-base
Branch point for: netbsd-10
Changes since 1.132: +3 -3 lines
Diff to previous 1.132 (colored)

s/features 2/features2/

Revision 1.132 / (download) - annotate - [select for diffs], Wed Nov 16 15:02:00 2022 UTC (15 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.131: +3 -4 lines
Diff to previous 1.131 (colored)

s/Instruction-Based Sampling/IBS/

Revision 1.131 / (download) - annotate - [select for diffs], Wed Nov 16 14:55:50 2022 UTC (15 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.130: +18 -2 lines
Diff to previous 1.130 (colored)

Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.

Revision 1.130 / (download) - annotate - [select for diffs], Wed Nov 16 14:01:41 2022 UTC (15 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.129: +8 -2 lines
Diff to previous 1.129 (colored)

Add CPUID Fn8000_0021 AMD Extended Features Identification 2.

Revision 1.129 / (download) - annotate - [select for diffs], Wed Nov 16 13:15:26 2022 UTC (15 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.128: +13 -2 lines
Diff to previous 1.128 (colored)

Print AMD RAS features and Instruction-Based Sampling features.

Revision 1.74.6.15 / (download) - annotate - [select for diffs], Sat Oct 15 10:16:08 2022 UTC (16 months, 1 week ago) by martin
Branch: netbsd-8
Changes since 1.74.6.14: +42 -7 lines
Diff to previous 1.74.6.14 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1775):

	sys/arch/x86/include/specialreg.h: revision 1.189
	usr.sbin/cpuctl/arch/i386.c: revision 1.128
	sys/arch/x86/include/specialreg.h: revision 1.190
	sys/arch/x86/include/specialreg.h: revision 1.191
	sys/arch/x86/include/specialreg.h: revision 1.192

s/shareing/sharing/. No functional change.

Add top-down slots event bit of architectural performance monitoring leaf.

Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.

Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().

Revision 1.104.2.11 / (download) - annotate - [select for diffs], Sat Oct 15 10:08:41 2022 UTC (16 months, 1 week ago) by martin
Branch: netbsd-9
Changes since 1.104.2.10: +42 -7 lines
Diff to previous 1.104.2.10 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1542):

	sys/arch/x86/include/specialreg.h: revision 1.189
	sys/dev/nvmm/x86/nvmm_x86.c: revision 1.23
	usr.sbin/cpuctl/arch/i386.c: revision 1.128
	sys/arch/x86/include/specialreg.h: revision 1.190
	sys/arch/x86/include/specialreg.h: revision 1.191
	sys/arch/x86/include/specialreg.h: revision 1.192

s/shareing/sharing/. No functional change.

Add top-down slots event bit of architectural performance monitoring leaf.

Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.

Modify output of CPUID Fn0000000a.
old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>
new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().

Revision 1.128 / (download) - annotate - [select for diffs], Wed Jun 15 16:28:01 2022 UTC (20 months, 1 week ago) by msaitoh
Branch: MAIN
Changes since 1.127: +42 -7 lines
Diff to previous 1.127 (colored)

Modify output of CPUID Fn0000000a.

old:
cpu0: Perfmon-eax 0x8300805<VERSION=0x5,GPCounter=0x8,GPBitwidth=0x30>
cpu0: Perfmon-eax 0x8300805<Vectorlen=0x8>
cpu0: Perfmon-edx 0x8604<FixedFunc=0x4,FFBitwidth=0x30,ANYTHREADDEPR>

new:
cpu0: Perfmon: Ver. 5
cpu0: Perfmon: General: bitwidth 48, 8 counters
cpu0: Perfmon: General: avail 0xff<CORECYCL,INST,REFCYCL,LLCREF,LLCMISS,BRINST>
cpu0: Perfmon: General: avail 0xff<BRMISPR,TOPDOWNSLOT>
cpu0: Perfmon: Fixed: bitwidth 48, 4 counters
cpu0: Perfmon: Fixed: avail 0xf<INST,CLK_CORETHREAD,CLK_REF_TSC,TOPDOWNSLOT>

Revision 1.74.6.14 / (download) - annotate - [select for diffs], Mon Jan 31 17:52:44 2022 UTC (2 years ago) by martin
Branch: netbsd-8
Changes since 1.74.6.13: +27 -27 lines
Diff to previous 1.74.6.13 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1732):

	usr.sbin/cpuctl/arch/i386.c: revision 1.125
	usr.sbin/cpuctl/arch/i386.c: revision 1.126
	usr.sbin/cpuctl/arch/i386.c: revision 1.127

Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.
Remove debug code and simplify. No functional change.
Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).

Revision 1.104.2.10 / (download) - annotate - [select for diffs], Mon Jan 31 17:51:00 2022 UTC (2 years ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE
Changes since 1.104.2.9: +27 -27 lines
Diff to previous 1.104.2.9 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1418):

	usr.sbin/cpuctl/arch/i386.c: revision 1.125
	usr.sbin/cpuctl/arch/i386.c: revision 1.126
	usr.sbin/cpuctl/arch/i386.c: revision 1.127

Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.
Remove debug code and simplify. No functional change.
Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).

Revision 1.127 / (download) - annotate - [select for diffs], Sat Jan 29 08:20:45 2022 UTC (2 years ago) by msaitoh
Branch: MAIN
Changes since 1.126: +14 -2 lines
Diff to previous 1.126 (colored)

Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).

Revision 1.126 / (download) - annotate - [select for diffs], Thu Jan 27 09:53:43 2022 UTC (2 years ago) by msaitoh
Branch: MAIN
Changes since 1.125: +10 -28 lines
Diff to previous 1.125 (colored)

Remove debug code and simplify. No functional change.

Revision 1.125 / (download) - annotate - [select for diffs], Thu Jan 13 16:02:44 2022 UTC (2 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.124: +8 -2 lines
Diff to previous 1.124 (colored)

Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.

Revision 1.74.6.13 / (download) - annotate - [select for diffs], Fri Dec 24 13:02:24 2021 UTC (2 years, 2 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.12: +86 -175 lines
Diff to previous 1.74.6.12 (colored) to branchpoint 1.74 (colored)

Pull up the following (all via patch), requested by msaitoh in ticket #1721:

	usr.sbin/cpuctl/arch/i386.c			1.118-1.119, 1.121-1.122
	usr.sbin/cpuctl/arch/cpuctl_i386.h		1.6
	sys/arch/x86/x86/identcpu_subr.c		1.8-1.9
	sys/arch/x86/x86/identcpu.c			1.123
	sys/arch/x86/include/cacheinfo.h		1.30
	sys/arch/x86/include/cpu.h			1.132

- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.

Revision 1.104.2.9 / (download) - annotate - [select for diffs], Fri Dec 24 12:58:14 2021 UTC (2 years, 2 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.8: +86 -175 lines
Diff to previous 1.104.2.8 (colored) to branchpoint 1.104 (colored)

Pull up the following (all via patch), requested by msaitoh in ticket #1396:

	usr.sbin/cpuctl/arch/i386.c			1.118-1.119, 1.121-1.122
	usr.sbin/cpuctl/arch/cpuctl_i386.h		1.6
	sys/arch/x86/x86/identcpu_subr.c		1.8-1.9
	sys/arch/x86/x86/identcpu.c			1.123
	sys/arch/x86/include/cacheinfo.h		1.30
	sys/arch/x86/include/cpu.h			1.132

- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.

Revision 1.124 / (download) - annotate - [select for diffs], Thu Dec 9 14:23:06 2021 UTC (2 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.123: +6 -18 lines
Diff to previous 1.123 (colored)

Print 1GB TLB entry at the same leve's line.

Example:
  before:
    cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
    cpu0: DTLB: 64 4KB entries 4-way
    cpu0: L2 STLB: 4K/2M: 1024 entries
    cpu0: L1 1GB page DTLB: 4 1GB entries 4-way

  after:
    cpu0: ITLB: 128 4KB entries 8-way, 2M/4M: 8 entries
    cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
    cpu0: L2 STLB: 4K/2M: 1024 entries

Revision 1.74.6.12 / (download) - annotate - [select for diffs], Wed Dec 8 15:56:18 2021 UTC (2 years, 2 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.11: +18 -8 lines
Diff to previous 1.74.6.11 (colored) to branchpoint 1.74 (colored)

Pull up the following, requested by msaitoh in ticket #1720:

	sys/arch/x86/include/specialreg.h		1.146, 1.171,
							1.173-1.178 via patch
	sys/arch/x86/x86/identcpu.c			1.106, 1.117,
							1.122 via patch
	sys/arch/x86/x86/pmap.c				patch
	sys/external/bsd/drm2/drm/drm_cache.c		1.14
	usr.sbin/cpuctl/arch/i386.c			1.114-1.117


- Add PT, PKRU, HDC, LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL,
  AVX512_BF16, TME_EN and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
  and Jasper Lake.
- Remove a few unused MSRs.
- Add comment.
- KNF. Whitespace fix.

Revision 1.104.2.8 / (download) - annotate - [select for diffs], Wed Dec 8 15:44:16 2021 UTC (2 years, 2 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.7: +18 -8 lines
Diff to previous 1.104.2.7 (colored) to branchpoint 1.104 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1391:

	sys/arch/x86/include/specialreg.h		1.171, 1.173-1.178
	sys/arch/x86/x86/identcpu.c			1.106, 1.117,
							1.122 via patch
	sys/dev/nvmm/x86/nvmm_x86.c			1.18
	sys/external/bsd/drm2/drm/drm_cache.c		1.14
	sys/external/bsd/drm2/include/asm/cpufeature.h	1.5
	usr.sbin/cpuctl/arch/i386.c			1.114-1.117


- Add LA57, PKE, PKS, CET, CET_U, CET_S, HWP, KL, AVX512_BF16, TME_EN
  and PCONFIG.
- Rename some macros to match the x86 specification and the other OSes.
- Print CPUID 0x8000008 %ebx on Intel, too.
- Print CPUID leaf 7 subleaf 1.
- Identify Tiger Lake, 3rd gen Xeon Scalable (Ice Lake), Elkhart Lake
  and Jasper Lake.
- Add comment.
- KNF. Whitespace fix.

Revision 1.104.2.7 / (download) - annotate - [select for diffs], Mon Nov 22 17:05:32 2021 UTC (2 years, 3 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.6: +3 -3 lines
Diff to previous 1.104.2.6 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by mrg in ticket #1375):

	usr.sbin/cpuctl/arch/i386.c: revision 1.123
	sys/arch/x86/x86/cpu_topology.c: revision 1.20

decode SMT parts for AMD family >= 0x17, not just 0x17.

now zen3 systems are properly identified by cpu topology for the
scheduler and cpuctl identify.

Revision 1.123 / (download) - annotate - [select for diffs], Wed Oct 27 04:15:42 2021 UTC (2 years, 4 months ago) by mrg
Branch: MAIN
Changes since 1.122: +3 -3 lines
Diff to previous 1.122 (colored)

decode SMT parts for AMD family >= 0x17, not just 0x17.

now zen3 systems are properly identified by cpu topology for the
scheduler and cpuctl identify.

Revision 1.122 / (download) - annotate - [select for diffs], Thu Oct 7 13:04:18 2021 UTC (2 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.121: +14 -93 lines
Diff to previous 1.121 (colored)

Move some common functions into x86/identcpu_subr.c. No functional change.

Revision 1.121 / (download) - annotate - [select for diffs], Mon Sep 27 17:05:58 2021 UTC (2 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.120: +39 -24 lines
Diff to previous 1.120 (colored)

Improve variable sized TLB's output.

 - Fix a bug that STLB is printed as DTLB.
 - If a TLB is variable sized, print the max size instead of error message.
   XXX This is temporary solution.

Revision 1.120 / (download) - annotate - [select for diffs], Mon Sep 27 16:52:15 2021 UTC (2 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.119: +15 -3 lines
Diff to previous 1.119 (colored)

Add Load Only TLB and Store Only TLB.

Revision 1.119 / (download) - annotate - [select for diffs], Mon Sep 27 16:47:15 2021 UTC (2 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.118: +45 -58 lines
Diff to previous 1.118 (colored)

Fix a bug that some TLB related lines were not printed.

Revision 1.118 / (download) - annotate - [select for diffs], Mon Sep 27 16:22:58 2021 UTC (2 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.117: +15 -15 lines
Diff to previous 1.117 (colored)

Add ':' for readability.

Revision 1.117 / (download) - annotate - [select for diffs], Mon Jul 12 12:56:52 2021 UTC (2 years, 7 months ago) by msaitoh
Branch: MAIN
Changes since 1.116: +4 -2 lines
Diff to previous 1.116 (colored)

 Add 0x96(Elkhart Lake) and 0x9c(Jasper Lake).
Not listed in SDM but listed in those spec update documents.

Revision 1.116 / (download) - annotate - [select for diffs], Sat Jul 10 17:18:05 2021 UTC (2 years, 7 months ago) by msaitoh
Branch: MAIN
Changes since 1.115: +4 -4 lines
Diff to previous 1.115 (colored)

0x6a and 0x6c are 3rd gen Xeon Scalable (Ice Lake).

Revision 1.115 / (download) - annotate - [select for diffs], Tue Nov 24 00:48:39 2020 UTC (3 years, 3 months ago) by msaitoh
Branch: MAIN
CVS Tags: cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Changes since 1.114: +12 -4 lines
Diff to previous 1.114 (colored)

- Print CPUID 0x8000008 %ebx on Intel, too. Intel now supports WBNOINVD.
- Print CPUID leaf 7 subleaf 1.

Revision 1.114 / (download) - annotate - [select for diffs], Sat Sep 5 07:45:44 2020 UTC (3 years, 5 months ago) by maxv
Branch: MAIN
Changes since 1.113: +4 -4 lines
Diff to previous 1.113 (colored)

x86: fix several CPUID flags

 - Rename: CPUID_PN      -> CPUID_PSN
           CPUID_CFLUSH  -> CPUID_CLFSH
           CPUID_SBF     -> CPUID_PBE
           CPUID_LZCNT   -> CPUID_ABM
           CPUID_P1GB    -> CPUID_PAGE1GB
           CPUID2_PCLMUL -> CPUID2_PCLMULQDQ
           CPUID2_CID    -> CPUID2_CNXTID
           CPUID2_xTPR   -> CPUID2_XTPR
           CPUID2_AES    -> CPUID2_AESNI
   To match the x86 specification and the other OSes.

 - Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.

Revision 1.74.6.11 / (download) - annotate - [select for diffs], Wed Aug 5 15:48:53 2020 UTC (3 years, 6 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.10: +34 -68 lines
Diff to previous 1.74.6.10 (colored) to branchpoint 1.74 (colored)

Pull up the following revisions, requested by msaitoh in ticket #1585:

	usr.sbin/cpuctl/Makefile			1.9
	usr.sbin/cpuctl/arch/cpuctl_i386.h		1.5
	usr.sbin/cpuctl/arch/i386.c			1.111-1.113 via patch
	usr.sbin/cpuctl/cpuctl.c			1.31
	usr.sbin/cpuctl/cpuctl.h			1.7
	sys/arch/x86/x86/identcpu_subr.c		1.1-1.7

- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
  processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
  ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.

Revision 1.104.2.6 / (download) - annotate - [select for diffs], Fri Jul 10 11:20:29 2020 UTC (3 years, 7 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-2-RELEASE, netbsd-9-1-RELEASE
Changes since 1.104.2.5: +35 -69 lines
Diff to previous 1.104.2.5 (colored) to branchpoint 1.104 (colored)

Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:

	usr.sbin/cpuctl/Makefile			1.9
	usr.sbin/cpuctl/arch/cpuctl_i386.h		1.5
	usr.sbin/cpuctl/arch/i386.c			1.111-1.113
	usr.sbin/cpuctl/cpuctl.c			1.31
	usr.sbin/cpuctl/cpuctl.h			1.7
	sys/arch/x86/x86/identcpu_subr.c		1.1-1.7

- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
  processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
  ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.

Revision 1.113 / (download) - annotate - [select for diffs], Mon Jun 1 08:33:40 2020 UTC (3 years, 8 months ago) by msaitoh
Branch: MAIN
Changes since 1.112: +4 -2 lines
Diff to previous 1.112 (colored)

 Add 0xa5 and 0xa6 for Comet Lake.

Revision 1.85.2.3 / (download) - annotate - [select for diffs], Tue Apr 21 18:42:47 2020 UTC (3 years, 10 months ago) by martin
Branch: phil-wifi
Changes since 1.85.2.2: +31 -67 lines
Diff to previous 1.85.2.2 (colored) to branchpoint 1.85 (colored) next main 1.86 (colored)

Sync with HEAD

Revision 1.112 / (download) - annotate - [select for diffs], Tue Apr 21 02:56:37 2020 UTC (3 years, 10 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-20200421
Changes since 1.111: +5 -41 lines
Diff to previous 1.111 (colored)

Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.

 - If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors
   can take TSC/core crystal clock ratio but core crystal clock frequency
   can't be taken. Intel SDM give us the values for some processors.
 - It also required to change lapic_per_second to make LAPIC timer correctly.
 - Add new file x86/x86/identcpu_subr.c to share common subroutines between
   kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c
   will be moved to this file in future.
 - Add comment to clarify.

Revision 1.111 / (download) - annotate - [select for diffs], Thu Apr 16 01:52:34 2020 UTC (3 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.110: +34 -34 lines
Diff to previous 1.110 (colored)

No functional change:
 - Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
   ci_max_ext_cpuid to match x86/include/cpu.h though cpuctl/arch/i386.c added
   them first.
 - Sort some entries.
 - Add comment.

Revision 1.74.6.10 / (download) - annotate - [select for diffs], Wed Apr 15 14:25:09 2020 UTC (3 years, 10 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.9: +9 -17 lines
Diff to previous 1.74.6.9 (colored) to branchpoint 1.74 (colored)

Pull up the following, requested by msaitoh in ticket #1530:

	sys/arch/x86/x86/procfs_machdep.c		1.33-1.36
	sys/arch/x86/x86/tsc.c				1.40
	sys/arch/x86/x86/specialreg.h			1.159-1.161
	usr.sbin/cpuctl/arch/i386.c			1.109-1.110 via patch

- Print avx512ifma, cqm_mbm_total, cqm_mbm_local, waitpkg, rdpru,
  Fast Short Rep Mov(fsrm), AVX512_VP2INTERSECT, SERIALIZE and
  TSXLDTRK.
- Rename CPUID Fn8000_0007 %edx bit 8 from "TSC" to "ITSC"
  (Invariant TSC) to avoid confusion.
- Print CPUID 0x80000007 %edx on both Intel and AMD.
- Remove ci_max_ext_cpuid from usr.sbin/cpuctl/arch/i386.c because it's
  the same as ci_cpuid_extlevel.
- Use unsigned to avoid undefined behavior in procfs_getonefeatreg().

Revision 1.104.2.5 / (download) - annotate - [select for diffs], Tue Apr 14 17:15:02 2020 UTC (3 years, 10 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.4: +10 -16 lines
Diff to previous 1.104.2.4 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #833):

	usr.sbin/cpuctl/arch/i386.c: revision 1.109
	sys/arch/x86/include/specialreg.h: revision 1.159
	usr.sbin/cpuctl/arch/i386.c: revision 1.110
	sys/arch/x86/include/specialreg.h: revision 1.160
	sys/arch/x86/include/specialreg.h: revision 1.161
	sys/arch/x86/x86/tsc.c: revision 1.40
	sys/arch/x86/x86/procfs_machdep.c: revision 1.35
	sys/arch/x86/x86/procfs_machdep.c: revision 1.36

  Add Fast Short Rep Mov(fsrm).

Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)

  CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
%edx bit 8 from "TSC" to "ITSC" (Invariant TSC) to avoid confusion.

  Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.

  Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.

  Print CPUID 0x80000007 %edx on both Intel and AMD.

Revision 1.85.2.2 / (download) - annotate - [select for diffs], Mon Apr 13 08:05:52 2020 UTC (3 years, 10 months ago) by martin
Branch: phil-wifi
Changes since 1.85.2.1: +115 -112 lines
Diff to previous 1.85.2.1 (colored) to branchpoint 1.85 (colored)

Mostly merge changes from HEAD upto 20200411

Revision 1.110 / (download) - annotate - [select for diffs], Mon Apr 6 09:48:44 2020 UTC (3 years, 10 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-20200411, phil-wifi-20200406
Changes since 1.109: +5 -5 lines
Diff to previous 1.109 (colored)

 Print CPUID 0x80000007 %edx on both Intel and AMD.

Revision 1.109 / (download) - annotate - [select for diffs], Mon Apr 6 09:46:21 2020 UTC (3 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.108: +7 -13 lines
Diff to previous 1.108 (colored)

 Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.

Revision 1.74.6.9 / (download) - annotate - [select for diffs], Fri Jan 31 10:53:29 2020 UTC (4 years ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-2-RELEASE
Changes since 1.74.6.8: +24 -5 lines
Diff to previous 1.74.6.8 (colored) to branchpoint 1.74 (colored)

Pull up the following, requested by msaitoh in ticket #1494:

	sys/arch/x86/include/specialreg.h	1.146, 1.151-1.154, 1.156 via patch
	usr.sbin/cpuctl/arch/i386.c		1.105-1.107 via patch

- Add definitions of AMD's CPUID Fn8000_0008 %ebx.
- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.
- Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag
  is set on AMD processor.
- Fix typos.

Revision 1.104.2.4 / (download) - annotate - [select for diffs], Tue Nov 19 13:15:57 2019 UTC (4 years, 3 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-0-RELEASE, netbsd-9-0-RC2, netbsd-9-0-RC1
Changes since 1.104.2.3: +4 -4 lines
Diff to previous 1.104.2.3 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #452):

	usr.sbin/cpuctl/arch/i386.c: revision 1.108
	sys/arch/x86/include/specialreg.h: revision 1.158

Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking
0x7d and 0x7e are for 10th generation Core (Ice Lake).

Revision 1.74.6.8 / (download) - annotate - [select for diffs], Tue Nov 19 10:45:11 2019 UTC (4 years, 3 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.7: +4 -4 lines
Diff to previous 1.74.6.7 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1450):

	usr.sbin/cpuctl/arch/i386.c: revision 1.108
	sys/arch/x86/include/specialreg.h: revision 1.158

Add the following bit definitions from the latest Intel SDM:
 - CET shadow stack
 - Fast Short REP MOV
 - Hybrid part
 - CET Indirect Branch Tracking

0x7d and 0x7e are for 10th generation Core (Ice Lake).

Revision 1.108 / (download) - annotate - [select for diffs], Sun Nov 17 15:32:00 2019 UTC (4 years, 3 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-20191119, is-mlppp-base, is-mlppp
Changes since 1.107: +4 -4 lines
Diff to previous 1.107 (colored)

0x7d and 0x7e are for 10th generation Core (Ice Lake).

Revision 1.104.2.3 / (download) - annotate - [select for diffs], Thu Oct 17 18:56:25 2019 UTC (4 years, 4 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.2: +7 -2 lines
Diff to previous 1.104.2.2 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #344):

	sys/arch/x86/include/specialreg.h: revision 1.154
	sys/arch/x86/include/specialreg.h: revision 1.155
	usr.sbin/cpuctl/arch/i386.c: revision 1.107
	sys/arch/x86/x86/procfs_machdep.c: revision 1.34

- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.

 Fix AMD Fn8000_0001f %eax bit 0's name.

Add rdpru.

Revision 1.107 / (download) - annotate - [select for diffs], Thu Oct 3 15:21:44 2019 UTC (4 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.106: +7 -2 lines
Diff to previous 1.106 (colored)

- Add definitions of AMD's CPUID Fn8000_001f Encrypted Memory features.
- Add definition of AMD's CPUID Fn8000_000a %edx bit 11 "GMET".
- Define CPUID_AMD_SVM_PFThreshold correctly.
- Modify comment a bit for consistency.

Revision 1.104.2.2 / (download) - annotate - [select for diffs], Thu Sep 26 18:50:18 2019 UTC (4 years, 5 months ago) by martin
Branch: netbsd-9
Changes since 1.104.2.1: +4 -3 lines
Diff to previous 1.104.2.1 (colored) to branchpoint 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #242):

	usr.sbin/cpuctl/arch/i386.c: revision 1.106
	sys/arch/x86/x86/identcpu.c: revision 1.94

Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag is set
on AMD processor.

Revision 1.104.2.1 / (download) - annotate - [select for diffs], Thu Sep 26 18:47:14 2019 UTC (4 years, 5 months ago) by martin
Branch: netbsd-9
Changes since 1.104: +10 -4 lines
Diff to previous 1.104 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #241):

	sys/arch/x86/include/specialreg.h: revision 1.152
	sys/arch/x86/include/specialreg.h: revision 1.153
	usr.sbin/cpuctl/arch/i386.c: revision 1.105
	sys/arch/x86/x86/spectre.c: revision 1.30
	sys/arch/x86/include/specialreg.h: revision 1.151

Add definitions of AMD's CPUID Fn8000_0008 %ebx.
Decode AMD's CPUID Fn8000_0008 %ebx.
Use macro.
Add MCOMMIT instruction.
Define CPUID_CAPEX_FLAGS's bit 10 correctly.

Revision 1.106 / (download) - annotate - [select for diffs], Mon Sep 9 05:36:21 2019 UTC (4 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.105: +4 -3 lines
Diff to previous 1.105 (colored)

 Call cpu_dcp_cacheinfo() only when the cpuid Topology Extension flag is set
on AMD prcessor.

Revision 1.105 / (download) - annotate - [select for diffs], Fri Aug 30 13:12:24 2019 UTC (4 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.104: +10 -4 lines
Diff to previous 1.104 (colored)

 Decode AMD's CPUID Fn8000_0008 %ebx.

Revision 1.74.6.7 / (download) - annotate - [select for diffs], Fri Aug 16 15:36:17 2019 UTC (4 years, 6 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.6: +95 -98 lines
Diff to previous 1.74.6.6 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1338):

	usr.sbin/cpuctl/arch/i386.c: revision 1.104
	sys/arch/x86/x86/identcpu.c: revision 1.93
	sys/arch/x86/include/cacheinfo.h: revision 1.28
	sys/arch/x86/include/specialreg.h: revision 1.150

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
  Intel Deterministic Cache Parameter Leaf(0x04), so make new
  cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
  common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

Revision 1.104 / (download) - annotate - [select for diffs], Fri Jul 26 10:03:40 2019 UTC (4 years, 7 months ago) by msaitoh
Branch: MAIN
CVS Tags: netbsd-9-base
Branch point for: netbsd-9
Changes since 1.103: +95 -98 lines
Diff to previous 1.103 (colored)

- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
  Intel Deterministic Cache Parameter Leaf(0x04), so make new
  cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
  common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

Revision 1.74.6.6 / (download) - annotate - [select for diffs], Wed Jul 17 16:01:43 2019 UTC (4 years, 7 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.5: +54 -40 lines
Diff to previous 1.74.6.5 (colored) to branchpoint 1.74 (colored)

Pull up the following revisions (via patch), requested by msaitoh
in ticket #1296:

	usr.sbin/cpuctl/arch/i386.c		1.91,1.93-1.95,1.100-1.103

- Handle NVMM and HAXM's signature.
- Regard "TCGTCGTCGTCG" as QEMU(TCG).
- Dump CPUID leaf 0x40000000 if available (for -v option).
- Add Cascade Lake, Copper Lake.
- Add Future Xeon (Cannon Lake)
- Add 06_7DH for another Ice Lake.
- Add Coffee Lake based Xeon E.
- White space fix. No functional change.

Revision 1.85.2.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:10:29 2019 UTC (4 years, 8 months ago) by christos
Branch: phil-wifi
Changes since 1.85: +298 -104 lines
Diff to previous 1.85 (colored)

Sync with HEAD

Revision 1.103 / (download) - annotate - [select for diffs], Wed May 29 03:24:23 2019 UTC (4 years, 9 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-20190609
Changes since 1.102: +13 -13 lines
Diff to previous 1.102 (colored)

 White space fix. No functional change.

Revision 1.102 / (download) - annotate - [select for diffs], Tue May 28 07:51:58 2019 UTC (4 years, 9 months ago) by msaitoh
Branch: MAIN
Changes since 1.101: +9 -6 lines
Diff to previous 1.101 (colored)

Update from the latest Intel SDM:
- Add Cascade Lake, Copper Lake
- Add Future Xeon (Cannon Lake)
- Add 06_7DH for another Ice Lake
- Add Coffee Lake based Xeon E

Revision 1.101 / (download) - annotate - [select for diffs], Tue May 28 07:44:14 2019 UTC (4 years, 9 months ago) by msaitoh
Branch: MAIN
Changes since 1.100: +4 -7 lines
Diff to previous 1.100 (colored)

 Revert previous (accidentally committed).

Revision 1.100 / (download) - annotate - [select for diffs], Tue May 28 07:41:50 2019 UTC (4 years, 9 months ago) by msaitoh
Branch: MAIN
Changes since 1.99: +9 -6 lines
Diff to previous 1.99 (colored)

 Use ETHER_LOCK()/ETHER_UNLOCK() for all ethernet drivers to protect ec_multi*.

Revision 1.99 / (download) - annotate - [select for diffs], Tue May 21 05:29:21 2019 UTC (4 years, 9 months ago) by mlelstv
Branch: MAIN
Changes since 1.98: +4 -2 lines
Diff to previous 1.98 (colored)

All MSRs can only be read at privilege level 0. The exact APIC ID cannot
be determined on some AMD CPUs.

Revision 1.98 / (download) - annotate - [select for diffs], Sat May 11 17:21:07 2019 UTC (4 years, 9 months ago) by kre
Branch: MAIN
Changes since 1.97: +2 -3 lines
Diff to previous 1.97 (colored)


Undo previous.   Not needed (and file included isn't installed anyway.

Revision 1.97 / (download) - annotate - [select for diffs], Sat May 11 12:59:50 2019 UTC (4 years, 9 months ago) by christos
Branch: MAIN
Changes since 1.96: +3 -2 lines
Diff to previous 1.96 (colored)

need cpufunc.h for rdmsr

Revision 1.96 / (download) - annotate - [select for diffs], Fri May 10 16:42:57 2019 UTC (4 years, 9 months ago) by mlelstv
Branch: MAIN
Changes since 1.95: +79 -2 lines
Diff to previous 1.95 (colored)

Get CPU topology data for AMD processors.

Revision 1.95 / (download) - annotate - [select for diffs], Sun Mar 24 04:43:54 2019 UTC (4 years, 11 months ago) by msaitoh
Branch: MAIN
Changes since 1.94: +6 -3 lines
Diff to previous 1.94 (colored)

 Add HAXM.

Revision 1.94 / (download) - annotate - [select for diffs], Fri Mar 22 04:39:02 2019 UTC (4 years, 11 months ago) by msaitoh
Branch: MAIN
Changes since 1.93: +4 -4 lines
Diff to previous 1.93 (colored)

 s/TGC/TCG/. Not Tokyo Game Show but Tiny Code Generator.

Revision 1.93 / (download) - annotate - [select for diffs], Fri Mar 22 02:33:08 2019 UTC (4 years, 11 months ago) by msaitoh
Branch: MAIN
Changes since 1.92: +29 -24 lines
Diff to previous 1.92 (colored)

- Dump CPUID leaf 0x40000000 if available (for -v option).
- Regard "TCGTCGTCGTCG" as QEMU(TGC).

Revision 1.74.6.5 / (download) - annotate - [select for diffs], Mon Feb 11 13:23:03 2019 UTC (5 years ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-1-RELEASE, netbsd-8-1-RC1
Changes since 1.74.6.4: +4 -2 lines
Diff to previous 1.74.6.4 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1187):

	usr.sbin/cpuctl/arch/i386.c: revision 1.92
	sys/arch/x86/include/specialreg.h: revision 1.138

 Add new CPUID flags WAITPKG, CLDEMOTE, MOVDIRI, MOVDIR64B and
IA32_CORE_CAPABILITIES from the latest Intel SDM.

 Add Ice Lake and Tremont from the latest Intel SDM.

 Fix bitstring format of Intel CPUID Architectural Performance Monitoring
Fn0000000a %ebx.

Revision 1.92 / (download) - annotate - [select for diffs], Tue Feb 5 08:07:59 2019 UTC (5 years ago) by msaitoh
Branch: MAIN
Changes since 1.91: +4 -2 lines
Diff to previous 1.91 (colored)

 Add Ice Lake and Tremont from the latest Intel SDM.

Revision 1.82.2.6 / (download) - annotate - [select for diffs], Fri Jan 18 08:51:02 2019 UTC (5 years, 1 month ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.82.2.5: +5 -2 lines
Diff to previous 1.82.2.5 (colored) to branchpoint 1.82 (colored) next main 1.83 (colored)

Synch with HEAD

Revision 1.91 / (download) - annotate - [select for diffs], Sun Jan 6 16:13:51 2019 UTC (5 years, 1 month ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-20190127, pgoyette-compat-20190118
Changes since 1.90: +5 -2 lines
Diff to previous 1.90 (colored)

Handle the NVMM signature.

Revision 1.82.2.5 / (download) - annotate - [select for diffs], Wed Dec 26 14:02:11 2018 UTC (5 years, 2 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.82.2.4: +11 -5 lines
Diff to previous 1.82.2.4 (colored) to branchpoint 1.82 (colored)

Sync with HEAD, resolve a few conflicts

Revision 1.74.6.4 / (download) - annotate - [select for diffs], Tue Dec 4 11:52:57 2018 UTC (5 years, 2 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.3: +189 -90 lines
Diff to previous 1.74.6.3 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1120):

	usr.sbin/cpuctl/arch/i386.c: revision 1.85
	usr.sbin/cpuctl/arch/i386.c: revision 1.86
	usr.sbin/cpuctl/arch/i386.c: revision 1.87
	usr.sbin/cpuctl/arch/i386.c: revision 1.88
	usr.sbin/cpuctl/arch/i386.c: revision 1.89
	usr.sbin/cpuctl/arch/i386.c: revision 1.90
	sys/arch/x86/include/specialreg.h: revision 1.132
	sys/arch/x86/include/specialreg.h: revision 1.133
	sys/arch/x86/include/specialreg.h: revision 1.134
	sys/arch/x86/include/specialreg.h: revision 1.135
	sys/arch/x86/include/specialreg.h: revision 1.136
	sys/arch/x86/x86/cpu_topology.c: revision 1.14

  Add MAWAU (for BND{LD,ST}X instruction) from the latest Intel SDM.

  Whitespace fix. No functional change.

Modify comment. No functional change:
- AMD also has CPUID 0x06 and 0x0d.
- PCOMMIT was obsoleted.
- Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].
- AMD also reports CPUID 7's highest subleaf. Print it.
- Use macro.
  Add Intel CPUID Extended Topology Enumeration Fn0000000b definitions.
  Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.

If the value is different from the kernel value, we should fix the kernel code.

TODO: Use 0x1f if it's available.

  Add Intel/AMD MONITOR/MWAIT leaf.
  Decode Intel/AMD MONITOR/MWAIT leaf.

  Add Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

  Print Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

Revision 1.90 / (download) - annotate - [select for diffs], Mon Nov 26 04:45:13 2018 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-1226
Changes since 1.89: +11 -5 lines
Diff to previous 1.89 (colored)

 Print Intel CPUID Architectural Performance Monitoring leaf Fn0000000a.

Revision 1.82.2.4 / (download) - annotate - [select for diffs], Mon Nov 26 01:52:54 2018 UTC (5 years, 3 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.82.2.3: +163 -70 lines
Diff to previous 1.82.2.3 (colored) to branchpoint 1.82 (colored)

Sync with HEAD, resolve a couple of conflicts

Revision 1.89 / (download) - annotate - [select for diffs], Thu Nov 22 06:15:06 2018 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-1126
Changes since 1.88: +25 -2 lines
Diff to previous 1.88 (colored)

 Decode Intel/AMD MONITOR/MWAIT leaf.

Revision 1.88 / (download) - annotate - [select for diffs], Wed Nov 21 12:19:51 2018 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.87: +97 -28 lines
Diff to previous 1.87 (colored)

 Decode package, core and SMT id if CPUID 0x0b is available on Intel processor.
If the value is different from the kernel value, we should fix the kernel code.

TODO: Use 0x1f if it's available.

Revision 1.87 / (download) - annotate - [select for diffs], Wed Nov 21 10:34:53 2018 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.86: +14 -8 lines
Diff to previous 1.86 (colored)

- AMD also reports CPUID 7's highest subleaf. Print it.
- Use macro.

Revision 1.86 / (download) - annotate - [select for diffs], Wed Nov 21 06:10:25 2018 UTC (5 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.85: +36 -41 lines
Diff to previous 1.85 (colored)

- Use ci_feat_val[7] as CPUID 7 %edx to match x86/cpu.h
- AMD also has CPUID 6.
- Remove unused code for coretemp.
- Consistently use descs[] instead of data[].

Revision 1.58.2.7 / (download) - annotate - [select for diffs], Tue Oct 9 15:43:38 2018 UTC (5 years, 4 months ago) by snj
Branch: netbsd-7
Changes since 1.58.2.6: +205 -48 lines
Diff to previous 1.58.2.6 (colored) to branchpoint 1.58 (colored) next main 1.59 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1636):
	sys/arch/x86/include/cacheinfo.h: 1.23-1.26
	sys/arch/x86/include/cpu.h: 1.70
	sys/arch/x86/include/specialreg.h: 1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
	sys/arch/x86/x86/cpu_topology.c: 1.10
	sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
	usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
  - Add CLWB bit.
  - Fix a few (unused) MSR values, and add some bit definitions of
    MSR_EFER from Murray Armfield in PR#42861.
  - CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
    comments and snprintb() string.
  - Define CPUID Fn00000001 %ebx bits and use them.
    No functional change.
  - Add Structured Extended Flags Enumeration Leaf's bit definitions:
    AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
  - Add Turbo Boost Max Technology 3.0 bit.
  - Add AMD SVM features definitions.
  - Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
  - Fix swapped comments for EFER LME and LMA
  - Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
  - Add MSR_IA32_ARCH_CAPABILITIES definition.
  - Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
  - Add Intel Deterministic Address Translation Parameter Leaf(0x18)
    definitions.
  - s/CLFUSH/CLFLUSH/
  - Add AMD's Disable Indirect Branch Predictor bit definition.
  - Add the MSR bits definitions for IBRS, STIBP and IBPB.
  - Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
  - Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
  - Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
  - Add RDCL_NO and IBRS_ALL.
  - Add SSBD and RSBA bit definitions.
  - Add AMD's SSB bit definitions for F15H, F16H and F17H.
  - Add cpuid 7 edx L1D_FLUSH bit.
  - Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
  - Add IA32_FLUSH_CMD MSR.
  - Add yet another Shared L2 TLB (2M/4M pages).
  - Add 3way and 6way of L2 cache or TLB on AMD CPU.
  - AMD L3 cache association bitfield is not 8bit but 4bit like others
    association bitfields.
  - Sort entries. No functional change.
  - Modify comment, fix typo in comment and add comment.
cpuctl(8):
  - Add detection for Quark X1000, Xeon E5 v4, E7 v4,
    Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
    Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
    Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
    Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
    7th or 8th gen Core (Kaby Lake, Coffee Lake).
  - Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
  - Print Fn0000_0007 %ecx on Intel.
  - Print Intel cpuid 7 %edx.
  - Parse the TLB info from `cpuid leaf 18H' on Intel processor.
  - Use aprint_error_dev() for error output.

Revision 1.82.2.3 / (download) - annotate - [select for diffs], Mon Jun 25 07:26:11 2018 UTC (5 years, 8 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.82.2.2: +24 -24 lines
Diff to previous 1.82.2.2 (colored) to branchpoint 1.82 (colored)

Sync with HEAD

Revision 1.85 / (download) - annotate - [select for diffs], Wed Jun 20 04:04:50 2018 UTC (5 years, 8 months ago) by msaitoh
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-1020, pgoyette-compat-0930, pgoyette-compat-0906, pgoyette-compat-0728, pgoyette-compat-0625
Branch point for: phil-wifi
Changes since 1.84: +24 -24 lines
Diff to previous 1.84 (colored)

 Whitespace fix. No functional change.

Revision 1.74.6.3 / (download) - annotate - [select for diffs], Mon Apr 9 18:04:32 2018 UTC (5 years, 10 months ago) by martin
Branch: netbsd-8
CVS Tags: netbsd-8-0-RELEASE, netbsd-8-0-RC2, netbsd-8-0-RC1
Changes since 1.74.6.2: +146 -8 lines
Diff to previous 1.74.6.2 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #715):

	sys/arch/x86/include/cacheinfo.h: revision 1.24-1.26
	usr.sbin/cpuctl/arch/i386.c: revision 1.81-1.84

- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
  this change doesn't decode perfectly.  Tested with Gemini Lake. It has
  two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
  printed yet:
        cpu0: ITLB 1 4KB entries 48-way
        cpu0: DTLB 1 4KB entries 32-way
        cpu0: L2 STLB 8 4MB entries 4-way
  Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.
 Calculate way and number of entries correctly from CPUID leaf 18H.
 Add yet another Shared L2 TLB (2M/4M pages).
XXX need redesign.

 Add 3way and 6way of L2 cache or TLB on AMD CPU.
 AMD L3 cache association bitfield is not 8bit but 4bit like others association
bitfields.

From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake

Revision 1.82.2.2 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:21 2018 UTC (5 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.82.2.1: +5 -5 lines
Diff to previous 1.82.2.1 (colored) to branchpoint 1.82 (colored)

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Revision 1.84 / (download) - annotate - [select for diffs], Fri Mar 30 09:24:40 2018 UTC (5 years, 10 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Changes since 1.83: +5 -5 lines
Diff to previous 1.83 (colored)

From the latest Intel SDM:
- Add Xeon Phi 7215, 7285 and 7295
- Add Coffee Lake

Revision 1.74.6.2 / (download) - annotate - [select for diffs], Fri Mar 16 13:05:32 2018 UTC (5 years, 11 months ago) by martin
Branch: netbsd-8
Changes since 1.74.6.1: +8 -2 lines
Diff to previous 1.74.6.1 (colored) to branchpoint 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #633):
	sys/arch/x86/include/specialreg.h: revision 1.107
	sys/arch/x86/include/specialreg.h: revision 1.108
	sys/arch/x86/include/specialreg.h: revision 1.109
	sys/arch/x86/include/cacheinfo.h: revision 1.23
	sys/arch/x86/include/specialreg.h: revision 1.110
	sys/arch/x86/include/specialreg.h: revision 1.111
	sys/arch/x86/include/specialreg.h: revision 1.112
	sys/arch/x86/include/specialreg.h: revision 1.113
	sys/arch/x86/include/specialreg.h: revision 1.114
	usr.sbin/cpuctl/arch/i386.c: revision 1.79
	sys/arch/x86/x86/identcpu.c: revision 1.70
	sys/arch/x86/include/specialreg.h: revision 1.106

  Add comment.

  Add Intel cpuid 7 %edx IBRS(IBPB Speculation Control) and
STIBP(STIBP Speculation Control) from OpenBSD.

  Print Intel cpuid 7 %edx.

Example output of cpuctl -v identify 0:
+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>

fix swapped comments for EFER LME and LMA

- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.
  Add MSR_IA32_ARCH_CAPABILITIES definition.

  Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.

Add Intel Deterministic Address Translation Parameter Leaf(0x18) definitions.

  Sort entries. No functional change.

s/CLFUSH/CLFLUSH/
No functional change.

Revision 1.82.2.1 / (download) - annotate - [select for diffs], Thu Mar 15 09:12:08 2018 UTC (5 years, 11 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.82: +67 -12 lines
Diff to previous 1.82 (colored)

Synch with HEAD

Revision 1.83 / (download) - annotate - [select for diffs], Fri Mar 9 08:49:32 2018 UTC (5 years, 11 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-0330, pgoyette-compat-0322, pgoyette-compat-0315
Changes since 1.82: +67 -12 lines
Diff to previous 1.82 (colored)

 Add yet another Shared L2 TLB (2M/4M pages).

XXX need redesign.

Revision 1.82 / (download) - annotate - [select for diffs], Mon Mar 5 10:54:05 2018 UTC (5 years, 11 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-compat-base
Branch point for: pgoyette-compat
Changes since 1.81: +9 -4 lines
Diff to previous 1.81 (colored)

 Calculate way and number of entries correctly from CPUID leaf 18H.

Revision 1.81 / (download) - annotate - [select for diffs], Mon Mar 5 05:50:37 2018 UTC (5 years, 11 months ago) by msaitoh
Branch: MAIN
Changes since 1.80: +83 -5 lines
Diff to previous 1.80 (colored)

- Parse the TLB info from `cpuid leaf 18H' on Intel processor. Currently,
  this change doesn't decode perfectly.  Tested with Gemini Lake. It has
  two L2 Shared TLB. One is 4MB and another is 2MB/4MB but former isn't
  printed yet:

	cpu0: ITLB 1 4KB entries 48-way
	cpu0: DTLB 1 4KB entries 32-way
	cpu0: L2 STLB 8 4MB entries 4-way

  Need some rework for struct x86_cache_info.
- Use aprint_error_dev() for error output.

Revision 1.80 / (download) - annotate - [select for diffs], Tue Jan 16 08:23:18 2018 UTC (6 years, 1 month ago) by mrg
Branch: MAIN
Changes since 1.79: +9 -2 lines
Diff to previous 1.79 (colored)

implement cpuctl identify for sparc and sparc64.

sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
  (this allows the new cache_printf_backend() to see them.)
  remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
  cpuctl.  it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname.  this
  changes the default output to show the local CPU not the
  generic CPU family.  eg:
  cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
  vs the generic "RT620/625" previously shown.
- for each CPU export these things:
  - name
  - fpuname
  - mid
  - cloc
  - freq
  - psr impl and version
  - mmu impl, version, and number of contexts
  - cacheinfo structure (which changed for the first time ever
    with this commit.)

sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
  size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
  export them via sysctl, as well as CPU ID and clock freq

cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
  identify routines do not need to run on a particular CPU to
  obtain its information, and use it to avoid trying to set
  affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
  exported values.

Revision 1.79 / (download) - annotate - [select for diffs], Wed Jan 10 07:08:35 2018 UTC (6 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.78: +8 -2 lines
Diff to previous 1.78 (colored)

 Print Intel cpuid 7 %edx.

Example output of cpuctl -v identify 0:

+cpu0: 00000007: 00000000 000027ab 00000000 0c000000
(snip)
+cpu0: SEF edx 0xc000000<IBRS,STIBP>

Revision 1.74.6.1 / (download) - annotate - [select for diffs], Tue Nov 21 15:03:20 2017 UTC (6 years, 3 months ago) by martin
Branch: netbsd-8
Changes since 1.74: +18 -13 lines
Diff to previous 1.74 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #365):
	sys/arch/x86/include/specialreg.h: revision 1.99
	usr.sbin/cpuctl/arch/i386.c: revision 1.75
	usr.sbin/cpuctl/arch/i386.c: revision 1.76
	usr.sbin/cpuctl/arch/i386.c: revision 1.77
	usr.sbin/cpuctl/arch/i386.c: revision 1.78
	sys/arch/x86/x86/identcpu.c: revision 1.56
	sys/arch/x86/x86/identcpu.c: revision 1.57
	sys/arch/x86/x86/cpu_topology.c: revision 1.10
	sys/arch/x86/include/specialreg.h: revision 1.100
	sys/arch/x86/include/specialreg.h: revision 1.101
	sys/arch/x86/include/specialreg.h: revision 1.102
	sys/arch/x86/include/specialreg.h: revision 1.103
	sys/arch/x86/include/specialreg.h: revision 1.104
	sys/arch/x86/include/specialreg.h: revision 1.105
Add EFER_TCE. This would be an interesting feature to have, since it
reduces the indirect cost of invlpg; but I'm not convinced the way we
flush upper-levels is correct for this yet.
Fix typo in comment
Add a comment about APICBASE_PHYSADDR. Has to do with PR/42597.
  Define CPUID Fn00000001 %ebx bits and use them. No functional change.
Set ci->ci_cflush_lsize correctly. This bug was added in the last commit(1.56).
  Add the following instruction bits in Structured Extended Flags Enumeration
Leaf from "Intel Architecture Instruction Set Extensions and Future Features
Programming Reference" (319433-030):
	AVX512_IFMA
	AVX512_VBMI
	AVX512_VBMI2
	GFNI
	VAES
	VPCLMULQDQ
	AVX512_VNNI
	AVX512_BITALG
	AVX512_VPOPCNTDQ
	AVX512_4VNNIW
	AVX512_4FMAPS
- Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
   AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.
Update from the latest Intel SDM:
  0x5c: Atom (Goldmont)
  0x5f: Atom (Goldmont, Denverton)
  0x7a: Atom (Goldmont Plus)
  Add Turbo Boost Max Technology 3.0 bit.
Update from Intel SDM:
  0x55: Xeon Scalable (Skylake)
  0x57: Xeon Phi [357]200 (Knights Landing)
  0x66: Future Core (Cannon Lake)
  0x85: Future Xeon Phi (Knights Mill)
  Add the following bits in AMD Fn8000000a %edx features (SVM features):
	PFThreshold (PAUSE filter threshold)
	AVIC (AMD virtual interrupt controller)
	V_VMSAVE_VMLOAD (virtualized VMSAVE and VMLOAD)
	vGIF (virtualized GIF)

Revision 1.78 / (download) - annotate - [select for diffs], Thu Oct 19 03:09:55 2017 UTC (6 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.77: +6 -5 lines
Diff to previous 1.77 (colored)

Update from Intel SDM:
 0x55: Xeon Scalable (Skylake)
 0x57: Xeon Phi [357]200 (Knights Landing)
 0x66: Future Core (Cannon Lake)
 0x85: Future Xeon Phi (Knights Mill)

Revision 1.77 / (download) - annotate - [select for diffs], Tue Oct 17 14:48:42 2017 UTC (6 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.76: +5 -4 lines
Diff to previous 1.76 (colored)

Update from the latest Intel SDM:
 0x5c: Atom (Goldmont)
 0x5f: Atom (Goldmont, Denverton)
 0x7a: Atom (Goldmont Plus)

Revision 1.76 / (download) - annotate - [select for diffs], Mon Oct 16 10:10:48 2017 UTC (6 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.75: +8 -5 lines
Diff to previous 1.75 (colored)

- Print ci_feat_val[5] (Structured Extended Feature leaf Fn0000_0007 %ebx) on
  AMD, too.
- Print ci_feat_val[6] (Fn0000_0007 %ecx) on Intel.

Revision 1.75 / (download) - annotate - [select for diffs], Thu Sep 7 06:40:42 2017 UTC (6 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.74: +5 -5 lines
Diff to previous 1.74 (colored)

 Define CPUID Fn00000001 %ebx bits and use them. No functional change.

Revision 1.58.2.5.2.1 / (download) - annotate - [select for diffs], Wed Jan 18 08:46:47 2017 UTC (7 years, 1 month ago) by skrll
Branch: netbsd-7-nhusb
Changes since 1.58.2.5: +11 -5 lines
Diff to previous 1.58.2.5 (colored) next main 1.58.2.6 (colored)

Sync with netbsd-5

Revision 1.58.2.6 / (download) - annotate - [select for diffs], Thu Dec 8 00:15:25 2016 UTC (7 years, 2 months ago) by snj
Branch: netbsd-7
CVS Tags: netbsd-7-nhusb-base-20170116, netbsd-7-2-RELEASE, netbsd-7-1-RELEASE, netbsd-7-1-RC2, netbsd-7-1-RC1, netbsd-7-1-2-RELEASE, netbsd-7-1-1-RELEASE, netbsd-7-1
Changes since 1.58.2.5: +11 -5 lines
Diff to previous 1.58.2.5 (colored) to branchpoint 1.58 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1285):
	sys/arch/x86/include/cacheinfo.h: revision 1.22
	sys/arch/x86/include/specialreg.h: revisions 1.87 and 1.90
	usr.sbin/cpuctl/arch/i386.c: revisions 1.72-1.74
Changes for x86's cpuctl(8):
- Add Quark X1000, Xeon E[57] v4, Core i7-69xx Extreme, 7th gen Core,
  Denverton, Xeon Phi [357]200, Future Xeon and Future Xeon Phi.
- Add SGX, UMIP, RDPID, SGXLC, AVX512DQ, AVX512BW and AVX512VL bit.
- Fix the bit location of CLFLUSHOPT.
- Add new TLB descriptor 0x64 and 0xc4.

Revision 1.72.2.2 / (download) - annotate - [select for diffs], Fri Nov 4 14:49:26 2016 UTC (7 years, 3 months ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.72.2.1: +6 -5 lines
Diff to previous 1.72.2.1 (colored) to branchpoint 1.72 (colored) next main 1.73 (colored)

Sync with HEAD

Revision 1.74 / (download) - annotate - [select for diffs], Tue Oct 11 04:16:28 2016 UTC (7 years, 4 months ago) by msaitoh
Branch: MAIN
CVS Tags: prg-localcount2-base3, prg-localcount2-base2, prg-localcount2-base1, prg-localcount2-base, prg-localcount2, pgoyette-localcount-20170426, pgoyette-localcount-20170320, pgoyette-localcount-20170107, pgoyette-localcount-20161104, perseant-stdc-iso10646-base, perseant-stdc-iso10646, netbsd-8-base, matt-nb8-mediatek-base, matt-nb8-mediatek, bouyer-socketcan-base1, bouyer-socketcan-base, bouyer-socketcan
Branch point for: netbsd-8
Changes since 1.73: +6 -5 lines
Diff to previous 1.73 (colored)

Update from the latest Intel SDM:
 - Denverton
 - Future Xeon Phi
 - 7th gen Core (Kaby Lake)

Revision 1.72.2.1 / (download) - annotate - [select for diffs], Tue Jul 26 03:24:24 2016 UTC (7 years, 7 months ago) by pgoyette
Branch: pgoyette-localcount
Changes since 1.72: +4 -4 lines
Diff to previous 1.72 (colored)

Sync with HEAD

Revision 1.73 / (download) - annotate - [select for diffs], Thu Jul 21 08:37:18 2016 UTC (7 years, 7 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-localcount-20160806, pgoyette-localcount-20160726, localcount-20160914
Changes since 1.72: +4 -4 lines
Diff to previous 1.72 (colored)

Update processor families from the latest Intel SDM:
- 06_4FH: Add Xeon E7 v4 and Core i7-69xx Extreme Edition
- 06_57H: Xeon Phi [357]200

Revision 1.72 / (download) - annotate - [select for diffs], Wed Apr 27 08:53:28 2016 UTC (7 years, 10 months ago) by msaitoh
Branch: MAIN
CVS Tags: pgoyette-localcount-base
Branch point for: pgoyette-localcount
Changes since 1.71: +9 -4 lines
Diff to previous 1.71 (colored)

Add some name from the latest Intel SDM.
 - Quark X1000, Xeon E5 v4 and the future processors.

Revision 1.71 / (download) - annotate - [select for diffs], Wed Apr 27 06:58:06 2016 UTC (7 years, 10 months ago) by msaitoh
Branch: MAIN
Changes since 1.70: +20 -12 lines
Diff to previous 1.70 (colored)

- Add structure extended feature registers into ci_feat_val[]. The locations
  are the same as x86/include/cpu.h. Curreltly those values are not used yet.
- KNF.

Revision 1.58.2.5 / (download) - annotate - [select for diffs], Sun Mar 6 17:49:56 2016 UTC (7 years, 11 months ago) by martin
Branch: netbsd-7
CVS Tags: netbsd-7-nhusb-base
Branch point for: netbsd-7-nhusb
Changes since 1.58.2.4: +9 -9 lines
Diff to previous 1.58.2.4 (colored) to branchpoint 1.58 (colored)

Pull up the following changes, requested by msaitoh in #1117:

	sys/arch/x86/include/cacheinfo.h		1.20-1.21
	sys/arch/x86/include/specialreg.h		1.83-1.86
	usr.sbin/cpuctl/arch/i386.c			1.67-1.70

Changes for x86's cpuctl(8):
- Add some TLB information (index 0x6a-0x6d).
- Add Hardware-Controlled Performance States (HWP) bits, FPU Data
  Pointer Updated Only bit and CLFLUSHOPT bit.
- Add some AMD's bit definitions from "BIOS and Kernel Developer(BKDG)
  for AMD Family 15h Models 60h-6Fh Processors".
- Add Xeon E5-4600 v3,
- Add Xeon E3-1200 v4 and v5.
- Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500.
- Change CPU family 0x1c from "Atom Family" to "45nm Atom Family"

Revision 1.70 / (download) - annotate - [select for diffs], Fri Jan 8 02:28:44 2016 UTC (8 years, 1 month ago) by msaitoh
Branch: MAIN
Changes since 1.69: +5 -5 lines
Diff to previous 1.69 (colored)

From the latest Intel SDM:
- Add Xeon E3-1200 v5
- Change 0x1c from "Atom Family" to "45nm Atom Family"

Revision 1.69 / (download) - annotate - [select for diffs], Fri Dec 4 05:34:59 2015 UTC (8 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.68: +3 -3 lines
Diff to previous 1.68 (colored)

 Model 0x5e is also 6th gen Core or Xeon E3-1500 v5 like model 0x4e.

Revision 1.68 / (download) - annotate - [select for diffs], Mon Oct 19 02:47:05 2015 UTC (8 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.67: +4 -4 lines
Diff to previous 1.67 (colored)

 Add 6th gen Core, Xeon E3-1500 v5 and Xeon D-1500 from the latest Intel SDM.

Revision 1.67 / (download) - annotate - [select for diffs], Wed Jul 1 15:46:26 2015 UTC (8 years, 7 months ago) by msaitoh
Branch: MAIN
Changes since 1.66: +7 -7 lines
Diff to previous 1.66 (colored)

 Add Xeon E5-4600 v3,  Xeon E3-1200 v4 etc. from the latest Intel SDM.

Revision 1.58.2.4 / (download) - annotate - [select for diffs], Sat May 9 08:35:10 2015 UTC (8 years, 9 months ago) by snj
Branch: netbsd-7
CVS Tags: netbsd-7-0-RELEASE, netbsd-7-0-RC3, netbsd-7-0-RC2, netbsd-7-0-RC1, netbsd-7-0-2-RELEASE, netbsd-7-0-1-RELEASE, netbsd-7-0
Changes since 1.58.2.3: +7 -5 lines
Diff to previous 1.58.2.3 (colored) to branchpoint 1.58 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #739):
	sys/arch/x86/include/specialreg.h: revision 1.82
	usr.sbin/cpuctl/arch/i386.c: revision 1.66
From Intel SDM:
- Add the Silicon Debug bit in CPUID Fn00000001 %ecx
- Add CPUID Fn0000_0007 %ecx bits
- Add comments.
--
Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).

Revision 1.66 / (download) - annotate - [select for diffs], Fri May 8 07:29:08 2015 UTC (8 years, 9 months ago) by msaitoh
Branch: MAIN
Changes since 1.65: +7 -5 lines
Diff to previous 1.65 (colored)

Update some Intel CPU models (Sky Lake, Broadwell and Atom X[357]).

Revision 1.58.2.3 / (download) - annotate - [select for diffs], Sun Apr 19 16:42:19 2015 UTC (8 years, 10 months ago) by riz
Branch: netbsd-7
Changes since 1.58.2.2: +17 -9 lines
Diff to previous 1.58.2.2 (colored) to branchpoint 1.58 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #701):
	usr.sbin/cpuctl/arch/i386.c: revision 1.65
Update from Intel SDM:
- Add Atom Z8000, Future gen Xeon (Broadwell), Next gen Xeon Phi and so on.
- Add comments.

Revision 1.65 / (download) - annotate - [select for diffs], Fri Mar 27 05:31:34 2015 UTC (8 years, 11 months ago) by msaitoh
Branch: MAIN
Changes since 1.64: +17 -9 lines
Diff to previous 1.64 (colored)

Update from Intel SDM:
- Add Atom Z8000, Future gen Xeon (Broadwell), Next gen Xeon Phi and so on.
- Add comments.

Revision 1.27.2.5 / (download) - annotate - [select for diffs], Fri Jan 16 08:30:50 2015 UTC (9 years, 1 month ago) by snj
Branch: netbsd-6
Changes since 1.27.2.4: +1284 -1114 lines
Diff to previous 1.27.2.4 (colored) to branchpoint 1.27 (colored) next main 1.28 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #1230):
	usr.sbin/cpuctl/cpuctl.8: revisions 1.9-1.12
	usr.sbin/cpuctl/cpuctl.c: revisions 1.22-1.23 and 1.25 via patch
	usr.sbin/cpuctl/cpuctl.h: revision 1.5 via patch
	usr.sbin/cpuctl/arch/cpuctl_i386.h: revisions 1.1-1.2
	usr.sbin/cpuctl/arch/i386-asm.S: revisions 1.2-1.3
	usr.sbin/cpuctl/arch/i386.c: revisions 1.34, 1.36-1.49, 1.51-1.63 via patch
	usr.sbin/cpuctl/arch/x86_64-asm.S: revisions 1.3-1.4
Update cpuctl(8). Microcode and ARM related changes are not included:
- Change the i386 asm x86_identify() so it returns a value instead of
  writing into global data. Fix a stack alignment fubar that would
  cause a crash on a cirix 486. Refactor identify code to common setup
  for normal identify and ucode identify - which was missing a
  memset().
- The Intel and AMD docs (more or less) agree on how the cpuid
  'extended family' and 'extended model' bits are used to create
  larger values than the original 16bit value allowed for.
  Calculate and save these values 'up-front' and use them throughout.
  Untangle the (backwards) nested switch statement for amd 'model 15'
  cpus.
- Use full model number to index name strings - a lot of 256 element
  arrays don't matter in usespace.
- Add support for the xsave related data from cpuid 8.n.
  Reorder the output so that the 'brand' string - which actually
  identifies the cpu is output first.
- Only complain about binding if we have more than 1 cpu.
- Check cpuid leaf 4 for newer Intel CPU to know the cache information.
- Support prefetch size.
- Print the highest extended info level as the basic info level.
- Update URL of AMD's web page.
- Add code to detect hypervisor. The code was based from FreeBSD and
  ported by Kengo Nakahara.
- Add verbose flag.
- Add newline if ci_tsc_freq is 0 to not to break the output.
- Update Intel's processor family names and models.
- Print some more bits.
- Add shared TLB
- Add prototypes.
- Add comments.
- Make some functions static.
- Sort functions.
- KNF.

Revision 1.58.2.2 / (download) - annotate - [select for diffs], Sun Dec 14 17:02:38 2014 UTC (9 years, 2 months ago) by martin
Branch: netbsd-7
Changes since 1.58.2.1: +80 -28 lines
Diff to previous 1.58.2.1 (colored) to branchpoint 1.58 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #326):
	usr.sbin/cpuctl/arch/i386.c: revision 1.60
	usr.sbin/cpuctl/arch/i386.c: revision 1.61
	usr.sbin/cpuctl/arch/i386.c: revision 1.62
	usr.sbin/cpuctl/arch/i386.c: revision 1.63
	usr.sbin/cpuctl/arch/i386.c: revision 1.64
Add code to detect hypervisor. The code was based from FreeBSD and ported
by Kengo Nakahara.
kern/49379: Hypervisor's name typo
 Move some printf()s from cpu_probe_base_features() to identifycpu().
Those printf()s are used for "identify" command but cpu_probe_base_features()
is shared by ucodeupdate_check(), too. This change fixes a problem that
the "ucode" command print extra output.
Add newline if ci_tsc_freq is 0 to not to break the output.
 Don't print the microcode version if the ioctl failed to not to
print garbage.

Revision 1.58.2.1 / (download) - annotate - [select for diffs], Fri Dec 12 16:44:35 2014 UTC (9 years, 2 months ago) by martin
Branch: netbsd-7
Changes since 1.58: +9 -5 lines
Diff to previous 1.58 (colored)

Pull up following revision(s) (requested by msaitoh in ticket #310):
	sys/arch/x86/include/specialreg.h: revision 1.79-1.80
	usr.sbin/cpuctl/arch/i386.c: revision 1.59
	sys/arch/x86/include/cacheinfo.h: revision 1.19

Update some cpuid related values:
- Add XSAVECC, XGETBV, XSAVES, SMAP and PQE
- Change XINUSE to XGETBV
- Add new cache descripter value (0xc3)
- Update signatures for the follwing CPUs:
  - Core M-5xxx
  - Core i7 Extreme
  - Future Core (0x4e)
  - Future Xeon (0x56)

Revision 1.64 / (download) - annotate - [select for diffs], Thu Dec 11 12:21:44 2014 UTC (9 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.63: +4 -2 lines
Diff to previous 1.63 (colored)

 Don't print the microcode version if the ioctl failed to not to
print garbage.

Revision 1.63 / (download) - annotate - [select for diffs], Thu Dec 11 10:07:45 2014 UTC (9 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.62: +4 -3 lines
Diff to previous 1.62 (colored)

Add newline if ci_tsc_freq is 0 to not to break the output.

Revision 1.62 / (download) - annotate - [select for diffs], Thu Nov 20 10:31:10 2014 UTC (9 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.61: +29 -27 lines
Diff to previous 1.61 (colored)

 Move some printf()s from cpu_probe_base_features() to identifycpu().
Those printf()s are used for "identify" command but cpu_probe_base_features()
is shared by ucodeupdate_check(), too. This change fixes a problem that
the "ucode" command print extra output.

Revision 1.61 / (download) - annotate - [select for diffs], Tue Nov 11 08:23:17 2014 UTC (9 years, 3 months ago) by skrll
Branch: MAIN
Changes since 1.60: +3 -3 lines
Diff to previous 1.60 (colored)

kern/49379: Hypervisor's name typo

Revision 1.60 / (download) - annotate - [select for diffs], Fri Nov 7 05:37:05 2014 UTC (9 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.59: +49 -2 lines
Diff to previous 1.59 (colored)

Add code to detect hypervisor. The code was based from FreeBSD and ported
by Kengo Nakahara.

Revision 1.59 / (download) - annotate - [select for diffs], Tue Sep 9 15:14:39 2014 UTC (9 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.58: +9 -5 lines
Diff to previous 1.58 (colored)

Update CPUID signature values from the latest Intel SDM.
- Core M-5xxx
- Core i7 extreme
- Future Core (0x4e)
- Future Xeon (0x56)

Revision 1.32.2.3 / (download) - annotate - [select for diffs], Wed Aug 20 00:05:07 2014 UTC (9 years, 6 months ago) by tls
Branch: tls-maxphys
Changes since 1.32.2.2: +1101 -921 lines
Diff to previous 1.32.2.2 (colored) to branchpoint 1.32 (colored) next main 1.33 (colored)

Rebase to HEAD as of a few days ago.

Revision 1.54.2.1 / (download) - annotate - [select for diffs], Sun Aug 10 06:59:25 2014 UTC (9 years, 6 months ago) by tls
Branch: tls-earlyentropy
Changes since 1.54: +12 -6 lines
Diff to previous 1.54 (colored) next main 1.55 (colored)

Rebase.

Revision 1.58 / (download) - annotate - [select for diffs], Fri Jul 25 14:18:49 2014 UTC (9 years, 7 months ago) by msaitoh
Branch: MAIN
CVS Tags: tls-maxphys-base, tls-earlyentropy-base, netbsd-7-base
Branch point for: netbsd-7
Changes since 1.57: +6 -3 lines
Diff to previous 1.57 (colored)

More update:
- Future Atom E3000, Z3000 (0x4a, 0x5a, 0x5d)
- Atom C2000 (0x4d)

Revision 1.57 / (download) - annotate - [select for diffs], Fri Jul 25 13:52:26 2014 UTC (9 years, 7 months ago) by msaitoh
Branch: MAIN
Changes since 1.56: +5 -5 lines
Diff to previous 1.56 (colored)

Update table for processor families and processor number series from the
latest Intel SDM.
- Atom Z3000 (0x37)
- Core M based on Broadwell (0x3d)
- Next gen Xeon based on Haswell (0x3f)

Revision 1.56 / (download) - annotate - [select for diffs], Thu Jul 3 04:11:37 2014 UTC (9 years, 7 months ago) by msaitoh
Branch: MAIN
Changes since 1.55: +3 -3 lines
Diff to previous 1.55 (colored)

Exclude descriptor 0xff of CPUID leaf 2. 0xff means the cacheinfo is in leaf 4.

Revision 1.55 / (download) - annotate - [select for diffs], Tue May 27 04:18:00 2014 UTC (9 years, 9 months ago) by msaitoh
Branch: MAIN
Changes since 1.54: +5 -2 lines
Diff to previous 1.54 (colored)

If -v is set and unknown cacheinfo desc is found, print it.

Revision 1.25.4.5 / (download) - annotate - [select for diffs], Thu May 22 11:43:02 2014 UTC (9 years, 9 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.25.4.4: +1096 -882 lines
Diff to previous 1.25.4.4 (colored) to branchpoint 1.25 (colored) next main 1.26 (colored)

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

Revision 1.54 / (download) - annotate - [select for diffs], Sat Jan 4 18:13:48 2014 UTC (10 years, 1 month ago) by msaitoh
Branch: MAIN
CVS Tags: yamt-pagecache-base9, riastradh-xf86-video-intel-2-7-1-pre-2-21-15, riastradh-drm2-base3
Branch point for: tls-earlyentropy
Changes since 1.53: +30 -37 lines
Diff to previous 1.53 (colored)

- Rename x86_print_cacheinfo() to x86_print_cache_and_tlb_info() because
  this function prints TLB info, too.
- Remove an extra printf when verbose flag is set.
- Print the highest extended info level as the basic info level.
- Sort function.

Revision 1.53 / (download) - annotate - [select for diffs], Mon Dec 23 12:35:33 2013 UTC (10 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.52: +24 -2 lines
Diff to previous 1.52 (colored)

Add verbose flag.
On x86 cpu, cpuctl -v identify dumps the return values of the cpuid
functions. The max levels are taken from CPUID 0 and CPUID 8000_0000.
It's useful for the future CPU.

Revision 1.52 / (download) - annotate - [select for diffs], Mon Dec 23 11:17:20 2013 UTC (10 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.51: +121 -97 lines
Diff to previous 1.51 (colored)

CPUID leaf 2 and 4 are only for Intel processors.

Revision 1.51 / (download) - annotate - [select for diffs], Mon Dec 23 10:13:59 2013 UTC (10 years, 2 months ago) by msaitoh
Branch: MAIN
Changes since 1.50: +28 -7 lines
Diff to previous 1.50 (colored)

Add comments. Remove comments. No functional change.

Revision 1.50 / (download) - annotate - [select for diffs], Fri Nov 15 08:47:55 2013 UTC (10 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.49: +9 -12 lines
Diff to previous 1.49 (colored)

 Modify some macros and add some new macros for CPU family and model
to reduce code duplication and to avoid bug.

CPUID_TO_STEPPING(cpuid)	(not changed)

CPUID_TO_FAMILY(cpuid)		(new)
CPUID_TO_MODEL(cpuid)		(new)

	Return the display family and the display model.
	The macro names are the same as FreeBSD.

CPUID_TO_BASEFAMILY(cpuid)	(The old name was CPUID2FAMILY)
CPUID_TO_BASEMODEL(cpuid)	(The old name was CPUID2MODEL)

	Only for the base field.

CPUID_TO_EXTFAMILY(cpuid)	(The old name was CPUID2EXTFAMILY)
CPUID_TO_EXTMODEL(cpuid)	(The old name was CPUID2EXTMODEL)

	Only for the extended field.

See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html

Revision 1.49 / (download) - annotate - [select for diffs], Thu Nov 7 18:59:01 2013 UTC (10 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.48: +3 -3 lines
Diff to previous 1.48 (colored)

Fix typo. From jnemeth.

Revision 1.48 / (download) - annotate - [select for diffs], Thu Nov 7 18:18:59 2013 UTC (10 years, 3 months ago) by msaitoh
Branch: MAIN
Changes since 1.47: +6 -5 lines
Diff to previous 1.47 (colored)

Update some processor names.

Revision 1.47 / (download) - annotate - [select for diffs], Wed Oct 30 08:42:16 2013 UTC (10 years, 3 months ago) by mrg
Branch: MAIN
Changes since 1.46: +3 -3 lines
Diff to previous 1.46 (colored)

avoid uninitialised variable use.

Revision 1.46 / (download) - annotate - [select for diffs], Mon Oct 28 05:41:49 2013 UTC (10 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.45: +8 -2 lines
Diff to previous 1.45 (colored)

Support prefetch size.

Revision 1.45 / (download) - annotate - [select for diffs], Mon Oct 21 06:33:11 2013 UTC (10 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.44: +57 -1 lines
Diff to previous 1.44 (colored)

Check cpuid leaf 4 for newer Intel CPU to know the cache information.

Revision 1.44 / (download) - annotate - [select for diffs], Mon Oct 21 06:28:15 2013 UTC (10 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.43: +577 -565 lines
Diff to previous 1.43 (colored)

No functional change:
- Add prototypes.
- Make some function static.
- Sort functions.

Revision 1.43 / (download) - annotate - [select for diffs], Fri Oct 4 17:12:48 2013 UTC (10 years, 4 months ago) by msaitoh
Branch: MAIN
Changes since 1.42: +3 -3 lines
Diff to previous 1.42 (colored)

Fix typo in comment (s/XRC0/XCR0/).

Revision 1.42 / (download) - annotate - [select for diffs], Sat Sep 14 17:23:18 2013 UTC (10 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.41: +16 -6 lines
Diff to previous 1.41 (colored)

Add shared TLB.
KNF.

Revision 1.41 / (download) - annotate - [select for diffs], Fri Sep 13 06:21:43 2013 UTC (10 years, 5 months ago) by msaitoh
Branch: MAIN
Changes since 1.40: +24 -7 lines
Diff to previous 1.40 (colored)

Update Intel processors' brand names and model names (e.g. Atom C2000 and
E3000) from the latest document.

Revision 1.40 / (download) - annotate - [select for diffs], Tue Jul 16 09:54:30 2013 UTC (10 years, 7 months ago) by msaitoh
Branch: MAIN
CVS Tags: riastradh-drm2-base2, riastradh-drm2-base1, riastradh-drm2-base, riastradh-drm2
Changes since 1.39: +27 -12 lines
Diff to previous 1.39 (colored)

 Update Intel's Processor Family Names of family == 6 from the latest document.
Add 0x35(Atom), 0x36(Atom S), 0x3f(future Xeon), 0x46(Haswell) and update some
models.

Revision 1.32.2.2 / (download) - annotate - [select for diffs], Sun Jun 23 06:29:03 2013 UTC (10 years, 8 months ago) by tls
Branch: tls-maxphys
Changes since 1.32.2.1: +43 -3 lines
Diff to previous 1.32.2.1 (colored) to branchpoint 1.32 (colored)

resync from head

Revision 1.39 / (download) - annotate - [select for diffs], Wed Mar 6 11:52:53 2013 UTC (10 years, 11 months ago) by yamt
Branch: MAIN
CVS Tags: agc-symver-base, agc-symver
Changes since 1.38: +43 -3 lines
Diff to previous 1.38 (colored)

print some more bits

Revision 1.32.2.1 / (download) - annotate - [select for diffs], Mon Feb 25 00:30:42 2013 UTC (11 years ago) by tls
Branch: tls-maxphys
Changes since 1.32: +309 -406 lines
Diff to previous 1.32 (colored)

resync with head

Revision 1.25.4.4 / (download) - annotate - [select for diffs], Wed Jan 23 00:06:41 2013 UTC (11 years, 1 month ago) by yamt
Branch: yamt-pagecache
CVS Tags: yamt-pagecache-tag8
Changes since 1.25.4.3: +309 -406 lines
Diff to previous 1.25.4.3 (colored) to branchpoint 1.25 (colored)

sync with head

Revision 1.38 / (download) - annotate - [select for diffs], Mon Jan 7 23:20:42 2013 UTC (11 years, 1 month ago) by dsl
Branch: MAIN
CVS Tags: yamt-pagecache-base8
Changes since 1.37: +89 -69 lines
Diff to previous 1.37 (colored)

Add support for the xsave related data from cpuid 8.n.
Reorder the output so that the 'brand' string - which actually identifies
  the cpu is output first.

Revision 1.37 / (download) - annotate - [select for diffs], Sun Jan 6 23:17:35 2013 UTC (11 years, 1 month ago) by dsl
Branch: MAIN
Changes since 1.36: +76 -130 lines
Diff to previous 1.36 (colored)

Use full model number to index name strings - a lot of 256 element arrays
don't matter in usespace.
Update list of intel family 6 model names (all current cpus) to include
everything upto and including sandy bridge and ivy bridge.
My i7 is no longer reported as a random P II.

Revision 1.36 / (download) - annotate - [select for diffs], Sat Jan 5 21:16:22 2013 UTC (11 years, 1 month ago) by dsl
Branch: MAIN
Changes since 1.35: +109 -181 lines
Diff to previous 1.35 (colored)

The Intel and AMD docs (more or less) agree on how the cpuid 'extended
  family' and 'extended model' bits are used to create larger values
  than the original 16bit value allowed for.
Calculate and save these values 'up-front' and use them throughout.
Untangle the (backwards) nested switch statement for amd 'model 15' cpus.
Works as badly as ever on my i7.

Revision 1.35 / (download) - annotate - [select for diffs], Sat Jan 5 16:38:12 2013 UTC (11 years, 1 month ago) by dsl
Branch: MAIN
Changes since 1.34: +18 -4 lines
Diff to previous 1.34 (colored)

If the IOC_CPU_UCODE_GET_VERSION fails with ENOTTY, try issuing the
request that the amd64 kernel understands.

Revision 1.34 / (download) - annotate - [select for diffs], Sat Jan 5 15:27:45 2013 UTC (11 years, 1 month ago) by dsl
Branch: MAIN
Changes since 1.33: +26 -32 lines
Diff to previous 1.33 (colored)

Change the i386 asm x86_identify() so it returns a value instead of writing
into global data.
Fix a stack alignment fubar that would cause a crash on a cirix 486.
Refactor identify code to common setup for normal identify and ucode
identify - which was missing a memset().

Revision 1.33 / (download) - annotate - [select for diffs], Wed Jan 2 19:24:30 2013 UTC (11 years, 1 month ago) by dsl
Branch: MAIN
Changes since 1.32: +3 -2 lines
Diff to previous 1.32 (colored)

#include sys/ioctl.h

Revision 1.25.4.3 / (download) - annotate - [select for diffs], Tue Oct 30 19:00:31 2012 UTC (11 years, 3 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.25.4.2: +71 -3 lines
Diff to previous 1.25.4.2 (colored) to branchpoint 1.25 (colored)

sync with head

Revision 1.32 / (download) - annotate - [select for diffs], Wed Aug 29 17:13:23 2012 UTC (11 years, 5 months ago) by drochner
Branch: MAIN
CVS Tags: yamt-pagecache-base7, yamt-pagecache-base6
Branch point for: tls-maxphys
Changes since 1.31: +71 -3 lines
Diff to previous 1.31 (colored)

Extend the CPU microcode update framework to support Intel x86 CPUs.
Contrary to the AMD implementation, it doesn't use xcalls to distribute
the update to all CPUs but relies on cpuctl(8) to bind itself to the
right CPU -- to keep it simple and avoid possible problems with
hyperthreading.
Also, it doesn't parse the vendor supplied file to pick the right
part for the present CPU model but relies on userland to prepare
files with specific filenames. I'll commit a pkg for this in a minute
(pkgsrc/sysutils/intel-microcode).
The ioctl interface changed; compatibility is provided (should be
limited to COMPAT_NETBSD6 as soon as this is available).

Revision 1.25.4.2 / (download) - annotate - [select for diffs], Wed May 23 10:08:28 2012 UTC (11 years, 9 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.25.4.1: +16 -18 lines
Diff to previous 1.25.4.1 (colored) to branchpoint 1.25 (colored)

sync with head.

Revision 1.27.2.4 / (download) - annotate - [select for diffs], Thu Apr 19 20:04:37 2012 UTC (11 years, 10 months ago) by riz
Branch: netbsd-6
CVS Tags: netbsd-6-1-RELEASE, netbsd-6-1-RC4, netbsd-6-1-RC3, netbsd-6-1-RC2, netbsd-6-1-RC1, netbsd-6-1-5-RELEASE, netbsd-6-1-4-RELEASE, netbsd-6-1-3-RELEASE, netbsd-6-1-2-RELEASE, netbsd-6-1-1-RELEASE, netbsd-6-1, netbsd-6-0-RELEASE, netbsd-6-0-RC2, netbsd-6-0-RC1, netbsd-6-0-6-RELEASE, netbsd-6-0-5-RELEASE, netbsd-6-0-4-RELEASE, netbsd-6-0-3-RELEASE, netbsd-6-0-2-RELEASE, netbsd-6-0-1-RELEASE, netbsd-6-0, matt-nb6-plus-nbase, matt-nb6-plus-base, matt-nb6-plus
Changes since 1.27.2.3: +16 -18 lines
Diff to previous 1.27.2.3 (colored) to branchpoint 1.27 (colored)

Pull up following revision(s) (requested by cegger in ticket #187):
	usr.sbin/cpuctl/arch/i386.c: revision 1.31
print cpu family for AMD CPU families 0x12 - 0x15

Revision 1.31 / (download) - annotate - [select for diffs], Tue Apr 17 13:00:09 2012 UTC (11 years, 10 months ago) by cegger
Branch: MAIN
CVS Tags: yamt-pagecache-base5
Changes since 1.30: +16 -18 lines
Diff to previous 1.30 (colored)

print cpu family for AMD CPU families 0x12 - 0x15

Revision 1.25.4.1 / (download) - annotate - [select for diffs], Tue Apr 17 00:09:45 2012 UTC (11 years, 10 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.25: +150 -15 lines
Diff to previous 1.25 (colored)

sync with head

Revision 1.27.2.3 / (download) - annotate - [select for diffs], Fri Apr 6 17:46:41 2012 UTC (11 years, 10 months ago) by riz
Branch: netbsd-6
Changes since 1.27.2.2: +4 -4 lines
Diff to previous 1.27.2.2 (colored) to branchpoint 1.27 (colored)

Pull up following revision(s) (requested by cegger in ticket #163):
	usr.sbin/cpuctl/arch/i386.c: revision 1.30
report l3 cache information on AMD Family 10h and newer processors

Revision 1.30 / (download) - annotate - [select for diffs], Thu Apr 5 11:05:53 2012 UTC (11 years, 10 months ago) by cegger
Branch: MAIN
CVS Tags: yamt-pagecache-base4
Changes since 1.29: +4 -4 lines
Diff to previous 1.29 (colored)

report l3 cache information on AMD Family 10h and newer processors

Revision 1.13.2.5 / (download) - annotate - [select for diffs], Sat Mar 17 18:41:15 2012 UTC (11 years, 11 months ago) by bouyer
Branch: netbsd-5
CVS Tags: netbsd-5-2-RELEASE, netbsd-5-2-RC1, netbsd-5-2-3-RELEASE, netbsd-5-2-2-RELEASE, netbsd-5-2-1-RELEASE, netbsd-5-2
Changes since 1.13.2.4: +6 -5 lines
Diff to previous 1.13.2.4 (colored) to branchpoint 1.13 (colored) next main 1.14 (colored)

Pull up following revision(s) (requested by sborrill in ticket #1735):
	usr.sbin/cpuctl/arch/i386.c: revision 1.29
Print CPU stepping level

Revision 1.27.2.2 / (download) - annotate - [select for diffs], Wed Mar 7 23:26:01 2012 UTC (11 years, 11 months ago) by riz
Branch: netbsd-6
Changes since 1.27.2.1: +6 -5 lines
Diff to previous 1.27.2.1 (colored) to branchpoint 1.27 (colored)

Pull up following revision(s) (requested by sborrill in ticket #79):
	usr.sbin/cpuctl/arch/i386.c: revision 1.29
Print CPU stepping level

Revision 1.27.2.1 / (download) - annotate - [select for diffs], Mon Mar 5 19:12:06 2012 UTC (11 years, 11 months ago) by sborrill
Branch: netbsd-6
Changes since 1.27: +5 -5 lines
Diff to previous 1.27 (colored)

Pull up the following revisions(s) (requested by joerg in ticket #75):
	usr.sbin/cpuctl/arch/i386.c:	revision 1.28
	usr.bin/unifdef/unifdef.c:	revision 1.21
	usr.bin/ktruss/dump.c:		revision 1.40
	usr.bin/error/error.h:		revision 1.19
	usr.bin/error/touch.c:		revision 1.27
	libexec/httpd/dir-index-bozo.c:	revision 1.14
	games/dab/algor.cc:		revision 1.5
	games/dab/board.h:		revision 1.4
	dist/pf/sbin/pflogd/pflogd.c:	revision 1.9
	dist/pf/sbin/pflogd/pflogd.h:	revision 1.5

Fix various format string mismatches

Revision 1.29 / (download) - annotate - [select for diffs], Fri Mar 2 16:29:31 2012 UTC (11 years, 11 months ago) by sborrill
Branch: MAIN
Changes since 1.28: +6 -5 lines
Diff to previous 1.28 (colored)

Print CPU stepping level

Revision 1.28 / (download) - annotate - [select for diffs], Wed Feb 29 23:34:01 2012 UTC (11 years, 11 months ago) by joerg
Branch: MAIN
Changes since 1.27: +5 -5 lines
Diff to previous 1.27 (colored)

Use uintmax_t for freqency computations to avoid differences between
platforms.

Revision 1.27 / (download) - annotate - [select for diffs], Fri Feb 3 05:07:17 2012 UTC (12 years ago) by yamt
Branch: MAIN
CVS Tags: netbsd-6-base
Branch point for: netbsd-6
Changes since 1.26: +3 -3 lines
Diff to previous 1.26 (colored)

use a correct macro.
releng@ ok

Revision 1.26 / (download) - annotate - [select for diffs], Sun Dec 4 17:00:10 2011 UTC (12 years, 2 months ago) by chs
Branch: MAIN
Changes since 1.25: +140 -6 lines
Diff to previous 1.25 (colored)

add info on L2 TLBs and 1GB pages.

Revision 1.25 / (download) - annotate - [select for diffs], Tue May 3 09:06:22 2011 UTC (12 years, 9 months ago) by jruoho
Branch: MAIN
CVS Tags: yamt-pagecache-base3, yamt-pagecache-base2, yamt-pagecache-base, cherry-xenmp-base, cherry-xenmp
Branch point for: yamt-pagecache
Changes since 1.24: +12 -2 lines
Diff to previous 1.24 (colored)

Identify AMD Family 11h. From PR bin/41188 by FUKAUMI Naoki.

Revision 1.23.2.1 / (download) - annotate - [select for diffs], Sat Mar 5 15:11:01 2011 UTC (12 years, 11 months ago) by bouyer
Branch: bouyer-quota2
Changes since 1.23: +6 -10 lines
Diff to previous 1.23 (colored) next main 1.24 (colored)

Sync with HEAD

Revision 1.24 / (download) - annotate - [select for diffs], Sat Feb 19 13:34:38 2011 UTC (13 years ago) by jmcneill
Branch: MAIN
CVS Tags: bouyer-quota2-nbase
Changes since 1.23: +6 -10 lines
Diff to previous 1.23 (colored)

fix printing of padlock features

Revision 1.23 / (download) - annotate - [select for diffs], Wed Dec 15 17:09:07 2010 UTC (13 years, 2 months ago) by cegger
Branch: MAIN
CVS Tags: matt-mips64-premerge-20101231, bouyer-quota2-base
Branch point for: bouyer-quota2
Changes since 1.22: +10 -5 lines
Diff to previous 1.22 (colored)

beautify printing of SVM features across multiple lines

Revision 1.13.2.2.4.1 / (download) - annotate - [select for diffs], Wed Apr 21 05:27:21 2010 UTC (13 years, 10 months ago) by matt
Branch: matt-nb5-mips64
CVS Tags: matt-nb5-mips64-premerge-20101231, matt-nb5-mips64-k15
Changes since 1.13.2.2: +74 -9 lines
Diff to previous 1.13.2.2 (colored) next main 1.13.2.3 (colored)

sync to netbsd-5

Revision 1.22 / (download) - annotate - [select for diffs], Tue Feb 23 08:46:33 2010 UTC (14 years ago) by cegger
Branch: MAIN
Changes since 1.21: +9 -10 lines
Diff to previous 1.21 (colored)

check for svm feature flags if cpuid function 0x8000000a is available.

Revision 1.21 / (download) - annotate - [select for diffs], Tue Feb 16 00:13:14 2010 UTC (14 years ago) by mrg
Branch: MAIN
Changes since 1.20: +3 -3 lines
Diff to previous 1.20 (colored)

don't call most/all Core2's "(Merom)".

Revision 1.13.2.4 / (download) - annotate - [select for diffs], Sun Oct 4 00:16:53 2009 UTC (14 years, 4 months ago) by snj
Branch: netbsd-5
CVS Tags: netbsd-5-1-RELEASE, netbsd-5-1-RC4, netbsd-5-1-RC3, netbsd-5-1-RC2, netbsd-5-1-RC1, netbsd-5-1-5-RELEASE, netbsd-5-1-4-RELEASE, netbsd-5-1-3-RELEASE, netbsd-5-1-2-RELEASE, netbsd-5-1-1-RELEASE, netbsd-5-1, matt-nb5-pq3-base, matt-nb5-pq3
Changes since 1.13.2.3: +5 -4 lines
Diff to previous 1.13.2.3 (colored) to branchpoint 1.13 (colored)

Pull up following revision(s) (requested by jmcneill in ticket #1055):
	usr.sbin/cpuctl/arch/i386.c: revision 1.20
- add newer VIA C7 core and VIA Nano.
- when printing an unknown VIA CPU, default to 'Unknown IDT/VIA' instead of 'C3'

Revision 1.20 / (download) - annotate - [select for diffs], Fri Oct 2 13:54:01 2009 UTC (14 years, 4 months ago) by jmcneill
Branch: MAIN
CVS Tags: matt-premerge-20091211
Changes since 1.19: +5 -4 lines
Diff to previous 1.19 (colored)

- add newer VIA C7 core and VIA Nano.
- when printing an unknown VIA CPU, default to 'Unknown IDT/VIA' instead of 'C3'

Revision 1.13.2.3 / (download) - annotate - [select for diffs], Mon May 18 19:43:55 2009 UTC (14 years, 9 months ago) by bouyer
Branch: netbsd-5
Changes since 1.13.2.2: +71 -7 lines
Diff to previous 1.13.2.2 (colored) to branchpoint 1.13 (colored)

Pull up following revision(s) (requested by pgoyette in ticket #761):
	sys/arch/x86/include/cacheinfo.h: revisions 1.11, 1.12
	usr.sbin/cpuctl/arch/i386.c: revisions 1.18, 1.19 via patch
1. Extend CPU probe of Intel processors to handle extended-models.  This
    allows us to properly identify new Intel 45nm processors, Core i7,
    Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
    most recent (March 2009) edition of Intel's Application Note 485.
Addresses my PR bin/41289
Addresses my PR bin/41290

Revision 1.19 / (download) - annotate - [select for diffs], Thu May 14 20:16:10 2009 UTC (14 years, 9 months ago) by pgoyette
Branch: MAIN
Changes since 1.18: +4 -4 lines
Diff to previous 1.18 (colored)

Add a few more processor extended models for Intel Family 6

Revision 1.18 / (download) - annotate - [select for diffs], Wed May 13 22:25:51 2009 UTC (14 years, 9 months ago) by pgoyette
Branch: MAIN
Changes since 1.17: +123 -71 lines
Diff to previous 1.17 (colored)

1. Extend CPU probe of Intel processors to handle extended-models.  This
   allows us to properly identify new Intel 45nm processors, Core i7,
   Atom, and the 45nm Xeon MP.

2. Properly decode several new Intel cache descriptors, as listed in the
   most recent (March 2009) edition of Intel's Application Note 485.

3. Convert decode of the various features masks to use the newly added
   snprintb_m(3) routine.

Addresses my PR bin/41289
Addresses my PR bin/41290

Revision 1.14.2.1 / (download) - annotate - [select for diffs], Wed May 13 19:20:20 2009 UTC (14 years, 9 months ago) by jym
Branch: jym-xensuspend
Changes since 1.14: +19 -7 lines
Diff to previous 1.14 (colored) next main 1.15 (colored)

Sync with HEAD.

Third (and last) commit. See http://mail-index.netbsd.org/source-changes/2009/05/13/msg221222.html

Revision 1.17 / (download) - annotate - [select for diffs], Wed Apr 22 18:10:38 2009 UTC (14 years, 10 months ago) by christos
Branch: MAIN
CVS Tags: jym-xensuspend-nbase, jym-xensuspend-base
Changes since 1.16: +6 -6 lines
Diff to previous 1.16 (colored)

WARNS=4

Revision 1.13.2.2 / (download) - annotate - [select for diffs], Tue Mar 24 20:34:56 2009 UTC (14 years, 11 months ago) by snj
Branch: netbsd-5
CVS Tags: netbsd-5-0-RELEASE, netbsd-5-0-RC4, netbsd-5-0-2-RELEASE, netbsd-5-0-1-RELEASE, netbsd-5-0, matt-nb5-mips64-u2-k2-k4-k7-k8-k9, matt-nb5-mips64-u1-k1-k5, matt-nb5-mips64-premerge-20091211, matt-nb4-mips64-k7-u2a-k9b
Branch point for: matt-nb5-mips64
Changes since 1.13.2.1: +3 -3 lines
Diff to previous 1.13.2.1 (colored) to branchpoint 1.13 (colored)

Pull up following revision(s) (requested by tsutsui in ticket #594):
	usr.sbin/cpuctl/arch/i386.c: revision 1.16
Increase size of buffer for humanize_number(3) to print cache sizes
so that it can return 128KB, 256KB and 512KB properly instead of
truncated 0MB or rounded 1MB.
Problem reported by nisimura@ on port-amd64 and port-i386.

Revision 1.16 / (download) - annotate - [select for diffs], Mon Mar 16 12:25:40 2009 UTC (14 years, 11 months ago) by tsutsui
Branch: MAIN
Changes since 1.15: +3 -3 lines
Diff to previous 1.15 (colored)

Increase size of buffer for humanize_number(3) to print cache sizes
so that it can return 128KB, 256KB and 512KB properly instead of
truncated 0MB or rounded 1MB.

Problem reported by nisimura@ on port-amd64 and port-i386.

Revision 1.15 / (download) - annotate - [select for diffs], Thu Mar 12 09:10:15 2009 UTC (14 years, 11 months ago) by yamt
Branch: MAIN
Changes since 1.14: +14 -2 lines
Diff to previous 1.14 (colored)

print some SVM info if available.

Revision 1.13.2.1 / (download) - annotate - [select for diffs], Tue Dec 23 03:36:43 2008 UTC (15 years, 2 months ago) by snj
Branch: netbsd-5
CVS Tags: netbsd-5-0-RC3, netbsd-5-0-RC2, netbsd-5-0-RC1
Changes since 1.13: +20 -23 lines
Diff to previous 1.13 (colored)

Pull up following revision(s) (requested by christos in ticket #193):
	usr.sbin/cpuctl/Makefile: revision 1.3
	usr.sbin/cpuctl/bitmask.c: file removal
	usr.sbin/cpuctl/cpuctl.h: revision 1.2
	usr.sbin/cpuctl/arch/i386.c: revision 1.14
Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.

Revision 1.14 / (download) - annotate - [select for diffs], Tue Dec 16 22:44:51 2008 UTC (15 years, 2 months ago) by christos
Branch: MAIN
Branch point for: jym-xensuspend
Changes since 1.13: +20 -23 lines
Diff to previous 1.13 (colored)

Remove 3rd buggy copy of this function and use snprintb(3) instead.
No need to allocate MAXPATHLEN buffers anymore.

Revision 1.13 / (download) - annotate - [select for diffs], Tue Oct 14 15:49:04 2008 UTC (15 years, 4 months ago) by cegger
Branch: MAIN
CVS Tags: netbsd-5-base, matt-mips64-base2
Branch point for: netbsd-5
Changes since 1.12: +3 -6 lines
Diff to previous 1.12 (colored)

do correct octal counting and use CPUID_APM_FLAGS in cpuctl

Revision 1.12 / (download) - annotate - [select for diffs], Mon Oct 13 21:11:46 2008 UTC (15 years, 4 months ago) by cegger
Branch: MAIN
Changes since 1.11: +24 -8 lines
Diff to previous 1.11 (colored)

print features4: cpuid fn80000001 %ecx on AMD CPUs.

Revision 1.11 / (download) - annotate - [select for diffs], Mon Oct 13 19:14:53 2008 UTC (15 years, 4 months ago) by cegger
Branch: MAIN
Changes since 1.10: +3 -3 lines
Diff to previous 1.10 (colored)

Add cpuid 0x80000001 %ecx features flags. Rename CPUID_MASK4 to CPUID_INTEL_MASK4 for consistency with new CPUID_AMD_MASK4

Revision 1.1.2.2 / (download) - annotate - [select for diffs], Thu Sep 18 04:30:02 2008 UTC (15 years, 5 months ago) by wrstuden
Branch: wrstuden-revivesa
Changes since 1.1.2.1: +11 -12 lines
Diff to previous 1.1.2.1 (colored) next main 1.2 (colored)

Sync with wrstuden-revivesa-base-2.

Revision 1.10 / (download) - annotate - [select for diffs], Sun Aug 24 20:27:34 2008 UTC (15 years, 6 months ago) by pgoyette
Branch: MAIN
CVS Tags: wrstuden-revivesa-base-3, wrstuden-revivesa-base-2
Changes since 1.9: +11 -12 lines
Diff to previous 1.9 (colored)

1. For non-Intel vendors, don't overload cpuflags with the extended
   flags from CPUID 80000001_EDX.  Instead, keep the extended flags
   separate, in ci_feature3_flags (Intel processors already kept a
   separate ci_feature3_flag value).

2. Decode/display ci_feature3_flag in a vendor-specific manner, since
   the definitions are vendor-specific.

OK cegger@

Revision 1.1.2.1 / (download) - annotate - [select for diffs], Mon Jun 23 04:32:12 2008 UTC (15 years, 8 months ago) by wrstuden
Branch: wrstuden-revivesa
Changes since 1.1: +86 -224 lines
Diff to previous 1.1 (colored)

Sync w/ -current. 34 merge conflicts to follow.

Revision 1.4.2.3 / (download) - annotate - [select for diffs], Wed Jun 4 02:05:59 2008 UTC (15 years, 8 months ago) by yamt
Branch: yamt-pf42
Changes since 1.4.2.2: +77 -234 lines
Diff to previous 1.4.2.2 (colored) to branchpoint 1.4 (colored) next main 1.5 (colored)

sync with head

Revision 1.9 / (download) - annotate - [select for diffs], Sat May 31 12:48:41 2008 UTC (15 years, 8 months ago) by christos
Branch: MAIN
CVS Tags: yamt-pf42-base4, yamt-pf42-base3, wrstuden-revivesa-base-1, wrstuden-revivesa-base
Changes since 1.8: +3 -3 lines
Diff to previous 1.8 (colored)

change HUMAN_NUMBER back to 5

Revision 1.8 / (download) - annotate - [select for diffs], Fri May 30 21:53:21 2008 UTC (15 years, 9 months ago) by christos
Branch: MAIN
Changes since 1.7: +3 -3 lines
Diff to previous 1.7 (colored)

remove stray `

Revision 1.7 / (download) - annotate - [select for diffs], Fri May 30 18:49:03 2008 UTC (15 years, 9 months ago) by christos
Branch: MAIN
Changes since 1.6: +54 -74 lines
Diff to previous 1.6 (colored)

- fix an amd cache entry.
- merge tables
- support phenom
from Paul Goyette

Revision 1.6 / (download) - annotate - [select for diffs], Fri May 30 14:41:57 2008 UTC (15 years, 9 months ago) by christos
Branch: MAIN
Changes since 1.5: +8 -150 lines
Diff to previous 1.5 (colored)

de-duplicated cacheinfo.h

Revision 1.5 / (download) - annotate - [select for diffs], Wed May 21 01:12:12 2008 UTC (15 years, 9 months ago) by ad
Branch: MAIN
Changes since 1.4: +24 -19 lines
Diff to previous 1.4 (colored)

Print AMD power management features.

Revision 1.4.2.2 / (download) - annotate - [select for diffs], Sun May 18 12:36:14 2008 UTC (15 years, 9 months ago) by yamt
Branch: yamt-pf42
Changes since 1.4.2.1: +1938 -0 lines
Diff to previous 1.4.2.1 (colored) to branchpoint 1.4 (colored)

sync with head.

Revision 1.4.2.1, Sat May 17 13:20:27 2008 UTC (15 years, 9 months ago) by yamt
Branch: yamt-pf42
Changes since 1.4: +0 -1938 lines
FILE REMOVED

file i386.c was added on branch yamt-pf42 on 2008-05-18 12:36:14 +0000

Revision 1.4 / (download) - annotate - [select for diffs], Sat May 17 13:20:27 2008 UTC (15 years, 9 months ago) by tsutsui
Branch: MAIN
CVS Tags: yamt-pf42-base2, yamt-pf42-base, hpcarm-cleanup-nbase
Branch point for: yamt-pf42
Changes since 1.3: +16 -2 lines
Diff to previous 1.3 (colored)

Sync intel_cpuid_cache_info with src/sys/arch/x86/x86/identcpu.c.

Revision 1.3 / (download) - annotate - [select for diffs], Thu May 15 23:31:56 2008 UTC (15 years, 9 months ago) by chris
Branch: MAIN
Changes since 1.2: +4 -4 lines
Diff to previous 1.2 (colored)

Fix two sizeof(__arraycount()) to not use sizeof when looking up the size
of the array.

This fixes a crash when run on amd phenom under amd64.

Issue reported and inital patch by Paul Goyette.

Revision 1.2 / (download) - annotate - [select for diffs], Sat May 10 15:01:05 2008 UTC (15 years, 9 months ago) by ad
Branch: MAIN
Changes since 1.1: +7 -2 lines
Diff to previous 1.1 (colored)

Report: family, model, extfamily, extmodel

Revision 1.1 / (download) - annotate - [select for diffs], Mon May 5 17:54:14 2008 UTC (15 years, 9 months ago) by ad
Branch: MAIN
Branch point for: wrstuden-revivesa

PR port-amd64/37461 x86 cpu dmesg output is noisy

Port identifycpu() to userspace. The kernel lies and reports on cpuN while
actually using the values from cpu0, but this attempts to bind itself to the
requested CPU if running as root. That doesn't work properly yet due to
kern/38588, but will do once that's fixed.

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