CVS log for src/usr.sbin/cpuctl/arch/arm.c
Up to [cvs.NetBSD.org] / src / usr.sbin / cpuctl / arch
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Keyword substitution: kv
Default branch: MAIN
Revision 1.6: download - view: text, markup, annotated - select for diffs
Sat Aug 6 18:26:43 2022 UTC (2 years, 4 months ago) by andvar
Branches: MAIN
CVS tags: perseant-exfatfs-base-20240630,
perseant-exfatfs-base,
perseant-exfatfs,
netbsd-10-base,
netbsd-10-0-RELEASE,
netbsd-10-0-RC6,
netbsd-10-0-RC5,
netbsd-10-0-RC4,
netbsd-10-0-RC3,
netbsd-10-0-RC2,
netbsd-10-0-RC1,
netbsd-10,
HEAD
Diff to: previous 1.5: preferred, colored
Changes since revision 1.5: +3 -3
lines
s/blity/bility/ in various words, mainly in comments.
Revision 1.5: download - view: text, markup, annotated - select for diffs
Sun Dec 5 04:25:33 2021 UTC (3 years ago) by msaitoh
Branches: MAIN
Diff to: previous 1.4: preferred, colored
Changes since revision 1.4: +3 -3
lines
auxilary -> auxiliary
Revision 1.4: download - view: text, markup, annotated - select for diffs
Sat Jan 16 15:35:28 2021 UTC (3 years, 10 months ago) by jmcneill
Branches: MAIN
CVS tags: cjep_sun2x-base1,
cjep_sun2x-base,
cjep_sun2x,
cjep_staticlib_x-base1,
cjep_staticlib_x-base,
cjep_staticlib_x
Diff to: previous 1.3: preferred, colored
Changes since revision 1.3: +24 -24
lines
trailing whitespace
Revision 1.2.4.1: download - view: text, markup, annotated - select for diffs
Mon Jun 10 22:10:29 2019 UTC (5 years, 6 months ago) by christos
Branches: phil-wifi
Diff to: previous 1.2: preferred, colored; next MAIN 1.3: preferred, colored
Changes since revision 1.2: +3 -3
lines
Sync with HEAD
Revision 1.3: download - view: text, markup, annotated - select for diffs
Sun Feb 3 10:48:47 2019 UTC (5 years, 10 months ago) by mrg
Branches: MAIN
CVS tags: phil-wifi-20200421,
phil-wifi-20200411,
phil-wifi-20200406,
phil-wifi-20191119,
phil-wifi-20190609,
netbsd-9-base,
netbsd-9-4-RELEASE,
netbsd-9-3-RELEASE,
netbsd-9-2-RELEASE,
netbsd-9-1-RELEASE,
netbsd-9-0-RELEASE,
netbsd-9-0-RC2,
netbsd-9-0-RC1,
netbsd-9,
is-mlppp-base,
is-mlppp
Diff to: previous 1.2: preferred, colored
Changes since revision 1.2: +3 -3
lines
- enlarge buffer to avoid snprintf() truncation
Revision 1.2: download - view: text, markup, annotated - select for diffs
Tue Jan 16 08:23:18 2018 UTC (6 years, 10 months ago) by mrg
Branches: MAIN
CVS tags: phil-wifi-base,
pgoyette-compat-merge-20190127,
pgoyette-compat-base,
pgoyette-compat-20190127,
pgoyette-compat-20190118,
pgoyette-compat-1226,
pgoyette-compat-1126,
pgoyette-compat-1020,
pgoyette-compat-0930,
pgoyette-compat-0906,
pgoyette-compat-0728,
pgoyette-compat-0625,
pgoyette-compat-0521,
pgoyette-compat-0502,
pgoyette-compat-0422,
pgoyette-compat-0415,
pgoyette-compat-0407,
pgoyette-compat-0330,
pgoyette-compat-0322,
pgoyette-compat-0315,
pgoyette-compat
Branch point for: phil-wifi
Diff to: previous 1.1: preferred, colored
Changes since revision 1.1: +9 -2
lines
implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
Revision 1.1.10.2: download - view: text, markup, annotated - select for diffs
Thu May 22 11:43:02 2014 UTC (10 years, 6 months ago) by yamt
Branches: yamt-pagecache
Diff to: previous 1.1.10.1: preferred, colored; branchpoint 1.1: preferred, colored; next MAIN 1.2: preferred, colored
Changes since revision 1.1.10.1: +269 -0
lines
sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
Revision 1.1.4.2: download - view: text, markup, annotated - select for diffs
Mon Feb 25 00:30:42 2013 UTC (11 years, 9 months ago) by tls
Branches: tls-maxphys
Diff to: previous 1.1.4.1: preferred, colored; branchpoint 1.1: preferred, colored; next MAIN 1.2: preferred, colored
Changes since revision 1.1.4.1: +269 -0
lines
resync with head
Revision 1.1.10.1
Thu Jan 31 23:40:48 2013 UTC (11 years, 10 months ago) by yamt
Branches: yamt-pagecache
FILE REMOVED
Changes since revision 1.1: +0 -269
lines
file arm.c was added on branch yamt-pagecache on 2014-05-22 11:43:02 +0000
Revision 1.1.4.1
Thu Jan 31 23:40:48 2013 UTC (11 years, 10 months ago) by tls
Branches: tls-maxphys
FILE REMOVED
Changes since revision 1.1: +0 -269
lines
file arm.c was added on branch tls-maxphys on 2013-02-25 00:30:42 +0000
Revision 1.1: download - view: text, markup, annotated - select for diffs
Thu Jan 31 23:40:48 2013 UTC (11 years, 10 months ago) by matt
Branches: MAIN
CVS tags: yamt-pagecache-base9,
tls-maxphys-base,
tls-earlyentropy-base,
tls-earlyentropy,
riastradh-xf86-video-intel-2-7-1-pre-2-21-15,
riastradh-drm2-base3,
riastradh-drm2-base2,
riastradh-drm2-base1,
riastradh-drm2-base,
riastradh-drm2,
prg-localcount2-base3,
prg-localcount2-base2,
prg-localcount2-base1,
prg-localcount2-base,
prg-localcount2,
pgoyette-localcount-base,
pgoyette-localcount-20170426,
pgoyette-localcount-20170320,
pgoyette-localcount-20170107,
pgoyette-localcount-20161104,
pgoyette-localcount-20160806,
pgoyette-localcount-20160726,
pgoyette-localcount,
perseant-stdc-iso10646-base,
perseant-stdc-iso10646,
netbsd-8-base,
netbsd-8-3-RELEASE,
netbsd-8-2-RELEASE,
netbsd-8-1-RELEASE,
netbsd-8-1-RC1,
netbsd-8-0-RELEASE,
netbsd-8-0-RC2,
netbsd-8-0-RC1,
netbsd-8,
netbsd-7-nhusb-base-20170116,
netbsd-7-nhusb-base,
netbsd-7-nhusb,
netbsd-7-base,
netbsd-7-2-RELEASE,
netbsd-7-1-RELEASE,
netbsd-7-1-RC2,
netbsd-7-1-RC1,
netbsd-7-1-2-RELEASE,
netbsd-7-1-1-RELEASE,
netbsd-7-1,
netbsd-7-0-RELEASE,
netbsd-7-0-RC3,
netbsd-7-0-RC2,
netbsd-7-0-RC1,
netbsd-7-0-2-RELEASE,
netbsd-7-0-1-RELEASE,
netbsd-7-0,
netbsd-7,
matt-nb8-mediatek-base,
matt-nb8-mediatek,
localcount-20160914,
bouyer-socketcan-base1,
bouyer-socketcan-base,
bouyer-socketcan,
agc-symver-base,
agc-symver
Branch point for: yamt-pagecache,
tls-maxphys
Add arm support for cpuctl identify
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