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CVS log for src/tests/lib/libnvmm/h_mem_assist_asm.S

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Revision 1.10 / (download) - annotate - [select for diffs], Sun Dec 27 20:56:14 2020 UTC (3 years, 3 months ago) by reinoud
Branch: MAIN
CVS Tags: netbsd-10-base, netbsd-10-0-RELEASE, netbsd-10-0-RC6, netbsd-10-0-RC5, netbsd-10-0-RC4, netbsd-10-0-RC3, netbsd-10-0-RC2, netbsd-10-0-RC1, netbsd-10, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x, HEAD
Changes since 1.9: +24 -1 lines
Diff to previous 1.9 (colored)

Implement support for trapping REP CMPS instructions in NVMM.

Qemu would abort hard when NVMM would get a memory trap on the instruction
since it didn't know it.

Revision 1.9 / (download) - annotate - [select for diffs], Sat Sep 5 07:22:26 2020 UTC (3 years, 7 months ago) by maxv
Branch: MAIN
Changes since 1.8: +14 -15 lines
Diff to previous 1.8 (colored)

nvmm: update copyright headers

Revision 1.6.2.3 / (download) - annotate - [select for diffs], Mon Apr 13 08:05:29 2020 UTC (4 years ago) by martin
Branch: phil-wifi
Changes since 1.6.2.2: +117 -2 lines
Diff to previous 1.6.2.2 (colored) to branchpoint 1.6 (colored) next main 1.7 (colored)

Mostly merge changes from HEAD upto 20200411

Revision 1.6.4.1 / (download) - annotate - [select for diffs], Sun Nov 10 12:58:30 2019 UTC (4 years, 5 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE, netbsd-9-0-RELEASE, netbsd-9-0-RC2, netbsd-9-0-RC1
Changes since 1.6: +117 -2 lines
Diff to previous 1.6 (colored) next main 1.7 (colored)

Pull up following revision(s) (requested by maxv in ticket #405):

	usr.sbin/nvmmctl/nvmmctl.8: revision 1.2
	lib/libnvmm/libnvmm.3: revision 1.24
	sys/dev/nvmm/nvmm.h: revision 1.11
	lib/libnvmm/libnvmm.3: revision 1.25
	sys/dev/nvmm/x86/nvmm_x86.h: revision 1.16
	sys/dev/nvmm/nvmm.h: revision 1.12
	sys/dev/nvmm/x86/nvmm_x86.h: revision 1.17
	tests/lib/libnvmm/h_mem_assist.c: revision 1.12
	sys/dev/nvmm/x86/nvmm_x86.h: revision 1.18
	share/mk/bsd.hostprog.mk: revision 1.82
	lib/libnvmm/libnvmm.c: revision 1.15
	distrib/sets/lists/base/md.amd64: revision 1.281
	tests/lib/libnvmm/h_mem_assist.c: revision 1.13
	lib/libnvmm/libnvmm.c: revision 1.16
	tests/lib/libnvmm/h_mem_assist.c: revision 1.14
	lib/libnvmm/libnvmm_x86.c: revision 1.32
	lib/libnvmm/libnvmm.c: revision 1.17
	tests/lib/libnvmm/h_mem_assist.c: revision 1.15
	lib/libnvmm/libnvmm_x86.c: revision 1.33
	lib/libnvmm/libnvmm.c: revision 1.18
	usr.sbin/nvmmctl/Makefile: revision 1.1
	tests/lib/libnvmm/h_mem_assist_asm.S: revision 1.7
	tests/lib/libnvmm/h_mem_assist.c: revision 1.16
	lib/libnvmm/libnvmm_x86.c: revision 1.34
	usr.sbin/nvmmctl/Makefile: revision 1.2
	tests/lib/libnvmm/h_mem_assist_asm.S: revision 1.8
	tests/lib/libnvmm/h_mem_assist.c: revision 1.17
	sys/dev/nvmm/nvmm_internal.h: revision 1.13
	lib/libnvmm/libnvmm_x86.c: revision 1.35
	lib/libnvmm/libnvmm_x86.c: revision 1.36
	usr.sbin/postinstall/postinstall.in: revision 1.8
	lib/libnvmm/libnvmm_x86.c: revision 1.37
	lib/libnvmm/libnvmm_x86.c: revision 1.38
	lib/libnvmm/libnvmm_x86.c: revision 1.39
	usr.sbin/Makefile: revision 1.282
	lib/libnvmm/nvmm.h: revision 1.13
	lib/libnvmm/nvmm.h: revision 1.14
	lib/libnvmm/nvmm.h: revision 1.15
	sys/dev/nvmm/nvmm.c: revision 1.23
	lib/libnvmm/nvmm.h: revision 1.16
	sys/dev/nvmm/nvmm.c: revision 1.24
	lib/libnvmm/nvmm.h: revision 1.17
	sys/dev/nvmm/nvmm.c: revision 1.25
	tests/lib/libnvmm/h_io_assist.c: revision 1.9
	etc/MAKEDEV.tmpl: revision 1.209
	tests/lib/libnvmm/h_io_assist.c: revision 1.10
	tests/lib/libnvmm/h_io_assist.c: revision 1.11
	etc/group: revision 1.35
	distrib/sets/lists/man/mi: revision 1.1660
	sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.40
	sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.41
	sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.42
	sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.43
	sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.44
	sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.51
	sys/dev/nvmm/nvmm_ioctl.h: revision 1.8
	sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.52
	sys/dev/nvmm/nvmm_ioctl.h: revision 1.9
	sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.53
	usr.sbin/nvmmctl/nvmmctl.c: revision 1.1
	lib/libnvmm/libnvmm.3: revision 1.20
	distrib/sets/lists/debug/md.amd64: revision 1.106
	lib/libnvmm/libnvmm.3: revision 1.21
	lib/libnvmm/libnvmm.3: revision 1.22
	usr.sbin/nvmmctl/nvmmctl.8: revision 1.1
	lib/libnvmm/libnvmm.3: revision 1.23

Fix incorrect parsing: the R/M field uses a special GPR map when the
address size is 16 bits, regardless of the actual operating mode. With
this special map there can be two registers referenced at once, and
also disp16-only.
Implement this special behavior, and add associated tests. While here
simplify a few things.
With this in place, the Windows 95 installer initializes correctly.
Part of PR/54611.
add missing initializer
Implement XCHG, add associated tests, and add comments to explain. With
this in place the Windows 95 installer completes successfuly.
Part of PR/54611.
Improve nvmm_vcpu_dump().
Put back 'default', because llvm apparently doesn't realize that all cases
are covered in the switch.
Miscellaneous changes in NVMM, to address several inconsistencies and
issues in the libnvmm API.
 - Rename NVMM_CAPABILITY_VERSION to NVMM_KERN_VERSION, and check it in
   libnvmm. Introduce NVMM_USER_VERSION, for future use.
 - In libnvmm, open "/dev/nvmm" as read-only and with O_CLOEXEC. This is to
   avoid sharing the VMs with the children if the process forks. In the
   NVMM driver, force O_CLOEXEC on open().
 - Rename the following things for consistency:
       nvmm_exit*              -> nvmm_vcpu_exit*
       nvmm_event*             -> nvmm_vcpu_event*
       NVMM_EXIT_*             -> NVMM_VCPU_EXIT_*
       NVMM_EVENT_INTERRUPT_HW -> NVMM_VCPU_EVENT_INTR
       NVMM_EVENT_EXCEPTION    -> NVMM_VCPU_EVENT_EXCP
   Delete NVMM_EVENT_INTERRUPT_SW, unused already.
 - Slightly reorganize the MI/MD definitions, for internal clarity.
 - Split NVMM_VCPU_EXIT_MSR in two: NVMM_VCPU_EXIT_{RD,WR}MSR. Also provide
   separate u.rdmsr and u.wrmsr fields. This is more consistent with the
   other exit reasons.
 - Change the types of several variables:
       event.type                  enum -> u_int
       event.vector                uint64_t -> uint8_t
       exit.u.*msr.msr:            uint64_t -> uint32_t
       exit.u.io.type:             enum -> bool
       exit.u.io.seg:              int -> int8_t
       cap.arch.mxcsr_mask:        uint64_t -> uint32_t
       cap.arch.conf_cpuid_maxops: uint64_t -> uint32_t
 - Delete NVMM_VCPU_EXIT_MWAIT_COND, it is AMD-only and confusing, and we
   already intercept 'monitor' so it is never armed.
 - Introduce vmx_exit_insn() for NVMM-Intel, similar to svm_exit_insn().
   The 'npc' field wasn't getting filled properly during certain VMEXITs.
 - Introduce nvmm_vcpu_configure(). Similar to nvmm_machine_configure(),
   but as its name indicates, the configuration is per-VCPU and not per-VM.
   Migrate and rename NVMM_MACH_CONF_X86_CPUID to NVMM_VCPU_CONF_CPUID.
   This becomes per-VCPU, which makes more sense than per-VM.
 - Extend the NVMM_VCPU_CONF_CPUID conf to allow triggering VMEXITs on
   specific leaves. Until now we could only mask the leaves. An uint32_t
   is added in the structure:
        uint32_t mask:1;
        uint32_t exit:1;
        uint32_t rsvd:30;
   The two first bits select the desired behavior on the leaf. Specifying
   zero on both resets the leaf to the default behavior. The new
   NVMM_VCPU_EXIT_CPUID exit reason is added.
Three changes in libnvmm:
 - Add 'mach' and 'vcpu' backpointers in the nvmm_io and nvmm_mem
   structures.
 - Rename 'nvmm_callbacks' to 'nvmm_assist_callbacks'.
 - Rename and migrate NVMM_MACH_CONF_CALLBACKS to NVMM_VCPU_CONF_CALLBACKS,
   it now becomes per-VCPU.
Update the libnvmm man page:
 - Sync the naming with reality.
 - Replace "relevant" by "desired" and "virtualizer" by "emulator", closer
   to what I meant.
 - Add a "VCPU Configuration" section.
 - Add a "Machine Ownership" section.
Add the "nvmm" group, and make nvmm_init() public. Sent to tech-kern@ a few
days ago.
Use the new PTE naming, and define CR3_FRAME_* separately. No functional
change.
Add a new VCPU conf option, that allows userland to request VMEXITs after a
TPR change. This is supported on all Intel CPUs, and not-too-old AMD CPUs.
The reason for wanting this option is that certain OSes (like Win10 64bit)
manage interrupt priority in hardware via CR8 directly, and for these OSes,
the emulator may want to sync its internal TPR state on each change.
Add two new fields in cap.arch, to report the conf capabilities. Report TPR
only on Intel for now, not AMD, because I don't have a recent AMD CPU on
which to test.
Mask CPUID leaf 0x0A on Intel, because we don't want the guest to try (and
fail) to probe the PMC MSRs. This avoids "Unexpected WRMSR" warnings in
qemu-nvmm.
Add PCID support in the guests. This speeds up most 64bit guests, because
since Meltdown, everybody uses PCID (including NetBSD).
Change the way root_owner works: consider the calling process as root_owner
not if it has root privileges, but if the /dev/nvmm device was opened with
write permissions. Introduce the undocumented nvmm_root_init() function to
achieve that.
The goal is to simplify the logic and have more granularity, eg if we want
a monitoring agent to access VMs but don't want to give this agent real
root access on the system.
A few changes:
 - Use smaller types in struct nvmm_capability.
 - Use smaller type for nvmm_io.port.
 - Switch exitstate to a compacted structure.
Add nram in struct nvmm_ctl_mach_info.
Add nvmmctl, with two commands for now.
Macro tidyness.
Sort SEE ALSO.
should be fork(2), noticed by wiz
Add debug entry for newly introduced nvmmctl utility.
Annotate a covering switch as such to avoid warnings about missing
returns.
Forgot to put nvmmctl in the "nvmm" group.
Add nvmm group.

Revision 1.8 / (download) - annotate - [select for diffs], Mon Oct 14 10:39:24 2019 UTC (4 years, 6 months ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, phil-wifi-20191119, is-mlppp-base, is-mlppp
Changes since 1.7: +46 -1 lines
Diff to previous 1.7 (colored)

Implement XCHG, add associated tests, and add comments to explain. With
this in place the Windows 95 installer completes successfuly.

Part of PR/54611.

Revision 1.7 / (download) - annotate - [select for diffs], Sun Oct 13 17:32:15 2019 UTC (4 years, 6 months ago) by maxv
Branch: MAIN
Changes since 1.6: +72 -2 lines
Diff to previous 1.6 (colored)

Fix incorrect parsing: the R/M field uses a special GPR map when the
address size is 16 bits, regardless of the actual operating mode. With
this special map there can be two registers referenced at once, and
also disp16-only.

Implement this special behavior, and add associated tests. While here
simplify a few things.

With this in place, the Windows 95 installer initializes correctly.

Part of PR/54611.

Revision 1.6.2.2 / (download) - annotate - [select for diffs], Mon Jun 10 22:10:07 2019 UTC (4 years, 10 months ago) by christos
Branch: phil-wifi
Changes since 1.6.2.1: +295 -0 lines
Diff to previous 1.6.2.1 (colored) to branchpoint 1.6 (colored)

Sync with HEAD

Revision 1.6.2.1, Tue Mar 19 19:23:39 2019 UTC (5 years ago) by christos
Branch: phil-wifi
Changes since 1.6: +0 -295 lines
FILE REMOVED

file h_mem_assist_asm.S was added on branch phil-wifi on 2019-06-10 22:10:07 +0000

Revision 1.6 / (download) - annotate - [select for diffs], Tue Mar 19 19:23:39 2019 UTC (5 years ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20190609, netbsd-9-base
Branch point for: phil-wifi, netbsd-9
Changes since 1.5: +2 -0 lines
Diff to previous 1.5 (colored)

Add CVS ids, and rename the PTE bits. No functional change.

Revision 1.5 / (download) - annotate - [select for diffs], Thu Feb 7 10:58:45 2019 UTC (5 years, 2 months ago) by maxv
Branch: MAIN
Changes since 1.4: +89 -0 lines
Diff to previous 1.4 (colored)

Improvements:

 - Emulate the instructions by executing them directly on the host CPU.
   This is easier and probably faster than doing it in software
   manually.

 - Decode SUB from Primary, CMP from Group1, TEST from Group3, and add
   associated tests.

 - Handle correctly the cases where an instruction that always implicitly
   reads the register operand is executed with the mem operand as source
   (eg: "orq (%rbx),%rax").

 - Fix the MMU handling of 32bit-PAE. Under PAE CR3 is not page-aligned,
   so there are extra bits that are valid.

With these changes in place I can boot Windows XP on Qemu+NVMM.

Revision 1.4 / (download) - annotate - [select for diffs], Wed Feb 6 15:42:31 2019 UTC (5 years, 2 months ago) by joerg
Branch: MAIN
Changes since 1.3: +2 -2 lines
Diff to previous 1.3 (colored)

movzx is not AT&T syntax, but some bastard version of Intel syntax.
Switch to the equivalent mnenomic.

Revision 1.3 / (download) - annotate - [select for diffs], Fri Feb 1 06:49:58 2019 UTC (5 years, 2 months ago) by maxv
Branch: MAIN
Changes since 1.2: +25 -0 lines
Diff to previous 1.2 (colored)

Fix two issues:

 * Uh I put the wrong masks in some GPRs, fuck.

 * When the opsize of MOVZX is 4, we need to combine the zero-extend from
   the instruction with the natural zero-extend of long mode.

Add two associated tests.

Revision 1.1.2.3 / (download) - annotate - [select for diffs], Fri Jan 18 08:51:00 2019 UTC (5 years, 2 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.1.2.2: +20 -0 lines
Diff to previous 1.1.2.2 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

Synch with HEAD

Revision 1.2 / (download) - annotate - [select for diffs], Thu Dec 27 07:22:31 2018 UTC (5 years, 3 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-20190127, pgoyette-compat-20190118
Changes since 1.1: +20 -0 lines
Diff to previous 1.1 (colored)

Several improvements and fixes:

 * Change the Assist API. Rather than passing callbacks in each call, the
   callbacks are now registered beforehand. Then change the I/O Assist to
   fetch MMIO data via the Mem callback. This allows a guest to perform an
   I/O string operation on a memory that is itself an MMIO.

 * Introduce two new functions internal to libnvmm, read_guest_memory and
   write_guest_memory. They can handle mapped memory, MMIO memory and
   cross-page transactions.

 * Allow nvmm_gva_to_gpa and nvmm_gpa_to_hva to take non-page-aligned
   addresses. This simplifies a lot of things.

 * Support the MOVS instruction, and add a test for it. This instruction
   is special, in that it takes two implicit memory operands. In
   particular, it means that the two buffers can both be in MMIO memory,
   and we handle this case.

 * Fix gross copy-pasto in nvmm_hva_unmap. Also fix a few things here and
   there.

Revision 1.1.2.2 / (download) - annotate - [select for diffs], Wed Dec 26 14:02:09 2018 UTC (5 years, 3 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.1: +159 -0 lines
Diff to previous 1.1.2.1 (colored) to branchpoint 1.1 (colored)

Sync with HEAD, resolve a few conflicts

Revision 1.1.2.1, Sun Dec 23 13:35:02 2018 UTC (5 years, 3 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1: +0 -159 lines
FILE REMOVED

file h_mem_assist_asm.S was added on branch pgoyette-compat on 2018-12-26 14:02:09 +0000

Revision 1.1 / (download) - annotate - [select for diffs], Sun Dec 23 13:35:02 2018 UTC (5 years, 3 months ago) by maxv
Branch: MAIN
CVS Tags: pgoyette-compat-1226
Branch point for: pgoyette-compat

Add initial tests for libnvmm's Mem Assist, with 8 test cases.

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