CVS log for src/sys/uvm/pmap/pmap_tlb.h

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Support CPUs that might not have ASIDs in the common pmap.

MI PMAP hardware page table walker support.

This is based on code given to me by Matt Thomas a long time ago with
many updates and bugs fixes from me.

KNF.  Add some whitespace to the TLBINV_MAP macro and tlb_invalidate_op
enum.

Provide a TLBINFO_OWNED

convert to use actual __BITMAP_*() macros from <sys/bitops.h>, and make
it possible to override the ASID bitmap length; default to 256 ASIDs as before

XXX NFCI; compile tested only on evbpcc and evbmips, unfortunately didn't
find any combination of port using the MI pmap_tlb.c and working in QEMU

make it possible to not use the icache evcnts

update from HEAD

Sync with HEAD

Multiple inclusion protection define consistency

Whitespace

Sync with HEAD

Changes so that MIPS can use the common pmap.
Change/augment the virtual cache alias callbacks.

Sync with HEAD

include <sys/evcnt.h>

Use PMAP_TLB_MAX instead of MAXCPUS.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

file pmap_tlb.h was added on branch tls-maxphys on 2014-08-20 00:04:45 +0000

file pmap_tlb.h was added on branch yamt-pagecache on 2014-05-22 11:41:19 +0000

Change cpu_tlb_info definition based on PMAP_TLB_MAX instead of MULTIPROCESSOR

Allow this to handle H/W tlbs.  Some ARM allow for a cheap way to flush all
entries using an ASID from the TLB.  Add support for taking advantage of it.
Most ARMs don't have an easy way to find out what's in the TLB so make
record_asids can just say all ASIDs are in use.  Fix some off by 1 errors.

Merge riastradh-drm2 to HEAD.

sync with head

sync with HEAD

file pmap_tlb.h was added on branch rmind-smpnet on 2013-08-28 23:59:38 +0000

If not MULTIPROCESSOR, just make cpu_tlb_info(ci) return &pmap_tlb0_info

Make this kcpuset_t instead of the private __cpuset_t
Add improvements for single TLB implementation (PPC, ARM).

Split tlb related stuff into pmap_tlb.h so that can be used for ASID mgmt
for non-soft TLB pmaps.