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Default branch: MAIN
Revision 1.39 / (download) - annotate - [select for diffs], Mon Jun 27 06:45:14 2022 UTC (7 months, 1 week ago) by martin
Branch: MAIN
CVS Tags: netbsd-10-base,
netbsd-10,
bouyer-sunxi-drm-base,
bouyer-sunxi-drm,
HEAD
Changes since 1.38: +1 -1
lines
Diff to previous 1.38 (colored)
Fix editing mishap, should fix the build
Revision 1.38 / (download) - annotate - [select for diffs], Sun Jun 26 14:31:33 2022 UTC (7 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.37: +16 -4
lines
Diff to previous 1.37 (colored)
Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined by GCC for HPPA to hold the return address where the signal trampoline will resume. XXX Same treatment is needed for HPPA64, but not done as part of this commit. Thanks to thorpej for help with this. (ages ago)
Revision 1.37 / (download) - annotate - [select for diffs], Wed Nov 24 00:21:59 2021 UTC (14 months, 1 week ago) by thorpej
Branch: MAIN
Changes since 1.36: +27 -7
lines
Diff to previous 1.36 (colored)
Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined by GCC for SuperH for GBR, MACH, MACL, and SR.
Revision 1.36 / (download) - annotate - [select for diffs], Mon Nov 22 16:41:00 2021 UTC (14 months, 1 week ago) by thorpej
Branch: MAIN
Changes since 1.35: +2 -2
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Diff to previous 1.35 (colored)
Gah, fix two typos.
Revision 1.35 / (download) - annotate - [select for diffs], Mon Nov 22 16:40:01 2021 UTC (14 months, 1 week ago) by thorpej
Branch: MAIN
Changes since 1.34: +15 -4
lines
Diff to previous 1.34 (colored)
Teach the LLVM-derived unwinder about the DWARF pseudo-register defined by GCC for AArch64 to hold the return address where the signal trampoline will resume.
Revision 1.34 / (download) - annotate - [select for diffs], Sun Nov 21 23:34:44 2021 UTC (14 months, 2 weeks ago) by thorpej
Branch: MAIN
Changes since 1.33: +4 -1
lines
Diff to previous 1.33 (colored)
Teach the LLVM-derived unwinder about the alternate DWARF pseudo-register that GCC defines for the PC / return address. This is simply an alias for the same internal PC register number.
Revision 1.33 / (download) - annotate - [select for diffs], Sun Nov 21 21:15:17 2021 UTC (14 months, 2 weeks ago) by thorpej
Branch: MAIN
Changes since 1.32: +43 -5
lines
Diff to previous 1.32 (colored)
Teach the LLVM-derived unwinder about the DWARF pseudo-register defined by GCC for PPC32 to hold the return address where the signal trampoline will resume, as well as for the CTR and XER registers.
Revision 1.32 / (download) - annotate - [select for diffs], Sun Nov 21 10:53:01 2021 UTC (14 months, 2 weeks ago) by skrll
Branch: MAIN
Changes since 1.31: +1 -1
lines
Diff to previous 1.31 (colored)
Add parentheses
Revision 1.31 / (download) - annotate - [select for diffs], Sat Nov 20 19:06:21 2021 UTC (14 months, 2 weeks ago) by thorpej
Branch: MAIN
Changes since 1.30: +15 -5
lines
Diff to previous 1.30 (colored)
Teach the LLVM-derived unwinder about the DWARF pseudo-register defined by GCC for Alpha to hold the return address where the signal trampoline will resume.
Revision 1.30 / (download) - annotate - [select for diffs], Sat Nov 20 18:19:18 2021 UTC (14 months, 2 weeks ago) by thorpej
Branch: MAIN
Changes since 1.29: +24 -6
lines
Diff to previous 1.29 (colored)
- Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined by GCC for MIPS64 to hold the MDHI and MDLO registers, as well as the return address where the signal trampoline will resume. - In the MIPS64 validFloatVectorRegister(), compare against the internal register numbers, not the DWARF register numbers.
Revision 1.29 / (download) - annotate - [select for diffs], Thu Nov 18 04:20:11 2021 UTC (14 months, 2 weeks ago) by thorpej
Branch: MAIN
Changes since 1.28: +24 -6
lines
Diff to previous 1.28 (colored)
- Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined by GCC for MIPS to hold the MDHI and MDLO registers, as well as the return address where the signal trampoline will resume. XXX Same treatment is needed for MIPS64, but not done as part of this commit. - In the MIPS validFloatVectorRegister(), compare against the internal register numbers, not the DWARF register numbers.
Revision 1.21.4.1 / (download) - annotate - [select for diffs], Thu Jun 17 04:46:34 2021 UTC (19 months, 2 weeks ago) by thorpej
Branch: thorpej-i2c-spi-conf
Changes since 1.21: +47 -22
lines
Diff to previous 1.21 (colored) next main 1.22 (colored)
Sync w/ HEAD.
Revision 1.21.6.1 / (download) - annotate - [select for diffs], Mon May 31 22:15:21 2021 UTC (20 months ago) by cjep
Branch: cjep_staticlib_x
Changes since 1.21: +44 -22
lines
Diff to previous 1.21 (colored) next main 1.22 (colored)
sync with head
Revision 1.28 / (download) - annotate - [select for diffs], Mon May 31 21:31:33 2021 UTC (20 months ago) by rin
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base,
thorpej-i2c-spi-conf2,
thorpej-i2c-spi-conf-base,
thorpej-futex2-base,
thorpej-futex2,
thorpej-cfargs2-base,
thorpej-cfargs2,
cjep_sun2x-base1,
cjep_sun2x-base,
cjep_sun2x
Changes since 1.27: +10 -7
lines
Diff to previous 1.27 (colored)
PR toolchain/55837 Stop using enum for flags, as per request from joerg. #define constants and #undef after use.
Revision 1.27 / (download) - annotate - [select for diffs], Mon May 31 12:12:24 2021 UTC (20 months ago) by rin
Branch: MAIN
CVS Tags: cjep_staticlib_x-base1
Changes since 1.26: +18 -2
lines
Diff to previous 1.26 (colored)
PR toolchain/55837 Bump LAST_REGISTER and LAST_RESTORE_REG to REGNO_ARM32_S31 for arm. There are two numbering schemes for VFPv2 registers: s0-s31 and d0-d15. The former is used by GCC, and the latter is by LLVM. Since libunwind was derived from LLVM, it has never supported the former. This results in crashes for GCC-compiled binaries in exception handler of C++, if it encounters VFPv2 registers when unwinding frames. This commit adds support for s0-s31 numbering to libunwind. I choose an implementation in which VFPv2 registers are ``double-counted'' as s0-s31 AND d0-d15. This does not cause real problems, since the former is only used by GCC, and the later is by LLVM. That is, different numbering schemes cannot appear in a same frame. To make sure, assertions are added in order to check this. I've confirmed that no regression for ATF both for GCC- and LLVM-compiled userlands.
Revision 1.26 / (download) - annotate - [select for diffs], Mon May 31 11:57:28 2021 UTC (20 months ago) by rin
Branch: MAIN
Changes since 1.25: +11 -10
lines
Diff to previous 1.25 (colored)
PR toolchain/55837 Fix logic error in copyFloatVectorRegister() for arm; copy s0-s31 or d0-d31, not both.
Revision 1.25 / (download) - annotate - [select for diffs], Mon May 31 11:54:01 2021 UTC (20 months ago) by rin
Branch: MAIN
Changes since 1.24: +1 -1
lines
Diff to previous 1.24 (colored)
PR toolchain/55837 Fix pointer arithmetic when copying s0-s31 registers for arm.
Revision 1.24 / (download) - annotate - [select for diffs], Mon May 31 11:50:43 2021 UTC (20 months ago) by rin
Branch: MAIN
Changes since 1.23: +2 -2
lines
Diff to previous 1.23 (colored)
PR toolchain/55837 Fix DWARF/internal register numbers of s31 for arm.
Revision 1.23 / (download) - annotate - [select for diffs], Mon May 31 11:44:06 2021 UTC (20 months ago) by rin
Branch: MAIN
Changes since 1.22: +1 -0
lines
Diff to previous 1.22 (colored)
PR toolchain/55837 copyFloatVectorRegister(): Assert register number is valid to make sure.
Revision 1.22 / (download) - annotate - [select for diffs], Mon May 31 11:41:22 2021 UTC (20 months ago) by rin
Branch: MAIN
Changes since 1.21: +17 -13
lines
Diff to previous 1.21 (colored)
PR toolchain/55837 Misc style fixes for clarity: - Rename lazyVFP1() and lazyVFP3() to lazyVFPv2() and lazyVFPv3(), respectively. Note that VFPv1 was obsoleted and replaced by VFPv2. - Introduce enum for flags. - Add few comments. No functional changes.
Revision 1.20.18.1 / (download) - annotate - [select for diffs], Sat Apr 3 22:29:01 2021 UTC (22 months ago) by thorpej
Branch: thorpej-futex
Changes since 1.20: +5 -12
lines
Diff to previous 1.20 (colored) next main 1.21 (colored)
Sync with HEAD.
Revision 1.21 / (download) - annotate - [select for diffs], Tue Feb 23 15:09:27 2021 UTC (23 months, 1 week ago) by joerg
Branch: MAIN
CVS Tags: thorpej-futex-base,
thorpej-cfargs-base,
thorpej-cfargs,
cjep_staticlib_x-base
Branch point for: thorpej-i2c-spi-conf,
cjep_staticlib_x
Changes since 1.20: +5 -12
lines
Diff to previous 1.20 (colored)
Redo the aarch64 support in libunwind. This included a number of bugs starting from returning the wrong value from the constructor to completely bogus offset computations. Drop the ELR support for now.
Revision 1.17.4.3 / (download) - annotate - [select for diffs], Sun Dec 3 11:38:47 2017 UTC (5 years, 2 months ago) by jdolecek
Branch: tls-maxphys
Changes since 1.17.4.2: +111 -8
lines
Diff to previous 1.17.4.2 (colored) to branchpoint 1.17 (colored) next main 1.18 (colored)
update from HEAD
Revision 1.19.2.1 / (download) - annotate - [select for diffs], Mon Aug 28 17:53:08 2017 UTC (5 years, 5 months ago) by skrll
Branch: nick-nhusb
Changes since 1.19: +26 -7
lines
Diff to previous 1.19 (colored) next main 1.20 (colored)
Sync with HEAD
Revision 1.19.12.1 / (download) - annotate - [select for diffs], Tue Jul 25 01:38:42 2017 UTC (5 years, 6 months ago) by snj
Branch: netbsd-8
CVS Tags: netbsd-8-2-RELEASE,
netbsd-8-1-RELEASE,
netbsd-8-1-RC1,
netbsd-8-0-RELEASE,
netbsd-8-0-RC2,
netbsd-8-0-RC1,
matt-nb8-mediatek-base,
matt-nb8-mediatek
Changes since 1.19: +26 -7
lines
Diff to previous 1.19 (colored) next main 1.20 (colored)
Pull up following revision(s) (requested by joerg in ticket #134): sys/lib/libunwind/Registers.hpp: revision 1.20 GCC 5.3 likes to emit unwind data with float registers, i.e. register halfs. Compensate.
Revision 1.20 / (download) - annotate - [select for diffs], Thu Jul 13 15:13:19 2017 UTC (5 years, 6 months ago) by joerg
Branch: MAIN
CVS Tags: tls-maxphys-base-20171202,
phil-wifi-base,
phil-wifi-20200421,
phil-wifi-20200411,
phil-wifi-20200406,
phil-wifi-20191119,
phil-wifi-20190609,
phil-wifi,
pgoyette-compat-merge-20190127,
pgoyette-compat-base,
pgoyette-compat-20190127,
pgoyette-compat-20190118,
pgoyette-compat-1226,
pgoyette-compat-1126,
pgoyette-compat-1020,
pgoyette-compat-0930,
pgoyette-compat-0906,
pgoyette-compat-0728,
pgoyette-compat-0625,
pgoyette-compat-0521,
pgoyette-compat-0502,
pgoyette-compat-0422,
pgoyette-compat-0415,
pgoyette-compat-0407,
pgoyette-compat-0330,
pgoyette-compat-0322,
pgoyette-compat-0315,
pgoyette-compat,
perseant-stdc-iso10646-base,
perseant-stdc-iso10646,
nick-nhusb-base-20170825,
netbsd-9-base,
netbsd-9-3-RELEASE,
netbsd-9-2-RELEASE,
netbsd-9-1-RELEASE,
netbsd-9-0-RELEASE,
netbsd-9-0-RC2,
netbsd-9-0-RC1,
netbsd-9,
isaki-audio2-base,
isaki-audio2,
is-mlppp-base,
is-mlppp,
bouyer-xenpvh-base2,
bouyer-xenpvh-base1,
bouyer-xenpvh-base,
bouyer-xenpvh,
ad-namecache-base3,
ad-namecache-base2,
ad-namecache-base1,
ad-namecache-base,
ad-namecache
Branch point for: thorpej-futex
Changes since 1.19: +26 -7
lines
Diff to previous 1.19 (colored)
GCC 5.3 likes to emit unwind data with float registers, i.e. register halfs. Compensate.
Revision 1.19 / (download) - annotate - [select for diffs], Sat Sep 27 12:08:46 2014 UTC (8 years, 4 months ago) by joerg
Branch: MAIN
CVS Tags: prg-localcount2-base3,
prg-localcount2-base2,
prg-localcount2-base1,
prg-localcount2-base,
prg-localcount2,
pgoyette-localcount-base,
pgoyette-localcount-20170426,
pgoyette-localcount-20170320,
pgoyette-localcount-20170107,
pgoyette-localcount-20161104,
pgoyette-localcount-20160806,
pgoyette-localcount-20160726,
pgoyette-localcount,
nick-nhusb-base-20170204,
nick-nhusb-base-20161204,
nick-nhusb-base-20161004,
nick-nhusb-base-20160907,
nick-nhusb-base-20160529,
nick-nhusb-base-20160422,
nick-nhusb-base-20160319,
nick-nhusb-base-20151226,
nick-nhusb-base-20150921,
nick-nhusb-base-20150606,
nick-nhusb-base-20150406,
nick-nhusb-base,
netbsd-8-base,
localcount-20160914,
jdolecek-ncq-base,
jdolecek-ncq,
bouyer-socketcan-base1,
bouyer-socketcan-base,
bouyer-socketcan
Branch point for: nick-nhusb,
netbsd-8
Changes since 1.18: +16 -1
lines
Diff to previous 1.18 (colored)
Introduce a separate bit mask for the return address. Use it on HPPA.
Revision 1.18 / (download) - annotate - [select for diffs], Wed Sep 3 19:27:21 2014 UTC (8 years, 5 months ago) by matt
Branch: MAIN
Changes since 1.17: +69 -0
lines
Diff to previous 1.17 (colored)
Add OR1K support
Revision 1.17.4.2 / (download) - annotate - [select for diffs], Wed Aug 20 00:04:30 2014 UTC (8 years, 5 months ago) by tls
Branch: tls-maxphys
Changes since 1.17.4.1: +1058 -0
lines
Diff to previous 1.17.4.1 (colored) to branchpoint 1.17 (colored)
Rebase to HEAD as of a few days ago.
Revision 1.8.2.1 / (download) - annotate - [select for diffs], Sun Aug 10 06:56:02 2014 UTC (8 years, 5 months ago) by tls
Branch: tls-earlyentropy
Changes since 1.8: +468 -14
lines
Diff to previous 1.8 (colored) next main 1.9 (colored)
Rebase.
Revision 1.17.4.1, Sun Aug 10 05:57:31 2014 UTC (8 years, 5 months ago) by tls
Branch: tls-maxphys
Changes since 1.17: +0 -1058
lines
FILE REMOVED
file Registers.hpp was added on branch tls-maxphys on 2014-08-20 00:04:30 +0000
Revision 1.17 / (download) - annotate - [select for diffs], Sun Aug 10 05:57:31 2014 UTC (8 years, 5 months ago) by matt
Branch: MAIN
CVS Tags: tls-maxphys-base,
netbsd-7-nhusb-base-20170116,
netbsd-7-nhusb-base,
netbsd-7-nhusb,
netbsd-7-base,
netbsd-7-2-RELEASE,
netbsd-7-1-RELEASE,
netbsd-7-1-RC2,
netbsd-7-1-RC1,
netbsd-7-1-2-RELEASE,
netbsd-7-1-1-RELEASE,
netbsd-7-1,
netbsd-7-0-RELEASE,
netbsd-7-0-RC3,
netbsd-7-0-RC2,
netbsd-7-0-RC1,
netbsd-7-0-2-RELEASE,
netbsd-7-0-1-RELEASE,
netbsd-7-0,
netbsd-7
Branch point for: tls-maxphys
Changes since 1.16: +81 -0
lines
Diff to previous 1.16 (colored)
Changes to existing files to enable building AARCH64 userland. evbarm64-el This is clang only. While gcc4.8 supports aarch64, no netbsd support has been written for aarch64 with gcc4.8.
Revision 1.16.4.2 / (download) - annotate - [select for diffs], Thu May 22 11:41:05 2014 UTC (8 years, 8 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.16.4.1: +977 -0
lines
Diff to previous 1.16.4.1 (colored) to branchpoint 1.16 (colored) next main 1.17 (colored)
sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
Revision 1.16.2.2 / (download) - annotate - [select for diffs], Sun May 18 17:46:09 2014 UTC (8 years, 8 months ago) by rmind
Branch: rmind-smpnet
Changes since 1.16.2.1: +977 -0
lines
Diff to previous 1.16.2.1 (colored) to branchpoint 1.16 (colored) next main 1.17 (colored)
sync with head
Revision 1.16.4.1, Sun May 11 02:07:35 2014 UTC (8 years, 8 months ago) by yamt
Branch: yamt-pagecache
Changes since 1.16: +0 -977
lines
FILE REMOVED
file Registers.hpp was added on branch yamt-pagecache on 2014-05-22 11:41:05 +0000
Revision 1.16.2.1, Sun May 11 02:07:35 2014 UTC (8 years, 8 months ago) by rmind
Branch: rmind-smpnet
Changes since 1.16: +0 -977
lines
FILE REMOVED
file Registers.hpp was added on branch rmind-smpnet on 2014-05-18 17:46:09 +0000
Revision 1.16 / (download) - annotate - [select for diffs], Sun May 11 02:07:35 2014 UTC (8 years, 8 months ago) by joerg
Branch: MAIN
CVS Tags: yamt-pagecache-base9,
tls-earlyentropy-base,
rmind-smpnet-nbase,
rmind-smpnet-base
Branch point for: yamt-pagecache,
rmind-smpnet
Changes since 1.15: +29 -8
lines
Diff to previous 1.15 (colored)
Support DWARFish unwind for ARM.
Revision 1.15 / (download) - annotate - [select for diffs], Sat Apr 26 23:17:38 2014 UTC (8 years, 9 months ago) by joerg
Branch: MAIN
Changes since 1.14: +0 -13
lines
Diff to previous 1.14 (colored)
Use the return address register from the CIE. Based on patch from Nick Kledzik.
Revision 1.14 / (download) - annotate - [select for diffs], Sat Apr 26 20:15:48 2014 UTC (8 years, 9 months ago) by joerg
Branch: MAIN
Changes since 1.13: +148 -0
lines
Diff to previous 1.13 (colored)
Add initial unwind support for MIPS and MIPS64.
Revision 1.13 / (download) - annotate - [select for diffs], Sat Apr 19 21:21:24 2014 UTC (8 years, 9 months ago) by joerg
Branch: MAIN
Changes since 1.12: +75 -0
lines
Diff to previous 1.12 (colored)
Basic unwind support for HPPA.
Revision 1.12 / (download) - annotate - [select for diffs], Tue Apr 15 18:40:34 2014 UTC (8 years, 9 months ago) by joerg
Branch: MAIN
Changes since 1.11: +69 -0
lines
Diff to previous 1.11 (colored)
Add basic Alpha support to libunwind.
Revision 1.11 / (download) - annotate - [select for diffs], Tue Apr 15 11:44:26 2014 UTC (8 years, 9 months ago) by joerg
Branch: MAIN
Changes since 1.10: +132 -0
lines
Diff to previous 1.10 (colored)
Add initial unwind support for SPARC/SPARC64.
Revision 1.10 / (download) - annotate - [select for diffs], Mon Apr 14 18:15:17 2014 UTC (8 years, 9 months ago) by joerg
Branch: MAIN
Changes since 1.9: +7 -0
lines
Diff to previous 1.9 (colored)
Some architectures like SPARC need to apply a fixed offset to the return address. Introduce such a constant.
Revision 1.9 / (download) - annotate - [select for diffs], Sun Apr 13 19:04:01 2014 UTC (8 years, 9 months ago) by joerg
Branch: MAIN
Changes since 1.8: +15 -0
lines
Diff to previous 1.8 (colored)
Move definition of what the native register layout is into Registers.hpp.
Revision 1.8 / (download) - annotate - [select for diffs], Wed Apr 2 22:34:29 2014 UTC (8 years, 10 months ago) by joerg
Branch: MAIN
Branch point for: tls-earlyentropy
Changes since 1.7: +64 -0
lines
Diff to previous 1.7 (colored)
Support SH3 in our unwinder.
Revision 1.7 / (download) - annotate - [select for diffs], Tue Mar 25 00:00:55 2014 UTC (8 years, 10 months ago) by joerg
Branch: MAIN
CVS Tags: riastradh-xf86-video-intel-2-7-1-pre-2-21-15
Changes since 1.6: +17 -4
lines
Diff to previous 1.6 (colored)
Save & restore FP registers.
Revision 1.6 / (download) - annotate - [select for diffs], Mon Mar 24 21:25:03 2014 UTC (8 years, 10 months ago) by joerg
Branch: MAIN
Changes since 1.5: +69 -0
lines
Diff to previous 1.5 (colored)
Add m68k support to our unwinder.
Revision 1.5 / (download) - annotate - [select for diffs], Tue Mar 18 13:08:15 2014 UTC (8 years, 10 months ago) by joerg
Branch: MAIN
Changes since 1.4: +64 -0
lines
Diff to previous 1.4 (colored)
Add basic unwind support for VAX. PSW handling and stack pointer after resume is still incomplete.
Revision 1.4 / (download) - annotate - [select for diffs], Wed Mar 12 00:01:12 2014 UTC (8 years, 10 months ago) by joerg
Branch: MAIN
CVS Tags: riastradh-drm2-base3
Changes since 1.3: +18 -11
lines
Diff to previous 1.3 (colored)
Add a dummy element as explicit padding for PPC32. Fix DWARF enumeration to match the values created by GCC. Fix DWARFish -> index conversion.
Revision 1.3 / (download) - annotate - [select for diffs], Tue Mar 11 23:57:42 2014 UTC (8 years, 10 months ago) by joerg
Branch: MAIN
Changes since 1.2: +8 -8
lines
Diff to previous 1.2 (colored)
Rename IP_PSEUDO_REG to RETURN_REG. Fix PPC value. Sort.
Revision 1.2 / (download) - annotate - [select for diffs], Wed Jan 29 06:59:53 2014 UTC (9 years ago) by matt
Branch: MAIN
Changes since 1.1: +72 -0
lines
Diff to previous 1.1 (colored)
Add support for non-EABI (DWARF) ARM exception handling.
Revision 1.1 / (download) - annotate - [select for diffs], Mon Oct 14 01:14:57 2013 UTC (9 years, 3 months ago) by joerg
Branch: MAIN
Add a heavily modified version of Apple's libunwind as released under MIT license in libc++abi. At the moment, only x86 support is tested.