CVS log for src/sys/lib/libunwind/Registers.hpp

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libunwind: Drop unused/wrong reg_t typedef for alpha

Fix editing mishap, should fix the build

Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined
by GCC for HPPA to hold the return address where the signal trampoline
will resume.  XXX Same treatment is needed for HPPA64, but not done as
part of this commit.

Thanks to thorpej for help with this. (ages ago)

Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined
by GCC for SuperH for GBR, MACH, MACL, and SR.

Gah, fix two typos.

Teach the LLVM-derived unwinder about the DWARF pseudo-register defined
by GCC for AArch64 to hold the return address where the signal trampoline
will resume.

Teach the LLVM-derived unwinder about the alternate DWARF pseudo-register
that GCC defines for the PC / return address.  This is simply an alias for
the same internal PC register number.

Teach the LLVM-derived unwinder about the DWARF pseudo-register defined
by GCC for PPC32 to hold the return address where the signal trampoline
will resume, as well as for the CTR and XER registers.

Add parentheses

Teach the LLVM-derived unwinder about the DWARF pseudo-register defined
by GCC for Alpha to hold the return address where the signal trampoline
will resume.

- Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined
  by GCC for MIPS64 to hold the MDHI and MDLO registers, as well as the return
  address where the signal trampoline will resume.
- In the MIPS64 validFloatVectorRegister(), compare against the internal
  register numbers, not the DWARF register numbers.

- Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined
  by GCC for MIPS to hold the MDHI and MDLO registers, as well as the return
  address where the signal trampoline will resume.  XXX Same treatment is
  needed for MIPS64, but not done as part of this commit.
- In the MIPS validFloatVectorRegister(), compare against the internal
  register numbers, not the DWARF register numbers.

Sync w/ HEAD.

sync with head

PR toolchain/55837

Stop using enum for flags, as per request from joerg.

#define constants and #undef after use.

PR toolchain/55837

Bump LAST_REGISTER and LAST_RESTORE_REG to REGNO_ARM32_S31 for arm.

There are two numbering schemes for VFPv2 registers: s0-s31 and d0-d15.
The former is used by GCC, and the latter is by LLVM. Since libunwind was
derived from LLVM, it has never supported the former. This results in
crashes for GCC-compiled binaries in exception handler of C++, if it
encounters VFPv2 registers when unwinding frames.

This commit adds support for s0-s31 numbering to libunwind. I choose an
implementation in which VFPv2 registers are ``double-counted'' as s0-s31
AND d0-d15. This does not cause real problems, since the former is only
used by GCC, and the later is by LLVM. That is, different numbering
schemes cannot appear in a same frame. To make sure, assertions are added
in order to check this.

I've confirmed that no regression for ATF both for GCC- and LLVM-compiled
userlands.

PR toolchain/55837

Fix logic error in copyFloatVectorRegister() for arm; copy s0-s31 or
d0-d31, not both.

PR toolchain/55837

Fix pointer arithmetic when copying s0-s31 registers for arm.

PR toolchain/55837

Fix DWARF/internal register numbers of s31 for arm.

PR toolchain/55837

copyFloatVectorRegister(): Assert register number is valid to make sure.

PR toolchain/55837

Misc style fixes for clarity:

- Rename lazyVFP1() and lazyVFP3() to lazyVFPv2() and lazyVFPv3(),
  respectively. Note that VFPv1 was obsoleted and replaced by VFPv2.

- Introduce enum for flags.

- Add few comments.

No functional changes.

Sync with HEAD.

Redo the aarch64 support in libunwind. This included a number of bugs
starting from returning the wrong value from the constructor to
completely bogus offset computations. Drop the ELR support for now.

update from HEAD

Sync with HEAD

Pull up following revision(s) (requested by joerg in ticket #134):
	sys/lib/libunwind/Registers.hpp: revision 1.20
GCC 5.3 likes to emit unwind data with float registers, i.e. register
halfs. Compensate.

GCC 5.3 likes to emit unwind data with float registers, i.e. register
halfs. Compensate.

Introduce a separate bit mask for the return address. Use it on HPPA.

Add OR1K support

Rebase to HEAD as of a few days ago.

Rebase.

file Registers.hpp was added on branch tls-maxphys on 2014-08-20 00:04:30 +0000

Changes to existing files to enable building AARCH64 userland.
evbarm64-el
This is clang only.  While gcc4.8 supports aarch64, no netbsd support has
been written for aarch64 with gcc4.8.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

file Registers.hpp was added on branch yamt-pagecache on 2014-05-22 11:41:05 +0000

file Registers.hpp was added on branch rmind-smpnet on 2014-05-18 17:46:09 +0000

Support DWARFish unwind for ARM.

Use the return address register from the CIE. Based on patch from Nick
Kledzik.

Add initial unwind support for MIPS and MIPS64.

Basic unwind support for HPPA.

Add basic Alpha support to libunwind.

Add initial unwind support for SPARC/SPARC64.

Some architectures like SPARC need to apply a fixed offset to the return
address. Introduce such a constant.

Move definition of what the native register layout is into
Registers.hpp.

Support SH3 in our unwinder.

Save & restore FP registers.

Add m68k support to our unwinder.

Add basic unwind support for VAX. PSW handling and stack pointer after
resume is still incomplete.

Add a dummy element as explicit padding for PPC32. Fix DWARF enumeration
to match the values created by GCC. Fix DWARFish -> index conversion.

Rename IP_PSEUDO_REG to RETURN_REG. Fix PPC value. Sort.

Add support for non-EABI (DWARF) ARM exception handling.

Add a heavily modified version of Apple's libunwind as released under
MIT license in libc++abi. At the moment, only x86 support is tested.