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Revision 1.1, Sun Nov 7 16:49:56 2021 UTC (2 years, 5 months ago) by jmcneill
Branch point for: MAIN 

Initial revision

/*	$NetBSD: pinctrl-zynqmp.h,v 1.1 2021/11/07 16:49:56 jmcneill Exp $	*/

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * MIO pin configuration defines for Xilinx ZynqMP
 *
 * Copyright (C) 2020 Xilinx, Inc.
 */

#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
#define _DT_BINDINGS_PINCTRL_ZYNQMP_H

/* Bit value for different voltage levels */
#define IO_STANDARD_LVCMOS33	0
#define IO_STANDARD_LVCMOS18	1

/* Bit values for Slew Rates */
#define SLEW_RATE_FAST		0
#define SLEW_RATE_SLOW		1

#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */