version 1.1.1.1.2.1, 2018/04/28 18:25:53 |
version 1.1.1.1.2.2, 2018/05/02 07:20:21 |
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/* $NetBSD$ */ |
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
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/* |
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* Meson-AXG clock tree IDs |
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* |
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved. |
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*/ |
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#ifndef __AXG_CLKC_H |
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#define __AXG_CLKC_H |
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#define CLKID_SYS_PLL 0 |
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#define CLKID_FIXED_PLL 1 |
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#define CLKID_FCLK_DIV2 2 |
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#define CLKID_FCLK_DIV3 3 |
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#define CLKID_FCLK_DIV4 4 |
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#define CLKID_FCLK_DIV5 5 |
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#define CLKID_FCLK_DIV7 6 |
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#define CLKID_GP0_PLL 7 |
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#define CLKID_CLK81 10 |
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#define CLKID_MPLL0 11 |
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#define CLKID_MPLL1 12 |
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#define CLKID_MPLL2 13 |
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#define CLKID_MPLL3 14 |
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#define CLKID_DDR 15 |
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#define CLKID_AUDIO_LOCKER 16 |
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#define CLKID_MIPI_DSI_HOST 17 |
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#define CLKID_ISA 18 |
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#define CLKID_PL301 19 |
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#define CLKID_PERIPHS 20 |
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#define CLKID_SPICC0 21 |
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#define CLKID_I2C 22 |
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#define CLKID_RNG0 23 |
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#define CLKID_UART0 24 |
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#define CLKID_MIPI_DSI_PHY 25 |
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#define CLKID_SPICC1 26 |
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#define CLKID_PCIE_A 27 |
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#define CLKID_PCIE_B 28 |
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#define CLKID_HIU_IFACE 29 |
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#define CLKID_ASSIST_MISC 30 |
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#define CLKID_SD_EMMC_B 31 |
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#define CLKID_SD_EMMC_C 32 |
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#define CLKID_DMA 33 |
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#define CLKID_SPI 34 |
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#define CLKID_AUDIO 35 |
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#define CLKID_ETH 36 |
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#define CLKID_UART1 37 |
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#define CLKID_G2D 38 |
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#define CLKID_USB0 39 |
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#define CLKID_USB1 40 |
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#define CLKID_RESET 41 |
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#define CLKID_USB 42 |
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#define CLKID_AHB_ARB0 43 |
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#define CLKID_EFUSE 44 |
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#define CLKID_BOOT_ROM 45 |
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#define CLKID_AHB_DATA_BUS 46 |
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#define CLKID_AHB_CTRL_BUS 47 |
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#define CLKID_USB1_DDR_BRIDGE 48 |
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#define CLKID_USB0_DDR_BRIDGE 49 |
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#define CLKID_MMC_PCLK 50 |
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#define CLKID_VPU_INTR 51 |
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#define CLKID_SEC_AHB_AHB3_BRIDGE 52 |
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#define CLKID_GIC 53 |
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#define CLKID_AO_MEDIA_CPU 54 |
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#define CLKID_AO_AHB_SRAM 55 |
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#define CLKID_AO_AHB_BUS 56 |
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#define CLKID_AO_IFACE 57 |
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#define CLKID_AO_I2C 58 |
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#define CLKID_SD_EMMC_B_CLK0 59 |
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#define CLKID_SD_EMMC_C_CLK0 60 |
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#define CLKID_HIFI_PLL 69 |
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#endif /* __AXG_CLKC_H */ |