version 1.1.1.4, 2020/01/03 14:33:33 |
version 1.1.1.5, 2021/11/07 16:50:00 |
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#qca,ddr-wb-channel-cells = <1>; |
#qca,ddr-wb-channel-cells = <1>; |
}; |
}; |
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uart: uart@18020000 { |
uart: serial@18020000 { |
compatible = "qca,ar9330-uart"; |
compatible = "qca,ar9330-uart"; |
reg = <0x18020000 0x14>; |
reg = <0x18020000 0x14>; |
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clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; |
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; |
clock-names = "eth", "mdio"; |
clock-names = "eth", "mdio"; |
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phy-mode = "mii"; |
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phy-handle = <&phy_port4>; |
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status = "disabled"; |
status = "disabled"; |
}; |
}; |
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compatible = "qca,ar9330-eth"; |
compatible = "qca,ar9330-eth"; |
reg = <0x1a000000 0x200>; |
reg = <0x1a000000 0x200>; |
interrupts = <5>; |
interrupts = <5>; |
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resets = <&rst 13>, <&rst 23>; |
resets = <&rst 13>, <&rst 23>; |
reset-names = "mac", "mdio"; |
reset-names = "mac", "mdio"; |
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; |
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; |
clock-names = "eth", "mdio"; |
clock-names = "eth", "mdio"; |
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phy-mode = "gmii"; |
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status = "disabled"; |
status = "disabled"; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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pause; |
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}; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch10: switch@10 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "qca,ar9331-switch"; |
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reg = <0x10>; |
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resets = <&rst 8>; |
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reset-names = "switch"; |
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interrupt-parent = <&miscintc>; |
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interrupts = <12>; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch_port0: port@0 { |
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reg = <0x0>; |
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label = "cpu"; |
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ethernet = <ð1>; |
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phy-mode = "gmii"; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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pause; |
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}; |
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}; |
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switch_port1: port@1 { |
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reg = <0x1>; |
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phy-handle = <&phy_port0>; |
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phy-mode = "internal"; |
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status = "disabled"; |
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}; |
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switch_port2: port@2 { |
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reg = <0x2>; |
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phy-handle = <&phy_port1>; |
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phy-mode = "internal"; |
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status = "disabled"; |
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}; |
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switch_port3: port@3 { |
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reg = <0x3>; |
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phy-handle = <&phy_port2>; |
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phy-mode = "internal"; |
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status = "disabled"; |
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}; |
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switch_port4: port@4 { |
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reg = <0x4>; |
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phy-handle = <&phy_port3>; |
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phy-mode = "internal"; |
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status = "disabled"; |
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}; |
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}; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupt-parent = <&switch10>; |
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phy_port0: phy@0 { |
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reg = <0x0>; |
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interrupts = <0>; |
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status = "disabled"; |
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}; |
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phy_port1: phy@1 { |
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reg = <0x1>; |
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interrupts = <0>; |
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status = "disabled"; |
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}; |
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phy_port2: phy@2 { |
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reg = <0x2>; |
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interrupts = <0>; |
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status = "disabled"; |
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}; |
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phy_port3: phy@3 { |
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reg = <0x3>; |
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interrupts = <0>; |
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status = "disabled"; |
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}; |
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phy_port4: phy@4 { |
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reg = <0x4>; |
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interrupts = <0>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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}; |
}; |
}; |
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usb: usb@1b000100 { |
usb: usb@1b000100 { |