Annotation of src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a77995.dtsi, Revision 1.1.1.6
1.1.1.5 jmcneill 1: // SPDX-License-Identifier: GPL-2.0
1.1 jmcneill 2: /*
1.1.1.5 jmcneill 3: * Device Tree Source for the R-Car D3 (R8A77995) SoC
1.1 jmcneill 4: *
5: * Copyright (C) 2016 Renesas Electronics Corp.
6: * Copyright (C) 2017 Glider bvba
7: */
8:
1.1.1.2 jmcneill 9: #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
1.1 jmcneill 10: #include <dt-bindings/interrupt-controller/arm-gic.h>
1.1.1.2 jmcneill 11: #include <dt-bindings/power/r8a77995-sysc.h>
1.1 jmcneill 12:
13: / {
14: compatible = "renesas,r8a77995";
15: #address-cells = <2>;
16: #size-cells = <2>;
17:
1.1.1.4 jmcneill 18: /* External CAN clock - to be overridden by boards that provide it */
19: can_clk: can {
20: compatible = "fixed-clock";
21: #clock-cells = <0>;
22: clock-frequency = <0>;
1.1 jmcneill 23: };
24:
25: cpus {
26: #address-cells = <1>;
27: #size-cells = <0>;
28:
29: a53_0: cpu@0 {
1.1.1.6 ! jmcneill 30: compatible = "arm,cortex-a53";
1.1 jmcneill 31: reg = <0x0>;
32: device_type = "cpu";
1.1.1.2 jmcneill 33: power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
1.1 jmcneill 34: next-level-cache = <&L2_CA53>;
35: enable-method = "psci";
36: };
37:
38: L2_CA53: cache-controller-1 {
39: compatible = "cache";
1.1.1.2 jmcneill 40: power-domains = <&sysc R8A77995_PD_CA53_SCU>;
1.1 jmcneill 41: cache-unified;
42: cache-level = <2>;
43: };
44: };
45:
46: extal_clk: extal {
47: compatible = "fixed-clock";
48: #clock-cells = <0>;
49: /* This value must be overridden by the board */
50: clock-frequency = <0>;
51: };
52:
1.1.1.3 jmcneill 53: pmu_a53 {
54: compatible = "arm,cortex-a53-pmu";
55: interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
56: };
57:
1.1.1.4 jmcneill 58: psci {
59: compatible = "arm,psci-1.0", "arm,psci-0.2";
60: method = "smc";
61: };
62:
1.1 jmcneill 63: scif_clk: scif {
64: compatible = "fixed-clock";
65: #clock-cells = <0>;
66: clock-frequency = <0>;
67: };
68:
69: soc {
70: compatible = "simple-bus";
71: interrupt-parent = <&gic>;
72: #address-cells = <2>;
73: #size-cells = <2>;
74: ranges;
75:
76: rwdt: watchdog@e6020000 {
77: compatible = "renesas,r8a77995-wdt",
78: "renesas,rcar-gen3-wdt";
79: reg = <0 0xe6020000 0 0x0c>;
80: clocks = <&cpg CPG_MOD 402>;
1.1.1.2 jmcneill 81: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1 jmcneill 82: resets = <&cpg 402>;
83: status = "disabled";
84: };
85:
1.1.1.4 jmcneill 86: gpio0: gpio@e6050000 {
87: compatible = "renesas,gpio-r8a77995",
1.1.1.5 jmcneill 88: "renesas,rcar-gen3-gpio";
1.1.1.4 jmcneill 89: reg = <0 0xe6050000 0 0x50>;
90: interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
91: #gpio-cells = <2>;
92: gpio-controller;
93: gpio-ranges = <&pfc 0 0 9>;
94: #interrupt-cells = <2>;
95: interrupt-controller;
96: clocks = <&cpg CPG_MOD 912>;
97: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
98: resets = <&cpg 912>;
1.1 jmcneill 99: };
100:
1.1.1.4 jmcneill 101: gpio1: gpio@e6051000 {
102: compatible = "renesas,gpio-r8a77995",
1.1.1.5 jmcneill 103: "renesas,rcar-gen3-gpio";
1.1.1.4 jmcneill 104: reg = <0 0xe6051000 0 0x50>;
105: interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
106: #gpio-cells = <2>;
107: gpio-controller;
108: gpio-ranges = <&pfc 0 32 32>;
109: #interrupt-cells = <2>;
110: interrupt-controller;
111: clocks = <&cpg CPG_MOD 911>;
112: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
113: resets = <&cpg 911>;
1.1.1.3 jmcneill 114: };
115:
1.1.1.4 jmcneill 116: gpio2: gpio@e6052000 {
117: compatible = "renesas,gpio-r8a77995",
1.1.1.5 jmcneill 118: "renesas,rcar-gen3-gpio";
1.1.1.4 jmcneill 119: reg = <0 0xe6052000 0 0x50>;
120: interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
121: #gpio-cells = <2>;
122: gpio-controller;
123: gpio-ranges = <&pfc 0 64 32>;
124: #interrupt-cells = <2>;
125: interrupt-controller;
126: clocks = <&cpg CPG_MOD 910>;
127: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
128: resets = <&cpg 910>;
1.1.1.3 jmcneill 129: };
130:
1.1.1.4 jmcneill 131: gpio3: gpio@e6053000 {
132: compatible = "renesas,gpio-r8a77995",
1.1.1.5 jmcneill 133: "renesas,rcar-gen3-gpio";
1.1.1.4 jmcneill 134: reg = <0 0xe6053000 0 0x50>;
135: interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
136: #gpio-cells = <2>;
137: gpio-controller;
138: gpio-ranges = <&pfc 0 96 10>;
139: #interrupt-cells = <2>;
140: interrupt-controller;
141: clocks = <&cpg CPG_MOD 909>;
142: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
143: resets = <&cpg 909>;
1.1.1.3 jmcneill 144: };
145:
1.1.1.4 jmcneill 146: gpio4: gpio@e6054000 {
147: compatible = "renesas,gpio-r8a77995",
1.1.1.5 jmcneill 148: "renesas,rcar-gen3-gpio";
1.1.1.4 jmcneill 149: reg = <0 0xe6054000 0 0x50>;
150: interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
151: #gpio-cells = <2>;
152: gpio-controller;
153: gpio-ranges = <&pfc 0 128 32>;
154: #interrupt-cells = <2>;
155: interrupt-controller;
156: clocks = <&cpg CPG_MOD 908>;
157: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
158: resets = <&cpg 908>;
1.1.1.3 jmcneill 159: };
160:
1.1.1.4 jmcneill 161: gpio5: gpio@e6055000 {
162: compatible = "renesas,gpio-r8a77995",
1.1.1.5 jmcneill 163: "renesas,rcar-gen3-gpio";
1.1.1.4 jmcneill 164: reg = <0 0xe6055000 0 0x50>;
165: interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
166: #gpio-cells = <2>;
167: gpio-controller;
168: gpio-ranges = <&pfc 0 160 21>;
169: #interrupt-cells = <2>;
170: interrupt-controller;
171: clocks = <&cpg CPG_MOD 907>;
172: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
173: resets = <&cpg 907>;
1.1.1.3 jmcneill 174: };
175:
1.1.1.4 jmcneill 176: gpio6: gpio@e6055400 {
177: compatible = "renesas,gpio-r8a77995",
1.1.1.5 jmcneill 178: "renesas,rcar-gen3-gpio";
1.1.1.4 jmcneill 179: reg = <0 0xe6055400 0 0x50>;
180: interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
181: #gpio-cells = <2>;
182: gpio-controller;
183: gpio-ranges = <&pfc 0 192 14>;
184: #interrupt-cells = <2>;
185: interrupt-controller;
186: clocks = <&cpg CPG_MOD 906>;
187: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
188: resets = <&cpg 906>;
1.1.1.3 jmcneill 189: };
190:
1.1.1.4 jmcneill 191: pfc: pin-controller@e6060000 {
192: compatible = "renesas,pfc-r8a77995";
193: reg = <0 0xe6060000 0 0x508>;
1.1.1.3 jmcneill 194: };
195:
1.1 jmcneill 196: cpg: clock-controller@e6150000 {
197: compatible = "renesas,r8a77995-cpg-mssr";
198: reg = <0 0xe6150000 0 0x1000>;
199: clocks = <&extal_clk>;
200: clock-names = "extal";
201: #clock-cells = <2>;
202: #power-domain-cells = <0>;
203: #reset-cells = <1>;
204: };
205:
206: rst: reset-controller@e6160000 {
207: compatible = "renesas,r8a77995-rst";
208: reg = <0 0xe6160000 0 0x0200>;
209: };
210:
211: sysc: system-controller@e6180000 {
212: compatible = "renesas,r8a77995-sysc";
213: reg = <0 0xe6180000 0 0x0400>;
214: #power-domain-cells = <1>;
215: };
216:
1.1.1.5 jmcneill 217: thermal: thermal@e6190000 {
218: compatible = "renesas,thermal-r8a77995";
219: reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
220: interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
221: <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
222: <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
223: clocks = <&cpg CPG_MOD 522>;
224: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
225: resets = <&cpg 522>;
226: #thermal-sensor-cells = <0>;
227: };
228:
1.1.1.2 jmcneill 229: intc_ex: interrupt-controller@e61c0000 {
230: compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
231: #interrupt-cells = <2>;
232: interrupt-controller;
233: reg = <0 0xe61c0000 0 0x200>;
234: interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
235: GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
236: GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
237: GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
238: GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
239: GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
240: clocks = <&cpg CPG_MOD 407>;
241: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
242: resets = <&cpg 407>;
243: };
244:
1.1.1.5 jmcneill 245: hscif0: serial@e6540000 {
246: compatible = "renesas,hscif-r8a77995",
247: "renesas,rcar-gen3-hscif",
248: "renesas,hscif";
249: reg = <0 0xe6540000 0 0x60>;
250: interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
251: clocks = <&cpg CPG_MOD 520>,
252: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
253: <&scif_clk>;
254: clock-names = "fck", "brg_int", "scif_clk";
255: dmas = <&dmac1 0x31>, <&dmac1 0x30>,
256: <&dmac2 0x31>, <&dmac2 0x30>;
257: dma-names = "tx", "rx", "tx", "rx";
258: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
259: resets = <&cpg 520>;
260: status = "disabled";
261: };
262:
263: hscif3: serial@e66a0000 {
264: compatible = "renesas,hscif-r8a77995",
265: "renesas,rcar-gen3-hscif",
266: "renesas,hscif";
267: reg = <0 0xe66a0000 0 0x60>;
268: interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
269: clocks = <&cpg CPG_MOD 517>,
270: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
271: <&scif_clk>;
272: clock-names = "fck", "brg_int", "scif_clk";
273: dmas = <&dmac0 0x37>, <&dmac0 0x36>;
274: dma-names = "tx", "rx";
275: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
276: resets = <&cpg 517>;
277: status = "disabled";
278: };
279:
1.1.1.4 jmcneill 280: i2c0: i2c@e6500000 {
281: #address-cells = <1>;
282: #size-cells = <0>;
283: compatible = "renesas,i2c-r8a77995",
284: "renesas,rcar-gen3-i2c";
285: reg = <0 0xe6500000 0 0x40>;
286: interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
287: clocks = <&cpg CPG_MOD 931>;
288: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
289: resets = <&cpg 931>;
290: dmas = <&dmac1 0x91>, <&dmac1 0x90>,
291: <&dmac2 0x91>, <&dmac2 0x90>;
292: dma-names = "tx", "rx", "tx", "rx";
293: i2c-scl-internal-delay-ns = <6>;
294: status = "disabled";
295: };
296:
297: i2c1: i2c@e6508000 {
298: #address-cells = <1>;
299: #size-cells = <0>;
300: compatible = "renesas,i2c-r8a77995",
301: "renesas,rcar-gen3-i2c";
302: reg = <0 0xe6508000 0 0x40>;
303: interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
304: clocks = <&cpg CPG_MOD 930>;
305: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
306: resets = <&cpg 930>;
307: dmas = <&dmac1 0x93>, <&dmac1 0x92>,
308: <&dmac2 0x93>, <&dmac2 0x92>;
309: dma-names = "tx", "rx", "tx", "rx";
310: i2c-scl-internal-delay-ns = <6>;
311: status = "disabled";
312: };
313:
314: i2c2: i2c@e6510000 {
315: #address-cells = <1>;
316: #size-cells = <0>;
317: compatible = "renesas,i2c-r8a77995",
318: "renesas,rcar-gen3-i2c";
319: reg = <0 0xe6510000 0 0x40>;
320: interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
321: clocks = <&cpg CPG_MOD 929>;
322: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
323: resets = <&cpg 929>;
324: dmas = <&dmac1 0x95>, <&dmac1 0x94>,
325: <&dmac2 0x95>, <&dmac2 0x94>;
326: dma-names = "tx", "rx", "tx", "rx";
327: i2c-scl-internal-delay-ns = <6>;
328: status = "disabled";
329: };
330:
331: i2c3: i2c@e66d0000 {
332: #address-cells = <1>;
333: #size-cells = <0>;
334: compatible = "renesas,i2c-r8a77995",
335: "renesas,rcar-gen3-i2c";
336: reg = <0 0xe66d0000 0 0x40>;
337: interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
338: clocks = <&cpg CPG_MOD 928>;
339: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
340: resets = <&cpg 928>;
341: dmas = <&dmac0 0x97>, <&dmac0 0x96>;
342: dma-names = "tx", "rx";
343: i2c-scl-internal-delay-ns = <6>;
344: status = "disabled";
345: };
346:
1.1.1.6 ! jmcneill 347: hsusb: usb@e6590000 {
! 348: compatible = "renesas,usbhs-r8a77995",
! 349: "renesas,rcar-gen3-usbhs";
! 350: reg = <0 0xe6590000 0 0x200>;
! 351: interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
! 352: clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
! 353: dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
! 354: <&usb_dmac1 0>, <&usb_dmac1 1>;
! 355: dma-names = "ch0", "ch1", "ch2", "ch3";
! 356: renesas,buswait = <11>;
! 357: phys = <&usb2_phy0>;
! 358: phy-names = "usb";
! 359: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
! 360: resets = <&cpg 704>, <&cpg 703>;
! 361: status = "disabled";
! 362: };
! 363:
! 364: usb_dmac0: dma-controller@e65a0000 {
! 365: compatible = "renesas,r8a77995-usb-dmac",
! 366: "renesas,usb-dmac";
! 367: reg = <0 0xe65a0000 0 0x100>;
! 368: interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
! 369: GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
! 370: interrupt-names = "ch0", "ch1";
! 371: clocks = <&cpg CPG_MOD 330>;
! 372: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
! 373: resets = <&cpg 330>;
! 374: #dma-cells = <1>;
! 375: dma-channels = <2>;
! 376: };
! 377:
! 378: usb_dmac1: dma-controller@e65b0000 {
! 379: compatible = "renesas,r8a77995-usb-dmac",
! 380: "renesas,usb-dmac";
! 381: reg = <0 0xe65b0000 0 0x100>;
! 382: interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
! 383: GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
! 384: interrupt-names = "ch0", "ch1";
! 385: clocks = <&cpg CPG_MOD 331>;
! 386: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
! 387: resets = <&cpg 331>;
! 388: #dma-cells = <1>;
! 389: dma-channels = <2>;
! 390: };
! 391:
1.1.1.4 jmcneill 392: canfd: can@e66c0000 {
393: compatible = "renesas,r8a77995-canfd",
394: "renesas,rcar-gen3-canfd";
395: reg = <0 0xe66c0000 0 0x8000>;
396: interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
397: <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
398: clocks = <&cpg CPG_MOD 914>,
399: <&cpg CPG_CORE R8A77995_CLK_CANFD>,
400: <&can_clk>;
401: clock-names = "fck", "canfd", "can_clk";
402: assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
403: assigned-clock-rates = <40000000>;
404: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
405: resets = <&cpg 914>;
406: status = "disabled";
407:
408: channel0 {
409: status = "disabled";
410: };
411:
412: channel1 {
413: status = "disabled";
414: };
415: };
416:
1.1.1.3 jmcneill 417: dmac0: dma-controller@e6700000 {
418: compatible = "renesas,dmac-r8a77995",
419: "renesas,rcar-dmac";
420: reg = <0 0xe6700000 0 0x10000>;
421: interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
422: GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
423: GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
424: GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
425: GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
426: GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
427: GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
428: GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
429: GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
430: interrupt-names = "error",
431: "ch0", "ch1", "ch2", "ch3",
432: "ch4", "ch5", "ch6", "ch7";
433: clocks = <&cpg CPG_MOD 219>;
434: clock-names = "fck";
435: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
436: resets = <&cpg 219>;
437: #dma-cells = <1>;
438: dma-channels = <8>;
1.1.1.5 jmcneill 439: iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
440: <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
441: <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
442: <&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
1.1.1.3 jmcneill 443: };
444:
445: dmac1: dma-controller@e7300000 {
446: compatible = "renesas,dmac-r8a77995",
447: "renesas,rcar-dmac";
448: reg = <0 0xe7300000 0 0x10000>;
449: interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
450: GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
451: GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
452: GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
453: GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
454: GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
455: GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
456: GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
457: GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
458: interrupt-names = "error",
459: "ch0", "ch1", "ch2", "ch3",
460: "ch4", "ch5", "ch6", "ch7";
461: clocks = <&cpg CPG_MOD 218>;
462: clock-names = "fck";
463: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
464: resets = <&cpg 218>;
465: #dma-cells = <1>;
466: dma-channels = <8>;
1.1.1.5 jmcneill 467: iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
468: <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
469: <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
470: <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
1.1.1.3 jmcneill 471: };
472:
473: dmac2: dma-controller@e7310000 {
474: compatible = "renesas,dmac-r8a77995",
475: "renesas,rcar-dmac";
476: reg = <0 0xe7310000 0 0x10000>;
477: interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
478: GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
479: GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
480: GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
481: GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
482: GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
483: GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
484: GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
485: GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
486: interrupt-names = "error",
487: "ch0", "ch1", "ch2", "ch3",
488: "ch4", "ch5", "ch6", "ch7";
489: clocks = <&cpg CPG_MOD 217>;
490: clock-names = "fck";
491: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
492: resets = <&cpg 217>;
493: #dma-cells = <1>;
494: dma-channels = <8>;
1.1.1.5 jmcneill 495: iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
496: <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
497: <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
498: <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
1.1.1.3 jmcneill 499: };
500:
1.1.1.4 jmcneill 501: ipmmu_ds0: mmu@e6740000 {
502: compatible = "renesas,ipmmu-r8a77995";
503: reg = <0 0xe6740000 0 0x1000>;
504: renesas,ipmmu-main = <&ipmmu_mm 0>;
1.1.1.5 jmcneill 505: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 506: #iommu-cells = <1>;
1.1.1.2 jmcneill 507: };
508:
1.1.1.4 jmcneill 509: ipmmu_ds1: mmu@e7740000 {
510: compatible = "renesas,ipmmu-r8a77995";
511: reg = <0 0xe7740000 0 0x1000>;
512: renesas,ipmmu-main = <&ipmmu_mm 1>;
1.1.1.5 jmcneill 513: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 514: #iommu-cells = <1>;
1.1.1.2 jmcneill 515: };
516:
1.1.1.4 jmcneill 517: ipmmu_hc: mmu@e6570000 {
518: compatible = "renesas,ipmmu-r8a77995";
519: reg = <0 0xe6570000 0 0x1000>;
520: renesas,ipmmu-main = <&ipmmu_mm 2>;
1.1.1.5 jmcneill 521: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 522: #iommu-cells = <1>;
1.1.1.2 jmcneill 523: };
524:
1.1.1.4 jmcneill 525: ipmmu_mm: mmu@e67b0000 {
526: compatible = "renesas,ipmmu-r8a77995";
527: reg = <0 0xe67b0000 0 0x1000>;
528: interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
529: <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1.1.1.5 jmcneill 530: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 531: #iommu-cells = <1>;
1.1.1.2 jmcneill 532: };
533:
1.1.1.4 jmcneill 534: ipmmu_mp: mmu@ec670000 {
535: compatible = "renesas,ipmmu-r8a77995";
536: reg = <0 0xec670000 0 0x1000>;
537: renesas,ipmmu-main = <&ipmmu_mm 4>;
1.1.1.5 jmcneill 538: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 539: #iommu-cells = <1>;
1.1.1.3 jmcneill 540: };
541:
1.1.1.4 jmcneill 542: ipmmu_pv0: mmu@fd800000 {
543: compatible = "renesas,ipmmu-r8a77995";
544: reg = <0 0xfd800000 0 0x1000>;
545: renesas,ipmmu-main = <&ipmmu_mm 6>;
1.1.1.5 jmcneill 546: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 547: #iommu-cells = <1>;
1.1.1.3 jmcneill 548: };
549:
1.1.1.4 jmcneill 550: ipmmu_rt: mmu@ffc80000 {
551: compatible = "renesas,ipmmu-r8a77995";
552: reg = <0 0xffc80000 0 0x1000>;
553: renesas,ipmmu-main = <&ipmmu_mm 10>;
1.1.1.5 jmcneill 554: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 555: #iommu-cells = <1>;
556: };
1.1.1.3 jmcneill 557:
1.1.1.4 jmcneill 558: ipmmu_vc0: mmu@fe6b0000 {
559: compatible = "renesas,ipmmu-r8a77995";
560: reg = <0 0xfe6b0000 0 0x1000>;
561: renesas,ipmmu-main = <&ipmmu_mm 12>;
1.1.1.5 jmcneill 562: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 563: #iommu-cells = <1>;
564: };
1.1.1.3 jmcneill 565:
1.1.1.4 jmcneill 566: ipmmu_vi0: mmu@febd0000 {
567: compatible = "renesas,ipmmu-r8a77995";
568: reg = <0 0xfebd0000 0 0x1000>;
569: renesas,ipmmu-main = <&ipmmu_mm 14>;
1.1.1.5 jmcneill 570: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 571: #iommu-cells = <1>;
572: };
573:
574: ipmmu_vp0: mmu@fe990000 {
575: compatible = "renesas,ipmmu-r8a77995";
576: reg = <0 0xfe990000 0 0x1000>;
577: renesas,ipmmu-main = <&ipmmu_mm 16>;
1.1.1.5 jmcneill 578: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 579: #iommu-cells = <1>;
1.1.1.3 jmcneill 580: };
581:
1.1.1.2 jmcneill 582: avb: ethernet@e6800000 {
583: compatible = "renesas,etheravb-r8a77995",
584: "renesas,etheravb-rcar-gen3";
1.1.1.3 jmcneill 585: reg = <0 0xe6800000 0 0x800>;
1.1.1.2 jmcneill 586: interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
587: <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
588: <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
589: <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
590: <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
591: <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
592: <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
593: <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
594: <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
595: <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
596: <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
597: <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
598: <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
599: <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
600: <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
601: <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
602: <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
603: <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
604: <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
605: <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
606: <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
607: <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
608: <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
609: <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
610: <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
611: interrupt-names = "ch0", "ch1", "ch2", "ch3",
612: "ch4", "ch5", "ch6", "ch7",
613: "ch8", "ch9", "ch10", "ch11",
614: "ch12", "ch13", "ch14", "ch15",
615: "ch16", "ch17", "ch18", "ch19",
616: "ch20", "ch21", "ch22", "ch23",
617: "ch24";
618: clocks = <&cpg CPG_MOD 812>;
619: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
620: resets = <&cpg 812>;
1.1.1.3 jmcneill 621: phy-mode = "rgmii";
622: iommus = <&ipmmu_ds0 16>;
1.1.1.2 jmcneill 623: #address-cells = <1>;
624: #size-cells = <0>;
625: status = "disabled";
626: };
627:
1.1.1.4 jmcneill 628: can0: can@e6c30000 {
629: compatible = "renesas,can-r8a77995",
630: "renesas,rcar-gen3-can";
631: reg = <0 0xe6c30000 0 0x1000>;
632: interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
633: clocks = <&cpg CPG_MOD 916>,
634: <&cpg CPG_CORE R8A77995_CLK_CANFD>,
635: <&can_clk>;
636: clock-names = "clkp1", "clkp2", "can_clk";
637: assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
638: assigned-clock-rates = <40000000>;
1.1.1.3 jmcneill 639: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 640: resets = <&cpg 916>;
1.1.1.3 jmcneill 641: status = "disabled";
642: };
643:
1.1.1.4 jmcneill 644: can1: can@e6c38000 {
645: compatible = "renesas,can-r8a77995",
646: "renesas,rcar-gen3-can";
647: reg = <0 0xe6c38000 0 0x1000>;
648: interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
649: clocks = <&cpg CPG_MOD 915>,
650: <&cpg CPG_CORE R8A77995_CLK_CANFD>,
651: <&can_clk>;
652: clock-names = "clkp1", "clkp2", "can_clk";
653: assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
654: assigned-clock-rates = <40000000>;
1.1.1.3 jmcneill 655: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 656: resets = <&cpg 915>;
1.1.1.3 jmcneill 657: status = "disabled";
658: };
659:
1.1.1.2 jmcneill 660: pwm0: pwm@e6e30000 {
661: compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
662: reg = <0 0xe6e30000 0 0x8>;
663: #pwm-cells = <2>;
664: clocks = <&cpg CPG_MOD 523>;
665: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
666: resets = <&cpg 523>;
667: status = "disabled";
668: };
669:
670: pwm1: pwm@e6e31000 {
671: compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
672: reg = <0 0xe6e31000 0 0x8>;
673: #pwm-cells = <2>;
674: clocks = <&cpg CPG_MOD 523>;
675: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
676: resets = <&cpg 523>;
677: status = "disabled";
678: };
679:
680: pwm2: pwm@e6e32000 {
681: compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
682: reg = <0 0xe6e32000 0 0x8>;
683: #pwm-cells = <2>;
684: clocks = <&cpg CPG_MOD 523>;
685: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
686: resets = <&cpg 523>;
687: status = "disabled";
688: };
689:
690: pwm3: pwm@e6e33000 {
691: compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
692: reg = <0 0xe6e33000 0 0x8>;
693: #pwm-cells = <2>;
694: clocks = <&cpg CPG_MOD 523>;
695: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
696: resets = <&cpg 523>;
697: status = "disabled";
698: };
699:
1.1.1.5 jmcneill 700: scif0: serial@e6e60000 {
701: compatible = "renesas,scif-r8a77995",
702: "renesas,rcar-gen3-scif", "renesas,scif";
703: reg = <0 0xe6e60000 0 64>;
704: interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
705: clocks = <&cpg CPG_MOD 207>,
706: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
707: <&scif_clk>;
708: clock-names = "fck", "brg_int", "scif_clk";
709: dmas = <&dmac1 0x51>, <&dmac1 0x50>,
710: <&dmac2 0x51>, <&dmac2 0x50>;
711: dma-names = "tx", "rx", "tx", "rx";
712: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
713: resets = <&cpg 207>;
714: status = "disabled";
715: };
716:
717: scif1: serial@e6e68000 {
718: compatible = "renesas,scif-r8a77995",
719: "renesas,rcar-gen3-scif", "renesas,scif";
720: reg = <0 0xe6e68000 0 64>;
721: interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
722: clocks = <&cpg CPG_MOD 206>,
723: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
724: <&scif_clk>;
725: clock-names = "fck", "brg_int", "scif_clk";
726: dmas = <&dmac1 0x53>, <&dmac1 0x52>,
727: <&dmac2 0x53>, <&dmac2 0x52>;
728: dma-names = "tx", "rx", "tx", "rx";
729: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
730: resets = <&cpg 206>;
731: status = "disabled";
732: };
733:
1.1.1.4 jmcneill 734: scif2: serial@e6e88000 {
735: compatible = "renesas,scif-r8a77995",
736: "renesas,rcar-gen3-scif", "renesas,scif";
737: reg = <0 0xe6e88000 0 64>;
738: interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
739: clocks = <&cpg CPG_MOD 310>,
740: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
741: <&scif_clk>;
742: clock-names = "fck", "brg_int", "scif_clk";
743: dmas = <&dmac1 0x13>, <&dmac1 0x12>,
744: <&dmac2 0x13>, <&dmac2 0x12>;
745: dma-names = "tx", "rx", "tx", "rx";
1.1.1.3 jmcneill 746: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.4 jmcneill 747: resets = <&cpg 310>;
1.1.1.3 jmcneill 748: status = "disabled";
749: };
750:
1.1.1.5 jmcneill 751: scif3: serial@e6c50000 {
752: compatible = "renesas,scif-r8a77995",
753: "renesas,rcar-gen3-scif", "renesas,scif";
754: reg = <0 0xe6c50000 0 64>;
755: interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
756: clocks = <&cpg CPG_MOD 204>,
757: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
758: <&scif_clk>;
759: clock-names = "fck", "brg_int", "scif_clk";
760: dmas = <&dmac0 0x57>, <&dmac0 0x56>;
761: dma-names = "tx", "rx";
762: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
763: resets = <&cpg 204>;
764: status = "disabled";
765: };
766:
767: scif4: serial@e6c40000 {
768: compatible = "renesas,scif-r8a77995",
769: "renesas,rcar-gen3-scif", "renesas,scif";
770: reg = <0 0xe6c40000 0 64>;
771: interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
772: clocks = <&cpg CPG_MOD 203>,
773: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
774: <&scif_clk>;
775: clock-names = "fck", "brg_int", "scif_clk";
776: dmas = <&dmac0 0x59>, <&dmac0 0x58>;
777: dma-names = "tx", "rx";
778: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
779: resets = <&cpg 203>;
780: status = "disabled";
781: };
782:
783: scif5: serial@e6f30000 {
784: compatible = "renesas,scif-r8a77995",
785: "renesas,rcar-gen3-scif", "renesas,scif";
786: reg = <0 0xe6f30000 0 64>;
787: interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
788: clocks = <&cpg CPG_MOD 202>,
789: <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
790: <&scif_clk>;
791: clock-names = "fck", "brg_int", "scif_clk";
792: dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
793: <&dmac2 0x5b>, <&dmac2 0x5a>;
794: dma-names = "tx", "rx", "tx", "rx";
795: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
796: resets = <&cpg 202>;
797: status = "disabled";
798: };
799:
800: msiof0: spi@e6e90000 {
801: compatible = "renesas,msiof-r8a77995",
802: "renesas,rcar-gen3-msiof";
803: reg = <0 0xe6e90000 0 0x64>;
804: interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
805: clocks = <&cpg CPG_MOD 211>;
806: dmas = <&dmac1 0x41>, <&dmac1 0x40>,
807: <&dmac2 0x41>, <&dmac2 0x40>;
808: dma-names = "tx", "rx", "tx", "rx";
809: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
810: resets = <&cpg 211>;
811: #address-cells = <1>;
812: #size-cells = <0>;
813: status = "disabled";
814: };
815:
816: msiof1: spi@e6ea0000 {
817: compatible = "renesas,msiof-r8a77995",
818: "renesas,rcar-gen3-msiof";
819: reg = <0 0xe6ea0000 0 0x64>;
820: interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
821: clocks = <&cpg CPG_MOD 210>;
822: dmas = <&dmac1 0x43>, <&dmac1 0x42>,
823: <&dmac2 0x43>, <&dmac2 0x42>;
824: dma-names = "tx", "rx", "tx", "rx";
825: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
826: resets = <&cpg 210>;
827: #address-cells = <1>;
828: #size-cells = <0>;
829: status = "disabled";
830: };
831:
832: msiof2: spi@e6c00000 {
833: compatible = "renesas,msiof-r8a77995",
834: "renesas,rcar-gen3-msiof";
835: reg = <0 0xe6c00000 0 0x64>;
836: interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
837: clocks = <&cpg CPG_MOD 209>;
838: dmas = <&dmac0 0x45>, <&dmac0 0x44>;
839: dma-names = "tx", "rx";
840: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
841: resets = <&cpg 209>;
842: #address-cells = <1>;
843: #size-cells = <0>;
844: status = "disabled";
845: };
846:
847: msiof3: spi@e6c10000 {
848: compatible = "renesas,msiof-r8a77995",
849: "renesas,rcar-gen3-msiof";
850: reg = <0 0xe6c10000 0 0x64>;
851: interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
852: clocks = <&cpg CPG_MOD 208>;
853: dmas = <&dmac0 0x47>, <&dmac0 0x46>;
854: dma-names = "tx", "rx";
855: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
856: resets = <&cpg 208>;
857: #address-cells = <1>;
858: #size-cells = <0>;
859: status = "disabled";
860: };
861:
1.1.1.4 jmcneill 862: vin4: video@e6ef4000 {
863: compatible = "renesas,vin-r8a77995";
864: reg = <0 0xe6ef4000 0 0x1000>;
865: interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
866: clocks = <&cpg CPG_MOD 807>;
867: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
868: resets = <&cpg 807>;
869: renesas,id = <4>;
870: status = "disabled";
871: };
872:
873: ohci0: usb@ee080000 {
874: compatible = "generic-ohci";
875: reg = <0 0xee080000 0 0x100>;
1.1.1.2 jmcneill 876: interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1.1.1.5 jmcneill 877: clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1.1.1.2 jmcneill 878: phys = <&usb2_phy0>;
879: phy-names = "usb";
880: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.5 jmcneill 881: resets = <&cpg 703>, <&cpg 704>;
1.1.1.2 jmcneill 882: status = "disabled";
883: };
884:
1.1.1.4 jmcneill 885: ehci0: usb@ee080100 {
886: compatible = "generic-ehci";
887: reg = <0 0xee080100 0 0x100>;
1.1.1.2 jmcneill 888: interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1.1.1.5 jmcneill 889: clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1.1.1.2 jmcneill 890: phys = <&usb2_phy0>;
891: phy-names = "usb";
1.1.1.4 jmcneill 892: companion = <&ohci0>;
1.1.1.2 jmcneill 893: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.5 jmcneill 894: resets = <&cpg 703>, <&cpg 704>;
1.1.1.2 jmcneill 895: status = "disabled";
896: };
897:
898: usb2_phy0: usb-phy@ee080200 {
899: compatible = "renesas,usb2-phy-r8a77995",
900: "renesas,rcar-gen3-usb2-phy";
901: reg = <0 0xee080200 0 0x700>;
902: interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1.1.1.5 jmcneill 903: clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1.1.1.2 jmcneill 904: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1.1.1.5 jmcneill 905: resets = <&cpg 703>, <&cpg 704>;
1.1.1.2 jmcneill 906: #phy-cells = <0>;
907: status = "disabled";
908: };
1.1.1.3 jmcneill 909:
1.1.1.4 jmcneill 910: sdhi2: sd@ee140000 {
911: compatible = "renesas,sdhi-r8a77995",
912: "renesas,rcar-gen3-sdhi";
913: reg = <0 0xee140000 0 0x2000>;
914: interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
915: clocks = <&cpg CPG_MOD 312>;
916: max-frequency = <200000000>;
917: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
918: resets = <&cpg 312>;
919: status = "disabled";
920: };
921:
922: gic: interrupt-controller@f1010000 {
923: compatible = "arm,gic-400";
924: #interrupt-cells = <3>;
925: #address-cells = <0>;
926: interrupt-controller;
927: reg = <0x0 0xf1010000 0 0x1000>,
928: <0x0 0xf1020000 0 0x20000>,
929: <0x0 0xf1040000 0 0x20000>,
930: <0x0 0xf1060000 0 0x20000>;
931: interrupts = <GIC_PPI 9
932: (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
933: clocks = <&cpg CPG_MOD 408>;
934: clock-names = "clk";
935: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
936: resets = <&cpg 408>;
937: };
938:
1.1.1.3 jmcneill 939: vspbs: vsp@fe960000 {
940: compatible = "renesas,vsp2";
941: reg = <0 0xfe960000 0 0x8000>;
942: interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
943: clocks = <&cpg CPG_MOD 627>;
944: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
945: resets = <&cpg 627>;
946: renesas,fcp = <&fcpvb0>;
947: };
948:
949: vspd0: vsp@fea20000 {
950: compatible = "renesas,vsp2";
1.1.1.5 jmcneill 951: reg = <0 0xfea20000 0 0x5000>;
1.1.1.3 jmcneill 952: interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
953: clocks = <&cpg CPG_MOD 623>;
954: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
955: resets = <&cpg 623>;
956: renesas,fcp = <&fcpvd0>;
957: };
958:
959: vspd1: vsp@fea28000 {
960: compatible = "renesas,vsp2";
1.1.1.5 jmcneill 961: reg = <0 0xfea28000 0 0x5000>;
1.1.1.3 jmcneill 962: interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
963: clocks = <&cpg CPG_MOD 622>;
964: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
965: resets = <&cpg 622>;
966: renesas,fcp = <&fcpvd1>;
967: };
968:
1.1.1.4 jmcneill 969: fcpvb0: fcp@fe96f000 {
970: compatible = "renesas,fcpv";
971: reg = <0 0xfe96f000 0 0x200>;
972: clocks = <&cpg CPG_MOD 607>;
973: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
974: resets = <&cpg 607>;
975: iommus = <&ipmmu_vp0 5>;
976: };
977:
978: fcpvd0: fcp@fea27000 {
979: compatible = "renesas,fcpv";
980: reg = <0 0xfea27000 0 0x200>;
981: clocks = <&cpg CPG_MOD 603>;
982: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
983: resets = <&cpg 603>;
984: iommus = <&ipmmu_vi0 8>;
985: };
986:
1.1.1.3 jmcneill 987: fcpvd1: fcp@fea2f000 {
988: compatible = "renesas,fcpv";
989: reg = <0 0xfea2f000 0 0x200>;
990: clocks = <&cpg CPG_MOD 602>;
991: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
992: resets = <&cpg 602>;
993: iommus = <&ipmmu_vi0 9>;
994: };
995:
996: du: display@feb00000 {
997: compatible = "renesas,du-r8a77995";
998: reg = <0 0xfeb00000 0 0x80000>;
999: interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1000: <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1001: clocks = <&cpg CPG_MOD 724>,
1002: <&cpg CPG_MOD 723>;
1003: clock-names = "du.0", "du.1";
1004: vsps = <&vspd0 0 &vspd1 0>;
1005: status = "disabled";
1006:
1007: ports {
1008: #address-cells = <1>;
1009: #size-cells = <0>;
1010:
1011: port@0 {
1012: reg = <0>;
1013: du_out_rgb: endpoint {
1014: };
1015: };
1016:
1017: port@1 {
1018: reg = <1>;
1019: du_out_lvds0: endpoint {
1.1.1.5 jmcneill 1020: remote-endpoint = <&lvds0_in>;
1.1.1.3 jmcneill 1021: };
1022: };
1023:
1024: port@2 {
1025: reg = <2>;
1026: du_out_lvds1: endpoint {
1.1.1.5 jmcneill 1027: remote-endpoint = <&lvds1_in>;
1028: };
1029: };
1030: };
1031: };
1032:
1033: lvds0: lvds-encoder@feb90000 {
1034: compatible = "renesas,r8a77995-lvds";
1035: reg = <0 0xfeb90000 0 0x20>;
1036: clocks = <&cpg CPG_MOD 727>;
1037: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1038: resets = <&cpg 727>;
1039: status = "disabled";
1040:
1041: ports {
1042: #address-cells = <1>;
1043: #size-cells = <0>;
1044:
1045: port@0 {
1046: reg = <0>;
1047: lvds0_in: endpoint {
1048: remote-endpoint = <&du_out_lvds0>;
1049: };
1050: };
1051:
1052: port@1 {
1053: reg = <1>;
1054: lvds0_out: endpoint {
1055: };
1056: };
1057: };
1058: };
1059:
1060: lvds1: lvds-encoder@feb90100 {
1061: compatible = "renesas,r8a77995-lvds";
1062: reg = <0 0xfeb90100 0 0x20>;
1063: clocks = <&cpg CPG_MOD 727>;
1064: power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1065: resets = <&cpg 726>;
1066: status = "disabled";
1067:
1068: ports {
1069: #address-cells = <1>;
1070: #size-cells = <0>;
1071:
1072: port@0 {
1073: reg = <0>;
1074: lvds1_in: endpoint {
1075: remote-endpoint = <&du_out_lvds1>;
1076: };
1077: };
1078:
1079: port@1 {
1080: reg = <1>;
1081: lvds1_out: endpoint {
1.1.1.3 jmcneill 1082: };
1083: };
1084: };
1085: };
1.1.1.4 jmcneill 1086:
1087: prr: chipid@fff00044 {
1088: compatible = "renesas,prr";
1089: reg = <0 0xfff00044 0 4>;
1090: };
1.1.1.3 jmcneill 1091: };
1092:
1.1.1.5 jmcneill 1093: thermal-zones {
1094: cpu_thermal: cpu-thermal {
1095: polling-delay-passive = <250>;
1096: polling-delay = <1000>;
1097: thermal-sensors = <&thermal>;
1098:
1099: trips {
1100: cpu-crit {
1101: temperature = <120000>;
1102: hysteresis = <2000>;
1103: type = "critical";
1104: };
1105: };
1106:
1107: cooling-maps {
1108: };
1109: };
1110: };
1111:
1.1.1.3 jmcneill 1112: timer {
1113: compatible = "arm,armv8-timer";
1114: interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1115: <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1116: <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1117: <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
1.1 jmcneill 1118: };
1119: };
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