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===================================================================
RCS file: /ftp/cvs/cvsroot/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/mt2712e.dtsi,v
rcsdiff: /ftp/cvs/cvsroot/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/mt2712e.dtsi,v: warning: Unknown phrases like `commitid ...;' are present.
retrieving revision 1.1.1.2.4.3
retrieving revision 1.1.1.3
diff -u -p -r1.1.1.2.4.3 -r1.1.1.3
--- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/mt2712e.dtsi	2019/01/26 22:00:31	1.1.1.2.4.3
+++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/mt2712e.dtsi	2018/04/28 18:25:53	1.1.1.3
@@ -9,7 +9,6 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/mt2712-power.h>
-#include "mt2712-pinfunc.h"
 
 / {
 	compatible = "mediatek,mt2712";
@@ -119,7 +118,7 @@
 		};
 
 		idle-states {
-			entry-method = "psci";
+			entry-method = "arm,psci";
 
 			CPU_SLEEP_0: cpu-sleep-0 {
 				compatible = "arm,idle-state";
@@ -200,34 +199,6 @@
 		clock-output-names = "clkaud_ext_i_2";
 	};
 
-	clki2si0_mck_i: oscillator@6 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <30000000>;
-		clock-output-names = "clki2si0_mck_i";
-	};
-
-	clki2si1_mck_i: oscillator@7 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <30000000>;
-		clock-output-names = "clki2si1_mck_i";
-	};
-
-	clki2si2_mck_i: oscillator@8 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <30000000>;
-		clock-output-names = "clki2si2_mck_i";
-	};
-
-	clktdmin_mclk_i: oscillator@9 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <30000000>;
-		clock-output-names = "clktdmin_mclk_i";
-	};
-
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
@@ -259,23 +230,6 @@
 		#clock-cells = <1>;
 	};
 
-	syscfg_pctl_a: syscfg_pctl_a@10005000 {
-		compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
-		reg = <0 0x10005000 0 0x1000>;
-	};
-
-	pio: pinctrl@10005000 {
-		compatible = "mediatek,mt2712-pinctrl";
-		reg = <0 0x1000b000 0 0x1000>;
-		mediatek,pctl-regmap = <&syscfg_pctl_a>;
-		pins-are-numbered;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
 	scpsys: scpsys@10006000 {
 		compatible = "mediatek,mt2712-scpsys", "syscon";
 		#power-domain-cells = <1>;
@@ -301,17 +255,6 @@
 		status = "disabled";
 	};
 
-	spis1: spi@10013000 {
-		compatible = "mediatek,mt2712-spi-slave";
-		reg = <0 0x10013000 0 0x100>;
-		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&infracfg CLK_INFRA_AO_SPI1>;
-		clock-names = "spi";
-		assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
-		status = "disabled";
-	};
-
 	apmixedsys: syscon@10209000 {
 		compatible = "mediatek,mt2712-apmixedsys", "syscon";
 		reg = <0 0x10209000 0 0x1000>;