version 1.1.1.2.2.2, 2019/06/10 22:08:49 |
version 1.1.1.2.2.3, 2020/04/08 14:08:39 |
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#clock-cells = <1>; |
#clock-cells = <1>; |
}; |
}; |
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crg_rst: crg_rst_controller { |
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compatible = "hisilicon,hi3670-reset", |
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"hisilicon,hi3660-reset"; |
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#reset-cells = <2>; |
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hisi,rst-syscon = <&crg_ctrl>; |
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}; |
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pctrl: pctrl@e8a09000 { |
pctrl: pctrl@e8a09000 { |
compatible = "hisilicon,hi3670-pctrl", "syscon"; |
compatible = "hisilicon,hi3670-pctrl", "syscon"; |
reg = <0x0 0xe8a09000 0x0 0x1000>; |
reg = <0x0 0xe8a09000 0x0 0x1000>; |
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clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; |
clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; |
clock-names = "apb_pclk"; |
clock-names = "apb_pclk"; |
}; |
}; |
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/* UFS */ |
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ufs: ufs@ff3c0000 { |
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compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; |
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/* 0: HCI standard */ |
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/* 1: UFS SYS CTRL */ |
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reg = <0x0 0xff3c0000 0x0 0x1000>, |
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<0x0 0xff3e0000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, |
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<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; |
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clock-names = "ref_clk", "phy_clk"; |
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freq-table-hz = <0 0>, <0 0>; |
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/* offset: 0x84; bit: 12 */ |
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resets = <&crg_rst 0x84 12>; |
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reset-names = "rst"; |
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}; |
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/* SD */ |
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dwmmc1: dwmmc1@ff37f000 { |
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compatible = "hisilicon,hi3670-dw-mshc", |
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"hisilicon,hi3660-dw-mshc"; |
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reg = <0x0 0xff37f000 0x0 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&crg_ctrl HI3670_CLK_GATE_SD>, |
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<&crg_ctrl HI3670_HCLK_GATE_SD>; |
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clock-names = "ciu", "biu"; |
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clock-frequency = <3200000>; |
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resets = <&crg_rst 0x94 18>; |
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reset-names = "reset"; |
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hisilicon,peripheral-syscon = <&sctrl>; |
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card-detect-delay = <200>; |
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status = "disabled"; |
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}; |
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/* SDIO */ |
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dwmmc2: dwmmc2@fc183000 { |
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compatible = "hisilicon,hi3670-dw-mshc", |
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"hisilicon,hi3660-dw-mshc"; |
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reg = <0x0 0xfc183000 0x0 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>, |
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<&crg_ctrl HI3670_HCLK_GATE_SDIO>; |
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clock-names = "ciu", "biu"; |
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clock-frequency = <3200000>; |
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resets = <&crg_rst 0x94 20>; |
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reset-names = "reset"; |
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card-detect-delay = <200>; |
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status = "disabled"; |
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}; |
}; |
}; |
}; |
}; |