version 1.1.1.4.2.2, 2020/04/08 14:08:38 |
version 1.1.1.5, 2019/01/22 14:57:03 |
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map0 { |
map0 { |
trip = <&cpu_alert>; |
trip = <&cpu_alert>; |
cooling-device = |
cooling-device = |
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
<&cpu0 THERMAL_NO_LIMIT |
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
THERMAL_NO_LIMIT>; |
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
}; |
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
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<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
map1 { |
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
trip = <&cpu_alert>; |
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
cooling-device = |
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
<&cpu4 THERMAL_NO_LIMIT |
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THERMAL_NO_LIMIT>; |
}; |
}; |
}; |
}; |
}; |
}; |
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<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ |
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ |
}; |
}; |
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fsl_mc: fsl-mc@80c000000 { |
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compatible = "fsl,qoriq-mc"; |
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ |
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */ |
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msi-parent = <&its>; |
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#address-cells = <3>; |
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#size-cells = <1>; |
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/* |
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* Region type 0x0 - MC portals |
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* Region type 0x1 - QBMAN portals |
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*/ |
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ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 |
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0x1 0x0 0x0 0x8 0x18000000 0x8000000>; |
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dpmacs { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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dpmac1: dpmac@1 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <1>; |
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}; |
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dpmac2: dpmac@2 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <2>; |
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}; |
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dpmac3: dpmac@3 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <3>; |
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}; |
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dpmac4: dpmac@4 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <4>; |
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}; |
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dpmac5: dpmac@5 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <5>; |
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}; |
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dpmac6: dpmac@6 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <6>; |
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}; |
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dpmac7: dpmac@7 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <7>; |
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}; |
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dpmac8: dpmac@8 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <8>; |
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}; |
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dpmac9: dpmac@9 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <9>; |
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}; |
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dpmac10: dpmac@a { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <0xa>; |
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}; |
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}; |
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}; |
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psci { |
psci { |
compatible = "arm,psci-0.2"; |
compatible = "arm,psci-0.2"; |
method = "smc"; |
method = "smc"; |
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#address-cells = <2>; |
#address-cells = <2>; |
#size-cells = <2>; |
#size-cells = <2>; |
ranges; |
ranges; |
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; |
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clockgen: clocking@1300000 { |
clockgen: clocking@1300000 { |
compatible = "fsl,ls1088a-clockgen"; |
compatible = "fsl,ls1088a-clockgen"; |
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#thermal-sensor-cells = <1>; |
#thermal-sensor-cells = <1>; |
}; |
}; |
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dspi: spi@2100000 { |
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compatible = "fsl,ls1088a-dspi", |
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"fsl,ls1021a-v1.0-dspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2100000 0x0 0x10000>; |
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "dspi"; |
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clocks = <&clockgen 4 1>; |
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spi-num-chipselects = <6>; |
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status = "disabled"; |
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}; |
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duart0: serial@21c0500 { |
duart0: serial@21c0500 { |
compatible = "fsl,ns16550", "ns16550a"; |
compatible = "fsl,ns16550", "ns16550a"; |
reg = <0x0 0x21c0500 0x0 0x100>; |
reg = <0x0 0x21c0500 0x0 0x100>; |
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}; |
}; |
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gpio0: gpio@2300000 { |
gpio0: gpio@2300000 { |
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; |
compatible = "fsl,qoriq-gpio"; |
reg = <0x0 0x2300000 0x0 0x10000>; |
reg = <0x0 0x2300000 0x0 0x10000>; |
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
little-endian; |
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gpio-controller; |
gpio-controller; |
#gpio-cells = <2>; |
#gpio-cells = <2>; |
interrupt-controller; |
interrupt-controller; |
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}; |
}; |
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gpio1: gpio@2310000 { |
gpio1: gpio@2310000 { |
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; |
compatible = "fsl,qoriq-gpio"; |
reg = <0x0 0x2310000 0x0 0x10000>; |
reg = <0x0 0x2310000 0x0 0x10000>; |
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
little-endian; |
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gpio-controller; |
gpio-controller; |
#gpio-cells = <2>; |
#gpio-cells = <2>; |
interrupt-controller; |
interrupt-controller; |
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}; |
}; |
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gpio2: gpio@2320000 { |
gpio2: gpio@2320000 { |
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; |
compatible = "fsl,qoriq-gpio"; |
reg = <0x0 0x2320000 0x0 0x10000>; |
reg = <0x0 0x2320000 0x0 0x10000>; |
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
little-endian; |
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gpio-controller; |
gpio-controller; |
#gpio-cells = <2>; |
#gpio-cells = <2>; |
interrupt-controller; |
interrupt-controller; |
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}; |
}; |
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gpio3: gpio@2330000 { |
gpio3: gpio@2330000 { |
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; |
compatible = "fsl,qoriq-gpio"; |
reg = <0x0 0x2330000 0x0 0x10000>; |
reg = <0x0 0x2330000 0x0 0x10000>; |
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
little-endian; |
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gpio-controller; |
gpio-controller; |
#gpio-cells = <2>; |
#gpio-cells = <2>; |
interrupt-controller; |
interrupt-controller; |
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#size-cells = <0>; |
#size-cells = <0>; |
reg = <0x0 0x2000000 0x0 0x10000>; |
reg = <0x0 0x2000000 0x0 0x10000>; |
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clockgen 4 7>; |
clocks = <&clockgen 4 3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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#size-cells = <0>; |
#size-cells = <0>; |
reg = <0x0 0x2010000 0x0 0x10000>; |
reg = <0x0 0x2010000 0x0 0x10000>; |
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clockgen 4 7>; |
clocks = <&clockgen 4 3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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#size-cells = <0>; |
#size-cells = <0>; |
reg = <0x0 0x2020000 0x0 0x10000>; |
reg = <0x0 0x2020000 0x0 0x10000>; |
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clockgen 4 7>; |
clocks = <&clockgen 4 3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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#size-cells = <0>; |
#size-cells = <0>; |
reg = <0x0 0x2030000 0x0 0x10000>; |
reg = <0x0 0x2030000 0x0 0x10000>; |
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clockgen 4 7>; |
clocks = <&clockgen 4 3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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dr_mode = "host"; |
dr_mode = "host"; |
snps,quirk-frame-length-adjustment = <0x20>; |
snps,quirk-frame-length-adjustment = <0x20>; |
snps,dis_rxdet_inp3_quirk; |
snps,dis_rxdet_inp3_quirk; |
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
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status = "disabled"; |
status = "disabled"; |
}; |
}; |
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}; |
}; |
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pcie@3400000 { |
pcie@3400000 { |
compatible = "fsl,ls1088a-pcie"; |
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; |
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ |
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ |
0x20 0x00000000 0x0 0x00002000>; /* configuration space */ |
0x20 0x00000000 0x0 0x00002000>; /* configuration space */ |
reg-names = "regs", "config"; |
reg-names = "regs", "config"; |
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#size-cells = <2>; |
#size-cells = <2>; |
device_type = "pci"; |
device_type = "pci"; |
dma-coherent; |
dma-coherent; |
num-viewport = <256>; |
num-lanes = <4>; |
bus-range = <0x0 0xff>; |
bus-range = <0x0 0xff>; |
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ |
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ |
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; |
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; |
status = "disabled"; |
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}; |
}; |
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pcie@3500000 { |
pcie@3500000 { |
compatible = "fsl,ls1088a-pcie"; |
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; |
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ |
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ |
0x28 0x00000000 0x0 0x00002000>; /* configuration space */ |
0x28 0x00000000 0x0 0x00002000>; /* configuration space */ |
reg-names = "regs", "config"; |
reg-names = "regs", "config"; |
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#size-cells = <2>; |
#size-cells = <2>; |
device_type = "pci"; |
device_type = "pci"; |
dma-coherent; |
dma-coherent; |
num-viewport = <6>; |
num-lanes = <4>; |
bus-range = <0x0 0xff>; |
bus-range = <0x0 0xff>; |
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ |
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ |
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; |
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; |
status = "disabled"; |
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}; |
}; |
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pcie@3600000 { |
pcie@3600000 { |
compatible = "fsl,ls1088a-pcie"; |
compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; |
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ |
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ |
0x30 0x00000000 0x0 0x00002000>; /* configuration space */ |
0x30 0x00000000 0x0 0x00002000>; /* configuration space */ |
reg-names = "regs", "config"; |
reg-names = "regs", "config"; |
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#size-cells = <2>; |
#size-cells = <2>; |
device_type = "pci"; |
device_type = "pci"; |
dma-coherent; |
dma-coherent; |
num-viewport = <6>; |
num-lanes = <8>; |
bus-range = <0x0 0xff>; |
bus-range = <0x0 0xff>; |
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ |
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ |
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, |
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; |
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; |
status = "disabled"; |
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}; |
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smmu: iommu@5000000 { |
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compatible = "arm,mmu-500"; |
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reg = <0 0x5000000 0 0x800000>; |
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#iommu-cells = <1>; |
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stream-match-mask = <0x7C00>; |
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#global-interrupts = <12>; |
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// global secure fault |
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
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// combined secure |
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
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// global non-secure fault |
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
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// combined non-secure |
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
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// performance counter interrupts 0-7 |
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, |
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// per context interrupt, 64 interrupts |
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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console@8340020 { |
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compatible = "fsl,dpaa2-console"; |
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reg = <0x00000000 0x08340020 0 0x2>; |
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}; |
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ptp-timer@8b95000 { |
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compatible = "fsl,dpaa2-ptp"; |
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reg = <0x0 0x8b95000 0x0 0x100>; |
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clocks = <&clockgen 4 0>; |
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little-endian; |
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fsl,extts-fifo; |
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}; |
}; |
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cluster1_core0_watchdog: wdt@c000000 { |
cluster1_core0_watchdog: wdt@c000000 { |
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clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
clock-names = "apb_pclk", "wdog_clk"; |
clock-names = "apb_pclk", "wdog_clk"; |
}; |
}; |
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fsl_mc: fsl-mc@80c000000 { |
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compatible = "fsl,qoriq-mc"; |
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ |
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */ |
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msi-parent = <&its>; |
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iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ |
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dma-coherent; |
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#address-cells = <3>; |
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#size-cells = <1>; |
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/* |
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* Region type 0x0 - MC portals |
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* Region type 0x1 - QBMAN portals |
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*/ |
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ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 |
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0x1 0x0 0x0 0x8 0x18000000 0x8000000>; |
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dpmacs { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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dpmac1: dpmac@1 { |
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compatible = "fsl,qoriq-mc-dpmac"; |
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reg = <1>; |
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}; |
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dpmac2: dpmac@2 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <2>; |
|
}; |
|
|
|
dpmac3: dpmac@3 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <3>; |
|
}; |
|
|
|
dpmac4: dpmac@4 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <4>; |
|
}; |
|
|
|
dpmac5: dpmac@5 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <5>; |
|
}; |
|
|
|
dpmac6: dpmac@6 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <6>; |
|
}; |
|
|
|
dpmac7: dpmac@7 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <7>; |
|
}; |
|
|
|
dpmac8: dpmac@8 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <8>; |
|
}; |
|
|
|
dpmac9: dpmac@9 { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <9>; |
|
}; |
|
|
|
dpmac10: dpmac@a { |
|
compatible = "fsl,qoriq-mc-dpmac"; |
|
reg = <0xa>; |
|
}; |
|
}; |
|
}; |
|
}; |
}; |
|
|
firmware { |
firmware { |
|
|
method = "smc"; |
method = "smc"; |
}; |
}; |
}; |
}; |
|
|
}; |
}; |