![[BACK]](/icons/back.gif){kind=icon}
Return to exynos7.dtsi CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / external / gpl2 / dts / dist / arch / arm64 / boot / dts / exynos|
Return to exynos7.dtsi CVS log | Up to [cvs.NetBSD.org] / src / sys / external / gpl2 / dts / dist / arch / arm64 / boot / dts / exynos |
1.1.1.2 jmcneill 1: // SPDX-License-Identifier: GPL-2.0
1.1 jmcneill 2: /*
1.1.1.7 ! jmcneill 3: * Samsung Exynos7 SoC device tree source
1.1 jmcneill 4: *
5: * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6: * http://www.samsung.com
7: */
8:
9: #include <dt-bindings/clock/exynos7-clk.h>
10: #include <dt-bindings/interrupt-controller/arm-gic.h>
11:
12: / {
13: compatible = "samsung,exynos7";
14: interrupt-parent = <&gic>;
1.1.1.6 skrll 15: #address-cells = <2>;
16: #size-cells = <2>;
1.1 jmcneill 17:
18: aliases {
19: pinctrl0 = &pinctrl_alive;
20: pinctrl1 = &pinctrl_bus0;
21: pinctrl2 = &pinctrl_nfc;
22: pinctrl3 = &pinctrl_touch;
23: pinctrl4 = &pinctrl_ff;
24: pinctrl5 = &pinctrl_ese;
25: pinctrl6 = &pinctrl_fsys0;
26: pinctrl7 = &pinctrl_fsys1;
27: pinctrl8 = &pinctrl_bus1;
28: tmuctrl0 = &tmuctrl_0;
29: };
30:
1.1.1.6 skrll 31: arm-pmu {
1.1.1.7 ! jmcneill 32: compatible = "arm,cortex-a57-pmu";
1.1.1.6 skrll 33: interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
34: <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
35: <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
36: <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
37: interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
38: <&cpu_atlas2>, <&cpu_atlas3>;
39: };
40:
41: fin_pll: clock {
42: /* XXTI */
43: compatible = "fixed-clock";
44: clock-output-names = "fin_pll";
45: #clock-cells = <0>;
46: };
47:
1.1 jmcneill 48: cpus {
49: #address-cells = <1>;
50: #size-cells = <0>;
51:
52: cpu_atlas0: cpu@0 {
53: device_type = "cpu";
1.1.1.5 jmcneill 54: compatible = "arm,cortex-a57";
1.1 jmcneill 55: reg = <0x0>;
56: enable-method = "psci";
1.1.1.7 ! jmcneill 57: i-cache-size = <0xc000>;
! 58: i-cache-line-size = <64>;
! 59: i-cache-sets = <256>;
! 60: d-cache-size = <0x8000>;
! 61: d-cache-line-size = <64>;
! 62: d-cache-sets = <256>;
! 63: next-level-cache = <&atlas_l2>;
1.1 jmcneill 64: };
65:
66: cpu_atlas1: cpu@1 {
67: device_type = "cpu";
1.1.1.5 jmcneill 68: compatible = "arm,cortex-a57";
1.1 jmcneill 69: reg = <0x1>;
70: enable-method = "psci";
1.1.1.7 ! jmcneill 71: i-cache-size = <0xc000>;
! 72: i-cache-line-size = <64>;
! 73: i-cache-sets = <256>;
! 74: d-cache-size = <0x8000>;
! 75: d-cache-line-size = <64>;
! 76: d-cache-sets = <256>;
! 77: next-level-cache = <&atlas_l2>;
1.1 jmcneill 78: };
79:
80: cpu_atlas2: cpu@2 {
81: device_type = "cpu";
1.1.1.5 jmcneill 82: compatible = "arm,cortex-a57";
1.1 jmcneill 83: reg = <0x2>;
84: enable-method = "psci";
1.1.1.7 ! jmcneill 85: i-cache-size = <0xc000>;
! 86: i-cache-line-size = <64>;
! 87: i-cache-sets = <256>;
! 88: d-cache-size = <0x8000>;
! 89: d-cache-line-size = <64>;
! 90: d-cache-sets = <256>;
! 91: next-level-cache = <&atlas_l2>;
1.1 jmcneill 92: };
93:
94: cpu_atlas3: cpu@3 {
95: device_type = "cpu";
1.1.1.5 jmcneill 96: compatible = "arm,cortex-a57";
1.1 jmcneill 97: reg = <0x3>;
98: enable-method = "psci";
1.1.1.7 ! jmcneill 99: i-cache-size = <0xc000>;
! 100: i-cache-line-size = <64>;
! 101: i-cache-sets = <256>;
! 102: d-cache-size = <0x8000>;
! 103: d-cache-line-size = <64>;
! 104: d-cache-sets = <256>;
! 105: next-level-cache = <&atlas_l2>;
! 106: };
! 107:
! 108: atlas_l2: l2-cache0 {
! 109: compatible = "cache";
! 110: cache-size = <0x200000>;
! 111: cache-line-size = <64>;
! 112: cache-sets = <2048>;
1.1 jmcneill 113: };
114: };
115:
116: psci {
1.1.1.7 ! jmcneill 117: compatible = "arm,psci";
1.1 jmcneill 118: method = "smc";
1.1.1.7 ! jmcneill 119: cpu_off = <0x84000002>;
! 120: cpu_on = <0xC4000003>;
1.1 jmcneill 121: };
122:
1.1.1.7 ! jmcneill 123: soc: soc@0 {
1.1 jmcneill 124: compatible = "simple-bus";
125: #address-cells = <1>;
126: #size-cells = <1>;
1.1.1.6 skrll 127: ranges = <0 0 0 0x18000000>;
1.1 jmcneill 128:
129: chipid@10000000 {
130: compatible = "samsung,exynos4210-chipid";
131: reg = <0x10000000 0x100>;
132: };
133:
134: gic: interrupt-controller@11001000 {
135: compatible = "arm,gic-400";
136: #interrupt-cells = <3>;
137: #address-cells = <0>;
138: interrupt-controller;
139: reg = <0x11001000 0x1000>,
1.1.1.7 ! jmcneill 140: <0x11002000 0x2000>,
1.1 jmcneill 141: <0x11004000 0x2000>,
142: <0x11006000 0x2000>;
143: };
144:
1.1.1.7 ! jmcneill 145: pdma0: pdma@10e10000 {
! 146: compatible = "arm,pl330", "arm,primecell";
! 147: reg = <0x10E10000 0x1000>;
! 148: interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
! 149: clocks = <&clock_fsys0 ACLK_PDMA0>;
! 150: clock-names = "apb_pclk";
! 151: #dma-cells = <1>;
! 152: #dma-channels = <8>;
! 153: #dma-requests = <32>;
! 154: };
! 155:
! 156: pdma1: pdma@10eb0000 {
! 157: compatible = "arm,pl330", "arm,primecell";
! 158: reg = <0x10EB0000 0x1000>;
! 159: interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
! 160: clocks = <&clock_fsys0 ACLK_PDMA1>;
! 161: clock-names = "apb_pclk";
! 162: #dma-cells = <1>;
! 163: #dma-channels = <8>;
! 164: #dma-requests = <32>;
1.1 jmcneill 165: };
166:
167: clock_topc: clock-controller@10570000 {
168: compatible = "samsung,exynos7-clock-topc";
169: reg = <0x10570000 0x10000>;
170: #clock-cells = <1>;
171: };
172:
173: clock_top0: clock-controller@105d0000 {
174: compatible = "samsung,exynos7-clock-top0";
175: reg = <0x105d0000 0xb000>;
176: #clock-cells = <1>;
177: clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
178: <&clock_topc DOUT_SCLK_BUS1_PLL>,
179: <&clock_topc DOUT_SCLK_CC_PLL>,
180: <&clock_topc DOUT_SCLK_MFC_PLL>;
181: clock-names = "fin_pll", "dout_sclk_bus0_pll",
182: "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
183: "dout_sclk_mfc_pll";
184: };
185:
186: clock_top1: clock-controller@105e0000 {
187: compatible = "samsung,exynos7-clock-top1";
188: reg = <0x105e0000 0xb000>;
189: #clock-cells = <1>;
190: clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
191: <&clock_topc DOUT_SCLK_BUS1_PLL>,
192: <&clock_topc DOUT_SCLK_CC_PLL>,
193: <&clock_topc DOUT_SCLK_MFC_PLL>;
194: clock-names = "fin_pll", "dout_sclk_bus0_pll",
195: "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
196: "dout_sclk_mfc_pll";
197: };
198:
199: clock_ccore: clock-controller@105b0000 {
200: compatible = "samsung,exynos7-clock-ccore";
201: reg = <0x105b0000 0xd00>;
202: #clock-cells = <1>;
203: clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
204: clock-names = "fin_pll", "dout_aclk_ccore_133";
205: };
206:
207: clock_peric0: clock-controller@13610000 {
208: compatible = "samsung,exynos7-clock-peric0";
209: reg = <0x13610000 0xd00>;
210: #clock-cells = <1>;
211: clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
212: <&clock_top0 CLK_SCLK_UART0>;
213: clock-names = "fin_pll", "dout_aclk_peric0_66",
214: "sclk_uart0";
215: };
216:
217: clock_peric1: clock-controller@14c80000 {
218: compatible = "samsung,exynos7-clock-peric1";
219: reg = <0x14c80000 0xd00>;
220: #clock-cells = <1>;
221: clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
222: <&clock_top0 CLK_SCLK_UART1>,
223: <&clock_top0 CLK_SCLK_UART2>,
224: <&clock_top0 CLK_SCLK_UART3>;
225: clock-names = "fin_pll", "dout_aclk_peric1_66",
226: "sclk_uart1", "sclk_uart2", "sclk_uart3";
227: };
228:
229: clock_peris: clock-controller@10040000 {
230: compatible = "samsung,exynos7-clock-peris";
231: reg = <0x10040000 0xd00>;
232: #clock-cells = <1>;
233: clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
234: clock-names = "fin_pll", "dout_aclk_peris_66";
235: };
236:
237: clock_fsys0: clock-controller@10e90000 {
238: compatible = "samsung,exynos7-clock-fsys0";
239: reg = <0x10e90000 0xd00>;
240: #clock-cells = <1>;
241: clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
242: <&clock_top1 DOUT_SCLK_MMC2>;
243: clock-names = "fin_pll", "dout_aclk_fsys0_200",
244: "dout_sclk_mmc2";
245: };
246:
247: clock_fsys1: clock-controller@156e0000 {
248: compatible = "samsung,exynos7-clock-fsys1";
249: reg = <0x156e0000 0xd00>;
250: #clock-cells = <1>;
251: clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
252: <&clock_top1 DOUT_SCLK_MMC0>,
1.1.1.7 ! jmcneill 253: <&clock_top1 DOUT_SCLK_MMC1>,
! 254: <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
! 255: <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
! 256: <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
1.1 jmcneill 257: clock-names = "fin_pll", "dout_aclk_fsys1_200",
1.1.1.7 ! jmcneill 258: "dout_sclk_mmc0", "dout_sclk_mmc1",
! 259: "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
! 260: "dout_sclk_phy_fsys1_26m";
1.1 jmcneill 261: };
262:
263: serial_0: serial@13630000 {
264: compatible = "samsung,exynos4210-uart";
265: reg = <0x13630000 0x100>;
266: interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
267: clocks = <&clock_peric0 PCLK_UART0>,
268: <&clock_peric0 SCLK_UART0>;
269: clock-names = "uart", "clk_uart_baud0";
270: status = "disabled";
271: };
272:
273: serial_1: serial@14c20000 {
274: compatible = "samsung,exynos4210-uart";
275: reg = <0x14c20000 0x100>;
276: interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
277: clocks = <&clock_peric1 PCLK_UART1>,
278: <&clock_peric1 SCLK_UART1>;
279: clock-names = "uart", "clk_uart_baud0";
280: status = "disabled";
281: };
282:
283: serial_2: serial@14c30000 {
284: compatible = "samsung,exynos4210-uart";
285: reg = <0x14c30000 0x100>;
286: interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
287: clocks = <&clock_peric1 PCLK_UART2>,
288: <&clock_peric1 SCLK_UART2>;
289: clock-names = "uart", "clk_uart_baud0";
290: status = "disabled";
291: };
292:
293: serial_3: serial@14c40000 {
294: compatible = "samsung,exynos4210-uart";
295: reg = <0x14c40000 0x100>;
296: interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
297: clocks = <&clock_peric1 PCLK_UART3>,
298: <&clock_peric1 SCLK_UART3>;
299: clock-names = "uart", "clk_uart_baud0";
300: status = "disabled";
301: };
302:
303: pinctrl_alive: pinctrl@10580000 {
304: compatible = "samsung,exynos7-pinctrl";
305: reg = <0x10580000 0x1000>;
306:
307: wakeup-interrupt-controller {
308: compatible = "samsung,exynos7-wakeup-eint";
309: interrupt-parent = <&gic>;
310: interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
311: };
312: };
313:
314: pinctrl_bus0: pinctrl@13470000 {
315: compatible = "samsung,exynos7-pinctrl";
316: reg = <0x13470000 0x1000>;
317: interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
318: };
319:
320: pinctrl_nfc: pinctrl@14cd0000 {
321: compatible = "samsung,exynos7-pinctrl";
322: reg = <0x14cd0000 0x1000>;
323: interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
324: };
325:
326: pinctrl_touch: pinctrl@14ce0000 {
327: compatible = "samsung,exynos7-pinctrl";
328: reg = <0x14ce0000 0x1000>;
329: interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
330: };
331:
332: pinctrl_ff: pinctrl@14c90000 {
333: compatible = "samsung,exynos7-pinctrl";
334: reg = <0x14c90000 0x1000>;
335: interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
336: };
337:
338: pinctrl_ese: pinctrl@14ca0000 {
339: compatible = "samsung,exynos7-pinctrl";
340: reg = <0x14ca0000 0x1000>;
341: interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
342: };
343:
344: pinctrl_fsys0: pinctrl@10e60000 {
345: compatible = "samsung,exynos7-pinctrl";
346: reg = <0x10e60000 0x1000>;
347: interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
348: };
349:
350: pinctrl_fsys1: pinctrl@15690000 {
351: compatible = "samsung,exynos7-pinctrl";
352: reg = <0x15690000 0x1000>;
353: interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
354: };
355:
356: pinctrl_bus1: pinctrl@14870000 {
357: compatible = "samsung,exynos7-pinctrl";
358: reg = <0x14870000 0x1000>;
359: interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
360: };
361:
362: hsi2c_0: hsi2c@13640000 {
363: compatible = "samsung,exynos7-hsi2c";
364: reg = <0x13640000 0x1000>;
365: interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
366: #address-cells = <1>;
367: #size-cells = <0>;
368: pinctrl-names = "default";
369: pinctrl-0 = <&hs_i2c0_bus>;
370: clocks = <&clock_peric0 PCLK_HSI2C0>;
371: clock-names = "hsi2c";
372: status = "disabled";
373: };
374:
375: hsi2c_1: hsi2c@13650000 {
376: compatible = "samsung,exynos7-hsi2c";
377: reg = <0x13650000 0x1000>;
378: interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
379: #address-cells = <1>;
380: #size-cells = <0>;
381: pinctrl-names = "default";
382: pinctrl-0 = <&hs_i2c1_bus>;
383: clocks = <&clock_peric0 PCLK_HSI2C1>;
384: clock-names = "hsi2c";
385: status = "disabled";
386: };
387:
388: hsi2c_2: hsi2c@14e60000 {
389: compatible = "samsung,exynos7-hsi2c";
390: reg = <0x14e60000 0x1000>;
391: interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
392: #address-cells = <1>;
393: #size-cells = <0>;
394: pinctrl-names = "default";
395: pinctrl-0 = <&hs_i2c2_bus>;
396: clocks = <&clock_peric1 PCLK_HSI2C2>;
397: clock-names = "hsi2c";
398: status = "disabled";
399: };
400:
401: hsi2c_3: hsi2c@14e70000 {
402: compatible = "samsung,exynos7-hsi2c";
403: reg = <0x14e70000 0x1000>;
404: interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
405: #address-cells = <1>;
406: #size-cells = <0>;
407: pinctrl-names = "default";
408: pinctrl-0 = <&hs_i2c3_bus>;
409: clocks = <&clock_peric1 PCLK_HSI2C3>;
410: clock-names = "hsi2c";
411: status = "disabled";
412: };
413:
414: hsi2c_4: hsi2c@13660000 {
415: compatible = "samsung,exynos7-hsi2c";
416: reg = <0x13660000 0x1000>;
417: interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
418: #address-cells = <1>;
419: #size-cells = <0>;
420: pinctrl-names = "default";
421: pinctrl-0 = <&hs_i2c4_bus>;
422: clocks = <&clock_peric0 PCLK_HSI2C4>;
423: clock-names = "hsi2c";
424: status = "disabled";
425: };
426:
427: hsi2c_5: hsi2c@13670000 {
428: compatible = "samsung,exynos7-hsi2c";
429: reg = <0x13670000 0x1000>;
430: interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
431: #address-cells = <1>;
432: #size-cells = <0>;
433: pinctrl-names = "default";
434: pinctrl-0 = <&hs_i2c5_bus>;
435: clocks = <&clock_peric0 PCLK_HSI2C5>;
436: clock-names = "hsi2c";
437: status = "disabled";
438: };
439:
440: hsi2c_6: hsi2c@14e00000 {
441: compatible = "samsung,exynos7-hsi2c";
442: reg = <0x14e00000 0x1000>;
443: interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
444: #address-cells = <1>;
445: #size-cells = <0>;
446: pinctrl-names = "default";
447: pinctrl-0 = <&hs_i2c6_bus>;
448: clocks = <&clock_peric1 PCLK_HSI2C6>;
449: clock-names = "hsi2c";
450: status = "disabled";
451: };
452:
453: hsi2c_7: hsi2c@13e10000 {
454: compatible = "samsung,exynos7-hsi2c";
455: reg = <0x13e10000 0x1000>;
456: interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
457: #address-cells = <1>;
458: #size-cells = <0>;
459: pinctrl-names = "default";
460: pinctrl-0 = <&hs_i2c7_bus>;
461: clocks = <&clock_peric1 PCLK_HSI2C7>;
462: clock-names = "hsi2c";
463: status = "disabled";
464: };
465:
466: hsi2c_8: hsi2c@14e20000 {
467: compatible = "samsung,exynos7-hsi2c";
468: reg = <0x14e20000 0x1000>;
469: interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
470: #address-cells = <1>;
471: #size-cells = <0>;
472: pinctrl-names = "default";
473: pinctrl-0 = <&hs_i2c8_bus>;
474: clocks = <&clock_peric1 PCLK_HSI2C8>;
475: clock-names = "hsi2c";
476: status = "disabled";
477: };
478:
479: hsi2c_9: hsi2c@13680000 {
480: compatible = "samsung,exynos7-hsi2c";
481: reg = <0x13680000 0x1000>;
482: interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
483: #address-cells = <1>;
484: #size-cells = <0>;
485: pinctrl-names = "default";
486: pinctrl-0 = <&hs_i2c9_bus>;
487: clocks = <&clock_peric0 PCLK_HSI2C9>;
488: clock-names = "hsi2c";
489: status = "disabled";
490: };
491:
492: hsi2c_10: hsi2c@13690000 {
493: compatible = "samsung,exynos7-hsi2c";
494: reg = <0x13690000 0x1000>;
495: interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
496: #address-cells = <1>;
497: #size-cells = <0>;
498: pinctrl-names = "default";
499: pinctrl-0 = <&hs_i2c10_bus>;
500: clocks = <&clock_peric0 PCLK_HSI2C10>;
501: clock-names = "hsi2c";
502: status = "disabled";
503: };
504:
505: hsi2c_11: hsi2c@136a0000 {
506: compatible = "samsung,exynos7-hsi2c";
507: reg = <0x136a0000 0x1000>;
508: interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
509: #address-cells = <1>;
510: #size-cells = <0>;
511: pinctrl-names = "default";
512: pinctrl-0 = <&hs_i2c11_bus>;
513: clocks = <&clock_peric0 PCLK_HSI2C11>;
514: clock-names = "hsi2c";
515: status = "disabled";
516: };
517:
518: pmu_system_controller: system-controller@105c0000 {
519: compatible = "samsung,exynos7-pmu", "syscon";
520: reg = <0x105c0000 0x5000>;
521: };
522:
523: rtc: rtc@10590000 {
524: compatible = "samsung,s3c6410-rtc";
525: reg = <0x10590000 0x100>;
526: interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
527: <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
528: clocks = <&clock_ccore PCLK_RTC>;
529: clock-names = "rtc";
530: status = "disabled";
531: };
532:
533: watchdog: watchdog@101d0000 {
534: compatible = "samsung,exynos7-wdt";
535: reg = <0x101d0000 0x100>;
536: interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
537: clocks = <&clock_peris PCLK_WDT>;
538: clock-names = "watchdog";
539: samsung,syscon-phandle = <&pmu_system_controller>;
540: status = "disabled";
541: };
542:
1.1.1.6 skrll 543: gpu: gpu@14ac0000 {
544: compatible = "samsung,exynos5433-mali", "arm,mali-t760";
545: reg = <0x14ac0000 0x5000>;
546: interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
547: <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
548: <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
549: interrupt-names = "job", "mmu", "gpu";
550: status = "disabled";
551: /* TODO: operating points for DVFS, cooling device */
552: };
553:
1.1 jmcneill 554: mmc_0: mmc@15740000 {
555: compatible = "samsung,exynos7-dw-mshc-smu";
556: interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
557: #address-cells = <1>;
558: #size-cells = <0>;
559: reg = <0x15740000 0x2000>;
560: clocks = <&clock_fsys1 ACLK_MMC0>,
561: <&clock_top1 CLK_SCLK_MMC0>;
562: clock-names = "biu", "ciu";
563: fifo-depth = <0x40>;
564: status = "disabled";
565: };
566:
567: mmc_1: mmc@15750000 {
568: compatible = "samsung,exynos7-dw-mshc";
569: interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
570: #address-cells = <1>;
571: #size-cells = <0>;
572: reg = <0x15750000 0x2000>;
573: clocks = <&clock_fsys1 ACLK_MMC1>,
574: <&clock_top1 CLK_SCLK_MMC1>;
575: clock-names = "biu", "ciu";
576: fifo-depth = <0x40>;
577: status = "disabled";
578: };
579:
580: mmc_2: mmc@15560000 {
581: compatible = "samsung,exynos7-dw-mshc-smu";
582: interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
583: #address-cells = <1>;
584: #size-cells = <0>;
585: reg = <0x15560000 0x2000>;
586: clocks = <&clock_fsys0 ACLK_MMC2>,
587: <&clock_top1 CLK_SCLK_MMC2>;
588: clock-names = "biu", "ciu";
589: fifo-depth = <0x40>;
590: status = "disabled";
591: };
592:
593: adc: adc@13620000 {
594: compatible = "samsung,exynos7-adc";
595: reg = <0x13620000 0x100>;
596: interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
597: clocks = <&clock_peric0 PCLK_ADCIF>;
598: clock-names = "adc";
599: #io-channel-cells = <1>;
600: status = "disabled";
601: };
602:
603: pwm: pwm@136c0000 {
604: compatible = "samsung,exynos4210-pwm";
605: reg = <0x136c0000 0x100>;
1.1.1.7 ! jmcneill 606: interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
! 607: <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
! 608: <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
! 609: <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
! 610: <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 611: samsung,pwm-outputs = <0>, <1>, <2>, <3>;
612: #pwm-cells = <3>;
613: clocks = <&clock_peric0 PCLK_PWM>;
614: clock-names = "timers";
615: };
616:
617: tmuctrl_0: tmu@10060000 {
618: compatible = "samsung,exynos7-tmu";
619: reg = <0x10060000 0x200>;
620: interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
621: clocks = <&clock_peris PCLK_TMU>,
622: <&clock_peris SCLK_TMU>;
623: clock-names = "tmu_apbif", "tmu_sclk";
1.1.1.4 jmcneill 624: #thermal-sensor-cells = <0>;
1.1 jmcneill 625: };
626:
1.1.1.7 ! jmcneill 627: ufs: ufs@15570000 {
! 628: compatible = "samsung,exynos7-ufs";
! 629: reg = <0x15570000 0x100>, /* 0: HCI standard */
! 630: <0x15570100 0x100>, /* 1: Vendor specificed */
! 631: <0x15571000 0x200>, /* 2: UNIPRO */
! 632: <0x15572000 0x300>; /* 3: UFS protector */
! 633: reg-names = "hci", "vs_hci", "unipro", "ufsp";
! 634: interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
! 635: clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
! 636: <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
! 637: clock-names = "core_clk", "sclk_unipro_main";
! 638: freq-table-hz = <0 0>, <0 0>;
! 639: pinctrl-names = "default";
! 640: pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
! 641: phys = <&ufs_phy>;
! 642: phy-names = "ufs-phy";
! 643: status = "disabled";
! 644: };
! 645:
! 646: ufs_phy: ufs-phy@15571800 {
! 647: compatible = "samsung,exynos7-ufs-phy";
! 648: reg = <0x15571800 0x240>;
! 649: reg-names = "phy-pma";
! 650: samsung,pmu-syscon = <&pmu_system_controller>;
! 651: #phy-cells = <0>;
! 652: clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
! 653: <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
! 654: <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
! 655: <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
! 656: clock-names = "ref_clk", "rx1_symbol_clk",
! 657: "rx0_symbol_clk",
! 658: "tx0_symbol_clk";
1.1 jmcneill 659: };
660:
661: usbdrd_phy: phy@15500000 {
662: compatible = "samsung,exynos7-usbdrd-phy";
663: reg = <0x15500000 0x100>;
664: clocks = <&clock_fsys0 ACLK_USBDRD300>,
665: <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
666: <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
667: <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
668: <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
669: clock-names = "phy", "ref", "phy_pipe",
670: "phy_utmi", "itp";
671: samsung,pmu-syscon = <&pmu_system_controller>;
672: #phy-cells = <1>;
673: };
674:
675: usbdrd3 {
676: compatible = "samsung,exynos7-dwusb3";
677: clocks = <&clock_fsys0 ACLK_USBDRD300>,
678: <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
679: <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
680: clock-names = "usbdrd30", "usbdrd30_susp_clk",
681: "usbdrd30_axius_clk";
682: #address-cells = <1>;
683: #size-cells = <1>;
684: ranges;
685:
1.1.1.7 ! jmcneill 686: usb@15400000 {
1.1 jmcneill 687: compatible = "snps,dwc3";
688: reg = <0x15400000 0x10000>;
689: interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
690: phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
691: phy-names = "usb2-phy", "usb3-phy";
692: };
693: };
694: };
1.1.1.6 skrll 695:
1.1.1.7 ! jmcneill 696: thermal-zones {
! 697: atlas_thermal: cluster0-thermal {
! 698: polling-delay-passive = <0>; /* milliseconds */
! 699: polling-delay = <0>; /* milliseconds */
! 700: thermal-sensors = <&tmuctrl_0>;
! 701: #include "exynos7-trip-points.dtsi"
! 702: };
! 703: };
! 704:
1.1.1.6 skrll 705: timer {
706: compatible = "arm,armv8-timer";
707: interrupts = <GIC_PPI 13
708: (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
709: <GIC_PPI 14
710: (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
711: <GIC_PPI 11
712: (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
713: <GIC_PPI 10
714: (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
715: };
1.1 jmcneill 716: };
717:
718: #include "exynos7-pinctrl.dtsi"
1.1.1.7 ! jmcneill 719: #include "arm/exynos-syscon-restart.dtsi"