version 1.1.1.4.2.1, 2017/11/30 19:40:50 |
version 1.1.1.4.2.2, 2017/12/03 11:38:25 |
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/* |
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* Device Tree Source for UniPhier sLD8 SoC |
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* |
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* Copyright (C) 2015-2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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*/ |
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/ { |
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compatible = "socionext,uniphier-sld8"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a9"; |
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reg = <0>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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clocks { |
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refclk: ref { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <25000000>; |
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}; |
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arm_timer_clk: arm-timer { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <50000000>; |
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}; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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interrupt-parent = <&intc>; |
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l2: l2-cache@500c0000 { |
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compatible = "socionext,uniphier-system-cache"; |
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, |
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<0x506c0000 0x400>; |
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interrupts = <0 174 4>, <0 175 4>; |
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cache-unified; |
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cache-size = <(256 * 1024)>; |
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cache-sets = <256>; |
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cache-line-size = <128>; |
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cache-level = <2>; |
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}; |
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serial0: serial@54006800 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006800 0x40>; |
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interrupts = <0 33 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart0>; |
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clocks = <&peri_clk 0>; |
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resets = <&peri_rst 0>; |
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}; |
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serial1: serial@54006900 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006900 0x40>; |
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interrupts = <0 35 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart1>; |
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clocks = <&peri_clk 1>; |
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resets = <&peri_rst 1>; |
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}; |
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serial2: serial@54006a00 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006a00 0x40>; |
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interrupts = <0 37 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart2>; |
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clocks = <&peri_clk 2>; |
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resets = <&peri_rst 2>; |
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}; |
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serial3: serial@54006b00 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006b00 0x40>; |
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interrupts = <0 29 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart3>; |
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clocks = <&peri_clk 3>; |
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resets = <&peri_rst 3>; |
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}; |
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gpio: gpio@55000000 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000000 0x200>; |
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interrupt-parent = <&aidet>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pinctrl 0 0 0>, |
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<&pinctrl 104 0 0>, |
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<&pinctrl 112 0 0>; |
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gpio-ranges-group-names = "gpio_range0", |
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"gpio_range1", |
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"gpio_range2"; |
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ngpios = <136>; |
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socionext,interrupt-ranges = <0 48 13>, <14 62 2>; |
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}; |
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i2c0: i2c@58400000 { |
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compatible = "socionext,uniphier-i2c"; |
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status = "disabled"; |
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reg = <0x58400000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 41 1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c0>; |
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clocks = <&peri_clk 4>; |
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resets = <&peri_rst 4>; |
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clock-frequency = <100000>; |
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}; |
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i2c1: i2c@58480000 { |
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compatible = "socionext,uniphier-i2c"; |
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status = "disabled"; |
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reg = <0x58480000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 42 1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c1>; |
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clocks = <&peri_clk 5>; |
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resets = <&peri_rst 5>; |
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clock-frequency = <100000>; |
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}; |
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/* chip-internal connection for DMD */ |
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i2c2: i2c@58500000 { |
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compatible = "socionext,uniphier-i2c"; |
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reg = <0x58500000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 43 1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c2>; |
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clocks = <&peri_clk 6>; |
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resets = <&peri_rst 6>; |
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clock-frequency = <400000>; |
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}; |
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i2c3: i2c@58580000 { |
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compatible = "socionext,uniphier-i2c"; |
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status = "disabled"; |
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reg = <0x58580000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 44 1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c3>; |
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clocks = <&peri_clk 7>; |
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resets = <&peri_rst 7>; |
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clock-frequency = <100000>; |
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}; |
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system_bus: system-bus@58c00000 { |
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compatible = "socionext,uniphier-system-bus"; |
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status = "disabled"; |
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reg = <0x58c00000 0x400>; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_system_bus>; |
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}; |
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smpctrl@59801000 { |
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compatible = "socionext,uniphier-smpctrl"; |
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reg = <0x59801000 0x400>; |
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}; |
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mioctrl@59810000 { |
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compatible = "socionext,uniphier-sld8-mioctrl", |
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"simple-mfd", "syscon"; |
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reg = <0x59810000 0x800>; |
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mio_clk: clock { |
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compatible = "socionext,uniphier-sld8-mio-clock"; |
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#clock-cells = <1>; |
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}; |
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mio_rst: reset { |
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compatible = "socionext,uniphier-sld8-mio-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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perictrl@59820000 { |
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compatible = "socionext,uniphier-sld8-perictrl", |
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"simple-mfd", "syscon"; |
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reg = <0x59820000 0x200>; |
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peri_clk: clock { |
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compatible = "socionext,uniphier-sld8-peri-clock"; |
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#clock-cells = <1>; |
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}; |
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peri_rst: reset { |
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compatible = "socionext,uniphier-sld8-peri-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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usb0: usb@5a800100 { |
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compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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status = "disabled"; |
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reg = <0x5a800100 0x100>; |
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interrupts = <0 80 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb0>; |
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, |
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<&mio_clk 12>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, |
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<&mio_rst 12>; |
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}; |
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usb1: usb@5a810100 { |
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compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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status = "disabled"; |
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reg = <0x5a810100 0x100>; |
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interrupts = <0 81 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb1>; |
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, |
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<&mio_clk 13>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, |
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<&mio_rst 13>; |
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}; |
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usb2: usb@5a820100 { |
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compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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status = "disabled"; |
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reg = <0x5a820100 0x100>; |
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interrupts = <0 82 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb2>; |
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, |
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<&mio_clk 14>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, |
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<&mio_rst 14>; |
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}; |
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soc-glue@5f800000 { |
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compatible = "socionext,uniphier-sld8-soc-glue", |
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"simple-mfd", "syscon"; |
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reg = <0x5f800000 0x2000>; |
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pinctrl: pinctrl { |
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compatible = "socionext,uniphier-sld8-pinctrl"; |
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}; |
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}; |
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timer@60000200 { |
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compatible = "arm,cortex-a9-global-timer"; |
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reg = <0x60000200 0x20>; |
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interrupts = <1 11 0x104>; |
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clocks = <&arm_timer_clk>; |
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}; |
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timer@60000600 { |
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compatible = "arm,cortex-a9-twd-timer"; |
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reg = <0x60000600 0x20>; |
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interrupts = <1 13 0x104>; |
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clocks = <&arm_timer_clk>; |
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}; |
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intc: interrupt-controller@60001000 { |
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compatible = "arm,cortex-a9-gic"; |
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reg = <0x60001000 0x1000>, |
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<0x60000100 0x100>; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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}; |
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aidet: aidet@61830000 { |
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compatible = "socionext,uniphier-sld8-aidet"; |
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reg = <0x61830000 0x200>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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sysctrl@61840000 { |
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compatible = "socionext,uniphier-sld8-sysctrl", |
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"simple-mfd", "syscon"; |
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reg = <0x61840000 0x10000>; |
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sys_clk: clock { |
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compatible = "socionext,uniphier-sld8-clock"; |
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#clock-cells = <1>; |
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}; |
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sys_rst: reset { |
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compatible = "socionext,uniphier-sld8-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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nand: nand@68000000 { |
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compatible = "socionext,uniphier-denali-nand-v5a"; |
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status = "disabled"; |
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reg-names = "nand_data", "denali_reg"; |
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reg = <0x68000000 0x20>, <0x68100000 0x1000>; |
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interrupts = <0 65 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_nand2cs>; |
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clocks = <&sys_clk 2>; |
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resets = <&sys_rst 2>; |
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}; |
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}; |
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}; |
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#include "uniphier-pinctrl.dtsi" |