src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi - diff

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Diff for /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi between version 1.1.1.1 and 1.1.1.1.2.4

version 1.1.1.1, 2018/04/28 18:25:53

version 1.1.1.1.2.4, 2019/01/26 22:00:29

Line 11

* Compatible for Revisions 2GB: V1.2A

/ {

model = "Toradex Apalis TK1";

memory@80000000 {

compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",

"nvidia,tegra124";

memory {

reg = <0x0 0x80000000 0x0 0x80000000>;

};

pcie@1003000 {

status = "okay";

avddio-pex-supply = <&vdd_1v05>;

avddio-pex-supply = <&reg_1v05_vdd>;

avdd-pex-pll-supply = <&vdd_1v05>;

avdd-pex-pll-supply = <&reg_1v05_vdd>;

avdd-pll-erefe-supply = <&avdd_1v05>;

avdd-pll-erefe-supply = <&reg_1v05_avdd>;

dvddio-pex-supply = <&vdd_1v05>;

dvddio-pex-supply = <&reg_1v05_vdd>;

hvdd-pex-pll-e-supply = <&reg_3v3>;

hvdd-pex-pll-e-supply = <&reg_module_3v3>;

hvdd-pex-supply = <&reg_3v3>;

hvdd-pex-supply = <&reg_module_3v3>;

vddio-pex-ctl-supply = <&reg_3v3>;

vddio-pex-ctl-supply = <&reg_module_3v3>;

/* Apalis PCIe (additional lane Apalis type specific) */

pci@1,0 {

Line 42

Line 38

phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;

phy-names = "pcie-0";

status = "okay";

pcie@0 {

reg = <0 0 0 0 0>;

local-mac-address = [00 00 00 00 00 00];

};

host1x@50000000 {

hdmi@54280000 {

pll-supply = <&reg_1v05_avdd_hdmi_pll>;

vdd-supply = <&reg_3v3_avdd_hdmi>;

nvidia,ddc-i2c-bus = <&hdmi_ddc>;

nvidia,hpd-gpio =

<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;

pll-supply = <&reg_1v05_avdd_hdmi_pll>;

vdd-supply = <&reg_3v3_avdd_hdmi>;

};

Line 60

Line 61

* Node left disabled on purpose - the bootloader will enable

* it after having set the VPR up

vdd-supply = <&vdd_gpu>;

vdd-supply = <&reg_vdd_gpu>;

};

pinmux: pinmux@70000868 {

pinmux@70000868 {

pinctrl-names = "default";

pinctrl-0 = <&state_default>;

state_default: pinmux {

/* Analogue Audio (On-module) */

dap3_fs_pp0 {

dap3-fs-pp0 {

nvidia,pins = "dap3_fs_pp0";

nvidia,function = "i2s2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap3_din_pp1 {

dap3-din-pp1 {

nvidia,pins = "dap3_din_pp1";

nvidia,function = "i2s2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

dap3_dout_pp2 {

dap3-dout-pp2 {

nvidia,pins = "dap3_dout_pp2";

nvidia,function = "i2s2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap3_sclk_pp3 {

dap3-sclk-pp3 {

nvidia,pins = "dap3_sclk_pp3";

nvidia,function = "i2s2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap_mclk1_pw4 {

dap-mclk1-pw4 {

nvidia,pins = "dap_mclk1_pw4";

nvidia,function = "extperiph1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 124

Line 125

};

/* Apalis CAM1_MCLK */

cam_mclk_pcc0 {

cam-mclk-pcc0 {

nvidia,pins = "cam_mclk_pcc0";

nvidia,function = "vi_alt3";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 133

Line 134

};

/* Apalis Digital Audio */

dap2_fs_pa2 {

dap2-fs-pa2 {

nvidia,pins = "dap2_fs_pa2";

nvidia,function = "hda";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

dap2_sclk_pa3 {

dap2-sclk-pa3 {

nvidia,pins = "dap2_sclk_pa3";

nvidia,function = "hda";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

dap2_din_pa4 {

dap2-din-pa4 {

nvidia,pins = "dap2_din_pa4";

nvidia,function = "hda";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

dap2_dout_pa5 {

dap2-dout-pa5 {

nvidia,pins = "dap2_dout_pa5";

nvidia,function = "hda";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 167

Line 168

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

clk3_out_pee0 {

clk3-out-pee0 {

nvidia,pins = "clk3_out_pee0";

nvidia,function = "extperiph3";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 176

Line 177

};

/* Apalis GPIO */

usb_vbus_en0_pn4 {

usb-vbus-en0-pn4 {

nvidia,pins = "usb_vbus_en0_pn4";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 184

Line 185

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

nvidia,open-drain = <TEGRA_PIN_DISABLE>;

};

usb_vbus_en1_pn5 {

usb-vbus-en1-pn5 {

nvidia,pins = "usb_vbus_en1_pn5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 192

Line 193

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

nvidia,open-drain = <TEGRA_PIN_DISABLE>;

};

pex_l0_rst_n_pdd1 {

pex-l0-rst-n-pdd1 {

nvidia,pins = "pex_l0_rst_n_pdd1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

pex_l0_clkreq_n_pdd2 {

pex-l0-clkreq-n-pdd2 {

nvidia,pins = "pex_l0_clkreq_n_pdd2";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

pex_l1_rst_n_pdd5 {

pex-l1-rst-n-pdd5 {

nvidia,pins = "pex_l1_rst_n_pdd5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

pex_l1_clkreq_n_pdd6 {

pex-l1-clkreq-n-pdd6 {

nvidia,pins = "pex_l1_clkreq_n_pdd6";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

dp_hpd_pff0 {

dp-hpd-pff0 {

nvidia,pins = "dp_hpd_pff0";

nvidia,function = "dp";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 244

Line 245

};

/* Apalis HDMI1_CEC */

hdmi_cec_pee3 {

hdmi-cec-pee3 {

nvidia,pins = "hdmi_cec_pee3";

nvidia,function = "cec";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 254

Line 255

};

/* Apalis HDMI1_HPD */

hdmi_int_pn7 {

hdmi-int-pn7 {

nvidia,pins = "hdmi_int_pn7";

nvidia,function = "rsvd1";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

Line 264

Line 265

};

/* Apalis I2C1 */

gen1_i2c_scl_pc4 {

gen1-i2c-scl-pc4 {

nvidia,pins = "gen1_i2c_scl_pc4";

nvidia,function = "i2c1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 272

Line 273

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

nvidia,open-drain = <TEGRA_PIN_ENABLE>;

};

gen1_i2c_sda_pc5 {

gen1-i2c-sda-pc5 {

nvidia,pins = "gen1_i2c_sda_pc5";

nvidia,function = "i2c1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 282

Line 283

};

/* Apalis I2C3 (CAM) */

cam_i2c_scl_pbb1 {

cam-i2c-scl-pbb1 {

nvidia,pins = "cam_i2c_scl_pbb1";

nvidia,function = "i2c3";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 290

Line 291

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

nvidia,open-drain = <TEGRA_PIN_ENABLE>;

};

cam_i2c_sda_pbb2 {

cam-i2c-sda-pbb2 {

nvidia,pins = "cam_i2c_sda_pbb2";

nvidia,function = "i2c3";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 300

Line 301

};

/* Apalis I2C4 (DDC) */

ddc_scl_pv4 {

ddc-scl-pv4 {

nvidia,pins = "ddc_scl_pv4";

nvidia,function = "i2c4";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 308

Line 309

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;

};

ddc_sda_pv5 {

ddc-sda-pv5 {

nvidia,pins = "ddc_sda_pv5";

nvidia,function = "i2c4";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 318

Line 319

};

/* Apalis MMC1 */

sdmmc1_cd_n_pv3 { /* CD# GPIO */

sdmmc1-cd-n-pv3 { /* CD# GPIO */

nvidia,pins = "sdmmc1_wp_n_pv3";

nvidia,function = "sdmmc1";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

clk2_out_pw5 { /* D5 GPIO */

clk2-out-pw5 { /* D5 GPIO */

nvidia,pins = "clk2_out_pw5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc1_dat3_py4 {

sdmmc1-dat3-py4 {

nvidia,pins = "sdmmc1_dat3_py4";

nvidia,function = "sdmmc1";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc1_dat2_py5 {

sdmmc1-dat2-py5 {

nvidia,pins = "sdmmc1_dat2_py5";

nvidia,function = "sdmmc1";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc1_dat1_py6 {

sdmmc1-dat1-py6 {

nvidia,pins = "sdmmc1_dat1_py6";

nvidia,function = "sdmmc1";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc1_dat0_py7 {

sdmmc1-dat0-py7 {

nvidia,pins = "sdmmc1_dat0_py7";

nvidia,function = "sdmmc1";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc1_clk_pz0 {

sdmmc1-clk-pz0 {

nvidia,pins = "sdmmc1_clk_pz0";

nvidia,function = "sdmmc1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc1_cmd_pz1 {

sdmmc1-cmd-pz1 {

nvidia,pins = "sdmmc1_cmd_pz1";

nvidia,function = "sdmmc1";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

clk2_req_pcc5 { /* D4 GPIO */

clk2-req-pcc5 { /* D4 GPIO */

nvidia,pins = "clk2_req_pcc5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */

sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */

nvidia,pins = "sdmmc3_clk_lb_in_pee5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

usb_vbus_en2_pff1 { /* D7 GPIO */

usb-vbus-en2-pff1 { /* D7 GPIO */

nvidia,pins = "usb_vbus_en2_pff1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 428

Line 429

};

/* Apalis SATA1_ACT# */

dap1_dout_pn2 {

dap1-dout-pn2 {

nvidia,pins = "dap1_dout_pn2";

nvidia,function = "gmi";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 437

Line 438

};

/* Apalis SD1 */

sdmmc3_clk_pa6 {

sdmmc3-clk-pa6 {

nvidia,pins = "sdmmc3_clk_pa6";

nvidia,function = "sdmmc3";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc3_cmd_pa7 {

sdmmc3-cmd-pa7 {

nvidia,pins = "sdmmc3_cmd_pa7";

nvidia,function = "sdmmc3";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc3_dat3_pb4 {

sdmmc3-dat3-pb4 {

nvidia,pins = "sdmmc3_dat3_pb4";

nvidia,function = "sdmmc3";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc3_dat2_pb5 {

sdmmc3-dat2-pb5 {

nvidia,pins = "sdmmc3_dat2_pb5";

nvidia,function = "sdmmc3";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc3_dat1_pb6 {

sdmmc3-dat1-pb6 {

nvidia,pins = "sdmmc3_dat1_pb6";

nvidia,function = "sdmmc3";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc3_dat0_pb7 {

sdmmc3-dat0-pb7 {

nvidia,pins = "sdmmc3_dat0_pb7";

nvidia,function = "sdmmc3";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc3_cd_n_pv2 { /* CD# GPIO */

sdmmc3-cd-n-pv2 { /* CD# GPIO */

nvidia,pins = "sdmmc3_cd_n_pv2";

nvidia,function = "rsvd3";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 488

Line 489

};

/* Apalis SPDIF */

spdif_out_pk5 {

spdif-out-pk5 {

nvidia,pins = "spdif_out_pk5";

nvidia,function = "spdif";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

spdif_in_pk6 {

spdif-in-pk6 {

nvidia,pins = "spdif_in_pk6";

nvidia,function = "spdif";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 504

Line 505

};

/* Apalis SPI1 */

ulpi_clk_py0 {

ulpi-clk-py0 {

nvidia,pins = "ulpi_clk_py0";

nvidia,function = "spi1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_dir_py1 {

ulpi-dir-py1 {

nvidia,pins = "ulpi_dir_py1";

nvidia,function = "spi1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

ulpi_nxt_py2 {

ulpi-nxt-py2 {

nvidia,pins = "ulpi_nxt_py2";

nvidia,function = "spi1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_stp_py3 {

ulpi-stp-py3 {

nvidia,pins = "ulpi_stp_py3";

nvidia,function = "spi1";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 578

Line 579

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

uart1_txd_pu0 {

uart1-txd-pu0 {

nvidia,pins = "pu0";

nvidia,function = "uarta";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

uart1_rxd_pu1 {

uart1-rxd-pu1 {

nvidia,pins = "pu1";

nvidia,function = "uarta";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

uart1_cts_n_pu2 {

uart1-cts-n-pu2 {

nvidia,pins = "pu2";

nvidia,function = "uarta";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

uart1_rts_n_pu3 {

uart1-rts-n-pu3 {

nvidia,pins = "pu3";

nvidia,function = "uarta";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

uart3_cts_n_pa1 { /* DSR GPIO */

uart3-cts-n-pa1 { /* DSR GPIO */

nvidia,pins = "uart3_cts_n_pa1";

nvidia,function = "gmi";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

uart3_rts_n_pc0 { /* DTR GPIO */

uart3-rts-n-pc0 { /* DTR GPIO */

nvidia,pins = "uart3_rts_n_pc0";

nvidia,function = "gmi";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 622

Line 623

};

/* Apalis UART2 */

uart2_txd_pc2 {

uart2-txd-pc2 {

nvidia,pins = "uart2_txd_pc2";

nvidia,function = "irda";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

uart2_rxd_pc3 {

uart2-rxd-pc3 {

nvidia,pins = "uart2_rxd_pc3";

nvidia,function = "irda";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

uart2_cts_n_pj5 {

uart2-cts-n-pj5 {

nvidia,pins = "uart2_cts_n_pj5";

nvidia,function = "uartb";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

uart2_rts_n_pj6 {

uart2-rts-n-pj6 {

nvidia,pins = "uart2_rts_n_pj6";

nvidia,function = "uartb";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 652

Line 653

};

/* Apalis UART3 */

uart3_txd_pw6 {

uart3-txd-pw6 {

nvidia,pins = "uart3_txd_pw6";

nvidia,function = "uartc";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

uart3_rxd_pw7 {

uart3-rxd-pw7 {

nvidia,pins = "uart3_rxd_pw7";

nvidia,function = "uartc";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 668

Line 669

};

/* Apalis UART4 */

uart4_rxd_pb0 {

uart4-rxd-pb0 {

nvidia,pins = "pb0";

nvidia,function = "uartd";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

uart4_txd_pj7 {

uart4-txd-pj7 {

nvidia,pins = "pj7";

nvidia,function = "uartd";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 684

Line 685

};

/* Apalis USBH_EN */

gen2_i2c_sda_pt6 {

gen2-i2c-sda-pt6 {

nvidia,pins = "gen2_i2c_sda_pt6";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 703

Line 704

};

/* Apalis USBO1_EN */

gen2_i2c_scl_pt5 {

gen2-i2c-scl-pt5 {

nvidia,pins = "gen2_i2c_scl_pt5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 722

Line 723

};

/* Apalis WAKE1_MICO */

pex_wake_n_pdd3 {

pex-wake-n-pdd3 {

nvidia,pins = "pex_wake_n_pdd3";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 731

Line 732

};

/* CORE_PWR_REQ */

core_pwr_req {

core-pwr-req {

nvidia,pins = "core_pwr_req";

nvidia,function = "pwron";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 740

Line 741

};

/* CPU_PWR_REQ */

cpu_pwr_req {

cpu-pwr-req {

nvidia,pins = "cpu_pwr_req";

nvidia,function = "cpu";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 749

Line 750

};

/* DVFS */

dvfs_pwm_px0 {

dvfs-pwm-px0 {

nvidia,pins = "dvfs_pwm_px0";

nvidia,function = "cldvfs";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dvfs_clk_px2 {

dvfs-clk-px2 {

nvidia,pins = "dvfs_clk_px2";

nvidia,function = "cldvfs";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 765

Line 766

};

/* eMMC */

sdmmc4_dat0_paa0 {

sdmmc4-dat0-paa0 {

nvidia,pins = "sdmmc4_dat0_paa0";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_dat1_paa1 {

sdmmc4-dat1-paa1 {

nvidia,pins = "sdmmc4_dat1_paa1";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_dat2_paa2 {

sdmmc4-dat2-paa2 {

nvidia,pins = "sdmmc4_dat2_paa2";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_dat3_paa3 {

sdmmc4-dat3-paa3 {

nvidia,pins = "sdmmc4_dat3_paa3";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_dat4_paa4 {

sdmmc4-dat4-paa4 {

nvidia,pins = "sdmmc4_dat4_paa4";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_dat5_paa5 {

sdmmc4-dat5-paa5 {

nvidia,pins = "sdmmc4_dat5_paa5";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_dat6_paa6 {

sdmmc4-dat6-paa6 {

nvidia,pins = "sdmmc4_dat6_paa6";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_dat7_paa7 {

sdmmc4-dat7-paa7 {

nvidia,pins = "sdmmc4_dat7_paa7";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_clk_pcc4 {

sdmmc4-clk-pcc4 {

nvidia,pins = "sdmmc4_clk_pcc4";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

sdmmc4_cmd_pt7 {

sdmmc4-cmd-pt7 {

nvidia,pins = "sdmmc4_cmd_pt7";

nvidia,function = "sdmmc4";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 837

Line 838

};

/* JTAG_RTCK */

jtag_rtck {

jtag-rtck {

nvidia,pins = "jtag_rtck";

nvidia,function = "rtck";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 846

Line 847

};

/* LAN_DEV_OFF# */

ulpi_data5_po6 {

ulpi-data5-po6 {

nvidia,pins = "ulpi_data5_po6";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 855

Line 856

};

/* LAN_RESET# */

kb_row10_ps2 {

kb-row10-ps2 {

nvidia,pins = "kb_row10_ps2";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 864

Line 865

};

/* LAN_WAKE# */

ulpi_data4_po5 {

ulpi-data4-po5 {

nvidia,pins = "ulpi_data4_po5";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 918

Line 919

};

/* MCU SPI */

gpio_x4_aud_px4 {

gpio-x4-aud-px4 {

nvidia,pins = "gpio_x4_aud_px4";

nvidia,function = "spi2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

gpio_x5_aud_px5 {

gpio-x5-aud-px5 {

nvidia,pins = "gpio_x5_aud_px5";

nvidia,function = "spi2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

gpio_x6_aud_px6 { /* MCU_CS */

gpio-x6-aud-px6 { /* MCU_CS */

nvidia,pins = "gpio_x6_aud_px6";

nvidia,function = "spi2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_DISABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

gpio_x7_aud_px7 {

gpio-x7-aud-px7 {

nvidia,pins = "gpio_x7_aud_px7";

nvidia,function = "spi2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

};

gpio_w2_aud_pw2 { /* MCU_CSEZP */

gpio-w2-aud-pw2 { /* MCU_CSEZP */

nvidia,pins = "gpio_w2_aud_pw2";

nvidia,function = "spi2";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 955

Line 956

};

/* PMIC_CLK_32K */

clk_32k_in {

clk-32k-in {

nvidia,pins = "clk_32k_in";

nvidia,function = "clk";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 964

Line 965

};

/* PMIC_CPU_OC_INT */

clk_32k_out_pa0 {

clk-32k-out-pa0 {

nvidia,pins = "clk_32k_out_pa0";

nvidia,function = "soc";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 973

Line 974

};

/* PWR_I2C */

pwr_i2c_scl_pz6 {

pwr-i2c-scl-pz6 {

nvidia,pins = "pwr_i2c_scl_pz6";

nvidia,function = "i2cpwr";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 981

Line 982

nvidia,enable-input = <TEGRA_PIN_ENABLE>;

nvidia,open-drain = <TEGRA_PIN_ENABLE>;

};

pwr_i2c_sda_pz7 {

pwr-i2c-sda-pz7 {

nvidia,pins = "pwr_i2c_sda_pz7";

nvidia,function = "i2cpwr";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 991

Line 992

};

/* PWR_INT_N */

pwr_int_n {

pwr-int-n {

nvidia,pins = "pwr_int_n";

nvidia,function = "pmi";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 1009

Line 1010

};

/* RESET_OUT_N */

reset_out_n {

reset-out-n {

nvidia,pins = "reset_out_n";

nvidia,function = "reset_out_n";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 1018

Line 1019

};

/* SHIFT_CTRL_DIR_IN */

kb_row0_pr0 {

kb-row0-pr0 {

nvidia,pins = "kb_row0_pr0";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row1_pr1 {

kb-row1-pr1 {

nvidia,pins = "kb_row1_pr1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

Line 1034

Line 1035

};

/* Configure level-shifter as output for HDA */

kb_row11_ps3 {

kb-row11-ps3 {

nvidia,pins = "kb_row11_ps3";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 1043

Line 1044

};

/* SHIFT_CTRL_DIR_OUT */

kb_col5_pq5 {

kb-col5-pq5 {

nvidia,pins = "kb_col5_pq5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_col6_pq6 {

kb-col6-pq6 {

nvidia,pins = "kb_col6_pq6";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_col7_pq7 {

kb-col7-pq7 {

nvidia,pins = "kb_col7_pq7";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_UP>;

Line 1066

Line 1067

};

/* SHIFT_CTRL_OE */

kb_col0_pq0 {

kb-col0-pq0 {

nvidia,pins = "kb_col0_pq0";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_col1_pq1 {

kb-col1-pq1 {

nvidia,pins = "kb_col1_pq1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_col2_pq2 {

kb-col2-pq2 {

nvidia,pins = "kb_col2_pq2";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_col4_pq4 {

kb-col4-pq4 {

nvidia,pins = "kb_col4_pq4";

nvidia,function = "kbc";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row2_pr2 {

kb-row2-pr2 {

nvidia,pins = "kb_row2_pr2";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

Line 1112

Line 1113

};

/* TOUCH_INT */

gpio_w3_aud_pw3 {

gpio-w3-aud-pw3 {

nvidia,pins = "gpio_w3_aud_pw3";

nvidia,function = "spi6";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 1253

Line 1254

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap1_fs_pn0 { /* NC */

dap1-fs-pn0 { /* NC */

nvidia,pins = "dap1_fs_pn0";

nvidia,function = "rsvd4";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap1_din_pn1 { /* NC */

dap1-din-pn1 { /* NC */

nvidia,pins = "dap1_din_pn1";

nvidia,function = "rsvd4";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap1_sclk_pn3 { /* NC */

dap1-sclk-pn3 { /* NC */

nvidia,pins = "dap1_sclk_pn3";

nvidia,function = "rsvd4";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_data7_po0 { /* NC */

ulpi-data7-po0 { /* NC */

nvidia,pins = "ulpi_data7_po0";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_data0_po1 { /* NC */

ulpi-data0-po1 { /* NC */

nvidia,pins = "ulpi_data0_po1";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_data1_po2 { /* NC */

ulpi-data1-po2 { /* NC */

nvidia,pins = "ulpi_data1_po2";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_data2_po3 { /* NC */

ulpi-data2-po3 { /* NC */

nvidia,pins = "ulpi_data2_po3";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_data3_po4 { /* NC */

ulpi-data3-po4 { /* NC */

nvidia,pins = "ulpi_data3_po4";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

ulpi_data6_po7 { /* NC */

ulpi-data6-po7 { /* NC */

nvidia,pins = "ulpi_data6_po7";

nvidia,function = "ulpi";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap4_fs_pp4 { /* NC */

dap4-fs-pp4 { /* NC */

nvidia,pins = "dap4_fs_pp4";

nvidia,function = "rsvd4";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap4_din_pp5 { /* NC */

dap4-din-pp5 { /* NC */

nvidia,pins = "dap4_din_pp5";

nvidia,function = "rsvd3";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap4_dout_pp6 { /* NC */

dap4-dout-pp6 { /* NC */

nvidia,pins = "dap4_dout_pp6";

nvidia,function = "rsvd4";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap4_sclk_pp7 { /* NC */

dap4-sclk-pp7 { /* NC */

nvidia,pins = "dap4_sclk_pp7";

nvidia,function = "rsvd3";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_col3_pq3 { /* NC */

kb-col3-pq3 { /* NC */

nvidia,pins = "kb_col3_pq3";

nvidia,function = "kbc";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row3_pr3 { /* NC */

kb-row3-pr3 { /* NC */

nvidia,pins = "kb_row3_pr3";

nvidia,function = "kbc";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row4_pr4 { /* NC */

kb-row4-pr4 { /* NC */

nvidia,pins = "kb_row4_pr4";

nvidia,function = "rsvd3";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row5_pr5 { /* NC */

kb-row5-pr5 { /* NC */

nvidia,pins = "kb_row5_pr5";

nvidia,function = "rsvd3";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row6_pr6 { /* NC */

kb-row6-pr6 { /* NC */

nvidia,pins = "kb_row6_pr6";

nvidia,function = "kbc";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row7_pr7 { /* NC */

kb-row7-pr7 { /* NC */

nvidia,pins = "kb_row7_pr7";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row8_ps0 { /* NC */

kb-row8-ps0 { /* NC */

nvidia,pins = "kb_row8_ps0";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row9_ps1 { /* NC */

kb-row9-ps1 { /* NC */

nvidia,pins = "kb_row9_ps1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row12_ps4 { /* NC */

kb-row12-ps4 { /* NC */

nvidia,pins = "kb_row12_ps4";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row13_ps5 { /* NC */

kb-row13-ps5 { /* NC */

nvidia,pins = "kb_row13_ps5";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row14_ps6 { /* NC */

kb-row14-ps6 { /* NC */

nvidia,pins = "kb_row14_ps6";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row15_ps7 { /* NC */

kb-row15-ps7 { /* NC */

nvidia,pins = "kb_row15_ps7";

nvidia,function = "rsvd3";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row16_pt0 { /* NC */

kb-row16-pt0 { /* NC */

nvidia,pins = "kb_row16_pt0";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

kb_row17_pt1 { /* NC */

kb-row17-pt1 { /* NC */

nvidia,pins = "kb_row17_pt1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

Line 1467

Line 1468

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

gpio_x1_aud_px1 { /* NC */

gpio-x1-aud-px1 { /* NC */

nvidia,pins = "gpio_x1_aud_px1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

gpio_x3_aud_px3 { /* NC */

gpio-x3-aud-px3 { /* NC */

nvidia,pins = "gpio_x3_aud_px3";

nvidia,function = "rsvd4";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

Line 1502

Line 1503

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

clk3_req_pee1 { /* NC */

clk3-req-pee1 { /* NC */

nvidia,pins = "clk3_req_pee1";

nvidia,function = "rsvd2";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

nvidia,tristate = <TEGRA_PIN_ENABLE>;

nvidia,enable-input = <TEGRA_PIN_DISABLE>;

};

dap_mclk1_req_pee2 { /* NC */

dap-mclk1-req-pee2 { /* NC */

nvidia,pins = "dap_mclk1_req_pee2";

nvidia,function = "rsvd4";

nvidia,pull = <TEGRA_PIN_PULL_DOWN>;

Line 1525

Line 1526

* SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1

* bits being set to 0xfffd according to the TRM!

sdmmc3_clk_lb_out_pee4 { /* NC */

sdmmc3-clk-lb-out-pee4 { /* NC */

nvidia,pins = "sdmmc3_clk_lb_out_pee4";

nvidia,function = "sdmmc3";

nvidia,pull = <TEGRA_PIN_PULL_NONE>;

Line 1536

Line 1537

};

serial@70006040 {

compatible = "nvidia,tegra124-hsuart";

compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";

};

serial@70006200 {

compatible = "nvidia,tegra124-hsuart";

compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";

};

serial@70006300 {

compatible = "nvidia,tegra124-hsuart";

compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";

};

hdmi_ddc: i2c@7000c700 {

Line 1560

Line 1561

sgtl5000: codec@a {

compatible = "fsl,sgtl5000";

reg = <0x0a>;

VDDA-supply = <&reg_3v3>;

VDDA-supply = <&reg_module_3v3_audio>;

VDDIO-supply = <&vddio_1v8>;

VDDD-supply = <&reg_1v8_vddio>;

VDDIO-supply = <&reg_1v8_vddio>;

clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;

};

Line 1578

Line 1580

pinctrl-0 = <&as3722_default>;

as3722_default: pinmux {

gpio2_7 {

gpio2-7 {

pins = "gpio2", /* PWR_EN_+V3.3 */

"gpio7"; /* +V1.6_LPO */

function = "gpio";

bias-pull-up;

};

gpio0_1_3_4_5_6 {

gpio0-1-3-4-5-6 {

pins = "gpio0", "gpio1", "gpio3",

"gpio4", "gpio5", "gpio6";

bias-high-impedance;

Line 1593

Line 1595

};

regulators {

vsup-sd2-supply = <&reg_3v3>;

vsup-sd2-supply = <&reg_module_3v3>;

vsup-sd3-supply = <&reg_3v3>;

vsup-sd3-supply = <&reg_module_3v3>;

vsup-sd4-supply = <&reg_3v3>;

vsup-sd4-supply = <&reg_module_3v3>;

vsup-sd5-supply = <&reg_3v3>;

vsup-sd5-supply = <&reg_module_3v3>;

vin-ldo0-supply = <&vddio_ddr_1v35>;

vin-ldo0-supply = <&reg_1v35_vddio_ddr>;

vin-ldo1-6-supply = <&reg_3v3>;

vin-ldo1-6-supply = <&reg_module_3v3>;

vin-ldo2-5-7-supply = <&vddio_1v8>;

vin-ldo2-5-7-supply = <&reg_1v8_vddio>;

vin-ldo3-4-supply = <&reg_3v3>;

vin-ldo3-4-supply = <&reg_module_3v3>;

vin-ldo9-10-supply = <&reg_3v3>;

vin-ldo9-10-supply = <&reg_module_3v3>;

vin-ldo11-supply = <&reg_3v3>;

vin-ldo11-supply = <&reg_module_3v3>;

vdd_cpu: sd0 {

reg_vdd_cpu: sd0 {

regulator-name = "+VDD_CPU_AP";

regulator-min-microvolt = <700000>;

regulator-max-microvolt = <1400000>;

Line 1626

Line 1628

ams,ext-control = <1>;

};

vddio_ddr_1v35: sd2 {

reg_1v35_vddio_ddr: sd2 {

regulator-name =

"+V1.35_VDDIO_DDR(sd2)";

regulator-min-microvolt = <1350000>;

Line 1644

Line 1646

regulator-boot-on;

};

vdd_1v05: sd4 {

reg_1v05_vdd: sd4 {

regulator-name = "+V1.05";

regulator-min-microvolt = <1050000>;

regulator-max-microvolt = <1050000>;

};

vddio_1v8: sd5 {

reg_1v8_vddio: sd5 {

regulator-name = "+V1.8";

regulator-min-microvolt = <1800000>;

regulator-max-microvolt = <1800000>;

Line 1658

Line 1660

regulator-always-on;

};

vdd_gpu: sd6 {

reg_vdd_gpu: sd6 {

regulator-name = "+VDD_GPU_AP";

regulator-min-microvolt = <650000>;

regulator-max-microvolt = <1200000>;

Line 1668

Line 1670

regulator-always-on;

};

avdd_1v05: ldo0 {

reg_1v05_avdd: ldo0 {

regulator-name = "+V1.05_AVDD";

regulator-min-microvolt = <1050000>;

regulator-max-microvolt = <1050000>;

Line 1743

Line 1745

* TMP451 temperature sensor

* Note: THERM_N directly connected to AS3722 PMIC THERM

temperature-sensor@4c {

temp-sensor@4c {

compatible = "ti,tmp451";

reg = <0x4c>;

interrupt-parent = <&gpio>;

interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;

#thermal-sensor-cells = <1>;

vcc-supply = <&reg_module_3v3>;

};

Line 1780

Line 1783

sata@70020000 {

phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;

phy-names = "sata-0";

avdd-supply = <&vdd_1v05>;

avdd-supply = <&reg_1v05_vdd>;

hvdd-supply = <&reg_3v3>;

hvdd-supply = <&reg_module_3v3>;

vddio-supply = <&vdd_1v05>;

vddio-supply = <&reg_1v05_vdd>;

};

usb@70090000 {

Line 1793

Line 1796

<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,

<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;

phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";

avddio-pex-supply = <&vdd_1v05>;

avddio-pex-supply = <&reg_1v05_vdd>;

avdd-pll-erefe-supply = <&avdd_1v05>;

avdd-pll-erefe-supply = <&reg_1v05_avdd>;

avdd-pll-utmip-supply = <&vddio_1v8>;

avdd-pll-utmip-supply = <&reg_1v8_vddio>;

avdd-usb-ss-pll-supply = <&vdd_1v05>;

avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;

avdd-usb-supply = <&reg_3v3>;

avdd-usb-supply = <&reg_module_3v3>;

dvddio-pex-supply = <&vdd_1v05>;

dvddio-pex-supply = <&reg_1v05_vdd>;

hvdd-usb-ss-pll-e-supply = <&reg_3v3>;

hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;

hvdd-usb-ss-supply = <&reg_3v3>;

hvdd-usb-ss-supply = <&reg_module_3v3>;

};

padctl@7009f000 {

Line 1810

Line 1813

lanes {

usb2-0 {

nvidia,function = "xusb";

status = "okay";

nvidia,function = "xusb";

};

usb2-1 {

nvidia,function = "xusb";

status = "okay";

nvidia,function = "xusb";

};

usb2-2 {

nvidia,function = "xusb";

status = "okay";

nvidia,function = "xusb";

};

Line 1831

Line 1834

lanes {

pcie-0 {

nvidia,function = "usb3-ss";

status = "okay";

nvidia,function = "usb3-ss";

};

pcie-1 {

nvidia,function = "usb3-ss";

status = "okay";

nvidia,function = "usb3-ss";

};

pcie-2 {

nvidia,function = "pcie";

status = "okay";

nvidia,function = "pcie";

};

pcie-3 {

nvidia,function = "pcie";

status = "okay";

nvidia,function = "pcie";

};

pcie-4 {

nvidia,function = "pcie";

status = "okay";

nvidia,function = "pcie";

};

Line 1862

Line 1865

lanes {

sata-0 {

nvidia,function = "sata";

status = "okay";

nvidia,function = "sata";

};

Line 1874

Line 1877

usb2-0 {

status = "okay";

mode = "otg";

vbus-supply = <&reg_usbo1_vbus>;

};

Line 1882

Line 1884

usb2-1 {

status = "okay";

mode = "host";

vbus-supply = <&reg_usbh_vbus>;

};

Line 1890

Line 1891

usb2-2 {

status = "okay";

mode = "host";

vbus-supply = <&reg_usbh_vbus>;

};

usb3-0 {

nvidia,usb2-companion = <2>;

status = "okay";

nvidia,usb2-companion = <2>;

vbus-supply = <&reg_usbh_vbus>;

};

usb3-1 {

nvidia,usb2-companion = <0>;

status = "okay";

nvidia,usb2-companion = <0>;

vbus-supply = <&reg_usbo1_vbus>;

};

Line 1911

Line 1913

status = "okay";

bus-width = <8>;

non-removable;

vmmc-supply = <&reg_module_3v3>; /* VCC */

vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */

mmc-ddr-1_8v;

};

/* CPU DFLL clock */

clock@70110000 {

status = "okay";

vdd-cpu-supply = <&vdd_cpu>;

nvidia,i2c-fs-rate = <400000>;

vdd-cpu-supply = <&reg_vdd_cpu>;

};

ahub@70300000 {

Line 1926

Line 1931

};

clocks {

clk32k_in: osc3 {

compatible = "simple-bus";

compatible = "fixed-clock";

#address-cells = <1>;

#clock-cells = <0>;

#size-cells = <0>;

clock-frequency = <32768>;

clk32k_in: clock@0 {

compatible = "fixed-clock";

reg = <0>;

#clock-cells = <0>;

clock-frequency = <32768>;

};

cpus {

cpu@0 {

vdd-cpu-supply = <&vdd_cpu>;

vdd-cpu-supply = <&reg_vdd_cpu>;

};

Line 1951

Line 1949

regulator-min-microvolt = <1050000>;

regulator-max-microvolt = <1050000>;

gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;

vin-supply = <&vdd_1v05>;

vin-supply = <&reg_1v05_vdd>;

};

reg_3v3_mxm: regulator-3v3-mxm {

Line 1963

Line 1961

regulator-boot-on;

};

reg_3v3: regulator-3v3 {

reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {

compatible = "regulator-fixed";

regulator-name = "+V3.3_AVDD_HDMI";

regulator-min-microvolt = <3300000>;

regulator-max-microvolt = <3300000>;

vin-supply = <&reg_1v05_vdd>;

};

reg_module_3v3: regulator-module-3v3 {

compatible = "regulator-fixed";

regulator-name = "+V3.3";

regulator-min-microvolt = <3300000>;

Line 1976

Line 1982

vin-supply = <&reg_3v3_mxm>;

};

reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {

reg_module_3v3_audio: regulator-module-3v3-audio {

compatible = "regulator-fixed";

regulator-name = "+V3.3_AVDD_HDMI";

regulator-name = "+V3.3_AUDIO_AVDD_S";

regulator-min-microvolt = <3300000>;

regulator-max-microvolt = <3300000>;

vin-supply = <&vdd_1v05>;

regulator-always-on;

};

sound {

Line 2035

Line 2041

&gpio {

/* I210 Gigabit Ethernet Controller Reset */

lan_reset_n {

lan-reset-n {

gpio-hog;

gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;

output-high;

Line 2043

Line 2049

};

/* Control MXM3 pin 26 Reset Module Output Carrier Input */

reset_moci_ctrl {

reset-moci-ctrl {

gpio-hog;

gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;

output-high;

CVSweb <webmaster@jp.NetBSD.org>