src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/r8a7794.dtsi - diff

Return to r8a7794.dtsi CVS log

Up to [cvs.NetBSD.org] / src / sys / external / gpl2 / dts / dist / arch / arm / boot / dts

Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.

Diff for /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/r8a7794.dtsi between version 1.1.1.7 and 1.1.1.8

version 1.1.1.7, 2019/01/22 14:57:02

version 1.1.1.8, 2021/11/07 16:50:04

Line 62

cpus {

#address-cells = <1>;

#size-cells = <0>;

enable-method = "renesas,apmu";

cpu0: cpu@0 {

device_type = "cpu";

Line 71

Line 70

clock-frequency = <1000000000>;

clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;

power-domains = <&sysc R8A7794_PD_CA7_CPU0>;

enable-method = "renesas,apmu";

next-level-cache = <&L2_CA7>;

};

Line 81

clock-frequency = <1000000000>;

clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;

power-domains = <&sysc R8A7794_PD_CA7_CPU1>;

enable-method = "renesas,apmu";

next-level-cache = <&L2_CA7>;

};

Line 238

Line 239

resets = <&cpg 905>;

};

pfc: pin-controller@e6060000 {

pfc: pinctrl@e6060000 {

compatible = "renesas,pfc-r8a7794";

reg = <0 0xe6060000 0 0x11c>;

};

Line 256

Line 257

apmu@e6151000 {

compatible = "renesas,r8a7794-apmu", "renesas,apmu";

reg = <0 0xe6151000 0 0x188>;

cpus = <&cpu0 &cpu1>;

cpus = <&cpu0>, <&cpu1>;

};

rst: reset-controller@e6160000 {

Line 290

Line 291

resets = <&cpg 407>;

};

ipmmu_sy0: mmu@e6280000 {

ipmmu_sy0: iommu@e6280000 {

compatible = "renesas,ipmmu-r8a7794",

"renesas,ipmmu-vmsa";

reg = <0 0xe6280000 0 0x1000>;

Line 300

Line 301

status = "disabled";

};

ipmmu_sy1: mmu@e6290000 {

ipmmu_sy1: iommu@e6290000 {

compatible = "renesas,ipmmu-r8a7794",

"renesas,ipmmu-vmsa";

reg = <0 0xe6290000 0 0x1000>;

Line 309

Line 310

status = "disabled";

};

ipmmu_ds: mmu@e6740000 {

ipmmu_ds: iommu@e6740000 {

compatible = "renesas,ipmmu-r8a7794",

"renesas,ipmmu-vmsa";

reg = <0 0xe6740000 0 0x1000>;

Line 319

Line 320

status = "disabled";

};

ipmmu_mp: mmu@ec680000 {

ipmmu_mp: iommu@ec680000 {

compatible = "renesas,ipmmu-r8a7794",

"renesas,ipmmu-vmsa";

reg = <0 0xec680000 0 0x1000>;

Line 328

Line 329

status = "disabled";

};

ipmmu_mx: mmu@fe951000 {

ipmmu_mx: iommu@fe951000 {

compatible = "renesas,ipmmu-r8a7794",

"renesas,ipmmu-vmsa";

reg = <0 0xfe951000 0 0x1000>;

Line 338

Line 339

status = "disabled";

};

ipmmu_gp: mmu@e62a0000 {

ipmmu_gp: iommu@e62a0000 {

compatible = "renesas,ipmmu-r8a7794",

"renesas,ipmmu-vmsa";

reg = <0 0xe62a0000 0 0x1000>;

Line 351

Line 352

icram0: sram@e63a0000 {

compatible = "mmio-sram";

reg = <0 0xe63a0000 0 0x12000>;

#address-cells = <1>;

#size-cells = <1>;

ranges = <0 0 0xe63a0000 0x12000>;

};

icram1: sram@e63c0000 {

Line 527

Line 531

compatible = "renesas,dmac-r8a7794",

"renesas,rcar-dmac";

reg = <0 0xe6700000 0 0x20000>;

interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH

interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;

<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;

interrupt-names = "error",

"ch0", "ch1", "ch2", "ch3",

"ch4", "ch5", "ch6", "ch7",

Line 560

Line 564

compatible = "renesas,dmac-r8a7794",

"renesas,rcar-dmac";

reg = <0 0xe6720000 0 0x20000>;

interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH

interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;

<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;

interrupt-names = "error",

"ch0", "ch1", "ch2", "ch3",

"ch4", "ch5", "ch6", "ch7",

Line 595

Line 599

reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;

interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&cpg CPG_MOD 812>;

clock-names = "fck";

power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;

resets = <&cpg 812>;

#address-cells = <1>;

Line 1132

Line 1137

compatible = "renesas,dmac-r8a7794",

"renesas,rcar-dmac";

reg = <0 0xec700000 0 0x10000>;

interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH

interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH

<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;

<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;

interrupt-names = "error",

"ch0", "ch1", "ch2", "ch3", "ch4",

"ch5", "ch6", "ch7", "ch8", "ch9",

Line 1176

Line 1181

#size-cells = <2>;

#interrupt-cells = <1>;

ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;

interrupt-map-mask = <0xff00 0 0 0x7>;

interrupt-map-mask = <0xf800 0 0 0x7>;

interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH

interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH

<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

usb@1,0 {

reg = <0x800 0 0 0 0>;

Line 1211

Line 1216

#size-cells = <2>;

#interrupt-cells = <1>;

ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;

interrupt-map-mask = <0xff00 0 0 0x7>;

interrupt-map-mask = <0xf800 0 0 0x7>;

interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH

interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH

<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

usb@1,0 {

reg = <0x10800 0 0 0 0>;

Line 1229

Line 1234

};

sdhi0: sd@ee100000 {

sdhi0: mmc@ee100000 {

compatible = "renesas,sdhi-r8a7794",

"renesas,rcar-gen2-sdhi";

reg = <0 0xee100000 0 0x328>;

Line 1244

Line 1249

status = "disabled";

};

sdhi1: sd@ee140000 {

sdhi1: mmc@ee140000 {

compatible = "renesas,sdhi-r8a7794",

"renesas,rcar-gen2-sdhi";

reg = <0 0xee140000 0 0x100>;

Line 1259

Line 1264

status = "disabled";

};

sdhi2: sd@ee160000 {

sdhi2: mmc@ee160000 {

compatible = "renesas,sdhi-r8a7794",

"renesas,rcar-gen2-sdhi";

reg = <0 0xee160000 0 0x100>;

Line 1353

Line 1358

<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;

clock-names = "du.0", "du.1";

resets = <&cpg 724>;

reset-names = "du.0";

status = "disabled";

ports {

CVSweb <webmaster@jp.NetBSD.org>