![[BACK]](/icons/back.gif){kind=icon}
Return to omap44xx-clocks.dtsi CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / external / gpl2 / dts / dist / arch / arm / boot / dts|
Return to omap44xx-clocks.dtsi CVS log | Up to [cvs.NetBSD.org] / src / sys / external / gpl2 / dts / dist / arch / arm / boot / dts |
1.1.1.4 skrll 1: // SPDX-License-Identifier: GPL-2.0-only
1.1 jmcneill 2: /*
3: * Device Tree Source for OMAP4 clock data
4: *
5: * Copyright (C) 2013 Texas Instruments, Inc.
6: */
7: &cm1_clocks {
8: extalt_clkin_ck: extalt_clkin_ck {
9: #clock-cells = <0>;
10: compatible = "fixed-clock";
11: clock-frequency = <59000000>;
12: };
13:
14: pad_clks_src_ck: pad_clks_src_ck {
15: #clock-cells = <0>;
16: compatible = "fixed-clock";
17: clock-frequency = <12000000>;
18: };
19:
20: pad_clks_ck: pad_clks_ck@108 {
21: #clock-cells = <0>;
22: compatible = "ti,gate-clock";
23: clocks = <&pad_clks_src_ck>;
24: ti,bit-shift = <8>;
25: reg = <0x0108>;
26: };
27:
28: pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
29: #clock-cells = <0>;
30: compatible = "fixed-clock";
31: clock-frequency = <12000000>;
32: };
33:
34: secure_32k_clk_src_ck: secure_32k_clk_src_ck {
35: #clock-cells = <0>;
36: compatible = "fixed-clock";
37: clock-frequency = <32768>;
38: };
39:
40: slimbus_src_clk: slimbus_src_clk {
41: #clock-cells = <0>;
42: compatible = "fixed-clock";
43: clock-frequency = <12000000>;
44: };
45:
46: slimbus_clk: slimbus_clk@108 {
47: #clock-cells = <0>;
48: compatible = "ti,gate-clock";
49: clocks = <&slimbus_src_clk>;
50: ti,bit-shift = <10>;
51: reg = <0x0108>;
52: };
53:
54: sys_32k_ck: sys_32k_ck {
55: #clock-cells = <0>;
56: compatible = "fixed-clock";
57: clock-frequency = <32768>;
58: };
59:
60: virt_12000000_ck: virt_12000000_ck {
61: #clock-cells = <0>;
62: compatible = "fixed-clock";
63: clock-frequency = <12000000>;
64: };
65:
66: virt_13000000_ck: virt_13000000_ck {
67: #clock-cells = <0>;
68: compatible = "fixed-clock";
69: clock-frequency = <13000000>;
70: };
71:
72: virt_16800000_ck: virt_16800000_ck {
73: #clock-cells = <0>;
74: compatible = "fixed-clock";
75: clock-frequency = <16800000>;
76: };
77:
78: virt_19200000_ck: virt_19200000_ck {
79: #clock-cells = <0>;
80: compatible = "fixed-clock";
81: clock-frequency = <19200000>;
82: };
83:
84: virt_26000000_ck: virt_26000000_ck {
85: #clock-cells = <0>;
86: compatible = "fixed-clock";
87: clock-frequency = <26000000>;
88: };
89:
90: virt_27000000_ck: virt_27000000_ck {
91: #clock-cells = <0>;
92: compatible = "fixed-clock";
93: clock-frequency = <27000000>;
94: };
95:
96: virt_38400000_ck: virt_38400000_ck {
97: #clock-cells = <0>;
98: compatible = "fixed-clock";
99: clock-frequency = <38400000>;
100: };
101:
102: tie_low_clock_ck: tie_low_clock_ck {
103: #clock-cells = <0>;
104: compatible = "fixed-clock";
105: clock-frequency = <0>;
106: };
107:
108: utmi_phy_clkout_ck: utmi_phy_clkout_ck {
109: #clock-cells = <0>;
110: compatible = "fixed-clock";
111: clock-frequency = <60000000>;
112: };
113:
114: xclk60mhsp1_ck: xclk60mhsp1_ck {
115: #clock-cells = <0>;
116: compatible = "fixed-clock";
117: clock-frequency = <60000000>;
118: };
119:
120: xclk60mhsp2_ck: xclk60mhsp2_ck {
121: #clock-cells = <0>;
122: compatible = "fixed-clock";
123: clock-frequency = <60000000>;
124: };
125:
126: xclk60motg_ck: xclk60motg_ck {
127: #clock-cells = <0>;
128: compatible = "fixed-clock";
129: clock-frequency = <60000000>;
130: };
131:
132: dpll_abe_ck: dpll_abe_ck@1e0 {
133: #clock-cells = <0>;
134: compatible = "ti,omap4-dpll-m4xen-clock";
135: clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
136: reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
137: };
138:
139: dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
140: #clock-cells = <0>;
141: compatible = "ti,omap4-dpll-x2-clock";
142: clocks = <&dpll_abe_ck>;
143: reg = <0x01f0>;
144: };
145:
146: dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
147: #clock-cells = <0>;
148: compatible = "ti,divider-clock";
149: clocks = <&dpll_abe_x2_ck>;
150: ti,max-div = <31>;
151: ti,autoidle-shift = <8>;
152: reg = <0x01f0>;
153: ti,index-starts-at-one;
154: ti,invert-autoidle-bit;
155: };
156:
157: abe_24m_fclk: abe_24m_fclk {
158: #clock-cells = <0>;
159: compatible = "fixed-factor-clock";
160: clocks = <&dpll_abe_m2x2_ck>;
161: clock-mult = <1>;
162: clock-div = <8>;
163: };
164:
165: abe_clk: abe_clk@108 {
166: #clock-cells = <0>;
167: compatible = "ti,divider-clock";
168: clocks = <&dpll_abe_m2x2_ck>;
169: ti,max-div = <4>;
170: reg = <0x0108>;
171: ti,index-power-of-two;
172: };
173:
174:
175: dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
176: #clock-cells = <0>;
177: compatible = "ti,divider-clock";
178: clocks = <&dpll_abe_x2_ck>;
179: ti,max-div = <31>;
180: ti,autoidle-shift = <8>;
181: reg = <0x01f4>;
182: ti,index-starts-at-one;
183: ti,invert-autoidle-bit;
184: };
185:
186: core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
187: #clock-cells = <0>;
188: compatible = "ti,mux-clock";
189: clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
190: ti,bit-shift = <23>;
191: reg = <0x012c>;
192: };
193:
194: dpll_core_ck: dpll_core_ck@120 {
195: #clock-cells = <0>;
196: compatible = "ti,omap4-dpll-core-clock";
197: clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
198: reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
199: };
200:
201: dpll_core_x2_ck: dpll_core_x2_ck {
202: #clock-cells = <0>;
203: compatible = "ti,omap4-dpll-x2-clock";
204: clocks = <&dpll_core_ck>;
205: };
206:
207: dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
208: #clock-cells = <0>;
209: compatible = "ti,divider-clock";
210: clocks = <&dpll_core_x2_ck>;
211: ti,max-div = <31>;
212: ti,autoidle-shift = <8>;
213: reg = <0x0140>;
214: ti,index-starts-at-one;
215: ti,invert-autoidle-bit;
216: };
217:
218: dpll_core_m2_ck: dpll_core_m2_ck@130 {
219: #clock-cells = <0>;
220: compatible = "ti,divider-clock";
221: clocks = <&dpll_core_ck>;
222: ti,max-div = <31>;
223: ti,autoidle-shift = <8>;
224: reg = <0x0130>;
225: ti,index-starts-at-one;
226: ti,invert-autoidle-bit;
227: };
228:
229: ddrphy_ck: ddrphy_ck {
230: #clock-cells = <0>;
231: compatible = "fixed-factor-clock";
232: clocks = <&dpll_core_m2_ck>;
233: clock-mult = <1>;
234: clock-div = <2>;
235: };
236:
237: dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
238: #clock-cells = <0>;
239: compatible = "ti,divider-clock";
240: clocks = <&dpll_core_x2_ck>;
241: ti,max-div = <31>;
242: ti,autoidle-shift = <8>;
243: reg = <0x013c>;
244: ti,index-starts-at-one;
245: ti,invert-autoidle-bit;
246: };
247:
248: div_core_ck: div_core_ck@100 {
249: #clock-cells = <0>;
250: compatible = "ti,divider-clock";
251: clocks = <&dpll_core_m5x2_ck>;
252: reg = <0x0100>;
253: ti,max-div = <2>;
254: };
255:
256: div_iva_hs_clk: div_iva_hs_clk@1dc {
257: #clock-cells = <0>;
258: compatible = "ti,divider-clock";
259: clocks = <&dpll_core_m5x2_ck>;
260: ti,max-div = <4>;
261: reg = <0x01dc>;
262: ti,index-power-of-two;
263: };
264:
265: div_mpu_hs_clk: div_mpu_hs_clk@19c {
266: #clock-cells = <0>;
267: compatible = "ti,divider-clock";
268: clocks = <&dpll_core_m5x2_ck>;
269: ti,max-div = <4>;
270: reg = <0x019c>;
271: ti,index-power-of-two;
272: };
273:
274: dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
275: #clock-cells = <0>;
276: compatible = "ti,divider-clock";
277: clocks = <&dpll_core_x2_ck>;
278: ti,max-div = <31>;
279: ti,autoidle-shift = <8>;
280: reg = <0x0138>;
281: ti,index-starts-at-one;
282: ti,invert-autoidle-bit;
283: };
284:
285: dll_clk_div_ck: dll_clk_div_ck {
286: #clock-cells = <0>;
287: compatible = "fixed-factor-clock";
288: clocks = <&dpll_core_m4x2_ck>;
289: clock-mult = <1>;
290: clock-div = <2>;
291: };
292:
293: dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
294: #clock-cells = <0>;
295: compatible = "ti,divider-clock";
296: clocks = <&dpll_abe_ck>;
297: ti,max-div = <31>;
298: reg = <0x01f0>;
299: ti,index-starts-at-one;
300: };
301:
302: dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
303: #clock-cells = <0>;
304: compatible = "ti,composite-no-wait-gate-clock";
305: clocks = <&dpll_core_x2_ck>;
306: ti,bit-shift = <8>;
307: reg = <0x0134>;
308: };
309:
310: dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
311: #clock-cells = <0>;
312: compatible = "ti,composite-divider-clock";
313: clocks = <&dpll_core_x2_ck>;
314: ti,max-div = <31>;
315: reg = <0x0134>;
316: ti,index-starts-at-one;
317: };
318:
319: dpll_core_m3x2_ck: dpll_core_m3x2_ck {
320: #clock-cells = <0>;
321: compatible = "ti,composite-clock";
322: clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
323: };
324:
325: dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
326: #clock-cells = <0>;
327: compatible = "ti,divider-clock";
328: clocks = <&dpll_core_x2_ck>;
329: ti,max-div = <31>;
330: ti,autoidle-shift = <8>;
331: reg = <0x0144>;
332: ti,index-starts-at-one;
333: ti,invert-autoidle-bit;
334: };
335:
336: iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
337: #clock-cells = <0>;
338: compatible = "ti,mux-clock";
339: clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
340: ti,bit-shift = <23>;
341: reg = <0x01ac>;
342: };
343:
344: dpll_iva_ck: dpll_iva_ck@1a0 {
345: #clock-cells = <0>;
346: compatible = "ti,omap4-dpll-clock";
347: clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
348: reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
1.1.1.2 jmcneill 349: assigned-clocks = <&dpll_iva_ck>;
350: assigned-clock-rates = <931200000>;
1.1 jmcneill 351: };
352:
353: dpll_iva_x2_ck: dpll_iva_x2_ck {
354: #clock-cells = <0>;
355: compatible = "ti,omap4-dpll-x2-clock";
356: clocks = <&dpll_iva_ck>;
357: };
358:
359: dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
360: #clock-cells = <0>;
361: compatible = "ti,divider-clock";
362: clocks = <&dpll_iva_x2_ck>;
363: ti,max-div = <31>;
364: ti,autoidle-shift = <8>;
365: reg = <0x01b8>;
366: ti,index-starts-at-one;
367: ti,invert-autoidle-bit;
1.1.1.2 jmcneill 368: assigned-clocks = <&dpll_iva_m4x2_ck>;
369: assigned-clock-rates = <465600000>;
1.1 jmcneill 370: };
371:
372: dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
373: #clock-cells = <0>;
374: compatible = "ti,divider-clock";
375: clocks = <&dpll_iva_x2_ck>;
376: ti,max-div = <31>;
377: ti,autoidle-shift = <8>;
378: reg = <0x01bc>;
379: ti,index-starts-at-one;
380: ti,invert-autoidle-bit;
1.1.1.2 jmcneill 381: assigned-clocks = <&dpll_iva_m5x2_ck>;
382: assigned-clock-rates = <266100000>;
1.1 jmcneill 383: };
384:
385: dpll_mpu_ck: dpll_mpu_ck@160 {
386: #clock-cells = <0>;
387: compatible = "ti,omap4-dpll-clock";
388: clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
389: reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
390: };
391:
392: dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
393: #clock-cells = <0>;
394: compatible = "ti,divider-clock";
395: clocks = <&dpll_mpu_ck>;
396: ti,max-div = <31>;
397: ti,autoidle-shift = <8>;
398: reg = <0x0170>;
399: ti,index-starts-at-one;
400: ti,invert-autoidle-bit;
401: };
402:
403: per_hs_clk_div_ck: per_hs_clk_div_ck {
404: #clock-cells = <0>;
405: compatible = "fixed-factor-clock";
406: clocks = <&dpll_abe_m3x2_ck>;
407: clock-mult = <1>;
408: clock-div = <2>;
409: };
410:
411: usb_hs_clk_div_ck: usb_hs_clk_div_ck {
412: #clock-cells = <0>;
413: compatible = "fixed-factor-clock";
414: clocks = <&dpll_abe_m3x2_ck>;
415: clock-mult = <1>;
416: clock-div = <3>;
417: };
418:
419: l3_div_ck: l3_div_ck@100 {
420: #clock-cells = <0>;
421: compatible = "ti,divider-clock";
422: clocks = <&div_core_ck>;
423: ti,bit-shift = <4>;
424: ti,max-div = <2>;
425: reg = <0x0100>;
426: };
427:
428: l4_div_ck: l4_div_ck@100 {
429: #clock-cells = <0>;
430: compatible = "ti,divider-clock";
431: clocks = <&l3_div_ck>;
432: ti,bit-shift = <8>;
433: ti,max-div = <2>;
434: reg = <0x0100>;
435: };
436:
437: lp_clk_div_ck: lp_clk_div_ck {
438: #clock-cells = <0>;
439: compatible = "fixed-factor-clock";
440: clocks = <&dpll_abe_m2x2_ck>;
441: clock-mult = <1>;
442: clock-div = <16>;
443: };
444:
445: mpu_periphclk: mpu_periphclk {
446: #clock-cells = <0>;
447: compatible = "fixed-factor-clock";
448: clocks = <&dpll_mpu_ck>;
449: clock-mult = <1>;
450: clock-div = <2>;
451: };
452:
453: ocp_abe_iclk: ocp_abe_iclk@528 {
454: #clock-cells = <0>;
455: compatible = "ti,divider-clock";
1.1.1.3 jmcneill 456: clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
1.1 jmcneill 457: ti,bit-shift = <24>;
458: reg = <0x0528>;
459: ti,dividers = <2>, <1>;
460: };
461:
462: per_abe_24m_fclk: per_abe_24m_fclk {
463: #clock-cells = <0>;
464: compatible = "fixed-factor-clock";
465: clocks = <&dpll_abe_m2_ck>;
466: clock-mult = <1>;
467: clock-div = <4>;
468: };
469:
470: dummy_ck: dummy_ck {
471: #clock-cells = <0>;
472: compatible = "fixed-clock";
473: clock-frequency = <0>;
474: };
475: };
1.1.1.3 jmcneill 476:
1.1 jmcneill 477: &prm_clocks {
478: sys_clkin_ck: sys_clkin_ck@110 {
479: #clock-cells = <0>;
480: compatible = "ti,mux-clock";
481: clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
482: reg = <0x0110>;
483: ti,index-starts-at-one;
484: };
485:
486: abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
487: #clock-cells = <0>;
488: compatible = "ti,mux-clock";
489: clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
490: ti,bit-shift = <24>;
491: reg = <0x0108>;
492: };
493:
494: abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
495: #clock-cells = <0>;
496: compatible = "ti,mux-clock";
497: clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
498: reg = <0x010c>;
499: };
500:
501: dbgclk_mux_ck: dbgclk_mux_ck {
502: #clock-cells = <0>;
503: compatible = "fixed-factor-clock";
504: clocks = <&sys_clkin_ck>;
505: clock-mult = <1>;
506: clock-div = <1>;
507: };
508:
509: l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
510: #clock-cells = <0>;
511: compatible = "ti,mux-clock";
512: clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
513: reg = <0x0108>;
514: };
515:
516: syc_clk_div_ck: syc_clk_div_ck@100 {
517: #clock-cells = <0>;
518: compatible = "ti,divider-clock";
519: clocks = <&sys_clkin_ck>;
520: reg = <0x0100>;
521: ti,max-div = <2>;
522: };
523:
524: usim_ck: usim_ck@1858 {
525: #clock-cells = <0>;
526: compatible = "ti,divider-clock";
527: clocks = <&dpll_per_m4x2_ck>;
528: ti,bit-shift = <24>;
529: reg = <0x1858>;
530: ti,dividers = <14>, <18>;
531: };
532:
533: usim_fclk: usim_fclk@1858 {
534: #clock-cells = <0>;
535: compatible = "ti,gate-clock";
536: clocks = <&usim_ck>;
537: ti,bit-shift = <8>;
538: reg = <0x1858>;
539: };
540:
541: trace_clk_div_ck: trace_clk_div_ck {
542: #clock-cells = <0>;
543: compatible = "ti,clkdm-gate-clock";
1.1.1.3 jmcneill 544: clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
1.1 jmcneill 545: };
546: };
547:
548: &prm_clockdomains {
549: emu_sys_clkdm: emu_sys_clkdm {
550: compatible = "ti,clockdomain";
551: clocks = <&trace_clk_div_ck>;
552: };
553: };
554:
555: &cm2_clocks {
556: per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
557: #clock-cells = <0>;
558: compatible = "ti,mux-clock";
559: clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
560: ti,bit-shift = <23>;
561: reg = <0x014c>;
562: };
563:
564: dpll_per_ck: dpll_per_ck@140 {
565: #clock-cells = <0>;
566: compatible = "ti,omap4-dpll-clock";
567: clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
568: reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
569: };
570:
571: dpll_per_m2_ck: dpll_per_m2_ck@150 {
572: #clock-cells = <0>;
573: compatible = "ti,divider-clock";
574: clocks = <&dpll_per_ck>;
575: ti,max-div = <31>;
576: reg = <0x0150>;
577: ti,index-starts-at-one;
578: };
579:
580: dpll_per_x2_ck: dpll_per_x2_ck@150 {
581: #clock-cells = <0>;
582: compatible = "ti,omap4-dpll-x2-clock";
583: clocks = <&dpll_per_ck>;
584: reg = <0x0150>;
585: };
586:
587: dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
588: #clock-cells = <0>;
589: compatible = "ti,divider-clock";
590: clocks = <&dpll_per_x2_ck>;
591: ti,max-div = <31>;
592: ti,autoidle-shift = <8>;
593: reg = <0x0150>;
594: ti,index-starts-at-one;
595: ti,invert-autoidle-bit;
596: };
597:
598: dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
599: #clock-cells = <0>;
600: compatible = "ti,composite-no-wait-gate-clock";
601: clocks = <&dpll_per_x2_ck>;
602: ti,bit-shift = <8>;
603: reg = <0x0154>;
604: };
605:
606: dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
607: #clock-cells = <0>;
608: compatible = "ti,composite-divider-clock";
609: clocks = <&dpll_per_x2_ck>;
610: ti,max-div = <31>;
611: reg = <0x0154>;
612: ti,index-starts-at-one;
613: };
614:
615: dpll_per_m3x2_ck: dpll_per_m3x2_ck {
616: #clock-cells = <0>;
617: compatible = "ti,composite-clock";
618: clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
619: };
620:
621: dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
622: #clock-cells = <0>;
623: compatible = "ti,divider-clock";
624: clocks = <&dpll_per_x2_ck>;
625: ti,max-div = <31>;
626: ti,autoidle-shift = <8>;
627: reg = <0x0158>;
628: ti,index-starts-at-one;
629: ti,invert-autoidle-bit;
630: };
631:
632: dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
633: #clock-cells = <0>;
634: compatible = "ti,divider-clock";
635: clocks = <&dpll_per_x2_ck>;
636: ti,max-div = <31>;
637: ti,autoidle-shift = <8>;
638: reg = <0x015c>;
639: ti,index-starts-at-one;
640: ti,invert-autoidle-bit;
641: };
642:
643: dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
644: #clock-cells = <0>;
645: compatible = "ti,divider-clock";
646: clocks = <&dpll_per_x2_ck>;
647: ti,max-div = <31>;
648: ti,autoidle-shift = <8>;
649: reg = <0x0160>;
650: ti,index-starts-at-one;
651: ti,invert-autoidle-bit;
652: };
653:
654: dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
655: #clock-cells = <0>;
656: compatible = "ti,divider-clock";
657: clocks = <&dpll_per_x2_ck>;
658: ti,max-div = <31>;
659: ti,autoidle-shift = <8>;
660: reg = <0x0164>;
661: ti,index-starts-at-one;
662: ti,invert-autoidle-bit;
663: };
664:
665: dpll_usb_ck: dpll_usb_ck@180 {
666: #clock-cells = <0>;
667: compatible = "ti,omap4-dpll-j-type-clock";
668: clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
669: reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
670: };
671:
672: dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
673: #clock-cells = <0>;
674: compatible = "ti,fixed-factor-clock";
675: clocks = <&dpll_usb_ck>;
676: ti,clock-div = <1>;
677: ti,autoidle-shift = <8>;
678: reg = <0x01b4>;
679: ti,clock-mult = <1>;
680: ti,invert-autoidle-bit;
681: };
682:
683: dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
684: #clock-cells = <0>;
685: compatible = "ti,divider-clock";
686: clocks = <&dpll_usb_ck>;
687: ti,max-div = <127>;
688: ti,autoidle-shift = <8>;
689: reg = <0x0190>;
690: ti,index-starts-at-one;
691: ti,invert-autoidle-bit;
692: };
693:
694: ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
695: #clock-cells = <0>;
696: compatible = "ti,mux-clock";
697: clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
698: reg = <0x0100>;
699: };
700:
701: func_12m_fclk: func_12m_fclk {
702: #clock-cells = <0>;
703: compatible = "fixed-factor-clock";
704: clocks = <&dpll_per_m2x2_ck>;
705: clock-mult = <1>;
706: clock-div = <16>;
707: };
708:
709: func_24m_clk: func_24m_clk {
710: #clock-cells = <0>;
711: compatible = "fixed-factor-clock";
712: clocks = <&dpll_per_m2_ck>;
713: clock-mult = <1>;
714: clock-div = <4>;
715: };
716:
717: func_24mc_fclk: func_24mc_fclk {
718: #clock-cells = <0>;
719: compatible = "fixed-factor-clock";
720: clocks = <&dpll_per_m2x2_ck>;
721: clock-mult = <1>;
722: clock-div = <8>;
723: };
724:
725: func_48m_fclk: func_48m_fclk@108 {
726: #clock-cells = <0>;
727: compatible = "ti,divider-clock";
728: clocks = <&dpll_per_m2x2_ck>;
729: reg = <0x0108>;
730: ti,dividers = <4>, <8>;
731: };
732:
733: func_48mc_fclk: func_48mc_fclk {
734: #clock-cells = <0>;
735: compatible = "fixed-factor-clock";
736: clocks = <&dpll_per_m2x2_ck>;
737: clock-mult = <1>;
738: clock-div = <4>;
739: };
740:
741: func_64m_fclk: func_64m_fclk@108 {
742: #clock-cells = <0>;
743: compatible = "ti,divider-clock";
744: clocks = <&dpll_per_m4x2_ck>;
745: reg = <0x0108>;
746: ti,dividers = <2>, <4>;
747: };
748:
749: func_96m_fclk: func_96m_fclk@108 {
750: #clock-cells = <0>;
751: compatible = "ti,divider-clock";
752: clocks = <&dpll_per_m2x2_ck>;
753: reg = <0x0108>;
754: ti,dividers = <2>, <4>;
755: };
756:
757: init_60m_fclk: init_60m_fclk@104 {
758: #clock-cells = <0>;
759: compatible = "ti,divider-clock";
760: clocks = <&dpll_usb_m2_ck>;
761: reg = <0x0104>;
762: ti,dividers = <1>, <8>;
763: };
764:
765: per_abe_nc_fclk: per_abe_nc_fclk@108 {
766: #clock-cells = <0>;
767: compatible = "ti,divider-clock";
768: clocks = <&dpll_abe_m2_ck>;
769: reg = <0x0108>;
770: ti,max-div = <2>;
771: };
772:
773: usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
774: #clock-cells = <0>;
775: compatible = "ti,gate-clock";
776: clocks = <&sys_32k_ck>;
777: ti,bit-shift = <8>;
778: reg = <0x0640>;
779: };
780: };
781:
782: &cm2_clockdomains {
783: l3_init_clkdm: l3_init_clkdm {
784: compatible = "ti,clockdomain";
1.1.1.3 jmcneill 785: clocks = <&dpll_usb_ck>;
1.1 jmcneill 786: };
787: };
788:
789: &scrm_clocks {
790: auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
791: #clock-cells = <0>;
792: compatible = "ti,composite-no-wait-gate-clock";
793: clocks = <&dpll_core_m3x2_ck>;
794: ti,bit-shift = <8>;
795: reg = <0x0310>;
796: };
797:
798: auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
799: #clock-cells = <0>;
800: compatible = "ti,composite-mux-clock";
801: clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
802: ti,bit-shift = <1>;
803: reg = <0x0310>;
804: };
805:
806: auxclk0_src_ck: auxclk0_src_ck {
807: #clock-cells = <0>;
808: compatible = "ti,composite-clock";
809: clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
810: };
811:
812: auxclk0_ck: auxclk0_ck@310 {
813: #clock-cells = <0>;
814: compatible = "ti,divider-clock";
815: clocks = <&auxclk0_src_ck>;
816: ti,bit-shift = <16>;
817: ti,max-div = <16>;
818: reg = <0x0310>;
819: };
820:
821: auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
822: #clock-cells = <0>;
823: compatible = "ti,composite-no-wait-gate-clock";
824: clocks = <&dpll_core_m3x2_ck>;
825: ti,bit-shift = <8>;
826: reg = <0x0314>;
827: };
828:
829: auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
830: #clock-cells = <0>;
831: compatible = "ti,composite-mux-clock";
832: clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
833: ti,bit-shift = <1>;
834: reg = <0x0314>;
835: };
836:
837: auxclk1_src_ck: auxclk1_src_ck {
838: #clock-cells = <0>;
839: compatible = "ti,composite-clock";
840: clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
841: };
842:
843: auxclk1_ck: auxclk1_ck@314 {
844: #clock-cells = <0>;
845: compatible = "ti,divider-clock";
846: clocks = <&auxclk1_src_ck>;
847: ti,bit-shift = <16>;
848: ti,max-div = <16>;
849: reg = <0x0314>;
850: };
851:
852: auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
853: #clock-cells = <0>;
854: compatible = "ti,composite-no-wait-gate-clock";
855: clocks = <&dpll_core_m3x2_ck>;
856: ti,bit-shift = <8>;
857: reg = <0x0318>;
858: };
859:
860: auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
861: #clock-cells = <0>;
862: compatible = "ti,composite-mux-clock";
863: clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
864: ti,bit-shift = <1>;
865: reg = <0x0318>;
866: };
867:
868: auxclk2_src_ck: auxclk2_src_ck {
869: #clock-cells = <0>;
870: compatible = "ti,composite-clock";
871: clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
872: };
873:
874: auxclk2_ck: auxclk2_ck@318 {
875: #clock-cells = <0>;
876: compatible = "ti,divider-clock";
877: clocks = <&auxclk2_src_ck>;
878: ti,bit-shift = <16>;
879: ti,max-div = <16>;
880: reg = <0x0318>;
881: };
882:
883: auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
884: #clock-cells = <0>;
885: compatible = "ti,composite-no-wait-gate-clock";
886: clocks = <&dpll_core_m3x2_ck>;
887: ti,bit-shift = <8>;
888: reg = <0x031c>;
889: };
890:
891: auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
892: #clock-cells = <0>;
893: compatible = "ti,composite-mux-clock";
894: clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
895: ti,bit-shift = <1>;
896: reg = <0x031c>;
897: };
898:
899: auxclk3_src_ck: auxclk3_src_ck {
900: #clock-cells = <0>;
901: compatible = "ti,composite-clock";
902: clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
903: };
904:
905: auxclk3_ck: auxclk3_ck@31c {
906: #clock-cells = <0>;
907: compatible = "ti,divider-clock";
908: clocks = <&auxclk3_src_ck>;
909: ti,bit-shift = <16>;
910: ti,max-div = <16>;
911: reg = <0x031c>;
912: };
913:
914: auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
915: #clock-cells = <0>;
916: compatible = "ti,composite-no-wait-gate-clock";
917: clocks = <&dpll_core_m3x2_ck>;
918: ti,bit-shift = <8>;
919: reg = <0x0320>;
920: };
921:
922: auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
923: #clock-cells = <0>;
924: compatible = "ti,composite-mux-clock";
925: clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
926: ti,bit-shift = <1>;
927: reg = <0x0320>;
928: };
929:
930: auxclk4_src_ck: auxclk4_src_ck {
931: #clock-cells = <0>;
932: compatible = "ti,composite-clock";
933: clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
934: };
935:
936: auxclk4_ck: auxclk4_ck@320 {
937: #clock-cells = <0>;
938: compatible = "ti,divider-clock";
939: clocks = <&auxclk4_src_ck>;
940: ti,bit-shift = <16>;
941: ti,max-div = <16>;
942: reg = <0x0320>;
943: };
944:
945: auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
946: #clock-cells = <0>;
947: compatible = "ti,composite-no-wait-gate-clock";
948: clocks = <&dpll_core_m3x2_ck>;
949: ti,bit-shift = <8>;
950: reg = <0x0324>;
951: };
952:
953: auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
954: #clock-cells = <0>;
955: compatible = "ti,composite-mux-clock";
956: clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
957: ti,bit-shift = <1>;
958: reg = <0x0324>;
959: };
960:
961: auxclk5_src_ck: auxclk5_src_ck {
962: #clock-cells = <0>;
963: compatible = "ti,composite-clock";
964: clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
965: };
966:
967: auxclk5_ck: auxclk5_ck@324 {
968: #clock-cells = <0>;
969: compatible = "ti,divider-clock";
970: clocks = <&auxclk5_src_ck>;
971: ti,bit-shift = <16>;
972: ti,max-div = <16>;
973: reg = <0x0324>;
974: };
975:
976: auxclkreq0_ck: auxclkreq0_ck@210 {
977: #clock-cells = <0>;
978: compatible = "ti,mux-clock";
979: clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
980: ti,bit-shift = <2>;
981: reg = <0x0210>;
982: };
983:
984: auxclkreq1_ck: auxclkreq1_ck@214 {
985: #clock-cells = <0>;
986: compatible = "ti,mux-clock";
987: clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
988: ti,bit-shift = <2>;
989: reg = <0x0214>;
990: };
991:
992: auxclkreq2_ck: auxclkreq2_ck@218 {
993: #clock-cells = <0>;
994: compatible = "ti,mux-clock";
995: clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
996: ti,bit-shift = <2>;
997: reg = <0x0218>;
998: };
999:
1000: auxclkreq3_ck: auxclkreq3_ck@21c {
1001: #clock-cells = <0>;
1002: compatible = "ti,mux-clock";
1003: clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1004: ti,bit-shift = <2>;
1005: reg = <0x021c>;
1006: };
1007:
1008: auxclkreq4_ck: auxclkreq4_ck@220 {
1009: #clock-cells = <0>;
1010: compatible = "ti,mux-clock";
1011: clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1012: ti,bit-shift = <2>;
1013: reg = <0x0220>;
1014: };
1015:
1016: auxclkreq5_ck: auxclkreq5_ck@224 {
1017: #clock-cells = <0>;
1018: compatible = "ti,mux-clock";
1019: clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1020: ti,bit-shift = <2>;
1021: reg = <0x0224>;
1022: };
1023: };
1.1.1.3 jmcneill 1024:
1025: &cm1 {
1026: mpuss_cm: mpuss_cm@300 {
1027: compatible = "ti,omap4-cm";
1028: reg = <0x300 0x100>;
1029: #address-cells = <1>;
1030: #size-cells = <1>;
1031: ranges = <0 0x300 0x100>;
1032:
1033: mpuss_clkctrl: clk@20 {
1034: compatible = "ti,clkctrl";
1035: reg = <0x20 0x4>;
1036: #clock-cells = <2>;
1037: };
1038: };
1039:
1040: tesla_cm: tesla_cm@400 {
1041: compatible = "ti,omap4-cm";
1042: reg = <0x400 0x100>;
1043: #address-cells = <1>;
1044: #size-cells = <1>;
1045: ranges = <0 0x400 0x100>;
1046:
1047: tesla_clkctrl: clk@20 {
1048: compatible = "ti,clkctrl";
1049: reg = <0x20 0x4>;
1050: #clock-cells = <2>;
1051: };
1052: };
1053:
1054: abe_cm: abe_cm@500 {
1055: compatible = "ti,omap4-cm";
1056: reg = <0x500 0x100>;
1057: #address-cells = <1>;
1058: #size-cells = <1>;
1059: ranges = <0 0x500 0x100>;
1060:
1061: abe_clkctrl: clk@20 {
1062: compatible = "ti,clkctrl";
1063: reg = <0x20 0x6c>;
1064: #clock-cells = <2>;
1065: };
1066: };
1067:
1068: };
1069:
1070: &cm2 {
1071: l4_ao_cm: l4_ao_cm@600 {
1072: compatible = "ti,omap4-cm";
1073: reg = <0x600 0x100>;
1074: #address-cells = <1>;
1075: #size-cells = <1>;
1076: ranges = <0 0x600 0x100>;
1077:
1078: l4_ao_clkctrl: clk@20 {
1079: compatible = "ti,clkctrl";
1080: reg = <0x20 0x1c>;
1081: #clock-cells = <2>;
1082: };
1083: };
1084:
1085: l3_1_cm: l3_1_cm@700 {
1086: compatible = "ti,omap4-cm";
1087: reg = <0x700 0x100>;
1088: #address-cells = <1>;
1089: #size-cells = <1>;
1090: ranges = <0 0x700 0x100>;
1091:
1092: l3_1_clkctrl: clk@20 {
1093: compatible = "ti,clkctrl";
1094: reg = <0x20 0x4>;
1095: #clock-cells = <2>;
1096: };
1097: };
1098:
1099: l3_2_cm: l3_2_cm@800 {
1100: compatible = "ti,omap4-cm";
1101: reg = <0x800 0x100>;
1102: #address-cells = <1>;
1103: #size-cells = <1>;
1104: ranges = <0 0x800 0x100>;
1105:
1106: l3_2_clkctrl: clk@20 {
1107: compatible = "ti,clkctrl";
1108: reg = <0x20 0x14>;
1109: #clock-cells = <2>;
1110: };
1111: };
1112:
1113: ducati_cm: ducati_cm@900 {
1114: compatible = "ti,omap4-cm";
1115: reg = <0x900 0x100>;
1116: #address-cells = <1>;
1117: #size-cells = <1>;
1118: ranges = <0 0x900 0x100>;
1119:
1120: ducati_clkctrl: clk@20 {
1121: compatible = "ti,clkctrl";
1122: reg = <0x20 0x4>;
1123: #clock-cells = <2>;
1124: };
1125: };
1126:
1127: l3_dma_cm: l3_dma_cm@a00 {
1128: compatible = "ti,omap4-cm";
1129: reg = <0xa00 0x100>;
1130: #address-cells = <1>;
1131: #size-cells = <1>;
1132: ranges = <0 0xa00 0x100>;
1133:
1134: l3_dma_clkctrl: clk@20 {
1135: compatible = "ti,clkctrl";
1136: reg = <0x20 0x4>;
1137: #clock-cells = <2>;
1138: };
1139: };
1140:
1141: l3_emif_cm: l3_emif_cm@b00 {
1142: compatible = "ti,omap4-cm";
1143: reg = <0xb00 0x100>;
1144: #address-cells = <1>;
1145: #size-cells = <1>;
1146: ranges = <0 0xb00 0x100>;
1147:
1148: l3_emif_clkctrl: clk@20 {
1149: compatible = "ti,clkctrl";
1150: reg = <0x20 0x1c>;
1151: #clock-cells = <2>;
1152: };
1153: };
1154:
1155: d2d_cm: d2d_cm@c00 {
1156: compatible = "ti,omap4-cm";
1157: reg = <0xc00 0x100>;
1158: #address-cells = <1>;
1159: #size-cells = <1>;
1160: ranges = <0 0xc00 0x100>;
1161:
1162: d2d_clkctrl: clk@20 {
1163: compatible = "ti,clkctrl";
1164: reg = <0x20 0x4>;
1165: #clock-cells = <2>;
1166: };
1167: };
1168:
1169: l4_cfg_cm: l4_cfg_cm@d00 {
1170: compatible = "ti,omap4-cm";
1171: reg = <0xd00 0x100>;
1172: #address-cells = <1>;
1173: #size-cells = <1>;
1174: ranges = <0 0xd00 0x100>;
1175:
1176: l4_cfg_clkctrl: clk@20 {
1177: compatible = "ti,clkctrl";
1178: reg = <0x20 0x14>;
1179: #clock-cells = <2>;
1180: };
1181: };
1182:
1183: l3_instr_cm: l3_instr_cm@e00 {
1184: compatible = "ti,omap4-cm";
1185: reg = <0xe00 0x100>;
1186: #address-cells = <1>;
1187: #size-cells = <1>;
1188: ranges = <0 0xe00 0x100>;
1189:
1190: l3_instr_clkctrl: clk@20 {
1191: compatible = "ti,clkctrl";
1192: reg = <0x20 0x24>;
1193: #clock-cells = <2>;
1194: };
1195: };
1196:
1197: ivahd_cm: ivahd_cm@f00 {
1198: compatible = "ti,omap4-cm";
1199: reg = <0xf00 0x100>;
1200: #address-cells = <1>;
1201: #size-cells = <1>;
1202: ranges = <0 0xf00 0x100>;
1203:
1204: ivahd_clkctrl: clk@20 {
1205: compatible = "ti,clkctrl";
1206: reg = <0x20 0xc>;
1207: #clock-cells = <2>;
1208: };
1209: };
1210:
1211: iss_cm: iss_cm@1000 {
1212: compatible = "ti,omap4-cm";
1213: reg = <0x1000 0x100>;
1214: #address-cells = <1>;
1215: #size-cells = <1>;
1216: ranges = <0 0x1000 0x100>;
1217:
1218: iss_clkctrl: clk@20 {
1219: compatible = "ti,clkctrl";
1220: reg = <0x20 0xc>;
1221: #clock-cells = <2>;
1222: };
1223: };
1224:
1225: l3_dss_cm: l3_dss_cm@1100 {
1226: compatible = "ti,omap4-cm";
1227: reg = <0x1100 0x100>;
1228: #address-cells = <1>;
1229: #size-cells = <1>;
1230: ranges = <0 0x1100 0x100>;
1231:
1232: l3_dss_clkctrl: clk@20 {
1233: compatible = "ti,clkctrl";
1234: reg = <0x20 0x4>;
1235: #clock-cells = <2>;
1236: };
1237: };
1238:
1239: l3_gfx_cm: l3_gfx_cm@1200 {
1240: compatible = "ti,omap4-cm";
1241: reg = <0x1200 0x100>;
1242: #address-cells = <1>;
1243: #size-cells = <1>;
1244: ranges = <0 0x1200 0x100>;
1245:
1246: l3_gfx_clkctrl: clk@20 {
1247: compatible = "ti,clkctrl";
1248: reg = <0x20 0x4>;
1249: #clock-cells = <2>;
1250: };
1251: };
1252:
1253: l3_init_cm: l3_init_cm@1300 {
1254: compatible = "ti,omap4-cm";
1255: reg = <0x1300 0x100>;
1256: #address-cells = <1>;
1257: #size-cells = <1>;
1258: ranges = <0 0x1300 0x100>;
1259:
1260: l3_init_clkctrl: clk@20 {
1261: compatible = "ti,clkctrl";
1262: reg = <0x20 0xc4>;
1263: #clock-cells = <2>;
1264: };
1265: };
1266:
1267: l4_per_cm: l4_per_cm@1400 {
1268: compatible = "ti,omap4-cm";
1269: reg = <0x1400 0x200>;
1270: #address-cells = <1>;
1271: #size-cells = <1>;
1272: ranges = <0 0x1400 0x200>;
1273:
1.1.1.5 ! jmcneill 1274: l4_per_clkctrl: clock@20 {
! 1275: compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
1.1.1.3 jmcneill 1276: reg = <0x20 0x144>;
1277: #clock-cells = <2>;
1278: };
1279:
1.1.1.5 ! jmcneill 1280: l4_secure_clkctrl: clock@1a0 {
! 1281: compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
! 1282: reg = <0x1a0 0x3c>;
! 1283: #clock-cells = <2>;
! 1284: };
! 1285: };
1.1.1.3 jmcneill 1286: };
1287:
1288: &prm {
1289: l4_wkup_cm: l4_wkup_cm@1800 {
1290: compatible = "ti,omap4-cm";
1291: reg = <0x1800 0x100>;
1292: #address-cells = <1>;
1293: #size-cells = <1>;
1294: ranges = <0 0x1800 0x100>;
1295:
1296: l4_wkup_clkctrl: clk@20 {
1297: compatible = "ti,clkctrl";
1298: reg = <0x20 0x5c>;
1299: #clock-cells = <2>;
1300: };
1301: };
1302:
1303: emu_sys_cm: emu_sys_cm@1a00 {
1304: compatible = "ti,omap4-cm";
1305: reg = <0x1a00 0x100>;
1306: #address-cells = <1>;
1307: #size-cells = <1>;
1308: ranges = <0 0x1a00 0x100>;
1309:
1310: emu_sys_clkctrl: clk@20 {
1311: compatible = "ti,clkctrl";
1312: reg = <0x20 0x4>;
1313: #clock-cells = <2>;
1314: };
1315: };
1316: };