version 1.1.1.2, 2017/07/27 18:10:49 |
version 1.1.1.3, 2017/10/28 10:30:31 |
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*/ |
*/ |
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#include <dt-bindings/clock/imx7d-clock.h> |
#include <dt-bindings/clock/imx7d-clock.h> |
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#include <dt-bindings/power/imx7-power.h> |
#include <dt-bindings/gpio/gpio.h> |
#include <dt-bindings/gpio/gpio.h> |
#include <dt-bindings/input/input.h> |
#include <dt-bindings/input/input.h> |
#include <dt-bindings/interrupt-controller/arm-gic.h> |
#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#address-cells = <1>; |
#address-cells = <1>; |
#size-cells = <1>; |
#size-cells = <1>; |
compatible = "simple-bus"; |
compatible = "simple-bus"; |
interrupt-parent = <&intc>; |
interrupt-parent = <&gpc>; |
ranges; |
ranges; |
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funnel@30041000 { |
funnel@30041000 { |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
#interrupt-cells = <3>; |
#interrupt-cells = <3>; |
interrupt-controller; |
interrupt-controller; |
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interrupt-parent = <&intc>; |
reg = <0x31001000 0x1000>, |
reg = <0x31001000 0x1000>, |
<0x31002000 0x2000>, |
<0x31002000 0x2000>, |
<0x31004000 0x2000>, |
<0x31004000 0x2000>, |
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timer { |
timer { |
compatible = "arm,armv7-timer"; |
compatible = "arm,armv7-timer"; |
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interrupt-parent = <&intc>; |
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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}; |
}; |
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gpr: iomuxc-gpr@30340000 { |
gpr: iomuxc-gpr@30340000 { |
compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; |
compatible = "fsl,imx7d-iomuxc-gpr", |
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"fsl,imx6q-iomuxc-gpr", "syscon"; |
reg = <0x30340000 0x10000>; |
reg = <0x30340000 0x10000>; |
}; |
}; |
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anatop-min-bit-val = <8>; |
anatop-min-bit-val = <8>; |
anatop-min-voltage = <800000>; |
anatop-min-voltage = <800000>; |
anatop-max-voltage = <1200000>; |
anatop-max-voltage = <1200000>; |
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anatop-enable-bit = <0>; |
}; |
}; |
}; |
}; |
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compatible = "syscon-poweroff"; |
compatible = "syscon-poweroff"; |
regmap = <&snvs>; |
regmap = <&snvs>; |
offset = <0x38>; |
offset = <0x38>; |
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value = <0x60>; |
mask = <0x60>; |
mask = <0x60>; |
}; |
}; |
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
#reset-cells = <1>; |
#reset-cells = <1>; |
}; |
}; |
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gpc: gpc@303a0000 { |
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compatible = "fsl,imx7d-gpc"; |
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reg = <0x303a0000 0x10000>; |
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interrupt-controller; |
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
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#interrupt-cells = <3>; |
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interrupt-parent = <&intc>; |
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#power-domain-cells = <1>; |
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pgc { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY { |
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#power-domain-cells = <0>; |
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reg = <IMX7_POWER_DOMAIN_PCIE_PHY>; |
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power-supply = <®_1p0d>; |
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}; |
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}; |
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}; |
}; |
}; |
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aips2: aips-bus@30400000 { |
aips2: aips-bus@30400000 { |
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clocks = <&clks IMX7D_PWM1_ROOT_CLK>, |
clocks = <&clks IMX7D_PWM1_ROOT_CLK>, |
<&clks IMX7D_PWM1_ROOT_CLK>; |
<&clks IMX7D_PWM1_ROOT_CLK>; |
clock-names = "ipg", "per"; |
clock-names = "ipg", "per"; |
#pwm-cells = <2>; |
#pwm-cells = <3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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clocks = <&clks IMX7D_PWM2_ROOT_CLK>, |
clocks = <&clks IMX7D_PWM2_ROOT_CLK>, |
<&clks IMX7D_PWM2_ROOT_CLK>; |
<&clks IMX7D_PWM2_ROOT_CLK>; |
clock-names = "ipg", "per"; |
clock-names = "ipg", "per"; |
#pwm-cells = <2>; |
#pwm-cells = <3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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clocks = <&clks IMX7D_PWM3_ROOT_CLK>, |
clocks = <&clks IMX7D_PWM3_ROOT_CLK>, |
<&clks IMX7D_PWM3_ROOT_CLK>; |
<&clks IMX7D_PWM3_ROOT_CLK>; |
clock-names = "ipg", "per"; |
clock-names = "ipg", "per"; |
#pwm-cells = <2>; |
#pwm-cells = <3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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clocks = <&clks IMX7D_PWM4_ROOT_CLK>, |
clocks = <&clks IMX7D_PWM4_ROOT_CLK>, |
<&clks IMX7D_PWM4_ROOT_CLK>; |
<&clks IMX7D_PWM4_ROOT_CLK>; |
clock-names = "ipg", "per"; |
clock-names = "ipg", "per"; |
#pwm-cells = <2>; |
#pwm-cells = <3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
reg = <0x30b40000 0x10000>; |
reg = <0x30b40000 0x10000>; |
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clks IMX7D_CLK_DUMMY>, |
clocks = <&clks IMX7D_IPG_ROOT_CLK>, |
<&clks IMX7D_CLK_DUMMY>, |
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, |
<&clks IMX7D_USDHC1_ROOT_CLK>; |
<&clks IMX7D_USDHC1_ROOT_CLK>; |
clock-names = "ipg", "ahb", "per"; |
clock-names = "ipg", "ahb", "per"; |
bus-width = <4>; |
bus-width = <4>; |
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compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
reg = <0x30b50000 0x10000>; |
reg = <0x30b50000 0x10000>; |
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clks IMX7D_CLK_DUMMY>, |
clocks = <&clks IMX7D_IPG_ROOT_CLK>, |
<&clks IMX7D_CLK_DUMMY>, |
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, |
<&clks IMX7D_USDHC2_ROOT_CLK>; |
<&clks IMX7D_USDHC2_ROOT_CLK>; |
clock-names = "ipg", "ahb", "per"; |
clock-names = "ipg", "ahb", "per"; |
bus-width = <4>; |
bus-width = <4>; |
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compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; |
reg = <0x30b60000 0x10000>; |
reg = <0x30b60000 0x10000>; |
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clks IMX7D_CLK_DUMMY>, |
clocks = <&clks IMX7D_IPG_ROOT_CLK>, |
<&clks IMX7D_CLK_DUMMY>, |
<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, |
<&clks IMX7D_USDHC3_ROOT_CLK>; |
<&clks IMX7D_USDHC3_ROOT_CLK>; |
clock-names = "ipg", "ahb", "per"; |
clock-names = "ipg", "ahb", "per"; |
bus-width = <4>; |
bus-width = <4>; |
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status = "disabled"; |
status = "disabled"; |
}; |
}; |
}; |
}; |
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dma_apbh: dma-apbh@33000000 { |
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compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; |
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reg = <0x33000000 0x2000>; |
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
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#dma-cells = <1>; |
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dma-channels = <4>; |
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clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; |
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}; |
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gpmi: gpmi-nand@33002000{ |
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compatible = "fsl,imx7d-gpmi-nand"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x33002000 0x2000>, <0x33004000 0x4000>; |
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reg-names = "gpmi-nand", "bch"; |
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "bch"; |
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clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, |
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<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; |
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clock-names = "gpmi_io", "gpmi_bch_apb"; |
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dmas = <&dma_apbh 0>; |
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dma-names = "rx-tx"; |
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status = "disabled"; |
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assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; |
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; |
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}; |
}; |
}; |
}; |
}; |