version 1.1.1.4, 2018/06/27 16:27:07 |
version 1.1.1.4.2.2, 2020/04/08 14:08:33 |
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cpu0: cpu@0 { |
cpu0: cpu@0 { |
clock-frequency = <996000000>; |
clock-frequency = <996000000>; |
operating-points-v2 = <&cpu0_opp_table>; |
operating-points-v2 = <&cpu0_opp_table>; |
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#cooling-cells = <2>; |
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nvmem-cells = <&cpu_speed_grade>; |
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nvmem-cell-names = "speed_grade"; |
}; |
}; |
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cpu1: cpu@1 { |
cpu1: cpu@1 { |
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reg = <1>; |
reg = <1>; |
clock-frequency = <996000000>; |
clock-frequency = <996000000>; |
operating-points-v2 = <&cpu0_opp_table>; |
operating-points-v2 = <&cpu0_opp_table>; |
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#cooling-cells = <2>; |
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cpu-idle-states = <&cpu_sleep_wait>; |
}; |
}; |
}; |
}; |
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timer { |
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compatible = "arm,armv7-timer"; |
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interrupt-parent = <&intc>; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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cpu0_opp_table: opp-table { |
cpu0_opp_table: opp-table { |
compatible = "operating-points-v2"; |
compatible = "operating-points-v2"; |
opp-shared; |
opp-shared; |
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opp-792000000 { |
opp-792000000 { |
opp-hz = /bits/ 64 <792000000>; |
opp-hz = /bits/ 64 <792000000>; |
opp-microvolt = <975000>; |
opp-microvolt = <1000000>; |
clock-latency-ns = <150000>; |
clock-latency-ns = <150000>; |
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opp-supported-hw = <0xd>, <0xf>; |
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opp-suspend; |
}; |
}; |
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opp-996000000 { |
opp-996000000 { |
opp-hz = /bits/ 64 <996000000>; |
opp-hz = /bits/ 64 <996000000>; |
opp-microvolt = <1075000>; |
opp-microvolt = <1100000>; |
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clock-latency-ns = <150000>; |
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opp-supported-hw = <0xc>, <0xf>; |
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opp-suspend; |
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}; |
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opp-1200000000 { |
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opp-hz = /bits/ 64 <1200000000>; |
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opp-microvolt = <1225000>; |
clock-latency-ns = <150000>; |
clock-latency-ns = <150000>; |
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opp-supported-hw = <0x8>, <0xf>; |
opp-suspend; |
opp-suspend; |
}; |
}; |
}; |
}; |
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clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
clock-names = "apb_pclk"; |
clock-names = "apb_pclk"; |
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port { |
out-ports { |
etm1_out_port: endpoint { |
port { |
remote-endpoint = <&ca_funnel_in_port1>; |
etm1_out_port: endpoint { |
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remote-endpoint = <&ca_funnel_in_port1>; |
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}; |
}; |
}; |
}; |
}; |
}; |
}; |
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intc: interrupt-controller@31001000 { |
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compatible = "arm,cortex-a7-gic"; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupt-parent = <&intc>; |
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reg = <0x31001000 0x1000>, |
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<0x31002000 0x2000>, |
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<0x31004000 0x2000>, |
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<0x31006000 0x2000>; |
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}; |
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}; |
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}; |
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&aips2 { |
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pcie_phy: pcie-phy@306d0000 { |
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compatible = "fsl,imx7d-pcie-phy"; |
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reg = <0x306d0000 0x10000>; |
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status = "disabled"; |
}; |
}; |
}; |
}; |
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<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; |
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; |
clock-names = "ipg", "ahb", "ptp", |
clock-names = "ipg", "ahb", "ptp", |
"enet_clk_ref", "enet_out"; |
"enet_clk_ref", "enet_out"; |
fsl,num-tx-queues=<3>; |
fsl,num-tx-queues = <3>; |
fsl,num-rx-queues=<3>; |
fsl,num-rx-queues = <3>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
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ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ |
ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ |
0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ |
0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ |
num-lanes = <1>; |
num-lanes = <1>; |
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num-viewport = <4>; |
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
interrupt-names = "msi"; |
interrupt-names = "msi"; |
#interrupt-cells = <1>; |
#interrupt-cells = <1>; |
interrupt-map-mask = <0 0 0 0x7>; |
interrupt-map-mask = <0 0 0 0x7>; |
interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
/* |
<0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
* Reference manual lists pci irqs incorrectly |
<0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
* Real hardware ordering is same as imx6: D+MSI, C, B, A |
<0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
*/ |
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interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, |
clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, |
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, |
<&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, |
<&clks IMX7D_PCIE_PHY_ROOT_CLK>; |
<&clks IMX7D_PCIE_PHY_ROOT_CLK>; |
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fsl,max-link-speed = <2>; |
fsl,max-link-speed = <2>; |
power-domains = <&pgc_pcie_phy>; |
power-domains = <&pgc_pcie_phy>; |
resets = <&src IMX7_RESET_PCIEPHY>, |
resets = <&src IMX7_RESET_PCIEPHY>, |
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>; |
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>, |
reset-names = "pciephy", "apps"; |
<&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; |
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reset-names = "pciephy", "apps", "turnoff"; |
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fsl,imx7d-pcie-phy = <&pcie_phy>; |
status = "disabled"; |
status = "disabled"; |
}; |
}; |
}; |
}; |
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&ca_funnel_ports { |
&ca_funnel_in_ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@1 { |
port@1 { |
reg = <1>; |
reg = <1>; |
ca_funnel_in_port1: endpoint { |
ca_funnel_in_port1: endpoint { |
slave-mode; |
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remote-endpoint = <&etm1_out_port>; |
remote-endpoint = <&etm1_out_port>; |
}; |
}; |
}; |
}; |