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Diff for /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/imx7d.dtsi between version 1.1.1.1.4.2 and 1.1.1.2

version 1.1.1.1.4.2, 2017/07/18 16:08:42 version 1.1.1.2, 2017/10/28 10:30:31
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  */   */
   
 #include "imx7s.dtsi"  #include "imx7s.dtsi"
   #include <dt-bindings/reset/imx7-reset.h>
   
 / {  / {
         cpus {          cpus {
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                 fsl,num-rx-queues=<3>;                  fsl,num-rx-queues=<3>;
                 status = "disabled";                  status = "disabled";
         };          };
   
           pcie: pcie@0x33800000 {
                   compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
                   reg = <0x33800000 0x4000>,
                         <0x4ff00000 0x80000>;
                   reg-names = "dbi", "config";
                   #address-cells = <3>;
                   #size-cells = <2>;
                   device_type = "pci";
                   ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
                             0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
                   num-lanes = <1>;
                   interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
                   interrupt-names = "msi";
                   #interrupt-cells = <1>;
                   interrupt-map-mask = <0 0 0 0x7>;
                   interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
                                   <0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                   <0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
                                   <0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                   clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
                            <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
                            <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
                   clock-names = "pcie", "pcie_bus", "pcie_phy";
                   assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
                                     <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
                   assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
                                            <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
   
                   fsl,max-link-speed = <2>;
                   power-domains = <&pgc_pcie_phy>;
                   resets = <&src IMX7_RESET_PCIEPHY>,
                            <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
                   reset-names = "pciephy", "apps";
                   status = "disabled";
           };
 };  };
   
 &ca_funnel_ports {  &ca_funnel_ports {
Legend:
Removed from v.1.1.1.1.4.2  
changed lines
  Added in v.1.1.1.2
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