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1.1 jmcneill 1: /*
2: * Copyright 2013 Gateworks Corporation
3: *
4: * The code contained herein is licensed under the GNU General Public
5: * License. You may obtain a copy of the GNU General Public License
6: * Version 2 or later at the following locations:
7: *
8: * http://www.opensource.org/licenses/gpl-license.html
9: * http://www.gnu.org/copyleft/gpl.html
10: */
11:
12: #include <dt-bindings/gpio/gpio.h>
13:
14: / {
15: /* these are used by bootloader for disabling nodes */
16: aliases {
17: led0 = &led0;
18: led1 = &led1;
19: led2 = &led2;
20: nand = &gpmi;
21: ssi0 = &ssi1;
22: usb0 = &usbh1;
23: usb1 = &usbotg;
24: };
25:
26: chosen {
27: bootargs = "console=ttymxc1,115200";
28: };
29:
30: backlight {
31: compatible = "pwm-backlight";
32: pwms = <&pwm4 0 5000000>;
33: brightness-levels = <0 4 8 16 32 64 128 255>;
34: default-brightness-level = <7>;
35: };
36:
37: leds {
38: compatible = "gpio-leds";
39: pinctrl-names = "default";
40: pinctrl-0 = <&pinctrl_gpio_leds>;
41:
42: led0: user1 {
43: label = "user1";
44: gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
45: default-state = "on";
46: linux,default-trigger = "heartbeat";
47: };
48:
49: led1: user2 {
50: label = "user2";
51: gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
52: default-state = "off";
53: };
54:
55: led2: user3 {
56: label = "user3";
57: gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
58: default-state = "off";
59: };
60: };
61:
62: memory {
63: reg = <0x10000000 0x20000000>;
64: };
65:
66: pps {
67: compatible = "pps-gpio";
68: pinctrl-names = "default";
69: pinctrl-0 = <&pinctrl_pps>;
70: gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
71: status = "okay";
72: };
73:
74: reg_1p0v: regulator-1p0v {
75: compatible = "regulator-fixed";
76: regulator-name = "1P0V";
77: regulator-min-microvolt = <1000000>;
78: regulator-max-microvolt = <1000000>;
79: regulator-always-on;
80: };
81:
82: reg_3p3v: regulator-3p3v {
83: compatible = "regulator-fixed";
84: regulator-name = "3P3V";
85: regulator-min-microvolt = <3300000>;
86: regulator-max-microvolt = <3300000>;
87: regulator-always-on;
88: };
89:
90: reg_5p0v: regulator-5p0v {
91: compatible = "regulator-fixed";
92: regulator-name = "5P0V";
93: regulator-min-microvolt = <5000000>;
94: regulator-max-microvolt = <5000000>;
95: regulator-always-on;
96: };
97:
98: reg_usb_otg_vbus: regulator-usb-otg-vbus {
99: compatible = "regulator-fixed";
100: regulator-name = "usb_otg_vbus";
101: regulator-min-microvolt = <5000000>;
102: regulator-max-microvolt = <5000000>;
103: gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
104: enable-active-high;
105: };
106:
107: sound {
108: compatible = "fsl,imx6q-ventana-sgtl5000",
109: "fsl,imx-audio-sgtl5000";
110: model = "sgtl5000-audio";
111: ssi-controller = <&ssi1>;
112: audio-codec = <&codec>;
113: audio-routing =
114: "MIC_IN", "Mic Jack",
115: "Mic Jack", "Mic Bias",
116: "Headphone Jack", "HP_OUT";
117: mux-int-port = <1>;
118: mux-ext-port = <4>;
119: };
120: };
121:
122: &audmux {
123: pinctrl-names = "default";
124: pinctrl-0 = <&pinctrl_audmux>;
125: status = "okay";
126: };
127:
128: &can1 {
129: pinctrl-names = "default";
130: pinctrl-0 = <&pinctrl_flexcan1>;
131: status = "okay";
132: };
133:
134: &clks {
135: assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
136: <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
137: assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
138: <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
139: };
140:
141: &ecspi3 {
142: cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
143: pinctrl-names = "default";
144: pinctrl-0 = <&pinctrl_ecspi3>;
145: status = "okay";
146: };
147:
148: &fec {
149: pinctrl-names = "default";
150: pinctrl-0 = <&pinctrl_enet>;
151: phy-mode = "rgmii-id";
152: phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
153: status = "okay";
154: };
155:
156: &gpmi {
157: pinctrl-names = "default";
158: pinctrl-0 = <&pinctrl_gpmi_nand>;
159: status = "okay";
160: };
161:
162: &hdmi {
163: ddc-i2c-bus = <&i2c3>;
164: status = "okay";
165: };
166:
167: &i2c1 {
168: clock-frequency = <100000>;
169: pinctrl-names = "default";
170: pinctrl-0 = <&pinctrl_i2c1>;
171: status = "okay";
172:
173: eeprom1: eeprom@50 {
174: compatible = "atmel,24c02";
175: reg = <0x50>;
176: pagesize = <16>;
177: };
178:
179: eeprom2: eeprom@51 {
180: compatible = "atmel,24c02";
181: reg = <0x51>;
182: pagesize = <16>;
183: };
184:
185: eeprom3: eeprom@52 {
186: compatible = "atmel,24c02";
187: reg = <0x52>;
188: pagesize = <16>;
189: };
190:
191: eeprom4: eeprom@53 {
192: compatible = "atmel,24c02";
193: reg = <0x53>;
194: pagesize = <16>;
195: };
196:
197: gpio: pca9555@23 {
198: compatible = "nxp,pca9555";
199: reg = <0x23>;
200: gpio-controller;
201: #gpio-cells = <2>;
202: };
203:
204: rtc: ds1672@68 {
205: compatible = "dallas,ds1672";
206: reg = <0x68>;
207: };
208: };
209:
210: &i2c2 {
211: clock-frequency = <100000>;
212: pinctrl-names = "default";
213: pinctrl-0 = <&pinctrl_i2c2>;
214: status = "okay";
215:
216: ltc3676: pmic@3c {
217: compatible = "lltc,ltc3676";
218: reg = <0x3c>;
219: pinctrl-names = "default";
220: pinctrl-0 = <&pinctrl_pmic>;
221: interrupt-parent = <&gpio1>;
222: interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
223:
224: regulators {
225: /* VDD_SOC (1+R1/R2 = 1.635) */
226: reg_vdd_soc: sw1 {
227: regulator-name = "vddsoc";
228: regulator-min-microvolt = <674400>;
229: regulator-max-microvolt = <1308000>;
230: lltc,fb-voltage-divider = <127000 200000>;
231: regulator-ramp-delay = <7000>;
232: regulator-boot-on;
233: regulator-always-on;
234: };
235:
236: /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
237: reg_1p8v: sw2 {
238: regulator-name = "vdd1p8";
239: regulator-min-microvolt = <1033310>;
240: regulator-max-microvolt = <2004000>;
241: lltc,fb-voltage-divider = <301000 200000>;
242: regulator-ramp-delay = <7000>;
243: regulator-boot-on;
244: regulator-always-on;
245: };
246:
247: /* VDD_ARM (1+R1/R2 = 1.635) */
248: reg_vdd_arm: sw3 {
249: regulator-name = "vddarm";
250: regulator-min-microvolt = <674400>;
251: regulator-max-microvolt = <1308000>;
252: lltc,fb-voltage-divider = <127000 200000>;
253: regulator-ramp-delay = <7000>;
254: regulator-boot-on;
255: regulator-always-on;
256: };
257:
258: /* VDD_DDR (1+R1/R2 = 2.105) */
259: reg_vdd_ddr: sw4 {
260: regulator-name = "vddddr";
261: regulator-min-microvolt = <868310>;
262: regulator-max-microvolt = <1684000>;
263: lltc,fb-voltage-divider = <221000 200000>;
264: regulator-ramp-delay = <7000>;
265: regulator-boot-on;
266: regulator-always-on;
267: };
268:
269: /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
270: reg_2p5v: ldo2 {
271: regulator-name = "vdd2p5";
272: regulator-min-microvolt = <2490375>;
273: regulator-max-microvolt = <2490375>;
274: lltc,fb-voltage-divider = <487000 200000>;
275: regulator-boot-on;
276: regulator-always-on;
277: };
278:
279: /* VDD_AUD_1P8: Audio codec */
280: reg_aud_1p8v: ldo3 {
281: regulator-name = "vdd1p8";
282: regulator-min-microvolt = <1800000>;
283: regulator-max-microvolt = <1800000>;
284: regulator-boot-on;
285: };
286:
287: /* VDD_HIGH (1+R1/R2 = 4.17) */
288: reg_3p0v: ldo4 {
289: regulator-name = "vdd3p0";
290: regulator-min-microvolt = <3023250>;
291: regulator-max-microvolt = <3023250>;
292: lltc,fb-voltage-divider = <634000 200000>;
293: regulator-boot-on;
294: regulator-always-on;
295: };
296: };
297: };
298: };
299:
300: &i2c3 {
301: clock-frequency = <100000>;
302: pinctrl-names = "default";
303: pinctrl-0 = <&pinctrl_i2c3>;
304: status = "okay";
305:
306: codec: sgtl5000@0a {
307: compatible = "fsl,sgtl5000";
308: reg = <0x0a>;
309: clocks = <&clks IMX6QDL_CLK_CKO>;
310: VDDA-supply = <®_1p8v>;
311: VDDIO-supply = <®_3p3v>;
312: };
313:
314: touchscreen: egalax_ts@04 {
315: compatible = "eeti,egalax_ts";
316: reg = <0x04>;
317: interrupt-parent = <&gpio7>;
318: interrupts = <12 2>;
319: wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
320: };
321: };
322:
323: &ldb {
324: status = "okay";
325:
326: lvds-channel@0 {
327: fsl,data-mapping = "spwg";
328: fsl,data-width = <18>;
329: status = "okay";
330:
331: display-timings {
332: native-mode = <&timing0>;
333: timing0: hsd100pxn1 {
334: clock-frequency = <65000000>;
335: hactive = <1024>;
336: vactive = <768>;
337: hback-porch = <220>;
338: hfront-porch = <40>;
339: vback-porch = <21>;
340: vfront-porch = <7>;
341: hsync-len = <60>;
342: vsync-len = <10>;
343: };
344: };
345: };
346: };
347:
348: &pcie {
349: pinctrl-names = "default";
350: pinctrl-0 = <&pinctrl_pcie>;
351: reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
352: status = "okay";
353: };
354:
355: &pwm2 {
356: pinctrl-names = "default";
357: pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
358: status = "disabled";
359: };
360:
361: &pwm3 {
362: pinctrl-names = "default";
363: pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
364: status = "disabled";
365: };
366:
367: &pwm4 {
368: pinctrl-names = "default";
369: pinctrl-0 = <&pinctrl_pwm4>;
370: status = "okay";
371: };
372:
373: &ssi1 {
374: status = "okay";
375: };
376:
377: &uart1 {
378: pinctrl-names = "default";
379: pinctrl-0 = <&pinctrl_uart1>;
380: uart-has-rtscts;
381: rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
382: status = "okay";
383: };
384:
385: &uart2 {
386: pinctrl-names = "default";
387: pinctrl-0 = <&pinctrl_uart2>;
388: status = "okay";
389: };
390:
391: &uart5 {
392: pinctrl-names = "default";
393: pinctrl-0 = <&pinctrl_uart5>;
394: status = "okay";
395: };
396:
397: &usbotg {
398: vbus-supply = <®_usb_otg_vbus>;
399: pinctrl-names = "default";
400: pinctrl-0 = <&pinctrl_usbotg>;
401: disable-over-current;
402: status = "okay";
403: };
404:
405: &usbh1 {
406: status = "okay";
407: };
408:
409: &usdhc3 {
410: pinctrl-names = "default", "state_100mhz", "state_200mhz";
411: pinctrl-0 = <&pinctrl_usdhc3>;
412: pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
413: pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
414: cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
415: vmmc-supply = <®_3p3v>;
416: no-1-8-v; /* firmware will remove if board revision supports */
417: status = "okay";
418: };
419:
420: &wdog1 {
421: pinctrl-names = "default";
422: pinctrl-0 = <&pinctrl_wdog>;
423: fsl,ext-reset-output;
424: };
425:
426: &iomuxc {
427: imx6qdl-gw52xx {
428: pinctrl_audmux: audmuxgrp {
429: fsl,pins = <
430: MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
431: MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
432: MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
433: MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
434: MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
435: >;
436: };
437:
438: pinctrl_ecspi3: escpi3grp {
439: fsl,pins = <
440: MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
441: MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
442: MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
443: MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
444: >;
445: };
446:
447: pinctrl_enet: enetgrp {
448: fsl,pins = <
449: MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
450: MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
451: MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
452: MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
453: MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
454: MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
455: MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
456: MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
457: MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
458: MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
459: MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
460: MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
461: MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
462: MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
463: MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
464: MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
465: MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
466: >;
467: };
468:
469: pinctrl_flexcan1: flexcan1grp {
470: fsl,pins = <
471: MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
472: MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
473: MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
474: >;
475: };
476:
477: pinctrl_gpio_leds: gpioledsgrp {
478: fsl,pins = <
479: MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
480: MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
481: MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
482: >;
483: };
484:
485: pinctrl_gpmi_nand: gpminandgrp {
486: fsl,pins = <
487: MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
488: MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
489: MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
490: MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
491: MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
492: MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
493: MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
494: MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
495: MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
496: MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
497: MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
498: MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
499: MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
500: MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
501: MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
502: >;
503: };
504:
505: pinctrl_i2c1: i2c1grp {
506: fsl,pins = <
507: MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
508: MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
509: >;
510: };
511:
512: pinctrl_i2c2: i2c2grp {
513: fsl,pins = <
514: MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
515: MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
516: >;
517: };
518:
519: pinctrl_i2c3: i2c3grp {
520: fsl,pins = <
521: MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
522: MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
523: >;
524: };
525:
526: pinctrl_pcie: pciegrp {
527: fsl,pins = <
528: MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
529: >;
530: };
531:
532: pinctrl_pmic: pmicgrp {
533: fsl,pins = <
534: MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
535: >;
536: };
537:
538: pinctrl_pps: ppsgrp {
539: fsl,pins = <
540: MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
541: >;
542: };
543:
544: pinctrl_pwm2: pwm2grp {
545: fsl,pins = <
546: MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
547: >;
548: };
549:
550: pinctrl_pwm3: pwm3grp {
551: fsl,pins = <
552: MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
553: >;
554: };
555:
556: pinctrl_pwm4: pwm4grp {
557: fsl,pins = <
558: MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
559: >;
560: };
561:
562: pinctrl_uart1: uart1grp {
563: fsl,pins = <
564: MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
565: MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
566: MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
567: >;
568: };
569:
570: pinctrl_uart2: uart2grp {
571: fsl,pins = <
572: MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
573: MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
574: >;
575: };
576:
577: pinctrl_uart5: uart5grp {
578: fsl,pins = <
579: MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
580: MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
581: >;
582: };
583:
584: pinctrl_usbotg: usbotggrp {
585: fsl,pins = <
586: MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
587: MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
588: >;
589: };
590:
591: pinctrl_usdhc3: usdhc3grp {
592: fsl,pins = <
593: MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
594: MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
595: MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
596: MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
597: MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
598: MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
599: MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
600: MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
601: >;
602: };
603:
604: pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
605: fsl,pins = <
606: MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
607: MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
608: MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
609: MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
610: MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
611: MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
612: MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
613: MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
614: >;
615: };
616:
617: pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
618: fsl,pins = <
619: MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
620: MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
621: MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
622: MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
623: MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
624: MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
625: MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
626: MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
627: >;
628: };
629:
630: pinctrl_wdog: wdoggrp {
631: fsl,pins = <
632: MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
633: >;
634: };
635: };
636: };