version 1.1.1.2, 2017/10/28 10:30:31 |
version 1.1.1.3, 2017/11/30 19:40:50 |
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pinctrl-0 = <&pinctrl_i2c3>; |
pinctrl-0 = <&pinctrl_i2c3>; |
status = "okay"; |
status = "okay"; |
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codec: sgtl5000@0a { |
codec: sgtl5000@a { |
compatible = "fsl,sgtl5000"; |
compatible = "fsl,sgtl5000"; |
reg = <0x0a>; |
reg = <0x0a>; |
clocks = <&clks IMX6QDL_CLK_CKO>; |
clocks = <&clks IMX6QDL_CLK_CKO>; |
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VDDIO-supply = <®_3p3v>; |
VDDIO-supply = <®_3p3v>; |
}; |
}; |
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touchscreen: egalax_ts@04 { |
touchscreen: egalax_ts@4 { |
compatible = "eeti,egalax_ts"; |
compatible = "eeti,egalax_ts"; |
reg = <0x04>; |
reg = <0x04>; |
interrupt-parent = <&gpio7>; |
interrupt-parent = <&gpio7>; |
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}; |
}; |
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&iomuxc { |
&iomuxc { |
imx6qdl-gw52xx { |
pinctrl_audmux: audmuxgrp { |
pinctrl_audmux: audmuxgrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 |
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 |
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 |
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 |
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 |
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 |
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 |
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 |
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ |
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ |
>; |
>; |
}; |
}; |
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pinctrl_ecspi3: escpi3grp { |
pinctrl_ecspi3: escpi3grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 |
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 |
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 |
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 |
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 |
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 |
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 |
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 |
>; |
>; |
}; |
}; |
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pinctrl_enet: enetgrp { |
pinctrl_enet: enetgrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 |
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 |
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 |
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 |
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 |
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 |
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 |
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 |
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 |
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 |
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 |
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 |
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 |
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 |
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 |
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 |
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 |
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 |
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 |
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 |
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 |
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 |
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 |
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 |
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ |
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ |
>; |
>; |
}; |
}; |
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pinctrl_flexcan1: flexcan1grp { |
pinctrl_flexcan1: flexcan1grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 |
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 |
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 |
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 |
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ |
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ |
>; |
>; |
}; |
}; |
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pinctrl_gpio_leds: gpioledsgrp { |
pinctrl_gpio_leds: gpioledsgrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 |
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 |
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 |
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 |
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 |
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 |
>; |
>; |
}; |
}; |
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pinctrl_gpmi_nand: gpminandgrp { |
pinctrl_gpmi_nand: gpminandgrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 |
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 |
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 |
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 |
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 |
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 |
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 |
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 |
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 |
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 |
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 |
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 |
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 |
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 |
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 |
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 |
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 |
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 |
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 |
>; |
>; |
}; |
}; |
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pinctrl_i2c1: i2c1grp { |
pinctrl_i2c1: i2c1grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
>; |
>; |
}; |
}; |
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pinctrl_i2c2: i2c2grp { |
pinctrl_i2c2: i2c2grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
>; |
>; |
}; |
}; |
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pinctrl_i2c3: i2c3grp { |
pinctrl_i2c3: i2c3grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 |
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 |
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 |
>; |
>; |
}; |
}; |
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pinctrl_pcie: pciegrp { |
pinctrl_pcie: pciegrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ |
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ |
>; |
>; |
}; |
}; |
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pinctrl_pmic: pmicgrp { |
pinctrl_pmic: pmicgrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ |
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ |
>; |
>; |
}; |
}; |
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pinctrl_pps: ppsgrp { |
pinctrl_pps: ppsgrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 |
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 |
>; |
>; |
}; |
}; |
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pinctrl_pwm2: pwm2grp { |
pinctrl_pwm2: pwm2grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 |
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 |
>; |
>; |
}; |
}; |
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pinctrl_pwm3: pwm3grp { |
pinctrl_pwm3: pwm3grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 |
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 |
>; |
>; |
}; |
}; |
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pinctrl_pwm4: pwm4grp { |
pinctrl_pwm4: pwm4grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 |
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 |
>; |
>; |
}; |
}; |
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pinctrl_uart1: uart1grp { |
pinctrl_uart1: uart1grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 |
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 |
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 |
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 |
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ |
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ |
>; |
>; |
}; |
}; |
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pinctrl_uart2: uart2grp { |
pinctrl_uart2: uart2grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 |
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 |
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 |
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 |
>; |
>; |
}; |
}; |
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pinctrl_uart5: uart5grp { |
pinctrl_uart5: uart5grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 |
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 |
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 |
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 |
>; |
>; |
}; |
}; |
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pinctrl_usbotg: usbotggrp { |
pinctrl_usbotg: usbotggrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 |
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 |
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ |
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ |
>; |
>; |
}; |
}; |
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pinctrl_usdhc3: usdhc3grp { |
pinctrl_usdhc3: usdhc3grp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ |
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ |
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 |
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 |
>; |
>; |
}; |
}; |
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz { |
pinctrl_usdhc3_100mhz: usdhc3grp100mhz { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 |
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 |
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 |
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 |
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 |
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 |
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 |
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 |
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 |
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 |
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 |
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 |
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ |
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ |
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 |
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 |
>; |
>; |
}; |
}; |
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz { |
pinctrl_usdhc3_200mhz: usdhc3grp200mhz { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 |
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 |
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 |
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 |
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 |
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 |
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 |
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 |
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 |
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 |
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 |
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 |
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ |
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ |
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 |
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 |
>; |
>; |
}; |
}; |
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pinctrl_wdog: wdoggrp { |
pinctrl_wdog: wdoggrp { |
fsl,pins = < |
fsl,pins = < |
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 |
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 |
>; |
>; |
}; |
|
}; |
}; |
}; |
}; |