version 1.1.1.1, 2017/06/15 20:14:24 |
version 1.1.1.2, 2017/10/28 10:30:31 |
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}; |
}; |
}; |
}; |
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capture-subsystem { |
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compatible = "fsl,imx-capture-subsystem"; |
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ports = <&ipu1_csi0>, <&ipu1_csi1>; |
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}; |
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display-subsystem { |
display-subsystem { |
compatible = "fsl,imx-display-subsystem"; |
compatible = "fsl,imx-display-subsystem"; |
ports = <&ipu1_di0>, <&ipu1_di1>; |
ports = <&ipu1_di0>, <&ipu1_di1>; |
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<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; |
<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; |
}; |
}; |
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&gpr { |
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ipu1_csi0_mux: ipu1_csi0_mux@34 { |
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compatible = "video-mux"; |
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mux-controls = <&mux 0>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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ipu1_csi0_mux_from_mipi_vc0: endpoint { |
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remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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ipu1_csi0_mux_from_mipi_vc1: endpoint { |
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remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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ipu1_csi0_mux_from_mipi_vc2: endpoint { |
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remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>; |
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}; |
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}; |
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port@3 { |
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reg = <3>; |
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ipu1_csi0_mux_from_mipi_vc3: endpoint { |
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remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>; |
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}; |
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}; |
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port@4 { |
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reg = <4>; |
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ipu1_csi0_mux_from_parallel_sensor: endpoint { |
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}; |
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}; |
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port@5 { |
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reg = <5>; |
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ipu1_csi0_mux_to_ipu1_csi0: endpoint { |
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remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; |
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}; |
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}; |
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}; |
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ipu1_csi1_mux: ipu1_csi1_mux@34 { |
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compatible = "video-mux"; |
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mux-controls = <&mux 1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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ipu1_csi1_mux_from_mipi_vc0: endpoint { |
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remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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ipu1_csi1_mux_from_mipi_vc1: endpoint { |
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remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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ipu1_csi1_mux_from_mipi_vc2: endpoint { |
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remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>; |
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}; |
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}; |
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port@3 { |
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reg = <3>; |
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ipu1_csi1_mux_from_mipi_vc3: endpoint { |
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remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>; |
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}; |
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}; |
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port@4 { |
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reg = <4>; |
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ipu1_csi1_mux_from_parallel_sensor: endpoint { |
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}; |
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}; |
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port@5 { |
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reg = <5>; |
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ipu1_csi1_mux_to_ipu1_csi1: endpoint { |
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remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>; |
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}; |
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}; |
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}; |
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}; |
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&gpt { |
&gpt { |
compatible = "fsl,imx6dl-gpt"; |
compatible = "fsl,imx6dl-gpt"; |
}; |
}; |
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compatible = "fsl,imx6dl-hdmi"; |
compatible = "fsl,imx6dl-hdmi"; |
}; |
}; |
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&ipu1_csi1 { |
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ipu1_csi1_from_ipu1_csi1_mux: endpoint { |
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remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; |
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}; |
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}; |
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&ldb { |
&ldb { |
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, |
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, |
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, |
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, |
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"di0", "di1"; |
"di0", "di1"; |
}; |
}; |
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&mipi_csi { |
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port@1 { |
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reg = <1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { |
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; |
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}; |
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mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { |
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { |
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; |
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}; |
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mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { |
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; |
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}; |
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}; |
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port@3 { |
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reg = <3>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { |
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; |
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}; |
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mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { |
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; |
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}; |
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}; |
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port@4 { |
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reg = <4>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { |
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; |
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}; |
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mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { |
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; |
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}; |
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}; |
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}; |
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&mux { |
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mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ |
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<0x34 0x00000038>, /* IPU_CSI1_MUX */ |
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<0x0c 0x0000000c>, /* HDMI_MUX_CTL */ |
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<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ |
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<0x0c 0x00000300>, /* LVDS1_MUX_CTL */ |
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<0x28 0x00000003>, /* DCIC1_MUX_CTL */ |
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<0x28 0x0000000c>; /* DCIC2_MUX_CTL */ |
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}; |
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&vpu { |
&vpu { |
compatible = "fsl,imx6dl-vpu", "cnm,coda960"; |
compatible = "fsl,imx6dl-vpu", "cnm,coda960"; |
}; |
}; |