version 1.1.1.3, 2017/11/30 19:40:50 |
version 1.1.1.3.4.1, 2018/05/02 07:20:14 |
|
|
* Also for U-Boot there must be a pre-existing /memory node. |
* Also for U-Boot there must be a pre-existing /memory node. |
*/ |
*/ |
chosen {}; |
chosen {}; |
memory { device_type = "memory"; reg = <0 0>; }; |
memory { device_type = "memory"; }; |
|
|
aliases { |
aliases { |
ethernet0 = &fec; |
ethernet0 = &fec; |
|
|
}; |
}; |
}; |
}; |
|
|
|
pmu { |
|
compatible = "arm,cortex-a8-pmu"; |
|
interrupt-parent = <&tzic>; |
|
interrupts = <77>; |
|
}; |
|
|
|
usbphy0: usbphy-0 { |
|
compatible = "usb-nop-xceiv"; |
|
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
|
clock-names = "main_clk"; |
|
#phy-cells = <0>; |
|
status = "okay"; |
|
}; |
|
|
|
usbphy1: usbphy-1 { |
|
compatible = "usb-nop-xceiv"; |
|
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
|
clock-names = "main_clk"; |
|
#phy-cells = <0>; |
|
status = "okay"; |
|
}; |
|
|
soc { |
soc { |
#address-cells = <1>; |
#address-cells = <1>; |
#size-cells = <1>; |
#size-cells = <1>; |
|
|
reg = <0x53f00000 0x60>; |
reg = <0x53f00000 0x60>; |
}; |
}; |
|
|
usbphy0: usbphy-0 { |
|
compatible = "usb-nop-xceiv"; |
|
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
|
clock-names = "main_clk"; |
|
status = "okay"; |
|
}; |
|
|
|
usbphy1: usbphy-1 { |
|
compatible = "usb-nop-xceiv"; |
|
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
|
clock-names = "main_clk"; |
|
status = "okay"; |
|
}; |
|
|
|
usbotg: usb@53f80000 { |
usbotg: usb@53f80000 { |
compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
reg = <0x53f80000 0x0200>; |
reg = <0x53f80000 0x0200>; |
|
|
clock-names = "ipg", "per"; |
clock-names = "ipg", "per"; |
}; |
}; |
|
|
srtc: srtc@53fa4000 { |
srtc: rtc@53fa4000 { |
compatible = "fsl,imx53-rtc", "fsl,imx25-rtc"; |
compatible = "fsl,imx53-rtc"; |
reg = <0x53fa4000 0x4000>; |
reg = <0x53fa4000 0x4000>; |
interrupts = <24>; |
interrupts = <24>; |
interrupt-parent = <&tzic>; |
|
clocks = <&clks IMX5_CLK_SRTC_GATE>; |
clocks = <&clks IMX5_CLK_SRTC_GATE>; |
clock-names = "ipg"; |
|
}; |
}; |
|
|
iomuxc: iomuxc@53fa8000 { |
iomuxc: iomuxc@53fa8000 { |
|
|
}; |
}; |
|
|
can1: can@53fc8000 { |
can1: can@53fc8000 { |
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
compatible = "fsl,imx53-flexcan"; |
reg = <0x53fc8000 0x4000>; |
reg = <0x53fc8000 0x4000>; |
interrupts = <82>; |
interrupts = <82>; |
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
|
|
}; |
}; |
|
|
can2: can@53fcc000 { |
can2: can@53fcc000 { |
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; |
compatible = "fsl,imx53-flexcan"; |
reg = <0x53fcc000 0x4000>; |
reg = <0x53fcc000 0x4000>; |
interrupts = <83>; |
interrupts = <83>; |
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
|
|
reg = <0xf8000000 0x20000>; |
reg = <0xf8000000 0x20000>; |
clocks = <&clks IMX5_CLK_OCRAM>; |
clocks = <&clks IMX5_CLK_OCRAM>; |
}; |
}; |
|
|
pmu { |
|
compatible = "arm,cortex-a8-pmu"; |
|
interrupts = <77>; |
|
}; |
|
}; |
}; |
}; |
}; |