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1.1.1.5 jmcneill 1: // SPDX-License-Identifier: GPL-2.0
1.1 jmcneill 2: /*
3: * SAMSUNG EXYNOS5420 SoC device tree source
4: *
5: * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6: * http://www.samsung.com
7: *
8: * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
9: * EXYNOS5420 based board files can include this file and provide
10: * values for board specfic bindings.
11: */
12:
13: #include "exynos54xx.dtsi"
14: #include <dt-bindings/clock/exynos5420.h>
15: #include <dt-bindings/clock/exynos-audss-clk.h>
16: #include <dt-bindings/interrupt-controller/arm-gic.h>
17:
18: / {
19: compatible = "samsung,exynos5420", "samsung,exynos5";
20:
21: aliases {
22: mshc0 = &mmc_0;
23: mshc1 = &mmc_1;
24: mshc2 = &mmc_2;
25: pinctrl0 = &pinctrl_0;
26: pinctrl1 = &pinctrl_1;
27: pinctrl2 = &pinctrl_2;
28: pinctrl3 = &pinctrl_3;
29: pinctrl4 = &pinctrl_4;
30: i2c8 = &hsi2c_8;
31: i2c9 = &hsi2c_9;
32: i2c10 = &hsi2c_10;
33: gsc0 = &gsc_0;
34: gsc1 = &gsc_1;
35: spi0 = &spi_0;
36: spi1 = &spi_1;
37: spi2 = &spi_2;
38: };
39:
40: /*
41: * The 'cpus' node is not present here but instead it is provided
42: * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
43: */
44:
45: soc: soc {
46: cluster_a15_opp_table: opp_table0 {
47: compatible = "operating-points-v2";
48: opp-shared;
1.1.1.2 jmcneill 49: opp-1800000000 {
1.1 jmcneill 50: opp-hz = /bits/ 64 <1800000000>;
51: opp-microvolt = <1250000>;
52: clock-latency-ns = <140000>;
53: };
1.1.1.2 jmcneill 54: opp-1700000000 {
1.1 jmcneill 55: opp-hz = /bits/ 64 <1700000000>;
56: opp-microvolt = <1212500>;
57: clock-latency-ns = <140000>;
58: };
1.1.1.2 jmcneill 59: opp-1600000000 {
1.1 jmcneill 60: opp-hz = /bits/ 64 <1600000000>;
61: opp-microvolt = <1175000>;
62: clock-latency-ns = <140000>;
63: };
1.1.1.2 jmcneill 64: opp-1500000000 {
1.1 jmcneill 65: opp-hz = /bits/ 64 <1500000000>;
66: opp-microvolt = <1137500>;
67: clock-latency-ns = <140000>;
68: };
1.1.1.2 jmcneill 69: opp-1400000000 {
1.1 jmcneill 70: opp-hz = /bits/ 64 <1400000000>;
71: opp-microvolt = <1112500>;
72: clock-latency-ns = <140000>;
73: };
1.1.1.2 jmcneill 74: opp-1300000000 {
1.1 jmcneill 75: opp-hz = /bits/ 64 <1300000000>;
76: opp-microvolt = <1062500>;
77: clock-latency-ns = <140000>;
78: };
1.1.1.2 jmcneill 79: opp-1200000000 {
1.1 jmcneill 80: opp-hz = /bits/ 64 <1200000000>;
81: opp-microvolt = <1037500>;
82: clock-latency-ns = <140000>;
83: };
1.1.1.2 jmcneill 84: opp-1100000000 {
1.1 jmcneill 85: opp-hz = /bits/ 64 <1100000000>;
86: opp-microvolt = <1012500>;
87: clock-latency-ns = <140000>;
88: };
1.1.1.2 jmcneill 89: opp-1000000000 {
1.1 jmcneill 90: opp-hz = /bits/ 64 <1000000000>;
91: opp-microvolt = < 987500>;
92: clock-latency-ns = <140000>;
93: };
1.1.1.2 jmcneill 94: opp-900000000 {
1.1 jmcneill 95: opp-hz = /bits/ 64 <900000000>;
96: opp-microvolt = < 962500>;
97: clock-latency-ns = <140000>;
98: };
1.1.1.2 jmcneill 99: opp-800000000 {
1.1 jmcneill 100: opp-hz = /bits/ 64 <800000000>;
101: opp-microvolt = < 937500>;
102: clock-latency-ns = <140000>;
103: };
1.1.1.2 jmcneill 104: opp-700000000 {
1.1 jmcneill 105: opp-hz = /bits/ 64 <700000000>;
106: opp-microvolt = < 912500>;
107: clock-latency-ns = <140000>;
108: };
109: };
110:
111: cluster_a7_opp_table: opp_table1 {
112: compatible = "operating-points-v2";
113: opp-shared;
1.1.1.2 jmcneill 114: opp-1300000000 {
1.1 jmcneill 115: opp-hz = /bits/ 64 <1300000000>;
116: opp-microvolt = <1275000>;
117: clock-latency-ns = <140000>;
118: };
1.1.1.2 jmcneill 119: opp-1200000000 {
1.1 jmcneill 120: opp-hz = /bits/ 64 <1200000000>;
121: opp-microvolt = <1212500>;
122: clock-latency-ns = <140000>;
123: };
1.1.1.2 jmcneill 124: opp-1100000000 {
1.1 jmcneill 125: opp-hz = /bits/ 64 <1100000000>;
126: opp-microvolt = <1162500>;
127: clock-latency-ns = <140000>;
128: };
1.1.1.2 jmcneill 129: opp-1000000000 {
1.1 jmcneill 130: opp-hz = /bits/ 64 <1000000000>;
131: opp-microvolt = <1112500>;
132: clock-latency-ns = <140000>;
133: };
1.1.1.2 jmcneill 134: opp-900000000 {
1.1 jmcneill 135: opp-hz = /bits/ 64 <900000000>;
136: opp-microvolt = <1062500>;
137: clock-latency-ns = <140000>;
138: };
1.1.1.2 jmcneill 139: opp-800000000 {
1.1 jmcneill 140: opp-hz = /bits/ 64 <800000000>;
141: opp-microvolt = <1025000>;
142: clock-latency-ns = <140000>;
143: };
1.1.1.2 jmcneill 144: opp-700000000 {
1.1 jmcneill 145: opp-hz = /bits/ 64 <700000000>;
146: opp-microvolt = <975000>;
147: clock-latency-ns = <140000>;
148: };
1.1.1.2 jmcneill 149: opp-600000000 {
1.1 jmcneill 150: opp-hz = /bits/ 64 <600000000>;
151: opp-microvolt = <937500>;
152: clock-latency-ns = <140000>;
153: };
154: };
155:
156: cci: cci@10d20000 {
157: compatible = "arm,cci-400";
158: #address-cells = <1>;
159: #size-cells = <1>;
160: reg = <0x10d20000 0x1000>;
161: ranges = <0x0 0x10d20000 0x6000>;
162:
163: cci_control0: slave-if@4000 {
164: compatible = "arm,cci-400-ctrl-if";
165: interface-type = "ace";
166: reg = <0x4000 0x1000>;
167: };
168: cci_control1: slave-if@5000 {
169: compatible = "arm,cci-400-ctrl-if";
170: interface-type = "ace";
171: reg = <0x5000 0x1000>;
172: };
173: };
174:
175: clock: clock-controller@10010000 {
176: compatible = "samsung,exynos5420-clock";
177: reg = <0x10010000 0x30000>;
178: #clock-cells = <1>;
179: };
180:
181: clock_audss: audss-clock-controller@3810000 {
182: compatible = "samsung,exynos5420-audss-clock";
183: reg = <0x03810000 0x0C>;
184: #clock-cells = <1>;
185: clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
186: <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
187: clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
1.1.1.5 jmcneill 188: power-domains = <&mau_pd>;
1.1 jmcneill 189: };
190:
191: mfc: codec@11000000 {
192: compatible = "samsung,mfc-v7";
193: reg = <0x11000000 0x10000>;
1.1.1.3 jmcneill 194: interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 195: clocks = <&clock CLK_MFC>;
196: clock-names = "mfc";
197: power-domains = <&mfc_pd>;
198: iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
199: iommu-names = "left", "right";
200: };
201:
202: mmc_0: mmc@12200000 {
203: compatible = "samsung,exynos5420-dw-mshc-smu";
1.1.1.3 jmcneill 204: interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 205: #address-cells = <1>;
206: #size-cells = <0>;
207: reg = <0x12200000 0x2000>;
208: clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
209: clock-names = "biu", "ciu";
210: fifo-depth = <0x40>;
211: status = "disabled";
212: };
213:
214: mmc_1: mmc@12210000 {
215: compatible = "samsung,exynos5420-dw-mshc-smu";
1.1.1.3 jmcneill 216: interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 217: #address-cells = <1>;
218: #size-cells = <0>;
219: reg = <0x12210000 0x2000>;
220: clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
221: clock-names = "biu", "ciu";
222: fifo-depth = <0x40>;
223: status = "disabled";
224: };
225:
226: mmc_2: mmc@12220000 {
227: compatible = "samsung,exynos5420-dw-mshc";
1.1.1.3 jmcneill 228: interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 229: #address-cells = <1>;
230: #size-cells = <0>;
231: reg = <0x12220000 0x1000>;
232: clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
233: clock-names = "biu", "ciu";
234: fifo-depth = <0x40>;
235: status = "disabled";
236: };
237:
1.1.1.5 jmcneill 238: nocp_mem0_0: nocp@10ca1000 {
1.1 jmcneill 239: compatible = "samsung,exynos5420-nocp";
240: reg = <0x10CA1000 0x200>;
241: status = "disabled";
242: };
243:
1.1.1.5 jmcneill 244: nocp_mem0_1: nocp@10ca1400 {
1.1 jmcneill 245: compatible = "samsung,exynos5420-nocp";
246: reg = <0x10CA1400 0x200>;
247: status = "disabled";
248: };
249:
1.1.1.5 jmcneill 250: nocp_mem1_0: nocp@10ca1800 {
1.1 jmcneill 251: compatible = "samsung,exynos5420-nocp";
252: reg = <0x10CA1800 0x200>;
253: status = "disabled";
254: };
255:
1.1.1.5 jmcneill 256: nocp_mem1_1: nocp@10ca1c00 {
1.1 jmcneill 257: compatible = "samsung,exynos5420-nocp";
258: reg = <0x10CA1C00 0x200>;
259: status = "disabled";
260: };
261:
1.1.1.5 jmcneill 262: nocp_g3d_0: nocp@11a51000 {
1.1 jmcneill 263: compatible = "samsung,exynos5420-nocp";
264: reg = <0x11A51000 0x200>;
265: status = "disabled";
266: };
267:
1.1.1.5 jmcneill 268: nocp_g3d_1: nocp@11a51400 {
1.1 jmcneill 269: compatible = "samsung,exynos5420-nocp";
270: reg = <0x11A51400 0x200>;
271: status = "disabled";
272: };
273:
274: gsc_pd: power-domain@10044000 {
275: compatible = "samsung,exynos4210-pd";
276: reg = <0x10044000 0x20>;
277: #power-domain-cells = <0>;
278: label = "GSC";
279: };
280:
281: isp_pd: power-domain@10044020 {
282: compatible = "samsung,exynos4210-pd";
283: reg = <0x10044020 0x20>;
284: #power-domain-cells = <0>;
285: label = "ISP";
286: };
287:
288: mfc_pd: power-domain@10044060 {
289: compatible = "samsung,exynos4210-pd";
290: reg = <0x10044060 0x20>;
291: #power-domain-cells = <0>;
292: label = "MFC";
293: };
294:
295: msc_pd: power-domain@10044120 {
296: compatible = "samsung,exynos4210-pd";
297: reg = <0x10044120 0x20>;
298: #power-domain-cells = <0>;
299: label = "MSC";
300: };
301:
1.1.1.5 jmcneill 302: disp_pd: power-domain@100440c0 {
1.1 jmcneill 303: compatible = "samsung,exynos4210-pd";
304: reg = <0x100440C0 0x20>;
305: #power-domain-cells = <0>;
306: label = "DISP";
307: };
308:
1.1.1.5 jmcneill 309: mau_pd: power-domain@100440e0 {
310: compatible = "samsung,exynos4210-pd";
311: reg = <0x100440E0 0x20>;
312: #power-domain-cells = <0>;
313: label = "MAU";
314: };
315:
1.1 jmcneill 316: pinctrl_0: pinctrl@13400000 {
317: compatible = "samsung,exynos5420-pinctrl";
318: reg = <0x13400000 0x1000>;
1.1.1.3 jmcneill 319: interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 320:
321: wakeup-interrupt-controller {
322: compatible = "samsung,exynos4210-wakeup-eint";
323: interrupt-parent = <&gic>;
1.1.1.3 jmcneill 324: interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 325: };
326: };
327:
328: pinctrl_1: pinctrl@13410000 {
329: compatible = "samsung,exynos5420-pinctrl";
330: reg = <0x13410000 0x1000>;
1.1.1.3 jmcneill 331: interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 332: };
333:
334: pinctrl_2: pinctrl@14000000 {
335: compatible = "samsung,exynos5420-pinctrl";
336: reg = <0x14000000 0x1000>;
1.1.1.3 jmcneill 337: interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 338: };
339:
340: pinctrl_3: pinctrl@14010000 {
341: compatible = "samsung,exynos5420-pinctrl";
342: reg = <0x14010000 0x1000>;
1.1.1.3 jmcneill 343: interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 344: };
345:
1.1.1.4 jmcneill 346: pinctrl_4: pinctrl@3860000 {
1.1 jmcneill 347: compatible = "samsung,exynos5420-pinctrl";
348: reg = <0x03860000 0x1000>;
1.1.1.3 jmcneill 349: interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1.1.1.5 jmcneill 350: power-domains = <&mau_pd>;
1.1 jmcneill 351: };
352:
353: amba {
354: #address-cells = <1>;
355: #size-cells = <1>;
356: compatible = "simple-bus";
357: interrupt-parent = <&gic>;
358: ranges;
359:
1.1.1.4 jmcneill 360: adma: adma@3880000 {
1.1 jmcneill 361: compatible = "arm,pl330", "arm,primecell";
362: reg = <0x03880000 0x1000>;
1.1.1.3 jmcneill 363: interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 364: clocks = <&clock_audss EXYNOS_ADMA>;
365: clock-names = "apb_pclk";
366: #dma-cells = <1>;
367: #dma-channels = <6>;
368: #dma-requests = <16>;
1.1.1.5 jmcneill 369: power-domains = <&mau_pd>;
1.1 jmcneill 370: };
371:
1.1.1.5 jmcneill 372: pdma0: pdma@121a0000 {
1.1 jmcneill 373: compatible = "arm,pl330", "arm,primecell";
374: reg = <0x121A0000 0x1000>;
1.1.1.3 jmcneill 375: interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 376: clocks = <&clock CLK_PDMA0>;
377: clock-names = "apb_pclk";
378: #dma-cells = <1>;
379: #dma-channels = <8>;
380: #dma-requests = <32>;
381: };
382:
1.1.1.5 jmcneill 383: pdma1: pdma@121b0000 {
1.1 jmcneill 384: compatible = "arm,pl330", "arm,primecell";
385: reg = <0x121B0000 0x1000>;
1.1.1.3 jmcneill 386: interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 387: clocks = <&clock CLK_PDMA1>;
388: clock-names = "apb_pclk";
389: #dma-cells = <1>;
390: #dma-channels = <8>;
391: #dma-requests = <32>;
392: };
393:
394: mdma0: mdma@10800000 {
395: compatible = "arm,pl330", "arm,primecell";
396: reg = <0x10800000 0x1000>;
1.1.1.3 jmcneill 397: interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 398: clocks = <&clock CLK_MDMA0>;
399: clock-names = "apb_pclk";
400: #dma-cells = <1>;
401: #dma-channels = <8>;
402: #dma-requests = <1>;
403: };
404:
1.1.1.5 jmcneill 405: mdma1: mdma@11c10000 {
1.1 jmcneill 406: compatible = "arm,pl330", "arm,primecell";
407: reg = <0x11C10000 0x1000>;
1.1.1.3 jmcneill 408: interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 409: clocks = <&clock CLK_MDMA1>;
410: clock-names = "apb_pclk";
411: #dma-cells = <1>;
412: #dma-channels = <8>;
413: #dma-requests = <1>;
414: /*
415: * MDMA1 can support both secure and non-secure
416: * AXI transactions. When this is enabled in
417: * the kernel for boards that run in secure
418: * mode, we are getting imprecise external
419: * aborts causing the kernel to oops.
420: */
421: status = "disabled";
422: };
423: };
424:
1.1.1.4 jmcneill 425: i2s0: i2s@3830000 {
1.1 jmcneill 426: compatible = "samsung,exynos5420-i2s";
427: reg = <0x03830000 0x100>;
428: dmas = <&adma 0
429: &adma 2
430: &adma 1>;
431: dma-names = "tx", "rx", "tx-sec";
432: clocks = <&clock_audss EXYNOS_I2S_BUS>,
433: <&clock_audss EXYNOS_I2S_BUS>,
434: <&clock_audss EXYNOS_SCLK_I2S>;
435: clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
436: #clock-cells = <1>;
437: clock-output-names = "i2s_cdclk0";
438: #sound-dai-cells = <1>;
439: samsung,idma-addr = <0x03000000>;
440: pinctrl-names = "default";
441: pinctrl-0 = <&i2s0_bus>;
1.1.1.5 jmcneill 442: power-domains = <&mau_pd>;
1.1 jmcneill 443: status = "disabled";
444: };
445:
1.1.1.5 jmcneill 446: i2s1: i2s@12d60000 {
1.1 jmcneill 447: compatible = "samsung,exynos5420-i2s";
448: reg = <0x12D60000 0x100>;
449: dmas = <&pdma1 12
450: &pdma1 11>;
451: dma-names = "tx", "rx";
452: clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
453: clock-names = "iis", "i2s_opclk0";
454: #clock-cells = <1>;
455: clock-output-names = "i2s_cdclk1";
456: #sound-dai-cells = <1>;
457: pinctrl-names = "default";
458: pinctrl-0 = <&i2s1_bus>;
459: status = "disabled";
460: };
461:
1.1.1.5 jmcneill 462: i2s2: i2s@12d70000 {
1.1 jmcneill 463: compatible = "samsung,exynos5420-i2s";
464: reg = <0x12D70000 0x100>;
465: dmas = <&pdma0 12
466: &pdma0 11>;
467: dma-names = "tx", "rx";
468: clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
469: clock-names = "iis", "i2s_opclk0";
470: #clock-cells = <1>;
471: clock-output-names = "i2s_cdclk2";
472: #sound-dai-cells = <1>;
473: pinctrl-names = "default";
474: pinctrl-0 = <&i2s2_bus>;
475: status = "disabled";
476: };
477:
478: spi_0: spi@12d20000 {
479: compatible = "samsung,exynos4210-spi";
480: reg = <0x12d20000 0x100>;
1.1.1.3 jmcneill 481: interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 482: dmas = <&pdma0 5
483: &pdma0 4>;
484: dma-names = "tx", "rx";
485: #address-cells = <1>;
486: #size-cells = <0>;
487: pinctrl-names = "default";
488: pinctrl-0 = <&spi0_bus>;
489: clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
490: clock-names = "spi", "spi_busclk0";
491: status = "disabled";
492: };
493:
494: spi_1: spi@12d30000 {
495: compatible = "samsung,exynos4210-spi";
496: reg = <0x12d30000 0x100>;
1.1.1.3 jmcneill 497: interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 498: dmas = <&pdma1 5
499: &pdma1 4>;
500: dma-names = "tx", "rx";
501: #address-cells = <1>;
502: #size-cells = <0>;
503: pinctrl-names = "default";
504: pinctrl-0 = <&spi1_bus>;
505: clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
506: clock-names = "spi", "spi_busclk0";
507: status = "disabled";
508: };
509:
510: spi_2: spi@12d40000 {
511: compatible = "samsung,exynos4210-spi";
512: reg = <0x12d40000 0x100>;
1.1.1.3 jmcneill 513: interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 514: dmas = <&pdma0 7
515: &pdma0 6>;
516: dma-names = "tx", "rx";
517: #address-cells = <1>;
518: #size-cells = <0>;
519: pinctrl-names = "default";
520: pinctrl-0 = <&spi2_bus>;
521: clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
522: clock-names = "spi", "spi_busclk0";
523: status = "disabled";
524: };
525:
526: dp_phy: dp-video-phy {
527: compatible = "samsung,exynos5420-dp-video-phy";
528: samsung,pmu-syscon = <&pmu_system_controller>;
529: #phy-cells = <0>;
530: };
531:
532: mipi_phy: mipi-video-phy {
533: compatible = "samsung,s5pv210-mipi-video-phy";
534: syscon = <&pmu_system_controller>;
535: #phy-cells = <1>;
536: };
537:
538: dsi@14500000 {
539: compatible = "samsung,exynos5410-mipi-dsi";
540: reg = <0x14500000 0x10000>;
1.1.1.3 jmcneill 541: interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 542: phys = <&mipi_phy 1>;
543: phy-names = "dsim";
544: clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
545: clock-names = "bus_clk", "pll_clk";
546: #address-cells = <1>;
547: #size-cells = <0>;
548: status = "disabled";
549: };
550:
1.1.1.5 jmcneill 551: adc: adc@12d10000 {
1.1 jmcneill 552: compatible = "samsung,exynos-adc-v2";
553: reg = <0x12D10000 0x100>;
1.1.1.3 jmcneill 554: interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 555: clocks = <&clock CLK_TSADC>;
556: clock-names = "adc";
557: #io-channel-cells = <1>;
558: io-channel-ranges;
559: samsung,syscon-phandle = <&pmu_system_controller>;
560: status = "disabled";
561: };
562:
1.1.1.5 jmcneill 563: hsi2c_8: i2c@12e00000 {
1.1 jmcneill 564: compatible = "samsung,exynos5250-hsi2c";
565: reg = <0x12E00000 0x1000>;
1.1.1.3 jmcneill 566: interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 567: #address-cells = <1>;
568: #size-cells = <0>;
569: pinctrl-names = "default";
570: pinctrl-0 = <&i2c8_hs_bus>;
571: clocks = <&clock CLK_USI4>;
572: clock-names = "hsi2c";
573: status = "disabled";
574: };
575:
1.1.1.5 jmcneill 576: hsi2c_9: i2c@12e10000 {
1.1 jmcneill 577: compatible = "samsung,exynos5250-hsi2c";
578: reg = <0x12E10000 0x1000>;
1.1.1.3 jmcneill 579: interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 580: #address-cells = <1>;
581: #size-cells = <0>;
582: pinctrl-names = "default";
583: pinctrl-0 = <&i2c9_hs_bus>;
584: clocks = <&clock CLK_USI5>;
585: clock-names = "hsi2c";
586: status = "disabled";
587: };
588:
1.1.1.5 jmcneill 589: hsi2c_10: i2c@12e20000 {
1.1 jmcneill 590: compatible = "samsung,exynos5250-hsi2c";
591: reg = <0x12E20000 0x1000>;
1.1.1.3 jmcneill 592: interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 593: #address-cells = <1>;
594: #size-cells = <0>;
595: pinctrl-names = "default";
596: pinctrl-0 = <&i2c10_hs_bus>;
597: clocks = <&clock CLK_USI6>;
598: clock-names = "hsi2c";
599: status = "disabled";
600: };
601:
602: hdmi: hdmi@14530000 {
603: compatible = "samsung,exynos5420-hdmi";
604: reg = <0x14530000 0x70000>;
1.1.1.3 jmcneill 605: interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 606: clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
607: <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
608: <&clock CLK_MOUT_HDMI>;
609: clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
610: "sclk_hdmiphy", "mout_hdmi";
611: phy = <&hdmiphy>;
612: samsung,syscon-phandle = <&pmu_system_controller>;
613: status = "disabled";
614: power-domains = <&disp_pd>;
1.1.1.5 jmcneill 615: #sound-dai-cells = <0>;
1.1 jmcneill 616: };
617:
1.1.1.5 jmcneill 618: hdmiphy: hdmiphy@145d0000 {
1.1 jmcneill 619: reg = <0x145D0000 0x20>;
620: };
621:
1.1.1.5 jmcneill 622: hdmicec: cec@101b0000 {
1.1.1.3 jmcneill 623: compatible = "samsung,s5p-cec";
624: reg = <0x101B0000 0x200>;
625: interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
626: clocks = <&clock CLK_HDMI_CEC>;
627: clock-names = "hdmicec";
628: samsung,syscon-phandle = <&pmu_system_controller>;
629: hdmi-phandle = <&hdmi>;
630: pinctrl-names = "default";
631: pinctrl-0 = <&hdmi_cec>;
632: status = "disabled";
633: };
634:
1.1 jmcneill 635: mixer: mixer@14450000 {
636: compatible = "samsung,exynos5420-mixer";
637: reg = <0x14450000 0x10000>;
1.1.1.3 jmcneill 638: interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 639: clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
640: <&clock CLK_SCLK_HDMI>;
641: clock-names = "mixer", "hdmi", "sclk_hdmi";
642: power-domains = <&disp_pd>;
643: iommus = <&sysmmu_tv>;
1.1.1.4 jmcneill 644: status = "disabled";
1.1 jmcneill 645: };
646:
1.1.1.5 jmcneill 647: rotator: rotator@11c00000 {
1.1 jmcneill 648: compatible = "samsung,exynos5250-rotator";
649: reg = <0x11C00000 0x64>;
1.1.1.3 jmcneill 650: interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 651: clocks = <&clock CLK_ROTATOR>;
652: clock-names = "rotator";
653: iommus = <&sysmmu_rotator>;
654: };
655:
656: gsc_0: video-scaler@13e00000 {
1.1.1.4 jmcneill 657: compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
1.1 jmcneill 658: reg = <0x13e00000 0x1000>;
1.1.1.3 jmcneill 659: interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 660: clocks = <&clock CLK_GSCL0>;
661: clock-names = "gscl";
662: power-domains = <&gsc_pd>;
663: iommus = <&sysmmu_gscl0>;
664: };
665:
666: gsc_1: video-scaler@13e10000 {
1.1.1.4 jmcneill 667: compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
1.1 jmcneill 668: reg = <0x13e10000 0x1000>;
1.1.1.3 jmcneill 669: interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 670: clocks = <&clock CLK_GSCL1>;
671: clock-names = "gscl";
672: power-domains = <&gsc_pd>;
673: iommus = <&sysmmu_gscl1>;
674: };
675:
1.1.1.6 jmcneill 676: scaler_0: scaler@12800000 {
677: compatible = "samsung,exynos5420-scaler";
678: reg = <0x12800000 0x1294>;
679: interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
680: clocks = <&clock CLK_MSCL0>;
681: clock-names = "mscl";
682: power-domains = <&msc_pd>;
683: iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
684: };
685:
686: scaler_1: scaler@12810000 {
687: compatible = "samsung,exynos5420-scaler";
688: reg = <0x12810000 0x1294>;
689: interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
690: clocks = <&clock CLK_MSCL1>;
691: clock-names = "mscl";
692: power-domains = <&msc_pd>;
693: iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
694: };
695:
696: scaler_2: scaler@12820000 {
697: compatible = "samsung,exynos5420-scaler";
698: reg = <0x12820000 0x1294>;
699: interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
700: clocks = <&clock CLK_MSCL2>;
701: clock-names = "mscl";
702: power-domains = <&msc_pd>;
703: iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
704: };
705:
1.1.1.5 jmcneill 706: jpeg_0: jpeg@11f50000 {
1.1 jmcneill 707: compatible = "samsung,exynos5420-jpeg";
708: reg = <0x11F50000 0x1000>;
1.1.1.3 jmcneill 709: interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 710: clock-names = "jpeg";
711: clocks = <&clock CLK_JPEG>;
712: iommus = <&sysmmu_jpeg0>;
713: };
714:
1.1.1.5 jmcneill 715: jpeg_1: jpeg@11f60000 {
1.1 jmcneill 716: compatible = "samsung,exynos5420-jpeg";
717: reg = <0x11F60000 0x1000>;
1.1.1.3 jmcneill 718: interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 719: clock-names = "jpeg";
720: clocks = <&clock CLK_JPEG2>;
721: iommus = <&sysmmu_jpeg1>;
722: };
723:
724: pmu_system_controller: system-controller@10040000 {
725: compatible = "samsung,exynos5420-pmu", "syscon";
726: reg = <0x10040000 0x5000>;
727: clock-names = "clkout16";
728: clocks = <&clock CLK_FIN_PLL>;
729: #clock-cells = <1>;
730: interrupt-controller;
731: #interrupt-cells = <3>;
732: interrupt-parent = <&gic>;
733: };
734:
735: tmu_cpu0: tmu@10060000 {
736: compatible = "samsung,exynos5420-tmu";
737: reg = <0x10060000 0x100>;
1.1.1.3 jmcneill 738: interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 739: clocks = <&clock CLK_TMU>;
740: clock-names = "tmu_apbif";
1.1.1.6.2.1! christos 741: #thermal-sensor-cells = <0>;
1.1 jmcneill 742: };
743:
744: tmu_cpu1: tmu@10064000 {
745: compatible = "samsung,exynos5420-tmu";
746: reg = <0x10064000 0x100>;
1.1.1.3 jmcneill 747: interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 748: clocks = <&clock CLK_TMU>;
749: clock-names = "tmu_apbif";
1.1.1.6.2.1! christos 750: #thermal-sensor-cells = <0>;
1.1 jmcneill 751: };
752:
753: tmu_cpu2: tmu@10068000 {
754: compatible = "samsung,exynos5420-tmu-ext-triminfo";
755: reg = <0x10068000 0x100>, <0x1006c000 0x4>;
1.1.1.3 jmcneill 756: interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 757: clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
758: clock-names = "tmu_apbif", "tmu_triminfo_apbif";
1.1.1.6.2.1! christos 759: #thermal-sensor-cells = <0>;
1.1 jmcneill 760: };
761:
762: tmu_cpu3: tmu@1006c000 {
763: compatible = "samsung,exynos5420-tmu-ext-triminfo";
764: reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
1.1.1.3 jmcneill 765: interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 766: clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
767: clock-names = "tmu_apbif", "tmu_triminfo_apbif";
1.1.1.6.2.1! christos 768: #thermal-sensor-cells = <0>;
1.1 jmcneill 769: };
770:
771: tmu_gpu: tmu@100a0000 {
772: compatible = "samsung,exynos5420-tmu-ext-triminfo";
773: reg = <0x100a0000 0x100>, <0x10068000 0x4>;
1.1.1.3 jmcneill 774: interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 775: clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
776: clock-names = "tmu_apbif", "tmu_triminfo_apbif";
1.1.1.6.2.1! christos 777: #thermal-sensor-cells = <0>;
1.1 jmcneill 778: };
779:
1.1.1.6 jmcneill 780: sysmmu_g2dr: sysmmu@10a60000 {
1.1 jmcneill 781: compatible = "samsung,exynos-sysmmu";
782: reg = <0x10A60000 0x1000>;
783: interrupt-parent = <&combiner>;
784: interrupts = <24 5>;
785: clock-names = "sysmmu", "master";
786: clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
787: #iommu-cells = <0>;
788: };
789:
1.1.1.6 jmcneill 790: sysmmu_g2dw: sysmmu@10a70000 {
1.1 jmcneill 791: compatible = "samsung,exynos-sysmmu";
792: reg = <0x10A70000 0x1000>;
793: interrupt-parent = <&combiner>;
794: interrupts = <22 2>;
795: clock-names = "sysmmu", "master";
796: clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
797: #iommu-cells = <0>;
798: };
799:
1.1.1.6 jmcneill 800: sysmmu_tv: sysmmu@14650000 {
1.1 jmcneill 801: compatible = "samsung,exynos-sysmmu";
802: reg = <0x14650000 0x1000>;
803: interrupt-parent = <&combiner>;
804: interrupts = <7 4>;
805: clock-names = "sysmmu", "master";
806: clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
807: power-domains = <&disp_pd>;
808: #iommu-cells = <0>;
809: };
810:
1.1.1.6 jmcneill 811: sysmmu_gscl0: sysmmu@13e80000 {
1.1 jmcneill 812: compatible = "samsung,exynos-sysmmu";
813: reg = <0x13E80000 0x1000>;
814: interrupt-parent = <&combiner>;
815: interrupts = <2 0>;
816: clock-names = "sysmmu", "master";
817: clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
818: power-domains = <&gsc_pd>;
819: #iommu-cells = <0>;
820: };
821:
1.1.1.6 jmcneill 822: sysmmu_gscl1: sysmmu@13e90000 {
1.1 jmcneill 823: compatible = "samsung,exynos-sysmmu";
824: reg = <0x13E90000 0x1000>;
825: interrupt-parent = <&combiner>;
826: interrupts = <2 2>;
827: clock-names = "sysmmu", "master";
828: clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
829: power-domains = <&gsc_pd>;
830: #iommu-cells = <0>;
831: };
832:
1.1.1.6 jmcneill 833: sysmmu_scaler0r: sysmmu@12880000 {
1.1 jmcneill 834: compatible = "samsung,exynos-sysmmu";
835: reg = <0x12880000 0x1000>;
836: interrupt-parent = <&combiner>;
837: interrupts = <22 4>;
838: clock-names = "sysmmu", "master";
839: clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1.1.1.6 jmcneill 840: power-domains = <&msc_pd>;
1.1 jmcneill 841: #iommu-cells = <0>;
842: };
843:
1.1.1.6 jmcneill 844: sysmmu_scaler1r: sysmmu@12890000 {
1.1 jmcneill 845: compatible = "samsung,exynos-sysmmu";
846: reg = <0x12890000 0x1000>;
1.1.1.3 jmcneill 847: interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 848: clock-names = "sysmmu", "master";
849: clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1.1.1.6 jmcneill 850: power-domains = <&msc_pd>;
1.1 jmcneill 851: #iommu-cells = <0>;
852: };
853:
1.1.1.6 jmcneill 854: sysmmu_scaler2r: sysmmu@128a0000 {
1.1 jmcneill 855: compatible = "samsung,exynos-sysmmu";
856: reg = <0x128A0000 0x1000>;
1.1.1.3 jmcneill 857: interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 858: clock-names = "sysmmu", "master";
859: clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1.1.1.6 jmcneill 860: power-domains = <&msc_pd>;
1.1 jmcneill 861: #iommu-cells = <0>;
862: };
863:
1.1.1.6 jmcneill 864: sysmmu_scaler0w: sysmmu@128c0000 {
1.1 jmcneill 865: compatible = "samsung,exynos-sysmmu";
866: reg = <0x128C0000 0x1000>;
867: interrupt-parent = <&combiner>;
868: interrupts = <27 2>;
869: clock-names = "sysmmu", "master";
870: clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1.1.1.6 jmcneill 871: power-domains = <&msc_pd>;
1.1 jmcneill 872: #iommu-cells = <0>;
873: };
874:
1.1.1.6 jmcneill 875: sysmmu_scaler1w: sysmmu@128d0000 {
1.1 jmcneill 876: compatible = "samsung,exynos-sysmmu";
877: reg = <0x128D0000 0x1000>;
878: interrupt-parent = <&combiner>;
879: interrupts = <22 6>;
880: clock-names = "sysmmu", "master";
881: clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1.1.1.6 jmcneill 882: power-domains = <&msc_pd>;
1.1 jmcneill 883: #iommu-cells = <0>;
884: };
885:
1.1.1.6 jmcneill 886: sysmmu_scaler2w: sysmmu@128e0000 {
1.1 jmcneill 887: compatible = "samsung,exynos-sysmmu";
888: reg = <0x128E0000 0x1000>;
889: interrupt-parent = <&combiner>;
890: interrupts = <19 6>;
891: clock-names = "sysmmu", "master";
892: clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1.1.1.6 jmcneill 893: power-domains = <&msc_pd>;
1.1 jmcneill 894: #iommu-cells = <0>;
895: };
896:
1.1.1.6 jmcneill 897: sysmmu_rotator: sysmmu@11d40000 {
1.1 jmcneill 898: compatible = "samsung,exynos-sysmmu";
899: reg = <0x11D40000 0x1000>;
900: interrupt-parent = <&combiner>;
901: interrupts = <4 0>;
902: clock-names = "sysmmu", "master";
903: clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
904: #iommu-cells = <0>;
905: };
906:
1.1.1.6 jmcneill 907: sysmmu_jpeg0: sysmmu@11f10000 {
1.1 jmcneill 908: compatible = "samsung,exynos-sysmmu";
909: reg = <0x11F10000 0x1000>;
910: interrupt-parent = <&combiner>;
911: interrupts = <4 2>;
912: clock-names = "sysmmu", "master";
913: clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
914: #iommu-cells = <0>;
915: };
916:
1.1.1.6 jmcneill 917: sysmmu_jpeg1: sysmmu@11f20000 {
1.1 jmcneill 918: compatible = "samsung,exynos-sysmmu";
919: reg = <0x11F20000 0x1000>;
1.1.1.3 jmcneill 920: interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1.1 jmcneill 921: clock-names = "sysmmu", "master";
922: clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
923: #iommu-cells = <0>;
924: };
925:
1.1.1.6 jmcneill 926: sysmmu_mfc_l: sysmmu@11200000 {
1.1 jmcneill 927: compatible = "samsung,exynos-sysmmu";
928: reg = <0x11200000 0x1000>;
929: interrupt-parent = <&combiner>;
930: interrupts = <6 2>;
931: clock-names = "sysmmu", "master";
932: clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
933: power-domains = <&mfc_pd>;
934: #iommu-cells = <0>;
935: };
936:
1.1.1.6 jmcneill 937: sysmmu_mfc_r: sysmmu@11210000 {
1.1 jmcneill 938: compatible = "samsung,exynos-sysmmu";
939: reg = <0x11210000 0x1000>;
940: interrupt-parent = <&combiner>;
941: interrupts = <8 5>;
942: clock-names = "sysmmu", "master";
943: clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
944: power-domains = <&mfc_pd>;
945: #iommu-cells = <0>;
946: };
947:
1.1.1.6 jmcneill 948: sysmmu_fimd1_0: sysmmu@14640000 {
1.1 jmcneill 949: compatible = "samsung,exynos-sysmmu";
950: reg = <0x14640000 0x1000>;
951: interrupt-parent = <&combiner>;
952: interrupts = <3 2>;
953: clock-names = "sysmmu", "master";
954: clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
955: power-domains = <&disp_pd>;
956: #iommu-cells = <0>;
957: };
958:
1.1.1.6 jmcneill 959: sysmmu_fimd1_1: sysmmu@14680000 {
1.1 jmcneill 960: compatible = "samsung,exynos-sysmmu";
961: reg = <0x14680000 0x1000>;
962: interrupt-parent = <&combiner>;
963: interrupts = <3 0>;
964: clock-names = "sysmmu", "master";
965: clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
966: power-domains = <&disp_pd>;
967: #iommu-cells = <0>;
968: };
969:
970: bus_wcore: bus_wcore {
971: compatible = "samsung,exynos-bus";
972: clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
973: clock-names = "bus";
974: operating-points-v2 = <&bus_wcore_opp_table>;
975: status = "disabled";
976: };
977:
978: bus_noc: bus_noc {
979: compatible = "samsung,exynos-bus";
980: clocks = <&clock CLK_DOUT_ACLK100_NOC>;
981: clock-names = "bus";
982: operating-points-v2 = <&bus_noc_opp_table>;
983: status = "disabled";
984: };
985:
986: bus_fsys_apb: bus_fsys_apb {
987: compatible = "samsung,exynos-bus";
988: clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
989: clock-names = "bus";
990: operating-points-v2 = <&bus_fsys_apb_opp_table>;
991: status = "disabled";
992: };
993:
994: bus_fsys: bus_fsys {
995: compatible = "samsung,exynos-bus";
996: clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
997: clock-names = "bus";
998: operating-points-v2 = <&bus_fsys_apb_opp_table>;
999: status = "disabled";
1000: };
1001:
1002: bus_fsys2: bus_fsys2 {
1003: compatible = "samsung,exynos-bus";
1004: clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1005: clock-names = "bus";
1006: operating-points-v2 = <&bus_fsys2_opp_table>;
1007: status = "disabled";
1008: };
1009:
1010: bus_mfc: bus_mfc {
1011: compatible = "samsung,exynos-bus";
1012: clocks = <&clock CLK_DOUT_ACLK333>;
1013: clock-names = "bus";
1014: operating-points-v2 = <&bus_mfc_opp_table>;
1015: status = "disabled";
1016: };
1017:
1018: bus_gen: bus_gen {
1019: compatible = "samsung,exynos-bus";
1020: clocks = <&clock CLK_DOUT_ACLK266>;
1021: clock-names = "bus";
1022: operating-points-v2 = <&bus_gen_opp_table>;
1023: status = "disabled";
1024: };
1025:
1026: bus_peri: bus_peri {
1027: compatible = "samsung,exynos-bus";
1028: clocks = <&clock CLK_DOUT_ACLK66>;
1029: clock-names = "bus";
1030: operating-points-v2 = <&bus_peri_opp_table>;
1031: status = "disabled";
1032: };
1033:
1034: bus_g2d: bus_g2d {
1035: compatible = "samsung,exynos-bus";
1036: clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1037: clock-names = "bus";
1038: operating-points-v2 = <&bus_g2d_opp_table>;
1039: status = "disabled";
1040: };
1041:
1042: bus_g2d_acp: bus_g2d_acp {
1043: compatible = "samsung,exynos-bus";
1044: clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1045: clock-names = "bus";
1046: operating-points-v2 = <&bus_g2d_acp_opp_table>;
1047: status = "disabled";
1048: };
1049:
1050: bus_jpeg: bus_jpeg {
1051: compatible = "samsung,exynos-bus";
1052: clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1053: clock-names = "bus";
1054: operating-points-v2 = <&bus_jpeg_opp_table>;
1055: status = "disabled";
1056: };
1057:
1058: bus_jpeg_apb: bus_jpeg_apb {
1059: compatible = "samsung,exynos-bus";
1060: clocks = <&clock CLK_DOUT_ACLK166>;
1061: clock-names = "bus";
1062: operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1063: status = "disabled";
1064: };
1065:
1066: bus_disp1_fimd: bus_disp1_fimd {
1067: compatible = "samsung,exynos-bus";
1068: clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1069: clock-names = "bus";
1070: operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1071: status = "disabled";
1072: };
1073:
1074: bus_disp1: bus_disp1 {
1075: compatible = "samsung,exynos-bus";
1076: clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1077: clock-names = "bus";
1078: operating-points-v2 = <&bus_disp1_opp_table>;
1079: status = "disabled";
1080: };
1081:
1082: bus_gscl_scaler: bus_gscl_scaler {
1083: compatible = "samsung,exynos-bus";
1084: clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1085: clock-names = "bus";
1086: operating-points-v2 = <&bus_gscl_opp_table>;
1087: status = "disabled";
1088: };
1089:
1090: bus_mscl: bus_mscl {
1091: compatible = "samsung,exynos-bus";
1092: clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1093: clock-names = "bus";
1094: operating-points-v2 = <&bus_mscl_opp_table>;
1095: status = "disabled";
1096: };
1097:
1098: bus_wcore_opp_table: opp_table2 {
1099: compatible = "operating-points-v2";
1100:
1101: opp00 {
1102: opp-hz = /bits/ 64 <84000000>;
1103: opp-microvolt = <925000>;
1104: };
1105: opp01 {
1106: opp-hz = /bits/ 64 <111000000>;
1107: opp-microvolt = <950000>;
1108: };
1109: opp02 {
1110: opp-hz = /bits/ 64 <222000000>;
1111: opp-microvolt = <950000>;
1112: };
1113: opp03 {
1114: opp-hz = /bits/ 64 <333000000>;
1115: opp-microvolt = <950000>;
1116: };
1117: opp04 {
1118: opp-hz = /bits/ 64 <400000000>;
1119: opp-microvolt = <987500>;
1120: };
1121: };
1122:
1123: bus_noc_opp_table: opp_table3 {
1124: compatible = "operating-points-v2";
1125:
1126: opp00 {
1127: opp-hz = /bits/ 64 <67000000>;
1128: };
1129: opp01 {
1130: opp-hz = /bits/ 64 <75000000>;
1131: };
1132: opp02 {
1133: opp-hz = /bits/ 64 <86000000>;
1134: };
1135: opp03 {
1136: opp-hz = /bits/ 64 <100000000>;
1137: };
1138: };
1139:
1140: bus_fsys_apb_opp_table: opp_table4 {
1141: compatible = "operating-points-v2";
1142: opp-shared;
1143:
1144: opp00 {
1145: opp-hz = /bits/ 64 <100000000>;
1146: };
1147: opp01 {
1148: opp-hz = /bits/ 64 <200000000>;
1149: };
1150: };
1151:
1152: bus_fsys2_opp_table: opp_table5 {
1153: compatible = "operating-points-v2";
1154:
1155: opp00 {
1156: opp-hz = /bits/ 64 <75000000>;
1157: };
1158: opp01 {
1159: opp-hz = /bits/ 64 <100000000>;
1160: };
1161: opp02 {
1162: opp-hz = /bits/ 64 <150000000>;
1163: };
1164: };
1165:
1166: bus_mfc_opp_table: opp_table6 {
1167: compatible = "operating-points-v2";
1168:
1169: opp00 {
1170: opp-hz = /bits/ 64 <96000000>;
1171: };
1172: opp01 {
1173: opp-hz = /bits/ 64 <111000000>;
1174: };
1175: opp02 {
1176: opp-hz = /bits/ 64 <167000000>;
1177: };
1178: opp03 {
1179: opp-hz = /bits/ 64 <222000000>;
1180: };
1181: opp04 {
1182: opp-hz = /bits/ 64 <333000000>;
1183: };
1184: };
1185:
1186: bus_gen_opp_table: opp_table7 {
1187: compatible = "operating-points-v2";
1188:
1189: opp00 {
1190: opp-hz = /bits/ 64 <89000000>;
1191: };
1192: opp01 {
1193: opp-hz = /bits/ 64 <133000000>;
1194: };
1195: opp02 {
1196: opp-hz = /bits/ 64 <178000000>;
1197: };
1198: opp03 {
1199: opp-hz = /bits/ 64 <267000000>;
1200: };
1201: };
1202:
1203: bus_peri_opp_table: opp_table8 {
1204: compatible = "operating-points-v2";
1205:
1206: opp00 {
1207: opp-hz = /bits/ 64 <67000000>;
1208: };
1209: };
1210:
1211: bus_g2d_opp_table: opp_table9 {
1212: compatible = "operating-points-v2";
1213:
1214: opp00 {
1215: opp-hz = /bits/ 64 <84000000>;
1216: };
1217: opp01 {
1218: opp-hz = /bits/ 64 <167000000>;
1219: };
1220: opp02 {
1221: opp-hz = /bits/ 64 <222000000>;
1222: };
1223: opp03 {
1224: opp-hz = /bits/ 64 <300000000>;
1225: };
1226: opp04 {
1227: opp-hz = /bits/ 64 <333000000>;
1228: };
1229: };
1230:
1231: bus_g2d_acp_opp_table: opp_table10 {
1232: compatible = "operating-points-v2";
1233:
1234: opp00 {
1235: opp-hz = /bits/ 64 <67000000>;
1236: };
1237: opp01 {
1238: opp-hz = /bits/ 64 <133000000>;
1239: };
1240: opp02 {
1241: opp-hz = /bits/ 64 <178000000>;
1242: };
1243: opp03 {
1244: opp-hz = /bits/ 64 <267000000>;
1245: };
1246: };
1247:
1248: bus_jpeg_opp_table: opp_table11 {
1249: compatible = "operating-points-v2";
1250:
1251: opp00 {
1252: opp-hz = /bits/ 64 <75000000>;
1253: };
1254: opp01 {
1255: opp-hz = /bits/ 64 <150000000>;
1256: };
1257: opp02 {
1258: opp-hz = /bits/ 64 <200000000>;
1259: };
1260: opp03 {
1261: opp-hz = /bits/ 64 <300000000>;
1262: };
1263: };
1264:
1265: bus_jpeg_apb_opp_table: opp_table12 {
1266: compatible = "operating-points-v2";
1267:
1268: opp00 {
1269: opp-hz = /bits/ 64 <84000000>;
1270: };
1271: opp01 {
1272: opp-hz = /bits/ 64 <111000000>;
1273: };
1274: opp02 {
1275: opp-hz = /bits/ 64 <134000000>;
1276: };
1277: opp03 {
1278: opp-hz = /bits/ 64 <167000000>;
1279: };
1280: };
1281:
1282: bus_disp1_fimd_opp_table: opp_table13 {
1283: compatible = "operating-points-v2";
1284:
1285: opp00 {
1286: opp-hz = /bits/ 64 <120000000>;
1287: };
1288: opp01 {
1289: opp-hz = /bits/ 64 <200000000>;
1290: };
1291: };
1292:
1293: bus_disp1_opp_table: opp_table14 {
1294: compatible = "operating-points-v2";
1295:
1296: opp00 {
1297: opp-hz = /bits/ 64 <120000000>;
1298: };
1299: opp01 {
1300: opp-hz = /bits/ 64 <200000000>;
1301: };
1302: opp02 {
1303: opp-hz = /bits/ 64 <300000000>;
1304: };
1305: };
1306:
1307: bus_gscl_opp_table: opp_table15 {
1308: compatible = "operating-points-v2";
1309:
1310: opp00 {
1311: opp-hz = /bits/ 64 <150000000>;
1312: };
1313: opp01 {
1314: opp-hz = /bits/ 64 <200000000>;
1315: };
1316: opp02 {
1317: opp-hz = /bits/ 64 <300000000>;
1318: };
1319: };
1320:
1321: bus_mscl_opp_table: opp_table16 {
1322: compatible = "operating-points-v2";
1323:
1324: opp00 {
1325: opp-hz = /bits/ 64 <84000000>;
1326: };
1327: opp01 {
1328: opp-hz = /bits/ 64 <167000000>;
1329: };
1330: opp02 {
1331: opp-hz = /bits/ 64 <222000000>;
1332: };
1333: opp03 {
1334: opp-hz = /bits/ 64 <333000000>;
1335: };
1336: opp04 {
1337: opp-hz = /bits/ 64 <400000000>;
1338: };
1339: };
1340: };
1341:
1342: thermal-zones {
1343: cpu0_thermal: cpu0-thermal {
1344: thermal-sensors = <&tmu_cpu0>;
1345: #include "exynos5420-trip-points.dtsi"
1346: };
1347: cpu1_thermal: cpu1-thermal {
1348: thermal-sensors = <&tmu_cpu1>;
1349: #include "exynos5420-trip-points.dtsi"
1350: };
1351: cpu2_thermal: cpu2-thermal {
1352: thermal-sensors = <&tmu_cpu2>;
1353: #include "exynos5420-trip-points.dtsi"
1354: };
1355: cpu3_thermal: cpu3-thermal {
1356: thermal-sensors = <&tmu_cpu3>;
1357: #include "exynos5420-trip-points.dtsi"
1358: };
1359: gpu_thermal: gpu-thermal {
1360: thermal-sensors = <&tmu_gpu>;
1361: #include "exynos5420-trip-points.dtsi"
1362: };
1363: };
1364: };
1365:
1366: &dp {
1367: clocks = <&clock CLK_DP1>;
1368: clock-names = "dp";
1369: phys = <&dp_phy>;
1370: phy-names = "dp";
1371: power-domains = <&disp_pd>;
1372: };
1373:
1374: &fimd {
1375: compatible = "samsung,exynos5420-fimd";
1376: clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1377: clock-names = "sclk_fimd", "fimd";
1378: power-domains = <&disp_pd>;
1379: iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1380: iommu-names = "m0", "m1";
1381: };
1382:
1.1.1.5 jmcneill 1383: &g2d {
1384: iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1385: clocks = <&clock CLK_G2D>;
1386: clock-names = "fimg2d";
1387: status = "okay";
1388: };
1389:
1.1 jmcneill 1390: &i2c_0 {
1391: clocks = <&clock CLK_I2C0>;
1392: clock-names = "i2c";
1393: pinctrl-names = "default";
1394: pinctrl-0 = <&i2c0_bus>;
1395: };
1396:
1397: &i2c_1 {
1398: clocks = <&clock CLK_I2C1>;
1399: clock-names = "i2c";
1400: pinctrl-names = "default";
1401: pinctrl-0 = <&i2c1_bus>;
1402: };
1403:
1404: &i2c_2 {
1405: clocks = <&clock CLK_I2C2>;
1406: clock-names = "i2c";
1407: pinctrl-names = "default";
1408: pinctrl-0 = <&i2c2_bus>;
1409: };
1410:
1411: &i2c_3 {
1412: clocks = <&clock CLK_I2C3>;
1413: clock-names = "i2c";
1414: pinctrl-names = "default";
1415: pinctrl-0 = <&i2c3_bus>;
1416: };
1417:
1418: &hsi2c_4 {
1419: clocks = <&clock CLK_USI0>;
1420: clock-names = "hsi2c";
1421: pinctrl-names = "default";
1422: pinctrl-0 = <&i2c4_hs_bus>;
1423: };
1424:
1425: &hsi2c_5 {
1426: clocks = <&clock CLK_USI1>;
1427: clock-names = "hsi2c";
1428: pinctrl-names = "default";
1429: pinctrl-0 = <&i2c5_hs_bus>;
1430: };
1431:
1432: &hsi2c_6 {
1433: clocks = <&clock CLK_USI2>;
1434: clock-names = "hsi2c";
1435: pinctrl-names = "default";
1436: pinctrl-0 = <&i2c6_hs_bus>;
1437: };
1438:
1439: &hsi2c_7 {
1440: clocks = <&clock CLK_USI3>;
1441: clock-names = "hsi2c";
1442: pinctrl-names = "default";
1443: pinctrl-0 = <&i2c7_hs_bus>;
1444: };
1445:
1446: &mct {
1447: clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1448: clock-names = "fin_pll", "mct";
1449: };
1450:
1.1.1.5 jmcneill 1451: &prng {
1452: clocks = <&clock CLK_SSS>;
1453: clock-names = "secss";
1454: };
1455:
1.1 jmcneill 1456: &pwm {
1457: clocks = <&clock CLK_PWM>;
1458: clock-names = "timers";
1459: };
1460:
1461: &rtc {
1462: clocks = <&clock CLK_RTC>;
1463: clock-names = "rtc";
1464: interrupt-parent = <&pmu_system_controller>;
1465: status = "disabled";
1466: };
1467:
1468: &serial_0 {
1469: clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1470: clock-names = "uart", "clk_uart_baud0";
1471: dmas = <&pdma0 13>, <&pdma0 14>;
1472: dma-names = "rx", "tx";
1473: };
1474:
1475: &serial_1 {
1476: clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1477: clock-names = "uart", "clk_uart_baud0";
1478: dmas = <&pdma1 15>, <&pdma1 16>;
1479: dma-names = "rx", "tx";
1480: };
1481:
1482: &serial_2 {
1483: clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1484: clock-names = "uart", "clk_uart_baud0";
1485: dmas = <&pdma0 15>, <&pdma0 16>;
1486: dma-names = "rx", "tx";
1487: };
1488:
1489: &serial_3 {
1490: clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1491: clock-names = "uart", "clk_uart_baud0";
1492: dmas = <&pdma1 17>, <&pdma1 18>;
1493: dma-names = "rx", "tx";
1494: };
1495:
1496: &sss {
1497: clocks = <&clock CLK_SSS>;
1498: clock-names = "secss";
1499: };
1500:
1.1.1.5 jmcneill 1501: &trng {
1502: clocks = <&clock CLK_SSS>;
1503: clock-names = "secss";
1504: };
1505:
1.1 jmcneill 1506: &usbdrd3_0 {
1507: clocks = <&clock CLK_USBD300>;
1508: clock-names = "usbdrd30";
1509: };
1510:
1511: &usbdrd_phy0 {
1512: clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1513: clock-names = "phy", "ref";
1514: samsung,pmu-syscon = <&pmu_system_controller>;
1515: };
1516:
1517: &usbdrd3_1 {
1518: clocks = <&clock CLK_USBD301>;
1519: clock-names = "usbdrd30";
1520: };
1521:
1522: &usbdrd_dwc3_1 {
1523: interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1524: };
1525:
1526: &usbdrd_phy1 {
1527: clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1528: clock-names = "phy", "ref";
1529: samsung,pmu-syscon = <&pmu_system_controller>;
1530: };
1531:
1532: &usbhost1 {
1533: clocks = <&clock CLK_USBH20>;
1534: clock-names = "usbhost";
1535: };
1536:
1537: &usbhost2 {
1538: clocks = <&clock CLK_USBH20>;
1539: clock-names = "usbhost";
1540: };
1541:
1542: &usb2_phy {
1543: clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1544: clock-names = "phy", "ref";
1545: samsung,sysreg-phandle = <&sysreg_system_controller>;
1546: samsung,pmureg-phandle = <&pmu_system_controller>;
1547: };
1548:
1549: &watchdog {
1550: clocks = <&clock CLK_WDT>;
1551: clock-names = "watchdog";
1552: samsung,syscon-phandle = <&pmu_system_controller>;
1553: };
1554:
1555: #include "exynos5420-pinctrl.dtsi"
1.1.1.6 jmcneill 1556: #include "exynos-syscon-restart.dtsi"