Annotation of src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/exynos4.dtsi, Revision 1.1.1.2
1.1 jmcneill 1: /*
2: * Samsung's Exynos4 SoC series common device tree source
3: *
4: * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5: * http://www.samsung.com
6: * Copyright (c) 2010-2011 Linaro Ltd.
7: * www.linaro.org
8: *
9: * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
10: * SoCs from Exynos4 series can include this file and provide values for SoCs
11: * specfic bindings.
12: *
13: * Note: This file does not include device nodes for all the controllers in
14: * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
15: * nodes can be added to this file.
16: *
17: * This program is free software; you can redistribute it and/or modify
18: * it under the terms of the GNU General Public License version 2 as
19: * published by the Free Software Foundation.
20: */
21:
22: #include <dt-bindings/clock/exynos4.h>
23: #include <dt-bindings/clock/exynos-audss-clk.h>
24: #include <dt-bindings/interrupt-controller/arm-gic.h>
25: #include <dt-bindings/interrupt-controller/irq.h>
26: #include "exynos-syscon-restart.dtsi"
27:
28: / {
29: interrupt-parent = <&gic>;
30: #address-cells = <1>;
31: #size-cells = <1>;
32:
33: aliases {
34: spi0 = &spi_0;
35: spi1 = &spi_1;
36: spi2 = &spi_2;
37: i2c0 = &i2c_0;
38: i2c1 = &i2c_1;
39: i2c2 = &i2c_2;
40: i2c3 = &i2c_3;
41: i2c4 = &i2c_4;
42: i2c5 = &i2c_5;
43: i2c6 = &i2c_6;
44: i2c7 = &i2c_7;
45: i2c8 = &i2c_8;
46: csis0 = &csis_0;
47: csis1 = &csis_1;
48: fimc0 = &fimc_0;
49: fimc1 = &fimc_1;
50: fimc2 = &fimc_2;
51: fimc3 = &fimc_3;
52: serial0 = &serial_0;
53: serial1 = &serial_1;
54: serial2 = &serial_2;
55: serial3 = &serial_3;
56: };
57:
58: clock_audss: clock-controller@03810000 {
59: compatible = "samsung,exynos4210-audss-clock";
60: reg = <0x03810000 0x0C>;
61: #clock-cells = <1>;
62: };
63:
64: i2s0: i2s@03830000 {
65: compatible = "samsung,s5pv210-i2s";
66: reg = <0x03830000 0x100>;
67: clocks = <&clock_audss EXYNOS_I2S_BUS>,
68: <&clock_audss EXYNOS_DOUT_AUD_BUS>,
69: <&clock_audss EXYNOS_SCLK_I2S>;
70: clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
71: #clock-cells = <1>;
72: clock-output-names = "i2s_cdclk0";
73: dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
74: dma-names = "tx", "rx", "tx-sec";
75: samsung,idma-addr = <0x03000000>;
76: #sound-dai-cells = <1>;
77: status = "disabled";
78: };
79:
80: chipid@10000000 {
81: compatible = "samsung,exynos4210-chipid";
82: reg = <0x10000000 0x100>;
83: };
84:
85: scu: snoop-control-unit@10500000 {
86: compatible = "arm,cortex-a9-scu";
87: reg = <0x10500000 0x2000>;
88: };
89:
90: memory-controller@12570000 {
91: compatible = "samsung,exynos4210-srom";
92: reg = <0x12570000 0x14>;
93: };
94:
95: mipi_phy: video-phy {
96: compatible = "samsung,s5pv210-mipi-video-phy";
97: #phy-cells = <1>;
98: syscon = <&pmu_system_controller>;
99: };
100:
101: pd_mfc: mfc-power-domain@10023C40 {
102: compatible = "samsung,exynos4210-pd";
103: reg = <0x10023C40 0x20>;
104: #power-domain-cells = <0>;
105: label = "MFC";
106: };
107:
108: pd_g3d: g3d-power-domain@10023C60 {
109: compatible = "samsung,exynos4210-pd";
110: reg = <0x10023C60 0x20>;
111: #power-domain-cells = <0>;
112: label = "G3D";
113: };
114:
115: pd_lcd0: lcd0-power-domain@10023C80 {
116: compatible = "samsung,exynos4210-pd";
117: reg = <0x10023C80 0x20>;
118: #power-domain-cells = <0>;
119: label = "LCD0";
120: };
121:
122: pd_tv: tv-power-domain@10023C20 {
123: compatible = "samsung,exynos4210-pd";
124: reg = <0x10023C20 0x20>;
125: #power-domain-cells = <0>;
126: power-domains = <&pd_lcd0>;
127: label = "TV";
128: };
129:
130: pd_cam: cam-power-domain@10023C00 {
131: compatible = "samsung,exynos4210-pd";
132: reg = <0x10023C00 0x20>;
133: #power-domain-cells = <0>;
134: label = "CAM";
135: };
136:
137: pd_gps: gps-power-domain@10023CE0 {
138: compatible = "samsung,exynos4210-pd";
139: reg = <0x10023CE0 0x20>;
140: #power-domain-cells = <0>;
141: label = "GPS";
142: };
143:
144: pd_gps_alive: gps-alive-power-domain@10023D00 {
145: compatible = "samsung,exynos4210-pd";
146: reg = <0x10023D00 0x20>;
147: #power-domain-cells = <0>;
148: label = "GPS alive";
149: };
150:
151: gic: interrupt-controller@10490000 {
152: compatible = "arm,cortex-a9-gic";
153: #interrupt-cells = <3>;
154: interrupt-controller;
155: reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
156: };
157:
158: combiner: interrupt-controller@10440000 {
159: compatible = "samsung,exynos4210-combiner";
160: #interrupt-cells = <2>;
161: interrupt-controller;
162: reg = <0x10440000 0x1000>;
163: };
164:
165: pmu {
166: compatible = "arm,cortex-a9-pmu";
167: interrupt-parent = <&combiner>;
168: interrupts = <2 2>, <3 2>;
169: };
170:
171: sys_reg: syscon@10010000 {
172: compatible = "samsung,exynos4-sysreg", "syscon";
173: reg = <0x10010000 0x400>;
174: };
175:
176: pmu_system_controller: system-controller@10020000 {
177: compatible = "samsung,exynos4210-pmu", "syscon";
178: reg = <0x10020000 0x4000>;
179: interrupt-controller;
180: #interrupt-cells = <3>;
181: interrupt-parent = <&gic>;
182: };
183:
184: dsi_0: dsi@11C80000 {
185: compatible = "samsung,exynos4210-mipi-dsi";
186: reg = <0x11C80000 0x10000>;
187: interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
188: power-domains = <&pd_lcd0>;
189: phys = <&mipi_phy 1>;
190: phy-names = "dsim";
191: clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
192: clock-names = "bus_clk", "sclk_mipi";
193: status = "disabled";
194: #address-cells = <1>;
195: #size-cells = <0>;
196: };
197:
198: camera {
199: compatible = "samsung,fimc", "simple-bus";
200: status = "disabled";
201: #address-cells = <1>;
202: #size-cells = <1>;
203: #clock-cells = <1>;
204: clock-output-names = "cam_a_clkout", "cam_b_clkout";
205: ranges;
206:
207: fimc_0: fimc@11800000 {
208: compatible = "samsung,exynos4210-fimc";
209: reg = <0x11800000 0x1000>;
210: interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
211: clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
212: clock-names = "fimc", "sclk_fimc";
213: power-domains = <&pd_cam>;
214: samsung,sysreg = <&sys_reg>;
215: iommus = <&sysmmu_fimc0>;
216: status = "disabled";
217: };
218:
219: fimc_1: fimc@11810000 {
220: compatible = "samsung,exynos4210-fimc";
221: reg = <0x11810000 0x1000>;
222: interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
223: clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
224: clock-names = "fimc", "sclk_fimc";
225: power-domains = <&pd_cam>;
226: samsung,sysreg = <&sys_reg>;
227: iommus = <&sysmmu_fimc1>;
228: status = "disabled";
229: };
230:
231: fimc_2: fimc@11820000 {
232: compatible = "samsung,exynos4210-fimc";
233: reg = <0x11820000 0x1000>;
234: interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
235: clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
236: clock-names = "fimc", "sclk_fimc";
237: power-domains = <&pd_cam>;
238: samsung,sysreg = <&sys_reg>;
239: iommus = <&sysmmu_fimc2>;
240: status = "disabled";
241: };
242:
243: fimc_3: fimc@11830000 {
244: compatible = "samsung,exynos4210-fimc";
245: reg = <0x11830000 0x1000>;
246: interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
247: clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
248: clock-names = "fimc", "sclk_fimc";
249: power-domains = <&pd_cam>;
250: samsung,sysreg = <&sys_reg>;
251: iommus = <&sysmmu_fimc3>;
252: status = "disabled";
253: };
254:
255: csis_0: csis@11880000 {
256: compatible = "samsung,exynos4210-csis";
257: reg = <0x11880000 0x4000>;
258: interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
259: clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
260: clock-names = "csis", "sclk_csis";
261: bus-width = <4>;
262: power-domains = <&pd_cam>;
263: phys = <&mipi_phy 0>;
264: phy-names = "csis";
265: status = "disabled";
266: #address-cells = <1>;
267: #size-cells = <0>;
268: };
269:
270: csis_1: csis@11890000 {
271: compatible = "samsung,exynos4210-csis";
272: reg = <0x11890000 0x4000>;
273: interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
274: clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
275: clock-names = "csis", "sclk_csis";
276: bus-width = <2>;
277: power-domains = <&pd_cam>;
278: phys = <&mipi_phy 2>;
279: phy-names = "csis";
280: status = "disabled";
281: #address-cells = <1>;
282: #size-cells = <0>;
283: };
284: };
285:
286: rtc: rtc@10070000 {
287: compatible = "samsung,s3c6410-rtc";
288: reg = <0x10070000 0x100>;
289: interrupt-parent = <&pmu_system_controller>;
290: interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
291: <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
292: clocks = <&clock CLK_RTC>;
293: clock-names = "rtc";
294: status = "disabled";
295: };
296:
297: keypad: keypad@100A0000 {
298: compatible = "samsung,s5pv210-keypad";
299: reg = <0x100A0000 0x100>;
300: interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
301: clocks = <&clock CLK_KEYIF>;
302: clock-names = "keypad";
303: status = "disabled";
304: };
305:
306: sdhci_0: sdhci@12510000 {
307: compatible = "samsung,exynos4210-sdhci";
308: reg = <0x12510000 0x100>;
309: interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
310: clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
311: clock-names = "hsmmc", "mmc_busclk.2";
312: status = "disabled";
313: };
314:
315: sdhci_1: sdhci@12520000 {
316: compatible = "samsung,exynos4210-sdhci";
317: reg = <0x12520000 0x100>;
318: interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
319: clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
320: clock-names = "hsmmc", "mmc_busclk.2";
321: status = "disabled";
322: };
323:
324: sdhci_2: sdhci@12530000 {
325: compatible = "samsung,exynos4210-sdhci";
326: reg = <0x12530000 0x100>;
327: interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
328: clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
329: clock-names = "hsmmc", "mmc_busclk.2";
330: status = "disabled";
331: };
332:
333: sdhci_3: sdhci@12540000 {
334: compatible = "samsung,exynos4210-sdhci";
335: reg = <0x12540000 0x100>;
336: interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
337: clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
338: clock-names = "hsmmc", "mmc_busclk.2";
339: status = "disabled";
340: };
341:
342: exynos_usbphy: exynos-usbphy@125B0000 {
343: compatible = "samsung,exynos4210-usb2-phy";
344: reg = <0x125B0000 0x100>;
345: samsung,pmureg-phandle = <&pmu_system_controller>;
346: clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
347: clock-names = "phy", "ref";
348: #phy-cells = <1>;
349: status = "disabled";
350: };
351:
352: hsotg: hsotg@12480000 {
353: compatible = "samsung,s3c6400-hsotg";
354: reg = <0x12480000 0x20000>;
355: interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
356: clocks = <&clock CLK_USB_DEVICE>;
357: clock-names = "otg";
358: phys = <&exynos_usbphy 0>;
359: phy-names = "usb2-phy";
360: status = "disabled";
361: };
362:
363: ehci: ehci@12580000 {
364: compatible = "samsung,exynos4210-ehci";
365: reg = <0x12580000 0x100>;
366: interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
367: clocks = <&clock CLK_USB_HOST>;
368: clock-names = "usbhost";
369: status = "disabled";
370: #address-cells = <1>;
371: #size-cells = <0>;
372: port@0 {
373: reg = <0>;
374: phys = <&exynos_usbphy 1>;
375: status = "disabled";
376: };
377: port@1 {
378: reg = <1>;
379: phys = <&exynos_usbphy 2>;
380: status = "disabled";
381: };
382: port@2 {
383: reg = <2>;
384: phys = <&exynos_usbphy 3>;
385: status = "disabled";
386: };
387: };
388:
389: ohci: ohci@12590000 {
390: compatible = "samsung,exynos4210-ohci";
391: reg = <0x12590000 0x100>;
392: interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
393: clocks = <&clock CLK_USB_HOST>;
394: clock-names = "usbhost";
395: status = "disabled";
396: #address-cells = <1>;
397: #size-cells = <0>;
398: port@0 {
399: reg = <0>;
400: phys = <&exynos_usbphy 1>;
401: status = "disabled";
402: };
403: };
404:
405: i2s1: i2s@13960000 {
406: compatible = "samsung,s3c6410-i2s";
407: reg = <0x13960000 0x100>;
408: clocks = <&clock CLK_I2S1>;
409: clock-names = "iis";
410: #clock-cells = <1>;
411: clock-output-names = "i2s_cdclk1";
412: dmas = <&pdma1 12>, <&pdma1 11>;
413: dma-names = "tx", "rx";
414: #sound-dai-cells = <1>;
415: status = "disabled";
416: };
417:
418: i2s2: i2s@13970000 {
419: compatible = "samsung,s3c6410-i2s";
420: reg = <0x13970000 0x100>;
421: clocks = <&clock CLK_I2S2>;
422: clock-names = "iis";
423: #clock-cells = <1>;
424: clock-output-names = "i2s_cdclk2";
425: dmas = <&pdma0 14>, <&pdma0 13>;
426: dma-names = "tx", "rx";
427: #sound-dai-cells = <1>;
428: status = "disabled";
429: };
430:
431: mfc: codec@13400000 {
432: compatible = "samsung,mfc-v5";
433: reg = <0x13400000 0x10000>;
434: interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
435: power-domains = <&pd_mfc>;
436: clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
437: clock-names = "mfc", "sclk_mfc";
438: iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
439: iommu-names = "left", "right";
440: };
441:
442: serial_0: serial@13800000 {
443: compatible = "samsung,exynos4210-uart";
444: reg = <0x13800000 0x100>;
445: interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
446: clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
447: clock-names = "uart", "clk_uart_baud0";
448: dmas = <&pdma0 15>, <&pdma0 16>;
449: dma-names = "rx", "tx";
450: status = "disabled";
451: };
452:
453: serial_1: serial@13810000 {
454: compatible = "samsung,exynos4210-uart";
455: reg = <0x13810000 0x100>;
456: interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
457: clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
458: clock-names = "uart", "clk_uart_baud0";
459: dmas = <&pdma1 15>, <&pdma1 16>;
460: dma-names = "rx", "tx";
461: status = "disabled";
462: };
463:
464: serial_2: serial@13820000 {
465: compatible = "samsung,exynos4210-uart";
466: reg = <0x13820000 0x100>;
467: interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
468: clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
469: clock-names = "uart", "clk_uart_baud0";
470: dmas = <&pdma0 17>, <&pdma0 18>;
471: dma-names = "rx", "tx";
472: status = "disabled";
473: };
474:
475: serial_3: serial@13830000 {
476: compatible = "samsung,exynos4210-uart";
477: reg = <0x13830000 0x100>;
478: interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
479: clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
480: clock-names = "uart", "clk_uart_baud0";
481: dmas = <&pdma1 17>, <&pdma1 18>;
482: dma-names = "rx", "tx";
483: status = "disabled";
484: };
485:
486: i2c_0: i2c@13860000 {
487: #address-cells = <1>;
488: #size-cells = <0>;
489: compatible = "samsung,s3c2440-i2c";
490: reg = <0x13860000 0x100>;
491: interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
492: clocks = <&clock CLK_I2C0>;
493: clock-names = "i2c";
494: pinctrl-names = "default";
495: pinctrl-0 = <&i2c0_bus>;
496: status = "disabled";
497: };
498:
499: i2c_1: i2c@13870000 {
500: #address-cells = <1>;
501: #size-cells = <0>;
502: compatible = "samsung,s3c2440-i2c";
503: reg = <0x13870000 0x100>;
504: interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
505: clocks = <&clock CLK_I2C1>;
506: clock-names = "i2c";
507: pinctrl-names = "default";
508: pinctrl-0 = <&i2c1_bus>;
509: status = "disabled";
510: };
511:
512: i2c_2: i2c@13880000 {
513: #address-cells = <1>;
514: #size-cells = <0>;
515: compatible = "samsung,s3c2440-i2c";
516: reg = <0x13880000 0x100>;
517: interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
518: clocks = <&clock CLK_I2C2>;
519: clock-names = "i2c";
520: pinctrl-names = "default";
521: pinctrl-0 = <&i2c2_bus>;
522: status = "disabled";
523: };
524:
525: i2c_3: i2c@13890000 {
526: #address-cells = <1>;
527: #size-cells = <0>;
528: compatible = "samsung,s3c2440-i2c";
529: reg = <0x13890000 0x100>;
530: interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
531: clocks = <&clock CLK_I2C3>;
532: clock-names = "i2c";
533: pinctrl-names = "default";
534: pinctrl-0 = <&i2c3_bus>;
535: status = "disabled";
536: };
537:
538: i2c_4: i2c@138A0000 {
539: #address-cells = <1>;
540: #size-cells = <0>;
541: compatible = "samsung,s3c2440-i2c";
542: reg = <0x138A0000 0x100>;
543: interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
544: clocks = <&clock CLK_I2C4>;
545: clock-names = "i2c";
546: pinctrl-names = "default";
547: pinctrl-0 = <&i2c4_bus>;
548: status = "disabled";
549: };
550:
551: i2c_5: i2c@138B0000 {
552: #address-cells = <1>;
553: #size-cells = <0>;
554: compatible = "samsung,s3c2440-i2c";
555: reg = <0x138B0000 0x100>;
556: interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
557: clocks = <&clock CLK_I2C5>;
558: clock-names = "i2c";
559: pinctrl-names = "default";
560: pinctrl-0 = <&i2c5_bus>;
561: status = "disabled";
562: };
563:
564: i2c_6: i2c@138C0000 {
565: #address-cells = <1>;
566: #size-cells = <0>;
567: compatible = "samsung,s3c2440-i2c";
568: reg = <0x138C0000 0x100>;
569: interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
570: clocks = <&clock CLK_I2C6>;
571: clock-names = "i2c";
572: pinctrl-names = "default";
573: pinctrl-0 = <&i2c6_bus>;
574: status = "disabled";
575: };
576:
577: i2c_7: i2c@138D0000 {
578: #address-cells = <1>;
579: #size-cells = <0>;
580: compatible = "samsung,s3c2440-i2c";
581: reg = <0x138D0000 0x100>;
582: interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
583: clocks = <&clock CLK_I2C7>;
584: clock-names = "i2c";
585: pinctrl-names = "default";
586: pinctrl-0 = <&i2c7_bus>;
587: status = "disabled";
588: };
589:
590: i2c_8: i2c@138E0000 {
591: #address-cells = <1>;
592: #size-cells = <0>;
593: compatible = "samsung,s3c2440-hdmiphy-i2c";
594: reg = <0x138E0000 0x100>;
595: interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
596: clocks = <&clock CLK_I2C_HDMI>;
597: clock-names = "i2c";
598: status = "disabled";
599:
600: hdmi_i2c_phy: hdmiphy@38 {
601: compatible = "exynos4210-hdmiphy";
602: reg = <0x38>;
603: };
604: };
605:
606: spi_0: spi@13920000 {
607: compatible = "samsung,exynos4210-spi";
608: reg = <0x13920000 0x100>;
609: interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
610: dmas = <&pdma0 7>, <&pdma0 6>;
611: dma-names = "tx", "rx";
612: #address-cells = <1>;
613: #size-cells = <0>;
614: clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
615: clock-names = "spi", "spi_busclk0";
616: pinctrl-names = "default";
617: pinctrl-0 = <&spi0_bus>;
618: status = "disabled";
619: };
620:
621: spi_1: spi@13930000 {
622: compatible = "samsung,exynos4210-spi";
623: reg = <0x13930000 0x100>;
624: interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
625: dmas = <&pdma1 7>, <&pdma1 6>;
626: dma-names = "tx", "rx";
627: #address-cells = <1>;
628: #size-cells = <0>;
629: clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
630: clock-names = "spi", "spi_busclk0";
631: pinctrl-names = "default";
632: pinctrl-0 = <&spi1_bus>;
633: status = "disabled";
634: };
635:
636: spi_2: spi@13940000 {
637: compatible = "samsung,exynos4210-spi";
638: reg = <0x13940000 0x100>;
639: interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
640: dmas = <&pdma0 9>, <&pdma0 8>;
641: dma-names = "tx", "rx";
642: #address-cells = <1>;
643: #size-cells = <0>;
644: clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
645: clock-names = "spi", "spi_busclk0";
646: pinctrl-names = "default";
647: pinctrl-0 = <&spi2_bus>;
648: status = "disabled";
649: };
650:
651: pwm: pwm@139D0000 {
652: compatible = "samsung,exynos4210-pwm";
653: reg = <0x139D0000 0x1000>;
654: interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
655: <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
656: <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
657: <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
658: <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
659: clocks = <&clock CLK_PWM>;
660: clock-names = "timers";
661: #pwm-cells = <3>;
662: status = "disabled";
663: };
664:
665: amba {
666: #address-cells = <1>;
667: #size-cells = <1>;
668: compatible = "simple-bus";
669: interrupt-parent = <&gic>;
670: ranges;
671:
672: pdma0: pdma@12680000 {
673: compatible = "arm,pl330", "arm,primecell";
674: reg = <0x12680000 0x1000>;
675: interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
676: clocks = <&clock CLK_PDMA0>;
677: clock-names = "apb_pclk";
678: #dma-cells = <1>;
679: #dma-channels = <8>;
680: #dma-requests = <32>;
681: };
682:
683: pdma1: pdma@12690000 {
684: compatible = "arm,pl330", "arm,primecell";
685: reg = <0x12690000 0x1000>;
686: interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
687: clocks = <&clock CLK_PDMA1>;
688: clock-names = "apb_pclk";
689: #dma-cells = <1>;
690: #dma-channels = <8>;
691: #dma-requests = <32>;
692: };
693:
694: mdma1: mdma@12850000 {
695: compatible = "arm,pl330", "arm,primecell";
696: reg = <0x12850000 0x1000>;
697: interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
698: clocks = <&clock CLK_MDMA>;
699: clock-names = "apb_pclk";
700: #dma-cells = <1>;
701: #dma-channels = <8>;
702: #dma-requests = <1>;
703: };
704: };
705:
706: fimd: fimd@11c00000 {
707: compatible = "samsung,exynos4210-fimd";
708: interrupt-parent = <&combiner>;
709: reg = <0x11c00000 0x20000>;
710: interrupt-names = "fifo", "vsync", "lcd_sys";
711: interrupts = <11 0>, <11 1>, <11 2>;
712: clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
713: clock-names = "sclk_fimd", "fimd";
714: power-domains = <&pd_lcd0>;
715: iommus = <&sysmmu_fimd0>;
716: samsung,sysreg = <&sys_reg>;
717: status = "disabled";
718: };
719:
720: tmu: tmu@100C0000 {
721: #include "exynos4412-tmu-sensor-conf.dtsi"
722: };
723:
724: jpeg_codec: jpeg-codec@11840000 {
725: compatible = "samsung,exynos4210-jpeg";
726: reg = <0x11840000 0x1000>;
727: interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
728: clocks = <&clock CLK_JPEG>;
729: clock-names = "jpeg";
730: power-domains = <&pd_cam>;
731: iommus = <&sysmmu_jpeg>;
732: };
733:
734: rotator: rotator@12810000 {
735: compatible = "samsung,exynos4210-rotator";
736: reg = <0x12810000 0x64>;
737: interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
738: clocks = <&clock CLK_ROTATOR>;
739: clock-names = "rotator";
740: iommus = <&sysmmu_rotator>;
741: };
742:
743: hdmi: hdmi@12D00000 {
744: compatible = "samsung,exynos4210-hdmi";
745: reg = <0x12D00000 0x70000>;
746: interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
747: clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
748: "mout_hdmi";
749: clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
750: <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
751: <&clock CLK_MOUT_HDMI>;
752: phy = <&hdmi_i2c_phy>;
753: power-domains = <&pd_tv>;
754: samsung,syscon-phandle = <&pmu_system_controller>;
755: status = "disabled";
756: };
757:
758: hdmicec: cec@100B0000 {
759: compatible = "samsung,s5p-cec";
760: reg = <0x100B0000 0x200>;
761: interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
762: clocks = <&clock CLK_HDMI_CEC>;
763: clock-names = "hdmicec";
764: samsung,syscon-phandle = <&pmu_system_controller>;
1.1.1.2 ! jmcneill 765: hdmi-phandle = <&hdmi>;
1.1 jmcneill 766: pinctrl-names = "default";
767: pinctrl-0 = <&hdmi_cec>;
768: status = "disabled";
769: };
770:
771: mixer: mixer@12C10000 {
772: compatible = "samsung,exynos4210-mixer";
773: interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
774: reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
775: power-domains = <&pd_tv>;
776: iommus = <&sysmmu_tv>;
777: status = "disabled";
778: };
779:
780: ppmu_dmc0: ppmu_dmc0@106a0000 {
781: compatible = "samsung,exynos-ppmu";
782: reg = <0x106a0000 0x2000>;
783: clocks = <&clock CLK_PPMUDMC0>;
784: clock-names = "ppmu";
785: status = "disabled";
786: };
787:
788: ppmu_dmc1: ppmu_dmc1@106b0000 {
789: compatible = "samsung,exynos-ppmu";
790: reg = <0x106b0000 0x2000>;
791: clocks = <&clock CLK_PPMUDMC1>;
792: clock-names = "ppmu";
793: status = "disabled";
794: };
795:
796: ppmu_cpu: ppmu_cpu@106c0000 {
797: compatible = "samsung,exynos-ppmu";
798: reg = <0x106c0000 0x2000>;
799: clocks = <&clock CLK_PPMUCPU>;
800: clock-names = "ppmu";
801: status = "disabled";
802: };
803:
804: ppmu_acp: ppmu_acp@10ae0000 {
805: compatible = "samsung,exynos-ppmu";
806: reg = <0x106e0000 0x2000>;
807: status = "disabled";
808: };
809:
810: ppmu_rightbus: ppmu_rightbus@112a0000 {
811: compatible = "samsung,exynos-ppmu";
812: reg = <0x112a0000 0x2000>;
813: clocks = <&clock CLK_PPMURIGHT>;
814: clock-names = "ppmu";
815: status = "disabled";
816: };
817:
818: ppmu_leftbus: ppmu_leftbus0@116a0000 {
819: compatible = "samsung,exynos-ppmu";
820: reg = <0x116a0000 0x2000>;
821: clocks = <&clock CLK_PPMULEFT>;
822: clock-names = "ppmu";
823: status = "disabled";
824: };
825:
826: ppmu_camif: ppmu_camif@11ac0000 {
827: compatible = "samsung,exynos-ppmu";
828: reg = <0x11ac0000 0x2000>;
829: clocks = <&clock CLK_PPMUCAMIF>;
830: clock-names = "ppmu";
831: status = "disabled";
832: };
833:
834: ppmu_lcd0: ppmu_lcd0@11e40000 {
835: compatible = "samsung,exynos-ppmu";
836: reg = <0x11e40000 0x2000>;
837: clocks = <&clock CLK_PPMULCD0>;
838: clock-names = "ppmu";
839: status = "disabled";
840: };
841:
842: ppmu_fsys: ppmu_g3d@12630000 {
843: compatible = "samsung,exynos-ppmu";
844: reg = <0x12630000 0x2000>;
845: status = "disabled";
846: };
847:
848: ppmu_image: ppmu_image@12aa0000 {
849: compatible = "samsung,exynos-ppmu";
850: reg = <0x12aa0000 0x2000>;
851: clocks = <&clock CLK_PPMUIMAGE>;
852: clock-names = "ppmu";
853: status = "disabled";
854: };
855:
856: ppmu_tv: ppmu_tv@12e40000 {
857: compatible = "samsung,exynos-ppmu";
858: reg = <0x12e40000 0x2000>;
859: clocks = <&clock CLK_PPMUTV>;
860: clock-names = "ppmu";
861: status = "disabled";
862: };
863:
864: ppmu_g3d: ppmu_g3d@13220000 {
865: compatible = "samsung,exynos-ppmu";
866: reg = <0x13220000 0x2000>;
867: clocks = <&clock CLK_PPMUG3D>;
868: clock-names = "ppmu";
869: status = "disabled";
870: };
871:
872: ppmu_mfc_left: ppmu_mfc_left@13660000 {
873: compatible = "samsung,exynos-ppmu";
874: reg = <0x13660000 0x2000>;
875: clocks = <&clock CLK_PPMUMFC_L>;
876: clock-names = "ppmu";
877: status = "disabled";
878: };
879:
880: ppmu_mfc_right: ppmu_mfc_right@13670000 {
881: compatible = "samsung,exynos-ppmu";
882: reg = <0x13670000 0x2000>;
883: clocks = <&clock CLK_PPMUMFC_R>;
884: clock-names = "ppmu";
885: status = "disabled";
886: };
887:
888: sysmmu_mfc_l: sysmmu@13620000 {
889: compatible = "samsung,exynos-sysmmu";
890: reg = <0x13620000 0x1000>;
891: interrupt-parent = <&combiner>;
892: interrupts = <5 5>;
893: clock-names = "sysmmu", "master";
894: clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
895: power-domains = <&pd_mfc>;
896: #iommu-cells = <0>;
897: };
898:
899: sysmmu_mfc_r: sysmmu@13630000 {
900: compatible = "samsung,exynos-sysmmu";
901: reg = <0x13630000 0x1000>;
902: interrupt-parent = <&combiner>;
903: interrupts = <5 6>;
904: clock-names = "sysmmu", "master";
905: clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
906: power-domains = <&pd_mfc>;
907: #iommu-cells = <0>;
908: };
909:
910: sysmmu_tv: sysmmu@12E20000 {
911: compatible = "samsung,exynos-sysmmu";
912: reg = <0x12E20000 0x1000>;
913: interrupt-parent = <&combiner>;
914: interrupts = <5 4>;
915: clock-names = "sysmmu", "master";
916: clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
917: power-domains = <&pd_tv>;
918: #iommu-cells = <0>;
919: };
920:
921: sysmmu_fimc0: sysmmu@11A20000 {
922: compatible = "samsung,exynos-sysmmu";
923: reg = <0x11A20000 0x1000>;
924: interrupt-parent = <&combiner>;
925: interrupts = <4 2>;
926: clock-names = "sysmmu", "master";
927: clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
928: power-domains = <&pd_cam>;
929: #iommu-cells = <0>;
930: };
931:
932: sysmmu_fimc1: sysmmu@11A30000 {
933: compatible = "samsung,exynos-sysmmu";
934: reg = <0x11A30000 0x1000>;
935: interrupt-parent = <&combiner>;
936: interrupts = <4 3>;
937: clock-names = "sysmmu", "master";
938: clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
939: power-domains = <&pd_cam>;
940: #iommu-cells = <0>;
941: };
942:
943: sysmmu_fimc2: sysmmu@11A40000 {
944: compatible = "samsung,exynos-sysmmu";
945: reg = <0x11A40000 0x1000>;
946: interrupt-parent = <&combiner>;
947: interrupts = <4 4>;
948: clock-names = "sysmmu", "master";
949: clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
950: power-domains = <&pd_cam>;
951: #iommu-cells = <0>;
952: };
953:
954: sysmmu_fimc3: sysmmu@11A50000 {
955: compatible = "samsung,exynos-sysmmu";
956: reg = <0x11A50000 0x1000>;
957: interrupt-parent = <&combiner>;
958: interrupts = <4 5>;
959: clock-names = "sysmmu", "master";
960: clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
961: power-domains = <&pd_cam>;
962: #iommu-cells = <0>;
963: };
964:
965: sysmmu_jpeg: sysmmu@11A60000 {
966: compatible = "samsung,exynos-sysmmu";
967: reg = <0x11A60000 0x1000>;
968: interrupt-parent = <&combiner>;
969: interrupts = <4 6>;
970: clock-names = "sysmmu", "master";
971: clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
972: power-domains = <&pd_cam>;
973: #iommu-cells = <0>;
974: };
975:
976: sysmmu_rotator: sysmmu@12A30000 {
977: compatible = "samsung,exynos-sysmmu";
978: reg = <0x12A30000 0x1000>;
979: interrupt-parent = <&combiner>;
980: interrupts = <5 0>;
981: clock-names = "sysmmu", "master";
982: clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
983: #iommu-cells = <0>;
984: };
985:
986: sysmmu_fimd0: sysmmu@11E20000 {
987: compatible = "samsung,exynos-sysmmu";
988: reg = <0x11E20000 0x1000>;
989: interrupt-parent = <&combiner>;
990: interrupts = <5 2>;
991: clock-names = "sysmmu", "master";
992: clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
993: power-domains = <&pd_lcd0>;
994: #iommu-cells = <0>;
995: };
996:
997: sss: sss@10830000 {
998: compatible = "samsung,exynos4210-secss";
999: reg = <0x10830000 0x300>;
1000: interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1001: clocks = <&clock CLK_SSS>;
1002: clock-names = "secss";
1003: };
1004:
1005: prng: rng@10830400 {
1006: compatible = "samsung,exynos4-rng";
1007: reg = <0x10830400 0x200>;
1008: clocks = <&clock CLK_SSS>;
1009: clock-names = "secss";
1010: };
1011: };
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