version 1.1.1.1.4.1, 2017/06/15 20:14:23 |
version 1.1.1.1.4.2, 2017/07/18 16:08:39 |
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/* |
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* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC |
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* |
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
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* |
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* based on GPL'ed 2.6 kernel sources |
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* (c) Marvell International Ltd. |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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#include <dt-bindings/clock/berlin2.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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model = "Marvell Armada 1500 (BG2) SoC"; |
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compatible = "marvell,berlin2", "marvell,berlin"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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aliases { |
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serial0 = &uart0; |
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serial1 = &uart1; |
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serial2 = &uart2; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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enable-method = "marvell,berlin-smp"; |
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cpu@0 { |
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compatible = "marvell,pj4b"; |
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device_type = "cpu"; |
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next-level-cache = <&l2>; |
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reg = <0>; |
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clocks = <&chip_clk CLKID_CPU>; |
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clock-latency = <100000>; |
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operating-points = < |
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/* kHz uV */ |
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1200000 1200000 |
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1000000 1200000 |
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800000 1200000 |
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600000 1200000 |
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>; |
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}; |
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cpu@1 { |
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compatible = "marvell,pj4b"; |
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device_type = "cpu"; |
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next-level-cache = <&l2>; |
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reg = <1>; |
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}; |
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}; |
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refclk: oscillator { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <25000000>; |
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}; |
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soc@f7000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&gic>; |
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ranges = <0 0xf7000000 0x1000000>; |
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sdhci0: sdhci@ab0000 { |
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compatible = "mrvl,pxav3-mmc"; |
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reg = <0xab0000 0x200>; |
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clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; |
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clock-names = "io", "core"; |
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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sdhci1: sdhci@ab0800 { |
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compatible = "mrvl,pxav3-mmc"; |
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reg = <0xab0800 0x200>; |
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clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; |
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clock-names = "io", "core"; |
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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sdhci2: sdhci@ab1000 { |
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compatible = "mrvl,pxav3-mmc"; |
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reg = <0xab1000 0x200>; |
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; |
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clock-names = "io", "core"; |
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pinctrl-0 = <&emmc_pmux>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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l2: l2-cache-controller@ac0000 { |
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compatible = "marvell,tauros3-cache", "arm,pl310-cache"; |
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reg = <0xac0000 0x1000>; |
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cache-unified; |
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cache-level = <2>; |
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}; |
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scu: snoop-control-unit@ad0000 { |
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compatible = "arm,cortex-a9-scu"; |
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reg = <0xad0000 0x58>; |
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}; |
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gic: interrupt-controller@ad1000 { |
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compatible = "arm,cortex-a9-gic"; |
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reg = <0xad1000 0x1000>, <0xad0100 0x0100>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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}; |
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local-timer@ad0600 { |
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compatible = "arm,cortex-a9-twd-timer"; |
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reg = <0xad0600 0x20>; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
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clocks = <&chip_clk CLKID_TWD>; |
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}; |
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eth1: ethernet@b90000 { |
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compatible = "marvell,pxa168-eth"; |
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reg = <0xb90000 0x10000>; |
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clocks = <&chip_clk CLKID_GETH1>; |
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
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/* set by bootloader */ |
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local-mac-address = [00 00 00 00 00 00]; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy-connection-type = "mii"; |
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phy-handle = <ðphy1>; |
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status = "disabled"; |
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ethphy1: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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cpu-ctrl@dd0000 { |
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compatible = "marvell,berlin-cpu-ctrl"; |
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reg = <0xdd0000 0x10000>; |
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}; |
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eth0: ethernet@e50000 { |
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compatible = "marvell,pxa168-eth"; |
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reg = <0xe50000 0x10000>; |
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clocks = <&chip_clk CLKID_GETH0>; |
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
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/* set by bootloader */ |
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local-mac-address = [00 00 00 00 00 00]; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy-connection-type = "mii"; |
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phy-handle = <ðphy0>; |
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status = "disabled"; |
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ethphy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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apb@e80000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0xe80000 0x10000>; |
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interrupt-parent = <&aic>; |
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gpio0: gpio@0400 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0400 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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porta: gpio-port@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <8>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <0>; |
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}; |
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}; |
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gpio1: gpio@0800 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0800 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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portb: gpio-port@1 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <8>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <1>; |
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}; |
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}; |
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gpio2: gpio@0c00 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0c00 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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portc: gpio-port@2 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <8>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <2>; |
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}; |
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}; |
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gpio3: gpio@1000 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x1000 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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portd: gpio-port@3 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <8>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <3>; |
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}; |
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}; |
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timer0: timer@2c00 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c00 0x14>; |
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interrupts = <8>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "okay"; |
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}; |
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timer1: timer@2c14 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c14 0x14>; |
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interrupts = <9>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "okay"; |
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}; |
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timer2: timer@2c28 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c28 0x14>; |
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interrupts = <10>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "disabled"; |
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}; |
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timer3: timer@2c3c { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c3c 0x14>; |
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interrupts = <11>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "disabled"; |
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}; |
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timer4: timer@2c50 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c50 0x14>; |
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interrupts = <12>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "disabled"; |
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}; |
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timer5: timer@2c64 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c64 0x14>; |
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interrupts = <13>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "disabled"; |
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}; |
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timer6: timer@2c78 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c78 0x14>; |
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interrupts = <14>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "disabled"; |
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}; |
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timer7: timer@2c8c { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x2c8c 0x14>; |
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interrupts = <15>; |
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clocks = <&chip_clk CLKID_CFG>; |
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clock-names = "timer"; |
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status = "disabled"; |
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}; |
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aic: interrupt-controller@3000 { |
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compatible = "snps,dw-apb-ictl"; |
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reg = <0x3000 0xc00>; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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ahci: sata@e90000 { |
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compatible = "marvell,berlin2-ahci", "generic-ahci"; |
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reg = <0xe90000 0x1000>; |
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&chip_clk CLKID_SATA>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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sata0: sata-port@0 { |
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reg = <0>; |
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phys = <&sata_phy 0>; |
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status = "disabled"; |
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}; |
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sata1: sata-port@1 { |
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reg = <1>; |
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phys = <&sata_phy 1>; |
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status = "disabled"; |
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}; |
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}; |
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sata_phy: phy@e900a0 { |
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compatible = "marvell,berlin2-sata-phy"; |
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reg = <0xe900a0 0x200>; |
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clocks = <&chip_clk CLKID_SATA>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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#phy-cells = <1>; |
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status = "disabled"; |
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sata-phy@0 { |
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reg = <0>; |
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}; |
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sata-phy@1 { |
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reg = <1>; |
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}; |
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}; |
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chip: chip-control@ea0000 { |
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compatible = "simple-mfd", "syscon"; |
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reg = <0xea0000 0x400>; |
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chip_clk: clock { |
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compatible = "marvell,berlin2-clk"; |
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#clock-cells = <1>; |
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clocks = <&refclk>; |
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clock-names = "refclk"; |
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}; |
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soc_pinctrl: pin-controller { |
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compatible = "marvell,berlin2-soc-pinctrl"; |
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emmc_pmux: emmc-pmux { |
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groups = "G26"; |
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function = "emmc"; |
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}; |
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}; |
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chip_rst: reset { |
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compatible = "marvell,berlin2-reset"; |
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#reset-cells = <2>; |
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}; |
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}; |
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pwm: pwm@f20000 { |
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compatible = "marvell,berlin-pwm"; |
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reg = <0xf20000 0x40>; |
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clocks = <&chip_clk CLKID_CFG>; |
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#pwm-cells = <3>; |
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}; |
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apb@fc0000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0xfc0000 0x10000>; |
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interrupt-parent = <&sic>; |
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wdt0: watchdog@1000 { |
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compatible = "snps,dw-wdt"; |
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reg = <0x1000 0x100>; |
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clocks = <&refclk>; |
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interrupts = <0>; |
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}; |
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wdt1: watchdog@2000 { |
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compatible = "snps,dw-wdt"; |
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reg = <0x2000 0x100>; |
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clocks = <&refclk>; |
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interrupts = <1>; |
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}; |
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wdt2: watchdog@3000 { |
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compatible = "snps,dw-wdt"; |
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reg = <0x3000 0x100>; |
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clocks = <&refclk>; |
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interrupts = <2>; |
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}; |
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sm_gpio1: gpio@5000 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x5000 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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portf: gpio-port@5 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <8>; |
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reg = <0>; |
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}; |
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}; |
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sm_gpio0: gpio@c000 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0xc000 0x400>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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porte: gpio-port@4 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <8>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <11>; |
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}; |
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}; |
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uart0: serial@9000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x9000 0x100>; |
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reg-shift = <2>; |
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reg-io-width = <1>; |
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interrupts = <8>; |
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clocks = <&refclk>; |
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pinctrl-0 = <&uart0_pmux>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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uart1: serial@a000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0xa000 0x100>; |
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reg-shift = <2>; |
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reg-io-width = <1>; |
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interrupts = <9>; |
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clocks = <&refclk>; |
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pinctrl-0 = <&uart1_pmux>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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uart2: serial@b000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0xb000 0x100>; |
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reg-shift = <2>; |
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reg-io-width = <1>; |
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interrupts = <10>; |
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clocks = <&refclk>; |
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pinctrl-0 = <&uart2_pmux>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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sysctrl: system-controller@d000 { |
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compatible = "simple-mfd", "syscon"; |
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reg = <0xd000 0x100>; |
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sys_pinctrl: pin-controller { |
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compatible = "marvell,berlin2-system-pinctrl"; |
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uart0_pmux: uart0-pmux { |
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groups = "GSM4"; |
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function = "uart0"; |
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}; |
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uart1_pmux: uart1-pmux { |
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groups = "GSM5"; |
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function = "uart1"; |
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}; |
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uart2_pmux: uart2-pmux { |
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groups = "GSM3"; |
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function = "uart2"; |
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}; |
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}; |
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}; |
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sic: interrupt-controller@e000 { |
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compatible = "snps,dw-apb-ictl"; |
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reg = <0xe000 0x400>; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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}; |
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}; |