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1.1 skrll 1: // SPDX-License-Identifier: GPL-2.0 2: 3: /* This include file covers the common peripherals and configuration between 4: * bcm2835, bcm2836 and bcm2837 implementations. 5: */ 6: 7: / { 8: interrupt-parent = <&intc>; 9: 10: soc { 11: dma: dma@7e007000 { 12: compatible = "brcm,bcm2835-dma"; 13: reg = <0x7e007000 0xf00>; 14: interrupts = <1 16>, 15: <1 17>, 16: <1 18>, 17: <1 19>, 18: <1 20>, 19: <1 21>, 20: <1 22>, 21: <1 23>, 22: <1 24>, 23: <1 25>, 24: <1 26>, 25: /* dma channel 11-14 share one irq */ 26: <1 27>, 27: <1 27>, 28: <1 27>, 29: <1 27>, 30: /* unused shared irq for all channels */ 31: <1 28>; 32: interrupt-names = "dma0", 33: "dma1", 34: "dma2", 35: "dma3", 36: "dma4", 37: "dma5", 38: "dma6", 39: "dma7", 40: "dma8", 41: "dma9", 42: "dma10", 43: "dma11", 44: "dma12", 45: "dma13", 46: "dma14", 47: "dma-shared-all"; 48: #dma-cells = <1>; 49: brcm,dma-channel-mask = <0x7f35>; 50: }; 51: 52: intc: interrupt-controller@7e00b200 { 53: compatible = "brcm,bcm2835-armctrl-ic"; 54: reg = <0x7e00b200 0x200>; 55: interrupt-controller; 56: #interrupt-cells = <2>; 57: }; 58: 59: pm: watchdog@7e100000 { 60: compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 61: #power-domain-cells = <1>; 62: #reset-cells = <1>; 63: reg = <0x7e100000 0x114>, 64: <0x7e00a000 0x24>; 65: clocks = <&clocks BCM2835_CLOCK_V3D>, 66: <&clocks BCM2835_CLOCK_PERI_IMAGE>, 67: <&clocks BCM2835_CLOCK_H264>, 68: <&clocks BCM2835_CLOCK_ISP>; 69: clock-names = "v3d", "peri_image", "h264", "isp"; 70: system-power-controller; 71: }; 72: 73: pixelvalve@7e206000 { 74: compatible = "brcm,bcm2835-pixelvalve0"; 75: reg = <0x7e206000 0x100>; 76: interrupts = <2 13>; /* pwa0 */ 1.3 ! skrll 77: status = "disabled"; 1.1 skrll 78: }; 79: 80: pixelvalve@7e207000 { 81: compatible = "brcm,bcm2835-pixelvalve1"; 82: reg = <0x7e207000 0x100>; 83: interrupts = <2 14>; /* pwa1 */ 1.3 ! skrll 84: status = "disabled"; 1.1 skrll 85: }; 86: 87: thermal: thermal@7e212000 { 88: compatible = "brcm,bcm2835-thermal"; 89: reg = <0x7e212000 0x8>; 90: clocks = <&clocks BCM2835_CLOCK_TSENS>; 91: #thermal-sensor-cells = <0>; 92: status = "disabled"; 93: }; 94: 95: i2c2: i2c@7e805000 { 96: compatible = "brcm,bcm2835-i2c"; 97: reg = <0x7e805000 0x1000>; 98: interrupts = <2 21>; 99: clocks = <&clocks BCM2835_CLOCK_VPU>; 100: #address-cells = <1>; 101: #size-cells = <0>; 102: status = "okay"; 103: }; 104: 105: pixelvalve@7e807000 { 106: compatible = "brcm,bcm2835-pixelvalve2"; 107: reg = <0x7e807000 0x100>; 108: interrupts = <2 10>; /* pixelvalve */ 1.3 ! skrll 109: status = "disabled"; 1.1 skrll 110: }; 111: 112: hdmi: hdmi@7e902000 { 113: compatible = "brcm,bcm2835-hdmi"; 114: reg = <0x7e902000 0x600>, 115: <0x7e808000 0x100>; 116: interrupts = <2 8>, <2 9>; 117: ddc = <&i2c2>; 118: clocks = <&clocks BCM2835_PLLH_PIX>, 119: <&clocks BCM2835_CLOCK_HSM>; 120: clock-names = "pixel", "hdmi"; 121: dmas = <&dma 17>; 122: dma-names = "audio-rx"; 123: status = "disabled"; 124: }; 125: 126: v3d: v3d@7ec00000 { 127: compatible = "brcm,bcm2835-v3d"; 128: reg = <0x7ec00000 0x1000>; 129: interrupts = <1 10>; 130: power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 1.2 skrll 131: status = "disabled"; 1.1 skrll 132: }; 133: 134: vc4: gpu { 135: compatible = "brcm,bcm2835-vc4"; 136: }; 1.2 skrll 137: 138: fb: fb { 139: compatible = "brcm,bcm2835-fb"; 140: status = "ok"; 141: }; 1.1 skrll 142: }; 143: }; 144: 145: &cpu_thermal { 146: thermal-sensors = <&thermal>; 147: }; 148: 149: &gpio { 150: i2c_slave_gpio18: i2c_slave_gpio18 { 151: brcm,pins = <18 19 20 21>; 152: brcm,function = <BCM2835_FSEL_ALT3>; 153: }; 154: 155: jtag_gpio4: jtag_gpio4 { 156: brcm,pins = <4 5 6 12 13>; 157: brcm,function = <BCM2835_FSEL_ALT5>; 158: }; 159: 160: pwm0_gpio12: pwm0_gpio12 { 161: brcm,pins = <12>; 162: brcm,function = <BCM2835_FSEL_ALT0>; 163: }; 164: pwm0_gpio18: pwm0_gpio18 { 165: brcm,pins = <18>; 166: brcm,function = <BCM2835_FSEL_ALT5>; 167: }; 168: pwm0_gpio40: pwm0_gpio40 { 169: brcm,pins = <40>; 170: brcm,function = <BCM2835_FSEL_ALT0>; 171: }; 172: pwm1_gpio13: pwm1_gpio13 { 173: brcm,pins = <13>; 174: brcm,function = <BCM2835_FSEL_ALT0>; 175: }; 176: pwm1_gpio19: pwm1_gpio19 { 177: brcm,pins = <19>; 178: brcm,function = <BCM2835_FSEL_ALT5>; 179: }; 180: pwm1_gpio41: pwm1_gpio41 { 181: brcm,pins = <41>; 182: brcm,function = <BCM2835_FSEL_ALT0>; 183: }; 184: pwm1_gpio45: pwm1_gpio45 { 185: brcm,pins = <45>; 186: brcm,function = <BCM2835_FSEL_ALT0>; 187: }; 188: }; 189: 190: &i2s { 191: dmas = <&dma 2>, <&dma 3>; 192: dma-names = "tx", "rx"; 193: }; 194: 195: &sdhost { 196: dmas = <&dma 13>; 197: dma-names = "rx-tx"; 198: }; 199: 200: &spi { 201: dmas = <&dma 6>, <&dma 7>; 202: dma-names = "tx", "rx"; 203: };