Annotation of src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h, Revision 1.20
1.12 riastrad 1: /* $NetBSD$ */
2:
1.1 riastrad 3: /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
4: */
5: /*
6: *
7: * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8: * All Rights Reserved.
9: *
10: * Permission is hereby granted, free of charge, to any person obtaining a
11: * copy of this software and associated documentation files (the
12: * "Software"), to deal in the Software without restriction, including
13: * without limitation the rights to use, copy, modify, merge, publish,
14: * distribute, sub license, and/or sell copies of the Software, and to
15: * permit persons to whom the Software is furnished to do so, subject to
16: * the following conditions:
17: *
18: * The above copyright notice and this permission notice (including the
19: * next paragraph) shall be included in all copies or substantial portions
20: * of the Software.
21: *
22: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
23: * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24: * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
25: * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
26: * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
27: * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
28: * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29: *
30: */
31:
32: #ifndef _I915_DRV_H_
33: #define _I915_DRV_H_
34:
1.11 nonaka 35: #if defined(__NetBSD__)
36: #ifdef _KERNEL_OPT
37: #if defined(i386) || defined(amd64)
1.10 nonaka 38: #include "acpica.h"
1.11 nonaka 39: #endif /* i386 || amd64 */
40: #endif /* _KERNEL_OPT */
1.10 nonaka 41: #if (NACPICA > 0)
42: #define CONFIG_ACPI
1.11 nonaka 43: #endif /* NACPICA > 0 */
44: #endif /* __NetBSD__ */
1.10 nonaka 45:
1.4 riastrad 46: #include <uapi/drm/i915_drm.h>
1.12 riastrad 47: #include <uapi/drm/drm_fourcc.h>
1.4 riastrad 48:
1.1 riastrad 49: #include "i915_reg.h"
50: #include "intel_bios.h"
51: #include "intel_ringbuffer.h"
1.12 riastrad 52: #include "intel_lrc.h"
53: #include "i915_gem_gtt.h"
54: #include "i915_gem_render_state.h"
1.1 riastrad 55: #include <linux/io-mapping.h>
56: #include <linux/i2c.h>
57: #include <linux/i2c-algo-bit.h>
58: #include <drm/intel-gtt.h>
1.12 riastrad 59: #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
60: #include <drm/drm_gem.h>
1.1 riastrad 61: #include <linux/backlight.h>
1.12 riastrad 62: #include <linux/hashtable.h>
1.1 riastrad 63: #include <linux/intel-iommu.h>
64: #include <linux/kref.h>
1.2 riastrad 65: #include <linux/completion.h>
66: #include <linux/shrinker.h>
1.4 riastrad 67: #include <linux/pm_qos.h>
1.5 riastrad 68: #include <linux/sched.h>
1.12 riastrad 69: #include "intel_guc.h"
1.1 riastrad 70:
71: /* General customization:
72: */
73:
74: #define DRIVER_NAME "i915"
75: #define DRIVER_DESC "Intel Graphics"
1.12 riastrad 76: #define DRIVER_DATE "20151010"
77:
78: #undef WARN_ON
79: /* Many gcc seem to no see through this and fall over :( */
80: #if 0
81: #define WARN_ON(x) ({ \
82: bool __i915_warn_cond = (x); \
83: if (__builtin_constant_p(__i915_warn_cond)) \
84: BUILD_BUG_ON(__i915_warn_cond); \
85: WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
86: #else
87: #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
88: #endif
89:
90: #undef WARN_ON_ONCE
91: #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
92:
93: #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
94: (long) (x), __func__);
95:
96: /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
97: * WARN_ON()) for hw state sanity checks to check for unexpected conditions
98: * which may not necessarily be a user visible problem. This will either
99: * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
100: * enable distros and users to tailor their preferred amount of i915 abrt
101: * spam.
102: */
103: #define I915_STATE_WARN(condition, format...) ({ \
104: int __ret_warn_on = !!(condition); \
105: if (unlikely(__ret_warn_on)) { \
106: if (i915.verbose_state_checks) \
107: WARN(1, format); \
108: else \
109: DRM_ERROR(format); \
110: } \
111: unlikely(__ret_warn_on); \
112: })
113:
114: #define I915_STATE_WARN_ON(condition) ({ \
115: int __ret_warn_on = !!(condition); \
116: if (unlikely(__ret_warn_on)) { \
117: if (i915.verbose_state_checks) \
118: WARN(1, "WARN_ON(" #condition ")\n"); \
119: else \
120: DRM_ERROR("WARN_ON(" #condition ")\n"); \
121: } \
122: unlikely(__ret_warn_on); \
123: })
124:
125: static inline const char *yesno(bool v)
126: {
127: return v ? "yes" : "no";
128: }
1.1 riastrad 129:
1.9 matt 130: enum i915_pipe {
1.4 riastrad 131: INVALID_PIPE = -1,
1.1 riastrad 132: PIPE_A = 0,
133: PIPE_B,
134: PIPE_C,
1.4 riastrad 135: _PIPE_EDP,
136: I915_MAX_PIPES = _PIPE_EDP
1.1 riastrad 137: };
138: #define pipe_name(p) ((p) + 'A')
139:
140: enum transcoder {
141: TRANSCODER_A = 0,
142: TRANSCODER_B,
143: TRANSCODER_C,
1.4 riastrad 144: TRANSCODER_EDP,
145: I915_MAX_TRANSCODERS
1.1 riastrad 146: };
147: #define transcoder_name(t) ((t) + 'A')
148:
1.12 riastrad 149: /*
150: * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
151: * number of planes per CRTC. Not all platforms really have this many planes,
152: * which means some arrays of size I915_MAX_PLANES may have unused entries
153: * between the topmost sprite plane and the cursor plane.
154: */
1.1 riastrad 155: enum plane {
156: PLANE_A = 0,
157: PLANE_B,
158: PLANE_C,
1.12 riastrad 159: PLANE_CURSOR,
160: I915_MAX_PLANES,
1.1 riastrad 161: };
162: #define plane_name(p) ((p) + 'A')
163:
1.4 riastrad 164: #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
165:
1.1 riastrad 166: enum port {
167: PORT_A = 0,
168: PORT_B,
169: PORT_C,
170: PORT_D,
171: PORT_E,
172: I915_MAX_PORTS
173: };
174: #define port_name(p) ((p) + 'A')
175:
1.12 riastrad 176: #define I915_NUM_PHYS_VLV 2
1.4 riastrad 177:
178: enum dpio_channel {
179: DPIO_CH0,
180: DPIO_CH1
181: };
182:
183: enum dpio_phy {
184: DPIO_PHY0,
185: DPIO_PHY1
186: };
187:
188: enum intel_display_power_domain {
189: POWER_DOMAIN_PIPE_A,
190: POWER_DOMAIN_PIPE_B,
191: POWER_DOMAIN_PIPE_C,
192: POWER_DOMAIN_PIPE_A_PANEL_FITTER,
193: POWER_DOMAIN_PIPE_B_PANEL_FITTER,
194: POWER_DOMAIN_PIPE_C_PANEL_FITTER,
195: POWER_DOMAIN_TRANSCODER_A,
196: POWER_DOMAIN_TRANSCODER_B,
197: POWER_DOMAIN_TRANSCODER_C,
198: POWER_DOMAIN_TRANSCODER_EDP,
199: POWER_DOMAIN_PORT_DDI_A_2_LANES,
200: POWER_DOMAIN_PORT_DDI_A_4_LANES,
201: POWER_DOMAIN_PORT_DDI_B_2_LANES,
202: POWER_DOMAIN_PORT_DDI_B_4_LANES,
203: POWER_DOMAIN_PORT_DDI_C_2_LANES,
204: POWER_DOMAIN_PORT_DDI_C_4_LANES,
205: POWER_DOMAIN_PORT_DDI_D_2_LANES,
206: POWER_DOMAIN_PORT_DDI_D_4_LANES,
1.12 riastrad 207: POWER_DOMAIN_PORT_DDI_E_2_LANES,
1.4 riastrad 208: POWER_DOMAIN_PORT_DSI,
209: POWER_DOMAIN_PORT_CRT,
210: POWER_DOMAIN_PORT_OTHER,
211: POWER_DOMAIN_VGA,
212: POWER_DOMAIN_AUDIO,
1.12 riastrad 213: POWER_DOMAIN_PLLS,
214: POWER_DOMAIN_AUX_A,
215: POWER_DOMAIN_AUX_B,
216: POWER_DOMAIN_AUX_C,
217: POWER_DOMAIN_AUX_D,
218: POWER_DOMAIN_GMBUS,
1.4 riastrad 219: POWER_DOMAIN_INIT,
220:
221: POWER_DOMAIN_NUM,
222: };
223:
224: #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
225: #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
226: ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
227: #define POWER_DOMAIN_TRANSCODER(tran) \
228: ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
229: (tran) + POWER_DOMAIN_TRANSCODER_A)
230:
231: enum hpd_pin {
232: HPD_NONE = 0,
233: HPD_TV = HPD_NONE, /* TV is known to be unreliable */
234: HPD_CRT,
235: HPD_SDVO_B,
236: HPD_SDVO_C,
1.12 riastrad 237: HPD_PORT_A,
1.4 riastrad 238: HPD_PORT_B,
239: HPD_PORT_C,
240: HPD_PORT_D,
1.12 riastrad 241: HPD_PORT_E,
1.4 riastrad 242: HPD_NUM_PINS
243: };
244:
1.12 riastrad 245: #define for_each_hpd_pin(__pin) \
246: for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
247:
248: struct i915_hotplug {
249: struct work_struct hotplug_work;
250:
251: struct {
252: unsigned long last_jiffies;
253: int count;
254: enum {
255: HPD_ENABLED = 0,
256: HPD_DISABLED = 1,
257: HPD_MARK_DISABLED = 2
258: } state;
259: } stats[HPD_NUM_PINS];
260: u32 event_bits;
261: struct delayed_work reenable_work;
262:
263: struct intel_digital_port *irq_port[I915_MAX_PORTS];
264: u32 long_port_mask;
265: u32 short_port_mask;
266: struct work_struct dig_port_work;
267:
268: /*
269: * if we get a HPD irq from DP and a HPD irq from non-DP
270: * the non-DP HPD could block the workqueue on a mode config
271: * mutex getting, that userspace may have taken. However
272: * userspace is waiting on the DP workqueue to run which is
273: * blocked behind the non-DP one.
274: */
275: struct workqueue_struct *dp_wq;
276: };
277:
1.4 riastrad 278: #define I915_GEM_GPU_DOMAINS \
279: (I915_GEM_DOMAIN_RENDER | \
280: I915_GEM_DOMAIN_SAMPLER | \
281: I915_GEM_DOMAIN_COMMAND | \
282: I915_GEM_DOMAIN_INSTRUCTION | \
283: I915_GEM_DOMAIN_VERTEX)
1.1 riastrad 284:
1.12 riastrad 285: #define for_each_pipe(__dev_priv, __p) \
286: for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
287: #define for_each_plane(__dev_priv, __pipe, __p) \
288: for ((__p) = 0; \
289: (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
290: (__p)++)
291: #define for_each_sprite(__dev_priv, __p, __s) \
292: for ((__s) = 0; \
293: (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
294: (__s)++)
295:
296: #define for_each_crtc(dev, crtc) \
297: list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
298:
299: #define for_each_intel_plane(dev, intel_plane) \
300: list_for_each_entry(intel_plane, \
301: &dev->mode_config.plane_list, \
302: base.head)
303:
304: #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
305: list_for_each_entry(intel_plane, \
306: &(dev)->mode_config.plane_list, \
307: base.head) \
308: if ((intel_plane)->pipe == (intel_crtc)->pipe)
309:
310: #define for_each_intel_crtc(dev, intel_crtc) \
311: list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
312:
313: #define for_each_intel_encoder(dev, intel_encoder) \
314: list_for_each_entry(intel_encoder, \
315: &(dev)->mode_config.encoder_list, \
316: base.head)
317:
318: #define for_each_intel_connector(dev, intel_connector) \
319: list_for_each_entry(intel_connector, \
320: &dev->mode_config.connector_list, \
321: base.head)
1.1 riastrad 322:
323: #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
324: list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
325: if ((intel_encoder)->base.crtc == (__crtc))
326:
1.4 riastrad 327: #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
328: list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
329: if ((intel_connector)->base.encoder == (__encoder))
330:
1.12 riastrad 331: #define for_each_power_domain(domain, mask) \
332: for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
333: if ((1 << (domain)) & (mask))
334:
1.4 riastrad 335: struct drm_i915_private;
1.12 riastrad 336: struct i915_mm_struct;
337: struct i915_mmu_object;
338:
339: struct drm_i915_file_private {
340: struct drm_i915_private *dev_priv;
341: struct drm_file *file;
342:
343: struct {
344: spinlock_t lock;
345: struct list_head request_list;
346: /* 20ms is a fairly arbitrary limit (greater than the average frame time)
347: * chosen to prevent the CPU getting more than a frame ahead of the GPU
348: * (when using lax throttling for the frontbuffer). We also use it to
349: * offer free GPU waitboosts for severely congested workloads.
350: */
351: #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
352: } mm;
353: struct idr context_idr;
354:
355: struct intel_rps_client {
356: struct list_head link;
357: unsigned boosts;
358: } rps;
359:
360: struct intel_engine_cs *bsd_ring;
361: };
1.4 riastrad 362:
363: enum intel_dpll_id {
364: DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
365: /* real shared dpll ids must be >= 0 */
1.12 riastrad 366: DPLL_ID_PCH_PLL_A = 0,
367: DPLL_ID_PCH_PLL_B = 1,
368: /* hsw/bdw */
369: DPLL_ID_WRPLL1 = 0,
370: DPLL_ID_WRPLL2 = 1,
371: DPLL_ID_SPLL = 2,
372:
373: /* skl */
374: DPLL_ID_SKL_DPLL1 = 0,
375: DPLL_ID_SKL_DPLL2 = 1,
376: DPLL_ID_SKL_DPLL3 = 2,
1.4 riastrad 377: };
1.12 riastrad 378: #define I915_NUM_PLLS 3
1.4 riastrad 379:
380: struct intel_dpll_hw_state {
1.12 riastrad 381: /* i9xx, pch plls */
1.4 riastrad 382: uint32_t dpll;
383: uint32_t dpll_md;
384: uint32_t fp0;
385: uint32_t fp1;
1.12 riastrad 386:
387: /* hsw, bdw */
388: uint32_t wrpll;
389: uint32_t spll;
390:
391: /* skl */
392: /*
393: * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
394: * lower part of ctrl1 and they get shifted into position when writing
395: * the register. This allows us to easily compare the state to share
396: * the DPLL.
397: */
398: uint32_t ctrl1;
399: /* HDMI only, 0 when used for DP */
400: uint32_t cfgcr1, cfgcr2;
401:
402: /* bxt */
403: uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
404: pcsdw12;
405: };
406:
407: struct intel_shared_dpll_config {
408: unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
409: struct intel_dpll_hw_state hw_state;
1.4 riastrad 410: };
411:
412: struct intel_shared_dpll {
1.12 riastrad 413: struct intel_shared_dpll_config config;
414:
1.1 riastrad 415: int active; /* count of number of active CRTCs (i.e. DPMS on) */
416: bool on; /* is the PLL actually active? Disabled during modeset */
1.4 riastrad 417: const char *name;
418: /* should match the index in the dev_priv->shared_dplls array */
419: enum intel_dpll_id id;
1.12 riastrad 420: /* The mode_set hook is optional and should be used together with the
421: * intel_prepare_shared_dpll function. */
1.4 riastrad 422: void (*mode_set)(struct drm_i915_private *dev_priv,
423: struct intel_shared_dpll *pll);
424: void (*enable)(struct drm_i915_private *dev_priv,
425: struct intel_shared_dpll *pll);
426: void (*disable)(struct drm_i915_private *dev_priv,
427: struct intel_shared_dpll *pll);
428: bool (*get_hw_state)(struct drm_i915_private *dev_priv,
429: struct intel_shared_dpll *pll,
430: struct intel_dpll_hw_state *hw_state);
431: };
432:
1.12 riastrad 433: #define SKL_DPLL0 0
434: #define SKL_DPLL1 1
435: #define SKL_DPLL2 2
436: #define SKL_DPLL3 3
437:
1.4 riastrad 438: /* Used by dp and fdi links */
439: struct intel_link_m_n {
440: uint32_t tu;
441: uint32_t gmch_m;
442: uint32_t gmch_n;
443: uint32_t link_m;
444: uint32_t link_n;
445: };
446:
447: void intel_link_compute_m_n(int bpp, int nlanes,
448: int pixel_clock, int link_clock,
449: struct intel_link_m_n *m_n);
1.1 riastrad 450:
451: /* Interface history:
452: *
453: * 1.1: Original.
454: * 1.2: Add Power Management
455: * 1.3: Add vblank support
456: * 1.4: Fix cmdbuffer path, add heap destroy
457: * 1.5: Add vblank pipe configuration
458: * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
459: * - Support vertical blank on secondary display pipe
460: */
461: #define DRIVER_MAJOR 1
462: #define DRIVER_MINOR 6
463: #define DRIVER_PATCHLEVEL 0
464:
465: #define WATCH_LISTS 0
466:
467: struct opregion_header;
468: struct opregion_acpi;
469: struct opregion_swsci;
470: struct opregion_asle;
471:
1.2 riastrad 472: #ifdef __NetBSD__ /* XXX acpi iomem */
473: # include <linux/acpi_io.h>
474: # define __iomem __acpi_iomem
475: #endif
476:
1.1 riastrad 477: struct intel_opregion {
1.20 ! riastrad 478: #ifdef __NetBSD__
! 479: bus_space_tag_t bst;
! 480: bus_space_handle_t bsh;
! 481: #endif
1.12 riastrad 482: struct opregion_header *header;
483: struct opregion_acpi *acpi;
484: struct opregion_swsci *swsci;
1.4 riastrad 485: u32 swsci_gbda_sub_functions;
486: u32 swsci_sbcb_sub_functions;
1.12 riastrad 487: struct opregion_asle *asle;
488: void *vbt;
489: u32 *lid_state;
1.4 riastrad 490: struct work_struct asle_work;
1.1 riastrad 491: };
492: #define OPREGION_SIZE (8*1024)
493:
1.2 riastrad 494: #ifdef __NetBSD__ /* XXX acpi iomem */
495: # undef __iomem
496: #endif
497:
1.1 riastrad 498: struct intel_overlay;
499: struct intel_overlay_error_state;
500:
501: #define I915_FENCE_REG_NONE -1
1.4 riastrad 502: #define I915_MAX_NUM_FENCES 32
503: /* 32 fences + sign bit for FENCE_REG_NONE */
504: #define I915_MAX_NUM_FENCE_BITS 6
1.1 riastrad 505:
506: struct drm_i915_fence_reg {
507: struct list_head lru_list;
508: struct drm_i915_gem_object *obj;
509: int pin_count;
510: };
511:
512: struct sdvo_device_mapping {
513: u8 initialized;
514: u8 dvo_port;
515: u8 slave_addr;
516: u8 dvo_wiring;
517: u8 i2c_pin;
518: u8 ddc_pin;
519: };
520:
521: struct intel_display_error_state;
522:
523: struct drm_i915_error_state {
524: struct kref ref;
1.4 riastrad 525: struct timeval time;
526:
527: char error_msg[128];
1.12 riastrad 528: int iommu;
1.4 riastrad 529: u32 reset_count;
530: u32 suspend_count;
531:
532: /* Generic register state */
1.1 riastrad 533: u32 eir;
534: u32 pgtbl_er;
535: u32 ier;
1.12 riastrad 536: u32 gtier[4];
1.1 riastrad 537: u32 ccid;
538: u32 derrmr;
539: u32 forcewake;
540: u32 error; /* gen6+ */
541: u32 err_int; /* gen7 */
1.12 riastrad 542: u32 fault_data0; /* gen8, gen9 */
543: u32 fault_data1; /* gen8, gen9 */
1.4 riastrad 544: u32 done_reg;
545: u32 gac_eco;
546: u32 gam_ecochk;
547: u32 gab_ctl;
548: u32 gfx_mode;
1.1 riastrad 549: u32 extra_instdone[I915_NUM_INSTDONE_REG];
550: u64 fence[I915_MAX_NUM_FENCES];
1.4 riastrad 551: struct intel_overlay_error_state *overlay;
552: struct intel_display_error_state *display;
1.12 riastrad 553: struct drm_i915_error_object *semaphore_obj;
1.4 riastrad 554:
1.1 riastrad 555: struct drm_i915_error_ring {
1.4 riastrad 556: bool valid;
557: /* Software tracked state */
558: bool waiting;
559: int hangcheck_score;
560: enum intel_ring_hangcheck_action hangcheck_action;
561: int num_requests;
562:
563: /* our own tracking of ring head and tail */
564: u32 cpu_ring_head;
565: u32 cpu_ring_tail;
566:
567: u32 semaphore_seqno[I915_NUM_RINGS - 1];
568:
569: /* Register state */
1.12 riastrad 570: u32 start;
1.4 riastrad 571: u32 tail;
572: u32 head;
573: u32 ctl;
574: u32 hws;
575: u32 ipeir;
576: u32 ipehr;
577: u32 instdone;
578: u32 bbstate;
579: u32 instpm;
580: u32 instps;
581: u32 seqno;
582: u64 bbaddr;
583: u64 acthd;
584: u32 fault_reg;
1.12 riastrad 585: u64 faddr;
1.4 riastrad 586: u32 rc_psmi; /* sleep state */
587: u32 semaphore_mboxes[I915_NUM_RINGS - 1];
588:
1.1 riastrad 589: struct drm_i915_error_object {
590: int page_count;
1.12 riastrad 591: u64 gtt_offset;
1.1 riastrad 592: u32 *pages[0];
1.4 riastrad 593: } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
594:
1.1 riastrad 595: struct drm_i915_error_request {
596: long jiffies;
597: u32 seqno;
598: u32 tail;
599: } *requests;
1.4 riastrad 600:
601: struct {
602: u32 gfx_mode;
603: union {
604: u64 pdp[4];
605: u32 pp_dir_base;
606: };
607: } vm_info;
608:
609: pid_t pid;
610: char comm[TASK_COMM_LEN];
1.1 riastrad 611: } ring[I915_NUM_RINGS];
1.12 riastrad 612:
1.1 riastrad 613: struct drm_i915_error_buffer {
614: u32 size;
615: u32 name;
1.12 riastrad 616: u32 rseqno[I915_NUM_RINGS], wseqno;
617: u64 gtt_offset;
1.1 riastrad 618: u32 read_domains;
619: u32 write_domain;
620: s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
621: s32 pinned:2;
622: u32 tiling:2;
623: u32 dirty:1;
624: u32 purgeable:1;
1.12 riastrad 625: u32 userptr:1;
1.1 riastrad 626: s32 ring:4;
1.4 riastrad 627: u32 cache_level:3;
628: } **active_bo, **pinned_bo;
629:
630: u32 *active_bo_count, *pinned_bo_count;
1.12 riastrad 631: u32 vm_count;
1.1 riastrad 632: };
633:
1.4 riastrad 634: struct intel_connector;
1.12 riastrad 635: struct intel_encoder;
636: struct intel_crtc_state;
637: struct intel_initial_plane_config;
1.4 riastrad 638: struct intel_crtc;
639: struct intel_limit;
640: struct dpll;
641:
1.1 riastrad 642: struct drm_i915_display_funcs {
643: int (*get_display_clock_speed)(struct drm_device *dev);
644: int (*get_fifo_size)(struct drm_device *dev, int plane);
1.4 riastrad 645: /**
646: * find_dpll() - Find the best values for the PLL
647: * @limit: limits for the PLL
648: * @crtc: current CRTC
649: * @target: target frequency in kHz
650: * @refclk: reference clock frequency in kHz
651: * @match_clock: if provided, @best_clock P divider must
652: * match the P divider from @match_clock
653: * used for LVDS downclocking
654: * @best_clock: best PLL values found
655: *
656: * Returns true on success, false on failure.
657: */
658: bool (*find_dpll)(const struct intel_limit *limit,
1.12 riastrad 659: struct intel_crtc_state *crtc_state,
1.4 riastrad 660: int target, int refclk,
661: struct dpll *match_clock,
662: struct dpll *best_clock);
663: void (*update_wm)(struct drm_crtc *crtc);
664: void (*update_sprite_wm)(struct drm_plane *plane,
665: struct drm_crtc *crtc,
1.12 riastrad 666: uint32_t sprite_width, uint32_t sprite_height,
667: int pixel_size, bool enable, bool scaled);
668: int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
669: void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
1.4 riastrad 670: /* Returns the active state of the crtc, and if the crtc is active,
671: * fills out the pipe-config with the hw state. */
672: bool (*get_pipe_config)(struct intel_crtc *,
1.12 riastrad 673: struct intel_crtc_state *);
674: void (*get_initial_plane_config)(struct intel_crtc *,
675: struct intel_initial_plane_config *);
676: int (*crtc_compute_clock)(struct intel_crtc *crtc,
677: struct intel_crtc_state *crtc_state);
1.1 riastrad 678: void (*crtc_enable)(struct drm_crtc *crtc);
679: void (*crtc_disable)(struct drm_crtc *crtc);
1.12 riastrad 680: void (*audio_codec_enable)(struct drm_connector *connector,
681: struct intel_encoder *encoder,
682: const struct drm_display_mode *adjusted_mode);
683: void (*audio_codec_disable)(struct intel_encoder *encoder);
1.1 riastrad 684: void (*fdi_link_train)(struct drm_crtc *crtc);
685: void (*init_clock_gating)(struct drm_device *dev);
686: int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
687: struct drm_framebuffer *fb,
1.4 riastrad 688: struct drm_i915_gem_object *obj,
1.12 riastrad 689: struct drm_i915_gem_request *req,
1.4 riastrad 690: uint32_t flags);
1.12 riastrad 691: void (*update_primary_plane)(struct drm_crtc *crtc,
692: struct drm_framebuffer *fb,
693: int x, int y);
1.4 riastrad 694: void (*hpd_irq_setup)(struct drm_device *dev);
1.1 riastrad 695: /* clock updates for mode set */
696: /* cursor updates */
697: /* render clock increase/decrease */
698: /* display clock increase/decrease */
699: /* pll clock increase/decrease */
1.12 riastrad 700: };
1.4 riastrad 701:
1.12 riastrad 702: enum forcewake_domain_id {
703: FW_DOMAIN_ID_RENDER = 0,
704: FW_DOMAIN_ID_BLITTER,
705: FW_DOMAIN_ID_MEDIA,
706:
707: FW_DOMAIN_ID_COUNT
708: };
709:
710: enum forcewake_domains {
711: FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
712: FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
713: FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
714: FORCEWAKE_ALL = (FORCEWAKE_RENDER |
715: FORCEWAKE_BLITTER |
716: FORCEWAKE_MEDIA)
1.4 riastrad 717: };
718:
719: struct intel_uncore_funcs {
720: void (*force_wake_get)(struct drm_i915_private *dev_priv,
1.12 riastrad 721: enum forcewake_domains domains);
1.4 riastrad 722: void (*force_wake_put)(struct drm_i915_private *dev_priv,
1.12 riastrad 723: enum forcewake_domains domains);
1.4 riastrad 724:
725: uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
726: uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
727: uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
728: uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
729:
730: void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
731: uint8_t val, bool trace);
732: void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
733: uint16_t val, bool trace);
734: void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
735: uint32_t val, bool trace);
736: void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
737: uint64_t val, bool trace);
1.1 riastrad 738: };
739:
1.4 riastrad 740: struct intel_uncore {
741: spinlock_t lock; /** lock is also taken in irq contexts. */
742:
743: struct intel_uncore_funcs funcs;
744:
745: unsigned fifo_count;
1.12 riastrad 746: enum forcewake_domains fw_domains;
1.4 riastrad 747:
1.12 riastrad 748: struct intel_uncore_forcewake_domain {
749: struct drm_i915_private *i915;
750: enum forcewake_domain_id id;
751: unsigned wake_count;
752: struct timer_list timer;
753: u32 reg_set;
754: u32 val_set;
755: u32 val_clear;
756: u32 reg_ack;
757: u32 reg_post;
758: u32 val_reset;
759: } fw_domain[FW_DOMAIN_ID_COUNT];
760: };
761:
762: /* Iterate over initialised fw domains */
763: #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
764: for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
765: (i__) < FW_DOMAIN_ID_COUNT; \
766: (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
767: if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
768:
769: #define for_each_fw_domain(domain__, dev_priv__, i__) \
770: for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
771:
772: enum csr_state {
773: FW_UNINITIALIZED = 0,
774: FW_LOADED,
775: FW_FAILED
776: };
777:
778: struct intel_csr {
779: const char *fw_path;
780: uint32_t *dmc_payload;
781: uint32_t dmc_fw_size;
782: uint32_t mmio_count;
783: uint32_t mmioaddr[8];
784: uint32_t mmiodata[8];
785: enum csr_state state;
1.4 riastrad 786: };
787:
788: #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
789: func(is_mobile) sep \
790: func(is_i85x) sep \
791: func(is_i915g) sep \
792: func(is_i945gm) sep \
793: func(is_g33) sep \
794: func(need_gfx_hws) sep \
795: func(is_g4x) sep \
796: func(is_pineview) sep \
797: func(is_broadwater) sep \
798: func(is_crestline) sep \
799: func(is_ivybridge) sep \
800: func(is_valleyview) sep \
801: func(is_haswell) sep \
1.12 riastrad 802: func(is_skylake) sep \
1.4 riastrad 803: func(is_preliminary) sep \
804: func(has_fbc) sep \
805: func(has_pipe_cxsr) sep \
806: func(has_hotplug) sep \
807: func(cursor_needs_physical) sep \
808: func(has_overlay) sep \
809: func(overlay_needs_physical) sep \
810: func(supports_tv) sep \
811: func(has_llc) sep \
812: func(has_ddi) sep \
813: func(has_fpga_dbg)
814:
815: #define DEFINE_FLAG(name) u8 name:1
816: #define SEP_SEMICOLON ;
1.1 riastrad 817:
818: struct intel_device_info {
1.4 riastrad 819: u32 display_mmio_offset;
1.12 riastrad 820: u16 device_id;
1.4 riastrad 821: u8 num_pipes:3;
822: u8 num_sprites[I915_MAX_PIPES];
1.1 riastrad 823: u8 gen;
1.4 riastrad 824: u8 ring_mask; /* Rings supported by the HW */
825: DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
826: /* Register offsets for the various display pipes and transcoders */
827: int pipe_offsets[I915_MAX_TRANSCODERS];
828: int trans_offsets[I915_MAX_TRANSCODERS];
829: int palette_offsets[I915_MAX_PIPES];
1.12 riastrad 830: int cursor_offsets[I915_MAX_PIPES];
831:
832: /* Slice/subslice/EU info */
833: u8 slice_total;
834: u8 subslice_total;
835: u8 subslice_per_slice;
836: u8 eu_total;
837: u8 eu_per_subslice;
838: /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
839: u8 subslice_7eu[3];
840: u8 has_slice_pg:1;
841: u8 has_subslice_pg:1;
842: u8 has_eu_pg:1;
1.4 riastrad 843: };
844:
845: #undef DEFINE_FLAG
846: #undef SEP_SEMICOLON
847:
848: enum i915_cache_level {
849: I915_CACHE_NONE = 0,
850: I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
851: I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
852: caches, eg sampler/render caches, and the
853: large Last-Level-Cache. LLC is coherent with
854: the CPU, but L3 is only visible to the GPU. */
855: I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
856: };
857:
858: struct i915_ctx_hang_stats {
859: /* This context had batch pending when hang was declared */
860: unsigned batch_pending;
861:
862: /* This context had batch active when hang was declared */
863: unsigned batch_active;
864:
865: /* Time when this context was last blamed for a GPU reset */
866: unsigned long guilty_ts;
867:
1.12 riastrad 868: /* If the contexts causes a second GPU hang within this time,
869: * it is permanently banned from submitting any more work.
870: */
871: unsigned long ban_period_seconds;
872:
1.4 riastrad 873: /* This context is banned to submit more work */
874: bool banned;
1.1 riastrad 875: };
876:
877: /* This must match up with the value previously used for execbuf2.rsvd1. */
1.12 riastrad 878: #define DEFAULT_CONTEXT_HANDLE 0
879:
880: #define CONTEXT_NO_ZEROMAP (1<<0)
881: /**
882: * struct intel_context - as the name implies, represents a context.
883: * @ref: reference count.
884: * @user_handle: userspace tracking identity for this context.
885: * @remap_slice: l3 row remapping information.
886: * @flags: context specific flags:
887: * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
888: * @file_priv: filp associated with this context (NULL for global default
889: * context).
890: * @hang_stats: information about the role of this context in possible GPU
891: * hangs.
892: * @ppgtt: virtual memory space used by this context.
893: * @legacy_hw_ctx: render context backing object and whether it is correctly
894: * initialized (legacy ring submission mechanism only).
895: * @link: link in the global list of contexts.
896: *
897: * Contexts are memory images used by the hardware to store copies of their
898: * internal state.
899: */
900: struct intel_context {
1.4 riastrad 901: struct kref ref;
1.12 riastrad 902: int user_handle;
1.4 riastrad 903: uint8_t remap_slice;
1.12 riastrad 904: struct drm_i915_private *i915;
905: int flags;
1.1 riastrad 906: struct drm_i915_file_private *file_priv;
1.4 riastrad 907: struct i915_ctx_hang_stats hang_stats;
1.12 riastrad 908: struct i915_hw_ppgtt *ppgtt;
909:
910: /* Legacy ring buffer submission */
911: struct {
912: struct drm_i915_gem_object *rcs_state;
913: bool initialized;
914: } legacy_hw_ctx;
915:
916: /* Execlists */
917: struct {
918: struct drm_i915_gem_object *state;
919: struct intel_ringbuffer *ringbuf;
920: int pin_count;
921: } engine[I915_NUM_RINGS];
1.4 riastrad 922:
923: struct list_head link;
1.1 riastrad 924: };
925:
1.12 riastrad 926: enum fb_op_origin {
927: ORIGIN_GTT,
928: ORIGIN_CPU,
929: ORIGIN_CS,
930: ORIGIN_FLIP,
931: ORIGIN_DIRTYFB,
932: };
933:
1.4 riastrad 934: struct i915_fbc {
1.12 riastrad 935: /* This is always the inner lock when overlapping with struct_mutex and
936: * it's the outer lock when overlapping with stolen_lock. */
937: struct mutex lock;
938: unsigned long uncompressed_size;
939: unsigned threshold;
1.4 riastrad 940: unsigned int fb_id;
1.12 riastrad 941: unsigned int possible_framebuffer_bits;
942: unsigned int busy_bits;
943: struct intel_crtc *crtc;
1.4 riastrad 944: int y;
945:
1.12 riastrad 946: struct drm_mm_node compressed_fb;
1.4 riastrad 947: struct drm_mm_node *compressed_llb;
948:
1.12 riastrad 949: bool false_color;
950:
951: /* Tracks whether the HW is actually enabled, not whether the feature is
952: * possible. */
953: bool enabled;
954:
1.4 riastrad 955: struct intel_fbc_work {
956: struct delayed_work work;
1.12 riastrad 957: struct intel_crtc *crtc;
1.4 riastrad 958: struct drm_framebuffer *fb;
959: } *fbc_work;
960:
961: enum no_fbc_reason {
962: FBC_OK, /* FBC is enabled */
963: FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
964: FBC_NO_OUTPUT, /* no outputs enabled to compress */
965: FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
966: FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
967: FBC_MODE_TOO_LARGE, /* mode too large for compression */
968: FBC_BAD_PLANE, /* fbc not supported on plane */
969: FBC_NOT_TILED, /* buffer not tiled */
970: FBC_MULTIPLE_PIPES, /* more than one pipe active */
971: FBC_MODULE_PARAM,
972: FBC_CHIP_DEFAULT, /* disabled by default on this chip */
1.12 riastrad 973: FBC_ROTATION, /* rotation is not supported */
974: FBC_IN_DBG_MASTER, /* kernel debugger is active */
975: FBC_BAD_STRIDE, /* stride is not supported */
976: FBC_PIXEL_RATE, /* pixel rate is too big */
977: FBC_PIXEL_FORMAT /* pixel format is invalid */
1.4 riastrad 978: } no_fbc_reason;
1.12 riastrad 979:
980: bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
981: void (*enable_fbc)(struct intel_crtc *crtc);
982: void (*disable_fbc)(struct drm_i915_private *dev_priv);
983: };
984:
985: /**
986: * HIGH_RR is the highest eDP panel refresh rate read from EDID
987: * LOW_RR is the lowest eDP panel refresh rate found from EDID
988: * parsing for same resolution.
989: */
990: enum drrs_refresh_rate_type {
991: DRRS_HIGH_RR,
992: DRRS_LOW_RR,
993: DRRS_MAX_RR, /* RR count */
994: };
995:
996: enum drrs_support_type {
997: DRRS_NOT_SUPPORTED = 0,
998: STATIC_DRRS_SUPPORT = 1,
999: SEAMLESS_DRRS_SUPPORT = 2
1000: };
1001:
1002: struct intel_dp;
1003: struct i915_drrs {
1004: struct mutex mutex;
1005: struct delayed_work work;
1006: struct intel_dp *dp;
1007: unsigned busy_frontbuffer_bits;
1008: enum drrs_refresh_rate_type refresh_rate_type;
1009: enum drrs_support_type type;
1.4 riastrad 1010: };
1011:
1012: struct i915_psr {
1.12 riastrad 1013: struct mutex lock;
1.4 riastrad 1014: bool sink_support;
1015: bool source_ok;
1.12 riastrad 1016: struct intel_dp *enabled;
1017: bool active;
1018: struct delayed_work work;
1019: unsigned busy_frontbuffer_bits;
1020: bool psr2_support;
1021: bool aux_frame_sync;
1.1 riastrad 1022: };
1023:
1024: enum intel_pch {
1025: PCH_NONE = 0, /* No PCH present */
1026: PCH_IBX, /* Ibexpeak PCH */
1027: PCH_CPT, /* Cougarpoint PCH */
1028: PCH_LPT, /* Lynxpoint PCH */
1.12 riastrad 1029: PCH_SPT, /* Sunrisepoint PCH */
1.4 riastrad 1030: PCH_NOP,
1.1 riastrad 1031: };
1032:
1033: enum intel_sbi_destination {
1034: SBI_ICLK,
1035: SBI_MPHY,
1036: };
1037:
1038: #define QUIRK_PIPEA_FORCE (1<<0)
1039: #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1040: #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1.12 riastrad 1041: #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1042: #define QUIRK_PIPEB_FORCE (1<<4)
1043: #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1.1 riastrad 1044:
1045: struct intel_fbdev;
1046: struct intel_fbc_work;
1047:
1048: struct intel_gmbus {
1049: struct i2c_adapter adapter;
1050: u32 force_bit;
1051: u32 reg0;
1052: u32 gpio_reg;
1053: struct i2c_algo_bit_data bit_algo;
1054: struct drm_i915_private *dev_priv;
1055: };
1056:
1057: struct i915_suspend_saved_registers {
1058: u32 saveDSPARB;
1059: u32 saveLVDS;
1060: u32 savePP_ON_DELAYS;
1061: u32 savePP_OFF_DELAYS;
1062: u32 savePP_ON;
1063: u32 savePP_OFF;
1064: u32 savePP_CONTROL;
1065: u32 savePP_DIVISOR;
1066: u32 saveFBC_CONTROL;
1067: u32 saveCACHE_MODE_0;
1068: u32 saveMI_ARB_STATE;
1069: u32 saveSWF0[16];
1070: u32 saveSWF1[16];
1.12 riastrad 1071: u32 saveSWF3[3];
1.1 riastrad 1072: uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1073: u32 savePCH_PORT_HOTPLUG;
1.12 riastrad 1074: u16 saveGCDGMBUS;
1075: };
1076:
1077: struct vlv_s0ix_state {
1078: /* GAM */
1079: u32 wr_watermark;
1080: u32 gfx_prio_ctrl;
1081: u32 arb_mode;
1082: u32 gfx_pend_tlb0;
1083: u32 gfx_pend_tlb1;
1084: u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1085: u32 media_max_req_count;
1086: u32 gfx_max_req_count;
1087: u32 render_hwsp;
1088: u32 ecochk;
1089: u32 bsd_hwsp;
1090: u32 blt_hwsp;
1091: u32 tlb_rd_addr;
1092:
1093: /* MBC */
1094: u32 g3dctl;
1095: u32 gsckgctl;
1096: u32 mbctl;
1097:
1098: /* GCP */
1099: u32 ucgctl1;
1100: u32 ucgctl3;
1101: u32 rcgctl1;
1102: u32 rcgctl2;
1103: u32 rstctl;
1104: u32 misccpctl;
1105:
1106: /* GPM */
1107: u32 gfxpause;
1108: u32 rpdeuhwtc;
1109: u32 rpdeuc;
1110: u32 ecobus;
1111: u32 pwrdwnupctl;
1112: u32 rp_down_timeout;
1113: u32 rp_deucsw;
1114: u32 rcubmabdtmr;
1115: u32 rcedata;
1116: u32 spare2gh;
1117:
1118: /* Display 1 CZ domain */
1119: u32 gt_imr;
1120: u32 gt_ier;
1121: u32 pm_imr;
1122: u32 pm_ier;
1123: u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1124:
1125: /* GT SA CZ domain */
1126: u32 tilectl;
1127: u32 gt_fifoctl;
1128: u32 gtlc_wake_ctrl;
1129: u32 gtlc_survive;
1130: u32 pmwgicz;
1131:
1132: /* Display 2 CZ domain */
1133: u32 gu_ctl0;
1134: u32 gu_ctl1;
1135: u32 pcbr;
1136: u32 clock_gate_dis2;
1137: };
1138:
1139: struct intel_rps_ei {
1140: u32 cz_clock;
1141: u32 render_c0;
1142: u32 media_c0;
1.1 riastrad 1143: };
1144:
1145: struct intel_gen6_power_mgmt {
1.12 riastrad 1146: /*
1147: * work, interrupts_enabled and pm_iir are protected by
1148: * dev_priv->irq_lock
1149: */
1.1 riastrad 1150: struct work_struct work;
1.12 riastrad 1151: bool interrupts_enabled;
1.1 riastrad 1152: u32 pm_iir;
1153:
1.4 riastrad 1154: /* Frequencies are stored in potentially platform dependent multiples.
1155: * In other words, *_freq needs to be multiplied by X to be interesting.
1156: * Soft limits are those which are used for the dynamic reclocking done
1157: * by the driver (raise frequencies under heavy loads, and lower for
1158: * lighter loads). Hard limits are those imposed by the hardware.
1159: *
1160: * A distinction is made for overclocking, which is never enabled by
1161: * default, and is considered to be above the hard limit if it's
1162: * possible at all.
1163: */
1164: u8 cur_freq; /* Current frequency (cached, may not == HW) */
1165: u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1166: u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1167: u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1168: u8 min_freq; /* AKA RPn. Minimum frequency */
1.12 riastrad 1169: u8 idle_freq; /* Frequency to request when we are idle */
1.4 riastrad 1170: u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1171: u8 rp1_freq; /* "less than" RP0 power/freqency */
1172: u8 rp0_freq; /* Non-overclocked max frequency. */
1173:
1.12 riastrad 1174: u8 up_threshold; /* Current %busy required to uplock */
1175: u8 down_threshold; /* Current %busy required to downclock */
1176:
1.4 riastrad 1177: int last_adj;
1178: enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1.1 riastrad 1179:
1.12 riastrad 1180: spinlock_t client_lock;
1181: struct list_head clients;
1182: bool client_boost;
1183:
1.4 riastrad 1184: bool enabled;
1.1 riastrad 1185: struct delayed_work delayed_resume_work;
1.12 riastrad 1186: unsigned boosts;
1187:
1188: struct intel_rps_client semaphores, mmioflips;
1189:
1190: /* manual wa residency calculations */
1191: struct intel_rps_ei ei;
1.1 riastrad 1192:
1193: /*
1194: * Protects RPS/RC6 register access and PCU communication.
1.12 riastrad 1195: * Must be taken after struct_mutex if nested. Note that
1196: * this lock may be held for long periods of time when
1197: * talking to hw - so only take it when talking to hw!
1.1 riastrad 1198: */
1199: struct mutex hw_lock;
1200: };
1201:
1.4 riastrad 1202: /* defined intel_pm.c */
1203: extern spinlock_t mchdev_lock;
1204:
1.1 riastrad 1205: struct intel_ilk_power_mgmt {
1206: u8 cur_delay;
1207: u8 min_delay;
1208: u8 max_delay;
1209: u8 fmax;
1210: u8 fstart;
1211:
1212: u64 last_count1;
1213: unsigned long last_time1;
1214: unsigned long chipset_power;
1215: u64 last_count2;
1.12 riastrad 1216: u64 last_time2;
1.1 riastrad 1217: unsigned long gfx_power;
1218: u8 corr;
1219:
1220: int c_m;
1221: int r_t;
1222: };
1223:
1.4 riastrad 1224: struct drm_i915_private;
1225: struct i915_power_well;
1226:
1227: struct i915_power_well_ops {
1228: /*
1229: * Synchronize the well's hw state to match the current sw state, for
1230: * example enable/disable it based on the current refcount. Called
1231: * during driver init and resume time, possibly after first calling
1232: * the enable/disable handlers.
1233: */
1234: void (*sync_hw)(struct drm_i915_private *dev_priv,
1235: struct i915_power_well *power_well);
1236: /*
1237: * Enable the well and resources that depend on it (for example
1238: * interrupts located on the well). Called after the 0->1 refcount
1239: * transition.
1240: */
1241: void (*enable)(struct drm_i915_private *dev_priv,
1242: struct i915_power_well *power_well);
1243: /*
1244: * Disable the well and resources that depend on it. Called after
1245: * the 1->0 refcount transition.
1246: */
1247: void (*disable)(struct drm_i915_private *dev_priv,
1248: struct i915_power_well *power_well);
1249: /* Returns the hw enabled state. */
1250: bool (*is_enabled)(struct drm_i915_private *dev_priv,
1251: struct i915_power_well *power_well);
1252: };
1253:
1254: /* Power well structure for haswell */
1255: struct i915_power_well {
1256: const char *name;
1257: bool always_on;
1258: /* power well enable/disable usage count */
1259: int count;
1.12 riastrad 1260: /* cached hw enabled state */
1261: bool hw_enabled;
1.4 riastrad 1262: unsigned long domains;
1263: unsigned long data;
1264: const struct i915_power_well_ops *ops;
1265: };
1266:
1267: struct i915_power_domains {
1268: /*
1269: * Power wells needed for initialization at driver init and suspend
1270: * time are on. They are kept on until after the first modeset.
1271: */
1272: bool init_power_on;
1.12 riastrad 1273: bool initializing;
1.4 riastrad 1274: int power_well_count;
1275:
1276: struct mutex lock;
1277: int domain_use_count[POWER_DOMAIN_NUM];
1278: struct i915_power_well *power_wells;
1279: };
1280:
1281: #define MAX_L3_SLICES 2
1.1 riastrad 1282: struct intel_l3_parity {
1.4 riastrad 1283: u32 *remap_info[MAX_L3_SLICES];
1.1 riastrad 1284: struct work_struct error_work;
1.4 riastrad 1285: int which_slice;
1286: };
1287:
1288: struct i915_gem_mm {
1289: /** Memory allocator for GTT stolen memory */
1290: struct drm_mm stolen;
1.12 riastrad 1291: /** Protects the usage of the GTT stolen memory allocator. This is
1292: * always the inner lock when overlapping with struct_mutex. */
1293: struct mutex stolen_lock;
1294:
1.4 riastrad 1295: /** List of all objects in gtt_space. Used to restore gtt
1296: * mappings on resume */
1297: struct list_head bound_list;
1298: /**
1299: * List of objects which are not bound to the GTT (thus
1300: * are idle and not used by the GPU) but still have
1301: * (presumably uncached) pages still attached.
1302: */
1303: struct list_head unbound_list;
1304:
1305: /** Usable portion of the GTT for GEM */
1306: unsigned long stolen_base; /* limited to low memory (32-bit) */
1307:
1308: /** PPGTT used for aliasing the PPGTT with the GTT */
1309: struct i915_hw_ppgtt *aliasing_ppgtt;
1310:
1.12 riastrad 1311: struct notifier_block oom_notifier;
1312: struct shrinker shrinker;
1.4 riastrad 1313: bool shrinker_no_lock_stealing;
1314:
1315: /** LRU list of objects with fence regs on them. */
1316: struct list_head fence_list;
1317:
1318: /**
1319: * We leave the user IRQ off as much as possible,
1320: * but this means that requests will finish and never
1321: * be retired once the system goes idle. Set a timer to
1322: * fire periodically while the ring is running. When it
1323: * fires, go retire requests.
1324: */
1325: struct delayed_work retire_work;
1326:
1327: /**
1328: * When we detect an idle GPU, we want to turn on
1329: * powersaving features. So once we see that there
1330: * are no more requests outstanding and no more
1331: * arrive within a small period of time, we fire
1332: * off the idle_work.
1333: */
1334: struct delayed_work idle_work;
1335:
1336: /**
1337: * Are we in a non-interruptible section of code like
1338: * modesetting?
1339: */
1340: bool interruptible;
1341:
1342: /**
1343: * Is the GPU currently considered idle, or busy executing userspace
1344: * requests? Whilst idle, we attempt to power down the hardware and
1345: * display clocks. In order to reduce the effect on performance, there
1346: * is a slight delay before we do so.
1347: */
1348: bool busy;
1349:
1.12 riastrad 1350: /* the indicator for dispatch video commands on two BSD rings */
1351: int bsd_ring_dispatch_index;
1352:
1.4 riastrad 1353: /** Bit 6 swizzling required for X tiling */
1354: uint32_t bit_6_swizzle_x;
1355: /** Bit 6 swizzling required for Y tiling */
1356: uint32_t bit_6_swizzle_y;
1357:
1358: /* accounting, useful for userland debugging */
1359: spinlock_t object_stat_lock;
1360: size_t object_memory;
1361: u32 object_count;
1362: };
1363:
1364: struct drm_i915_error_state_buf {
1.12 riastrad 1365: struct drm_i915_private *i915;
1.4 riastrad 1366: unsigned bytes;
1367: unsigned size;
1368: int err;
1369: u8 *buf;
1370: loff_t start;
1371: loff_t pos;
1372: };
1373:
1374: struct i915_error_state_file_priv {
1375: struct drm_device *dev;
1376: struct drm_i915_error_state *error;
1377: };
1378:
1379: struct i915_gpu_error {
1380: /* For hangcheck timer */
1381: #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1382: #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1383: /* Hang gpu twice in this window and your context gets banned */
1384: #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1385:
1.12 riastrad 1386: struct workqueue_struct *hangcheck_wq;
1387: struct delayed_work hangcheck_work;
1.4 riastrad 1388:
1389: /* For reset and error_state handling. */
1390: spinlock_t lock;
1391: /* Protected by the above dev->gpu_error.lock. */
1392: struct drm_i915_error_state *first_error;
1393:
1394: unsigned long missed_irq_rings;
1395:
1396: /**
1397: * State variable controlling the reset flow and count
1398: *
1399: * This is a counter which gets incremented when reset is triggered,
1400: * and again when reset has been handled. So odd values (lowest bit set)
1401: * means that reset is in progress and even values that
1402: * (reset_counter >> 1):th reset was successfully completed.
1403: *
1404: * If reset is not completed succesfully, the I915_WEDGE bit is
1405: * set meaning that hardware is terminally sour and there is no
1406: * recovery. All waiters on the reset_queue will be woken when
1407: * that happens.
1408: *
1409: * This counter is used by the wait_seqno code to notice that reset
1410: * event happened and it needs to restart the entire ioctl (since most
1411: * likely the seqno it waited for won't ever signal anytime soon).
1412: *
1413: * This is important for lock-free wait paths, where no contended lock
1414: * naturally enforces the correct ordering between the bail-out of the
1415: * waiter and the gpu reset work code.
1416: */
1417: atomic_t reset_counter;
1418:
1419: #define I915_RESET_IN_PROGRESS_FLAG 1
1420: #define I915_WEDGED (1 << 31)
1421:
1422: /**
1423: * Waitqueue to signal when the reset has completed. Used by clients
1424: * that wait for dev_priv->mm.wedged to settle.
1425: */
1426: #ifdef __NetBSD__
1.5 riastrad 1427: spinlock_t reset_lock;
1.4 riastrad 1428: drm_waitqueue_t reset_queue;
1429: #else
1430: wait_queue_head_t reset_queue;
1431: #endif
1432:
1.12 riastrad 1433: /* Userspace knobs for gpu hang simulation;
1434: * combines both a ring mask, and extra flags
1435: */
1436: u32 stop_rings;
1437: #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1438: #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1.4 riastrad 1439:
1440: /* For missed irq/seqno simulation. */
1441: unsigned int test_irq_rings;
1.12 riastrad 1442:
1443: /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1444: bool reload_in_reset;
1.4 riastrad 1445: };
1446:
1447: enum modeset_restore {
1448: MODESET_ON_LID_OPEN,
1449: MODESET_DONE,
1450: MODESET_SUSPENDED,
1451: };
1452:
1.12 riastrad 1453: #define DP_AUX_A 0x40
1454: #define DP_AUX_B 0x10
1455: #define DP_AUX_C 0x20
1456: #define DP_AUX_D 0x30
1457:
1458: #define DDC_PIN_B 0x05
1459: #define DDC_PIN_C 0x04
1460: #define DDC_PIN_D 0x06
1461:
1.4 riastrad 1462: struct ddi_vbt_port_info {
1.12 riastrad 1463: /*
1464: * This is an index in the HDMI/DVI DDI buffer translation table.
1465: * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1466: * populate this field.
1467: */
1468: #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1.4 riastrad 1469: uint8_t hdmi_level_shift;
1470:
1471: uint8_t supports_dvi:1;
1472: uint8_t supports_hdmi:1;
1473: uint8_t supports_dp:1;
1.12 riastrad 1474:
1475: uint8_t alternate_aux_channel;
1476: uint8_t alternate_ddc_pin;
1477:
1478: uint8_t dp_boost_level;
1479: uint8_t hdmi_boost_level;
1480: };
1481:
1482: enum psr_lines_to_wait {
1483: PSR_0_LINES_TO_WAIT = 0,
1484: PSR_1_LINE_TO_WAIT,
1485: PSR_4_LINES_TO_WAIT,
1486: PSR_8_LINES_TO_WAIT
1.4 riastrad 1487: };
1488:
1489: struct intel_vbt_data {
1490: struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1491: struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1492:
1493: /* Feature bits */
1494: unsigned int int_tv_support:1;
1495: unsigned int lvds_dither:1;
1496: unsigned int lvds_vbt:1;
1497: unsigned int int_crt_support:1;
1498: unsigned int lvds_use_ssc:1;
1499: unsigned int display_clock_mode:1;
1500: unsigned int fdi_rx_polarity_inverted:1;
1.12 riastrad 1501: unsigned int has_mipi:1;
1.4 riastrad 1502: int lvds_ssc_freq;
1503: unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1504:
1.12 riastrad 1505: enum drrs_support_type drrs_type;
1506:
1.4 riastrad 1507: /* eDP */
1508: int edp_rate;
1509: int edp_lanes;
1510: int edp_preemphasis;
1511: int edp_vswing;
1512: bool edp_initialized;
1513: bool edp_support;
1514: int edp_bpp;
1515: struct edp_power_seq edp_pps;
1516:
1517: struct {
1.12 riastrad 1518: bool full_link;
1519: bool require_aux_wakeup;
1520: int idle_frames;
1521: enum psr_lines_to_wait lines_to_wait;
1522: int tp1_wakeup_time;
1523: int tp2_tp3_wakeup_time;
1524: } psr;
1525:
1526: struct {
1.4 riastrad 1527: u16 pwm_freq_hz;
1528: bool present;
1529: bool active_low_pwm;
1.12 riastrad 1530: u8 min_brightness; /* min_brightness/255 of max */
1.4 riastrad 1531: } backlight;
1532:
1533: /* MIPI DSI */
1534: struct {
1.12 riastrad 1535: u16 port;
1.4 riastrad 1536: u16 panel_id;
1.12 riastrad 1537: struct mipi_config *config;
1538: struct mipi_pps_data *pps;
1539: u8 seq_version;
1540: u32 size;
1541: u8 *data;
1542: u8 *sequence[MIPI_SEQ_MAX];
1.4 riastrad 1543: } dsi;
1544:
1545: int crt_ddc_pin;
1546:
1547: int child_dev_num;
1548: union child_device_config *child_dev;
1549:
1550: struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1551: };
1552:
1553: enum intel_ddb_partitioning {
1554: INTEL_DDB_PART_1_2,
1555: INTEL_DDB_PART_5_6, /* IVB+ */
1556: };
1557:
1558: struct intel_wm_level {
1559: bool enable;
1560: uint32_t pri_val;
1561: uint32_t spr_val;
1562: uint32_t cur_val;
1563: uint32_t fbc_val;
1564: };
1565:
1566: struct ilk_wm_values {
1567: uint32_t wm_pipe[3];
1568: uint32_t wm_lp[3];
1569: uint32_t wm_lp_spr[3];
1570: uint32_t wm_linetime[3];
1571: bool enable_fbc_wm;
1572: enum intel_ddb_partitioning partitioning;
1573: };
1574:
1.12 riastrad 1575: struct vlv_pipe_wm {
1576: uint16_t primary;
1577: uint16_t sprite[2];
1578: uint8_t cursor;
1579: };
1580:
1581: struct vlv_sr_wm {
1582: uint16_t plane;
1583: uint8_t cursor;
1584: };
1585:
1586: struct vlv_wm_values {
1587: struct vlv_pipe_wm pipe[3];
1588: struct vlv_sr_wm sr;
1589: struct {
1590: uint8_t cursor;
1591: uint8_t sprite[2];
1592: uint8_t primary;
1593: } ddl[3];
1594: uint8_t level;
1595: bool cxsr;
1596: };
1597:
1598: struct skl_ddb_entry {
1599: uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1600: };
1601:
1602: static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1603: {
1604: return entry->end - entry->start;
1605: }
1606:
1607: static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1608: const struct skl_ddb_entry *e2)
1609: {
1610: if (e1->start == e2->start && e1->end == e2->end)
1611: return true;
1612:
1613: return false;
1614: }
1615:
1616: struct skl_ddb_allocation {
1617: struct skl_ddb_entry pipe[I915_MAX_PIPES];
1618: struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1619: struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1620: };
1621:
1622: struct skl_wm_values {
1623: bool dirty[I915_MAX_PIPES];
1624: struct skl_ddb_allocation ddb;
1625: uint32_t wm_linetime[I915_MAX_PIPES];
1626: uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1627: uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1628: };
1629:
1630: struct skl_wm_level {
1631: bool plane_en[I915_MAX_PLANES];
1632: uint16_t plane_res_b[I915_MAX_PLANES];
1633: uint8_t plane_res_l[I915_MAX_PLANES];
1634: };
1635:
1.4 riastrad 1636: /*
1637: * This struct helps tracking the state needed for runtime PM, which puts the
1638: * device in PCI D3 state. Notice that when this happens, nothing on the
1639: * graphics device works, even register access, so we don't get interrupts nor
1640: * anything else.
1641: *
1642: * Every piece of our code that needs to actually touch the hardware needs to
1643: * either call intel_runtime_pm_get or call intel_display_power_get with the
1644: * appropriate power domain.
1645: *
1646: * Our driver uses the autosuspend delay feature, which means we'll only really
1647: * suspend if we stay with zero refcount for a certain amount of time. The
1.12 riastrad 1648: * default value is currently very conservative (see intel_runtime_pm_enable), but
1.4 riastrad 1649: * it can be changed with the standard runtime PM files from sysfs.
1650: *
1651: * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1652: * goes back to false exactly before we reenable the IRQs. We use this variable
1653: * to check if someone is trying to enable/disable IRQs while they're supposed
1654: * to be disabled. This shouldn't happen and we'll print some error messages in
1.12 riastrad 1655: * case it happens.
1.4 riastrad 1656: *
1657: * For more, read the Documentation/power/runtime_pm.txt.
1658: */
1659: struct i915_runtime_pm {
1660: bool suspended;
1.12 riastrad 1661: bool irqs_enabled;
1.4 riastrad 1662: };
1663:
1664: enum intel_pipe_crc_source {
1665: INTEL_PIPE_CRC_SOURCE_NONE,
1666: INTEL_PIPE_CRC_SOURCE_PLANE1,
1667: INTEL_PIPE_CRC_SOURCE_PLANE2,
1668: INTEL_PIPE_CRC_SOURCE_PF,
1669: INTEL_PIPE_CRC_SOURCE_PIPE,
1670: /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1671: INTEL_PIPE_CRC_SOURCE_TV,
1672: INTEL_PIPE_CRC_SOURCE_DP_B,
1673: INTEL_PIPE_CRC_SOURCE_DP_C,
1674: INTEL_PIPE_CRC_SOURCE_DP_D,
1675: INTEL_PIPE_CRC_SOURCE_AUTO,
1676: INTEL_PIPE_CRC_SOURCE_MAX,
1677: };
1678:
1679: struct intel_pipe_crc_entry {
1680: uint32_t frame;
1681: uint32_t crc[5];
1682: };
1683:
1684: #define INTEL_PIPE_CRC_ENTRIES_NR 128
1685: struct intel_pipe_crc {
1686: spinlock_t lock;
1687: bool opened; /* exclusive access to the result file */
1688: struct intel_pipe_crc_entry *entries;
1689: enum intel_pipe_crc_source source;
1690: int head, tail;
1.5 riastrad 1691: #ifdef __NetBSD__
1692: drm_waitqueue_t wq;
1693: #else
1.4 riastrad 1694: wait_queue_head_t wq;
1.5 riastrad 1695: #endif
1.1 riastrad 1696: };
1697:
1.12 riastrad 1698: struct i915_frontbuffer_tracking {
1699: struct mutex lock;
1700:
1701: /*
1702: * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1703: * scheduled flips.
1704: */
1705: unsigned busy_bits;
1706: unsigned flip_bits;
1707: };
1708:
1709: struct i915_wa_reg {
1710: u32 addr;
1711: u32 value;
1712: /* bitmask representing WA bits */
1713: u32 mask;
1714: };
1715:
1716: #define I915_MAX_WA_REGS 16
1717:
1718: struct i915_workarounds {
1719: struct i915_wa_reg reg[I915_MAX_WA_REGS];
1720: u32 count;
1721: };
1722:
1723: struct i915_virtual_gpu {
1724: bool active;
1725: };
1726:
1727: struct i915_execbuffer_params {
1728: struct drm_device *dev;
1729: struct drm_file *file;
1730: uint32_t dispatch_flags;
1731: uint32_t args_batch_start_offset;
1732: uint64_t batch_obj_vm_offset;
1733: struct intel_engine_cs *ring;
1734: struct drm_i915_gem_object *batch_obj;
1735: struct intel_context *ctx;
1736: struct drm_i915_gem_request *request;
1737: };
1738:
1.5 riastrad 1739: #ifdef __NetBSD__
1740: # define __i915_iomem
1741: # define __iomem __i915_iomem
1742: #endif
1743:
1.12 riastrad 1744: struct drm_i915_private {
1.1 riastrad 1745: struct drm_device *dev;
1.12 riastrad 1746: struct kmem_cache *objects;
1747: struct kmem_cache *vmas;
1748: struct kmem_cache *requests;
1.1 riastrad 1749:
1.5 riastrad 1750: struct intel_device_info info;
1.1 riastrad 1751:
1752: int relative_constants_mode;
1753:
1.2 riastrad 1754: #ifdef __NetBSD__
1.5 riastrad 1755: bus_space_tag_t regs_bst;
1756: bus_space_handle_t regs_bsh;
1757: #endif
1.1 riastrad 1758: void __iomem *regs;
1759:
1.4 riastrad 1760: struct intel_uncore uncore;
1.1 riastrad 1761:
1.12 riastrad 1762: struct i915_virtual_gpu vgpu;
1763:
1764: struct intel_guc guc;
1.1 riastrad 1765:
1.12 riastrad 1766: struct intel_csr csr;
1767:
1768: /* Display CSR-related protection */
1769: struct mutex csr_lock;
1770:
1771: struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1.4 riastrad 1772:
1.1 riastrad 1773: /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1774: * controller on different i2c buses. */
1775: struct mutex gmbus_mutex;
1776:
1777: /**
1778: * Base address of the gmbus and gpio block.
1779: */
1780: uint32_t gpio_mmio_base;
1781:
1.12 riastrad 1782: /* MMIO base address for MIPI regs */
1783: uint32_t mipi_mmio_base;
1784:
1.5 riastrad 1785: #ifdef __NetBSD__
1786: spinlock_t gmbus_wait_lock;
1787: drm_waitqueue_t gmbus_wait_queue;
1788: #else
1.4 riastrad 1789: wait_queue_head_t gmbus_wait_queue;
1.5 riastrad 1790: #endif
1.4 riastrad 1791:
1.1 riastrad 1792: struct pci_dev *bridge_dev;
1.12 riastrad 1793: struct intel_engine_cs ring[I915_NUM_RINGS];
1794: struct drm_i915_gem_object *semaphore_obj;
1.4 riastrad 1795: uint32_t last_seqno, next_seqno;
1.1 riastrad 1796:
1.12 riastrad 1797: struct drm_dma_handle *status_page_dmah;
1.1 riastrad 1798: struct resource mch_res;
1799:
1800: /* protects the irq masks */
1801: spinlock_t irq_lock;
1802:
1.12 riastrad 1803: /* protects the mmio flip data */
1804: spinlock_t mmio_flip_lock;
1805:
1.4 riastrad 1806: bool display_irqs_enabled;
1807:
1808: /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1809: struct pm_qos_request pm_qos;
1810:
1.12 riastrad 1811: /* Sideband mailbox protection */
1812: struct mutex sb_lock;
1.1 riastrad 1813:
1814: /** Cached value of IMR to avoid reads in updating the bitfield */
1.4 riastrad 1815: union {
1816: u32 irq_mask;
1817: u32 de_irq_mask[I915_MAX_PIPES];
1818: };
1.1 riastrad 1819: u32 gt_irq_mask;
1.4 riastrad 1820: u32 pm_irq_mask;
1821: u32 pm_rps_events;
1822: u32 pipestat_irq_mask[I915_MAX_PIPES];
1.1 riastrad 1823:
1.12 riastrad 1824: struct i915_hotplug hotplug;
1.4 riastrad 1825: struct i915_fbc fbc;
1.12 riastrad 1826: struct i915_drrs drrs;
1.1 riastrad 1827: struct intel_opregion opregion;
1.4 riastrad 1828: struct intel_vbt_data vbt;
1.1 riastrad 1829:
1.12 riastrad 1830: bool preserve_bios_swizzle;
1831:
1.1 riastrad 1832: /* overlay */
1833: struct intel_overlay *overlay;
1834:
1.4 riastrad 1835: /* backlight registers and fields in struct intel_panel */
1.12 riastrad 1836: struct mutex backlight_lock;
1.1 riastrad 1837:
1.4 riastrad 1838: /* LVDS info */
1.1 riastrad 1839: bool no_aux_handshake;
1840:
1.12 riastrad 1841: /* protects panel power sequencer state */
1842: struct mutex pps_mutex;
1843:
1.1 riastrad 1844: struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1845: int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1846:
1847: unsigned int fsb_freq, mem_freq, is_ddr3;
1.12 riastrad 1848: unsigned int skl_boot_cdclk;
1849: unsigned int cdclk_freq, max_cdclk_freq;
1850: unsigned int max_dotclk_freq;
1851: unsigned int hpll_freq;
1852: unsigned int czclk_freq;
1.1 riastrad 1853:
1.4 riastrad 1854: /**
1855: * wq - Driver workqueue for GEM.
1856: *
1857: * NOTE: Work items scheduled here are not allowed to grab any modeset
1858: * locks, for otherwise the flushing done in the pageflip code will
1859: * result in deadlocks.
1860: */
1.1 riastrad 1861: struct workqueue_struct *wq;
1862:
1863: /* Display functions */
1864: struct drm_i915_display_funcs display;
1865:
1866: /* PCH chipset type */
1867: enum intel_pch pch_type;
1868: unsigned short pch_id;
1869:
1870: unsigned long quirks;
1871:
1.4 riastrad 1872: enum modeset_restore modeset_restore;
1873: struct mutex modeset_restore_lock;
1.1 riastrad 1874:
1.4 riastrad 1875: struct list_head vm_list; /* Global list of all address spaces */
1.12 riastrad 1876: struct i915_gtt gtt; /* VM representing the global address space */
1.1 riastrad 1877:
1.4 riastrad 1878: struct i915_gem_mm mm;
1.12 riastrad 1879: DECLARE_HASHTABLE(mm_structs, 7);
1880: struct mutex mm_lock;
1.1 riastrad 1881:
1882: /* Kernel Modesetting */
1883:
1884: struct sdvo_device_mapping sdvo_mappings[2];
1885:
1.4 riastrad 1886: struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1887: struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1.2 riastrad 1888: #ifdef __NetBSD__
1889: /* XXX The locking scheme looks broken. This mutex is a stop-gap. */
1.3 riastrad 1890: struct spinlock pending_flip_lock;
1.2 riastrad 1891: drm_waitqueue_t pending_flip_queue;
1892: #else
1.1 riastrad 1893: wait_queue_head_t pending_flip_queue;
1.2 riastrad 1894: #endif
1.1 riastrad 1895:
1.4 riastrad 1896: #ifdef CONFIG_DEBUG_FS
1897: struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1898: #endif
1899:
1900: int num_shared_dpll;
1901: struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1902: int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1.1 riastrad 1903:
1.12 riastrad 1904: struct i915_workarounds workarounds;
1905:
1.1 riastrad 1906: /* Reclocking support */
1907: bool render_reclock_avail;
1.12 riastrad 1908:
1909: struct i915_frontbuffer_tracking fb_tracking;
1910:
1.1 riastrad 1911: u16 orig_clock;
1912:
1913: bool mchbar_need_disable;
1914:
1915: struct intel_l3_parity l3_parity;
1916:
1.4 riastrad 1917: /* Cannot be determined by PCIID. You must always read a register. */
1918: size_t ellc_size;
1919:
1.1 riastrad 1920: /* gen6+ rps state */
1921: struct intel_gen6_power_mgmt rps;
1922:
1923: /* ilk-only ips/rps state. Everything in here is protected by the global
1924: * mchdev_lock in intel_pm.c */
1925: struct intel_ilk_power_mgmt ips;
1926:
1.4 riastrad 1927: struct i915_power_domains power_domains;
1.1 riastrad 1928:
1.4 riastrad 1929: struct i915_psr psr;
1930:
1931: struct i915_gpu_error gpu_error;
1.1 riastrad 1932:
1.4 riastrad 1933: struct drm_i915_gem_object *vlv_pctx;
1.1 riastrad 1934:
1.12 riastrad 1935: #ifdef CONFIG_DRM_FBDEV_EMULATION
1.1 riastrad 1936: /* list of fbdev register on this device */
1937: struct intel_fbdev *fbdev;
1.12 riastrad 1938: struct work_struct fbdev_suspend_work;
1.4 riastrad 1939: #endif
1.1 riastrad 1940:
1941: struct drm_property *broadcast_rgb_property;
1942: struct drm_property *force_audio_property;
1943:
1.12 riastrad 1944: /* hda/i915 audio component */
1945: struct i915_audio_component *audio_component;
1946: bool audio_component_registered;
1947: /**
1948: * av_mutex - mutex for audio/video sync
1949: *
1950: */
1951: struct mutex av_mutex;
1952:
1.1 riastrad 1953: uint32_t hw_context_size;
1.4 riastrad 1954: struct list_head context_list;
1.1 riastrad 1955:
1.4 riastrad 1956: u32 fdi_rx_config;
1.1 riastrad 1957:
1.12 riastrad 1958: u32 chv_phy_control;
1959:
1.4 riastrad 1960: u32 suspend_count;
1.1 riastrad 1961: struct i915_suspend_saved_registers regfile;
1.12 riastrad 1962: struct vlv_s0ix_state vlv_s0ix_state;
1.1 riastrad 1963:
1.4 riastrad 1964: struct {
1965: /*
1966: * Raw watermark latency values:
1967: * in 0.1us units for WM0,
1968: * in 0.5us units for WM1+.
1969: */
1970: /* primary */
1971: uint16_t pri_latency[5];
1972: /* sprite */
1973: uint16_t spr_latency[5];
1974: /* cursor */
1975: uint16_t cur_latency[5];
1.12 riastrad 1976: /*
1977: * Raw watermark memory latency values
1978: * for SKL for all 8 levels
1979: * in 1us units.
1980: */
1981: uint16_t skl_latency[8];
1982:
1983: /*
1984: * The skl_wm_values structure is a bit too big for stack
1985: * allocation, so we keep the staging struct where we store
1986: * intermediate results here instead.
1987: */
1988: struct skl_wm_values skl_results;
1.4 riastrad 1989:
1990: /* current hardware state */
1.12 riastrad 1991: union {
1992: struct ilk_wm_values hw;
1993: struct skl_wm_values skl_hw;
1994: struct vlv_wm_values vlv;
1995: };
1996:
1997: uint8_t max_level;
1.4 riastrad 1998: } wm;
1999:
2000: struct i915_runtime_pm pm;
2001:
1.12 riastrad 2002: /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2003: struct {
2004: int (*execbuf_submit)(struct i915_execbuffer_params *params,
2005: struct drm_i915_gem_execbuffer2 *args,
2006: struct list_head *vmas);
2007: int (*init_rings)(struct drm_device *dev);
2008: void (*cleanup_ring)(struct intel_engine_cs *ring);
2009: void (*stop_ring)(struct intel_engine_cs *ring);
2010: } gt;
2011:
2012: bool edp_low_vswing;
2013:
2014: /* perform PHY state sanity checks? */
2015: bool chv_phy_assert[2];
2016:
2017: /*
2018: * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2019: * will be rejected. Instead look for a better place.
2020: */
2021: };
1.1 riastrad 2022:
1.5 riastrad 2023: #ifdef __NetBSD__
2024: # undef __iomem
2025: # undef __i915_iomem
2026: #endif
2027:
1.4 riastrad 2028: static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2029: {
2030: return dev->dev_private;
2031: }
2032:
1.14 riastrad 2033: #ifndef __NetBSD__
1.12 riastrad 2034: static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2035: {
2036: return to_i915(dev_get_drvdata(dev));
2037: }
1.14 riastrad 2038: #endif
1.12 riastrad 2039:
2040: static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2041: {
2042: return container_of(guc, struct drm_i915_private, guc);
2043: }
2044:
1.1 riastrad 2045: /* Iterate over initialised rings */
2046: #define for_each_ring(ring__, dev_priv__, i__) \
2047: for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2048: if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
2049:
2050: enum hdmi_force_audio {
2051: HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2052: HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2053: HDMI_AUDIO_AUTO, /* trust EDID */
2054: HDMI_AUDIO_ON, /* force turn on HDMI audio */
2055: };
2056:
1.4 riastrad 2057: #define I915_GTT_OFFSET_NONE ((u32)-1)
1.1 riastrad 2058:
2059: struct drm_i915_gem_object_ops {
2060: /* Interface between the GEM object and its backing storage.
2061: * get_pages() is called once prior to the use of the associated set
2062: * of pages before to binding them into the GTT, and put_pages() is
2063: * called after we no longer need them. As we expect there to be
2064: * associated cost with migrating pages between the backing storage
2065: * and making them available for the GPU (e.g. clflush), we may hold
2066: * onto the pages after they are no longer referenced by the GPU
2067: * in case they may be used again shortly (for example migrating the
2068: * pages to a different memory domain within the GTT). put_pages()
2069: * will therefore most likely be called when the object itself is
2070: * being released or under memory pressure (where we attempt to
2071: * reap pages for the shrinker).
2072: */
2073: int (*get_pages)(struct drm_i915_gem_object *);
2074: void (*put_pages)(struct drm_i915_gem_object *);
1.12 riastrad 2075: int (*dmabuf_export)(struct drm_i915_gem_object *);
2076: void (*release)(struct drm_i915_gem_object *);
1.1 riastrad 2077: };
2078:
1.12 riastrad 2079: /*
2080: * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2081: * considered to be the frontbuffer for the given plane interface-wise. This
2082: * doesn't mean that the hw necessarily already scans it out, but that any
2083: * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2084: *
2085: * We have one bit per pipe and per scanout plane type.
2086: */
2087: #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2088: #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2089: #define INTEL_FRONTBUFFER_BITS \
2090: (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2091: #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2092: (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2093: #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2094: (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2095: #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2096: (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2097: #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2098: (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2099: #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2100: (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2101:
1.1 riastrad 2102: struct drm_i915_gem_object {
2103: struct drm_gem_object base;
2104:
2105: const struct drm_i915_gem_object_ops *ops;
2106:
1.4 riastrad 2107: /** List of VMAs backed by this object */
2108: struct list_head vma_list;
2109:
2110: /** Stolen memory for this object, instead of being backed by shmem. */
2111: struct drm_mm_node *stolen;
2112: struct list_head global_list;
1.1 riastrad 2113:
1.12 riastrad 2114: struct list_head ring_list[I915_NUM_RINGS];
1.4 riastrad 2115: /** Used in execbuf to temporarily hold a ref */
2116: struct list_head obj_exec_link;
1.1 riastrad 2117:
1.12 riastrad 2118: struct list_head batch_pool_link;
2119:
1.1 riastrad 2120: /**
2121: * This is set if the object is on the active lists (has pending
2122: * rendering and so a non-zero seqno), and is not set if it i s on
2123: * inactive (ready to be unbound) list.
2124: */
1.12 riastrad 2125: unsigned int active:I915_NUM_RINGS;
1.1 riastrad 2126:
2127: /**
2128: * This is set if the object has been written to since last bound
2129: * to the GTT
2130: */
2131: unsigned int dirty:1;
2132:
2133: /**
2134: * Fence register bits (if any) for this object. Will be set
2135: * as needed when mapped into the GTT.
2136: * Protected by dev->struct_mutex.
2137: */
2138: signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2139:
2140: /**
2141: * Advice: are the backing pages purgeable?
2142: */
2143: unsigned int madv:2;
2144:
2145: /**
2146: * Current tiling mode for the object.
2147: */
2148: unsigned int tiling_mode:2;
2149: /**
2150: * Whether the tiling parameters for the currently associated fence
2151: * register have changed. Note that for the purposes of tracking
2152: * tiling changes we also treat the unfenced register, the register
2153: * slot that the object occupies whilst it executes a fenced
2154: * command (such as BLT on gen2/3), as a "fence".
2155: */
2156: unsigned int fence_dirty:1;
2157:
2158: /**
2159: * Is the object at the current location in the gtt mappable and
2160: * fenceable? Used to avoid costly recalculations.
2161: */
2162: unsigned int map_and_fenceable:1;
2163:
2164: /**
2165: * Whether the current gtt mapping needs to be mappable (and isn't just
2166: * mappable by accident). Track pin and fault separate for a more
2167: * accurate mappable working set.
2168: */
2169: unsigned int fault_mappable:1;
2170:
2171: /*
1.12 riastrad 2172: * Is the object to be mapped as read-only to the GPU
2173: * Only honoured if hardware has relevant pte bit
1.1 riastrad 2174: */
1.12 riastrad 2175: unsigned long gt_ro:1;
2176: unsigned int cache_level:3;
2177: unsigned int cache_dirty:1;
1.1 riastrad 2178:
1.12 riastrad 2179: unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1.1 riastrad 2180:
1.12 riastrad 2181: unsigned int pin_display;
1.1 riastrad 2182:
1.2 riastrad 2183: #ifdef __NetBSD__
1.18 riastrad 2184: struct pglist pageq;
2185: bus_dmamap_t pages; /* expedient misnomer */
1.2 riastrad 2186: #else
1.1 riastrad 2187: struct sg_table *pages;
1.2 riastrad 2188: #endif
1.1 riastrad 2189: int pages_pin_count;
1.12 riastrad 2190: #ifndef __NetBSD__
2191: struct get_page {
2192: struct scatterlist *sg;
2193: int last;
2194: } get_page;
2195: #endif
1.1 riastrad 2196:
2197: /* prime dma-buf support */
2198: void *dma_buf_vmapping;
2199: int vmapping_count;
2200:
1.12 riastrad 2201: /** Breadcrumb of last rendering to the buffer.
2202: * There can only be one writer, but we allow for multiple readers.
2203: * If there is a writer that necessarily implies that all other
2204: * read requests are complete - but we may only be lazily clearing
2205: * the read requests. A read request is naturally the most recent
2206: * request on a ring, so we may have two different write and read
2207: * requests on one ring where the write request is older than the
2208: * read request. This allows for the CPU to read from an active
2209: * buffer by only waiting for the write to complete.
2210: * */
2211: struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2212: struct drm_i915_gem_request *last_write_req;
1.1 riastrad 2213: /** Breadcrumb of last fenced GPU access to the buffer. */
1.12 riastrad 2214: struct drm_i915_gem_request *last_fenced_req;
1.1 riastrad 2215:
2216: /** Current tiling stride for the object, if it's tiled. */
2217: uint32_t stride;
2218:
1.4 riastrad 2219: /** References from framebuffers, locks out tiling changes. */
2220: unsigned long framebuffer_references;
2221:
1.1 riastrad 2222: /** Record of address bit 17 of each page at last unbind. */
2223: unsigned long *bit_17;
2224:
1.12 riastrad 2225: struct i915_gem_userptr {
2226: uintptr_t ptr;
2227: unsigned read_only :1;
2228: unsigned workers :4;
2229: #define I915_GEM_USERPTR_MAX_WORKERS 15
2230:
2231: struct i915_mm_struct *mm;
2232: struct i915_mmu_object *mmu_object;
2233: struct work_struct *work;
2234: } userptr;
1.1 riastrad 2235:
1.12 riastrad 2236: /** for phys allocated objects */
2237: struct drm_dma_handle *phys_handle;
1.1 riastrad 2238: };
1.12 riastrad 2239: #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1.1 riastrad 2240:
1.12 riastrad 2241: void i915_gem_track_fb(struct drm_i915_gem_object *old,
2242: struct drm_i915_gem_object *new,
2243: unsigned frontbuffer_bits);
1.1 riastrad 2244:
2245: /**
2246: * Request queue structure.
2247: *
2248: * The request queue allows us to note sequence numbers that have been emitted
2249: * and may be associated with active buffers to be retired.
2250: *
1.12 riastrad 2251: * By keeping this list, we can avoid having to do questionable sequence
2252: * number comparisons on buffer last_read|write_seqno. It also allows an
2253: * emission time to be associated with the request for tracking how far ahead
2254: * of the GPU the submission is.
2255: *
2256: * The requests are reference counted, so upon creation they should have an
2257: * initial reference taken using kref_init
1.1 riastrad 2258: */
2259: struct drm_i915_gem_request {
1.12 riastrad 2260: struct kref ref;
2261:
1.1 riastrad 2262: /** On Which ring this request was generated */
1.12 riastrad 2263: struct drm_i915_private *i915;
2264: struct intel_engine_cs *ring;
1.1 riastrad 2265:
1.12 riastrad 2266: /** GEM sequence number associated with the previous request,
2267: * when the HWS breadcrumb is equal to this the GPU is processing
2268: * this request.
2269: */
2270: u32 previous_seqno;
2271:
2272: /** GEM sequence number associated with this request,
2273: * when the HWS breadcrumb is equal or greater than this the GPU
2274: * has finished processing this request.
2275: */
2276: u32 seqno;
1.1 riastrad 2277:
1.4 riastrad 2278: /** Position in the ringbuffer of the start of the request */
2279: u32 head;
2280:
1.12 riastrad 2281: /**
2282: * Position in the ringbuffer of the start of the postfix.
2283: * This is required to calculate the maximum available ringbuffer
2284: * space without overwriting the postfix.
2285: */
2286: u32 postfix;
2287:
2288: /** Position in the ringbuffer of the end of the whole request */
1.1 riastrad 2289: u32 tail;
2290:
1.12 riastrad 2291: /**
2292: * Context and ring buffer related to this request
2293: * Contexts are refcounted, so when this request is associated with a
2294: * context, we must increment the context's refcount, to guarantee that
2295: * it persists while any request is linked to it. Requests themselves
2296: * are also refcounted, so the request will only be freed when the last
2297: * reference to it is dismissed, and the code in
2298: * i915_gem_request_free() will then decrement the refcount on the
2299: * context.
2300: */
2301: struct intel_context *ctx;
2302: struct intel_ringbuffer *ringbuf;
1.4 riastrad 2303:
1.12 riastrad 2304: /** Batch buffer related to this request if any (used for
2305: error state dump only) */
1.4 riastrad 2306: struct drm_i915_gem_object *batch_obj;
2307:
1.1 riastrad 2308: /** Time at which this request was emitted, in jiffies. */
2309: unsigned long emitted_jiffies;
2310:
2311: /** global list entry for this request */
2312: struct list_head list;
2313:
2314: struct drm_i915_file_private *file_priv;
2315: /** file_priv list entry for this request */
2316: struct list_head client_list;
1.12 riastrad 2317:
2318: /** process identifier submitting this request */
2319: struct pid *pid;
2320:
2321: /**
2322: * The ELSP only accepts two elements at a time, so we queue
2323: * context/tail pairs on a given queue (ring->execlist_queue) until the
2324: * hardware is available. The queue serves a double purpose: we also use
2325: * it to keep track of the up to 2 contexts currently in the hardware
2326: * (usually one in execution and the other queued up by the GPU): We
2327: * only remove elements from the head of the queue when the hardware
2328: * informs us that an element has been completed.
2329: *
2330: * All accesses to the queue are mediated by a spinlock
2331: * (ring->execlist_lock).
2332: */
2333:
2334: /** Execlist link in the submission queue.*/
2335: struct list_head execlist_link;
2336:
2337: /** Execlists no. of times this request has been sent to the ELSP */
2338: int elsp_submitted;
2339:
1.1 riastrad 2340: };
2341:
1.12 riastrad 2342: int i915_gem_request_alloc(struct intel_engine_cs *ring,
2343: struct intel_context *ctx,
2344: struct drm_i915_gem_request **req_out);
2345: void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2346: void i915_gem_request_free(struct kref *req_ref);
2347: int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2348: struct drm_file *file);
2349:
2350: static inline uint32_t
2351: i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2352: {
2353: return req ? req->seqno : 0;
2354: }
2355:
2356: static inline struct intel_engine_cs *
2357: i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2358: {
2359: return req ? req->ring : NULL;
2360: }
2361:
2362: static inline struct drm_i915_gem_request *
2363: i915_gem_request_reference(struct drm_i915_gem_request *req)
2364: {
2365: if (req)
2366: kref_get(&req->ref);
2367: return req;
2368: }
2369:
2370: static inline void
2371: i915_gem_request_unreference(struct drm_i915_gem_request *req)
2372: {
2373: WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2374: kref_put(&req->ref, i915_gem_request_free);
2375: }
2376:
2377: static inline void
2378: i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2379: {
2380: struct drm_device *dev;
2381:
2382: if (!req)
2383: return;
2384:
2385: dev = req->ring->dev;
2386: if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2387: mutex_unlock(&dev->struct_mutex);
2388: }
2389:
2390: static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2391: struct drm_i915_gem_request *src)
2392: {
2393: if (src)
2394: i915_gem_request_reference(src);
2395:
2396: if (*pdst)
2397: i915_gem_request_unreference(*pdst);
1.4 riastrad 2398:
1.12 riastrad 2399: *pdst = src;
2400: }
1.4 riastrad 2401:
1.12 riastrad 2402: /*
2403: * XXX: i915_gem_request_completed should be here but currently needs the
2404: * definition of i915_seqno_passed() which is below. It will be moved in
2405: * a later patch when the call to i915_seqno_passed() is obsoleted...
2406: */
1.4 riastrad 2407:
2408: /*
2409: * A command that requires special handling by the command parser.
2410: */
2411: struct drm_i915_cmd_descriptor {
2412: /*
2413: * Flags describing how the command parser processes the command.
2414: *
2415: * CMD_DESC_FIXED: The command has a fixed length if this is set,
2416: * a length mask if not set
2417: * CMD_DESC_SKIP: The command is allowed but does not follow the
2418: * standard length encoding for the opcode range in
2419: * which it falls
2420: * CMD_DESC_REJECT: The command is never allowed
2421: * CMD_DESC_REGISTER: The command should be checked against the
2422: * register whitelist for the appropriate ring
2423: * CMD_DESC_MASTER: The command is allowed if the submitting process
2424: * is the DRM master
2425: */
2426: u32 flags;
2427: #define CMD_DESC_FIXED (1<<0)
2428: #define CMD_DESC_SKIP (1<<1)
2429: #define CMD_DESC_REJECT (1<<2)
2430: #define CMD_DESC_REGISTER (1<<3)
2431: #define CMD_DESC_BITMASK (1<<4)
2432: #define CMD_DESC_MASTER (1<<5)
2433:
2434: /*
2435: * The command's unique identification bits and the bitmask to get them.
2436: * This isn't strictly the opcode field as defined in the spec and may
2437: * also include type, subtype, and/or subop fields.
2438: */
2439: struct {
2440: u32 value;
2441: u32 mask;
2442: } cmd;
2443:
2444: /*
2445: * The command's length. The command is either fixed length (i.e. does
2446: * not include a length field) or has a length field mask. The flag
2447: * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2448: * a length mask. All command entries in a command table must include
2449: * length information.
2450: */
2451: union {
2452: u32 fixed;
2453: u32 mask;
2454: } length;
2455:
2456: /*
2457: * Describes where to find a register address in the command to check
2458: * against the ring's register whitelist. Only valid if flags has the
2459: * CMD_DESC_REGISTER bit set.
1.12 riastrad 2460: *
2461: * A non-zero step value implies that the command may access multiple
2462: * registers in sequence (e.g. LRI), in that case step gives the
2463: * distance in dwords between individual offset fields.
1.4 riastrad 2464: */
2465: struct {
2466: u32 offset;
2467: u32 mask;
1.12 riastrad 2468: u32 step;
1.4 riastrad 2469: } reg;
2470:
2471: #define MAX_CMD_DESC_BITMASKS 3
2472: /*
2473: * Describes command checks where a particular dword is masked and
2474: * compared against an expected value. If the command does not match
2475: * the expected value, the parser rejects it. Only valid if flags has
2476: * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2477: * are valid.
1.12 riastrad 2478: *
2479: * If the check specifies a non-zero condition_mask then the parser
2480: * only performs the check when the bits specified by condition_mask
2481: * are non-zero.
1.4 riastrad 2482: */
2483: struct {
2484: u32 offset;
2485: u32 mask;
2486: u32 expected;
1.12 riastrad 2487: u32 condition_offset;
2488: u32 condition_mask;
1.4 riastrad 2489: } bits[MAX_CMD_DESC_BITMASKS];
2490: };
2491:
2492: /*
2493: * A table of commands requiring special handling by the command parser.
2494: *
2495: * Each ring has an array of tables. Each table consists of an array of command
2496: * descriptors, which must be sorted with command opcodes in ascending order.
2497: */
2498: struct drm_i915_cmd_table {
2499: const struct drm_i915_cmd_descriptor *table;
2500: int count;
1.1 riastrad 2501: };
2502:
1.12 riastrad 2503: /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2504: #define __I915__(p) ({ \
2505: struct drm_i915_private *__p; \
2506: if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2507: __p = (struct drm_i915_private *)p; \
2508: else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2509: __p = to_i915((struct drm_device *)p); \
2510: else \
2511: BUILD_BUG(); \
2512: __p; \
2513: })
2514: #define INTEL_INFO(p) (&__I915__(p)->info)
2515: #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2516: #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
1.1 riastrad 2517:
1.12 riastrad 2518: #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2519: #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
1.1 riastrad 2520: #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1.12 riastrad 2521: #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
1.1 riastrad 2522: #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1.12 riastrad 2523: #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2524: #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
1.1 riastrad 2525: #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2526: #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2527: #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1.12 riastrad 2528: #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
1.1 riastrad 2529: #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1.12 riastrad 2530: #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2531: #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
1.1 riastrad 2532: #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2533: #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1.12 riastrad 2534: #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
1.1 riastrad 2535: #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1.12 riastrad 2536: #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2537: INTEL_DEVID(dev) == 0x0152 || \
2538: INTEL_DEVID(dev) == 0x015a)
1.1 riastrad 2539: #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1.12 riastrad 2540: #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1.1 riastrad 2541: #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1.12 riastrad 2542: #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2543: #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2544: #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
1.1 riastrad 2545: #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1.4 riastrad 2546: #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1.12 riastrad 2547: (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
1.4 riastrad 2548: #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1.12 riastrad 2549: ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2550: (INTEL_DEVID(dev) & 0xf) == 0xb || \
2551: (INTEL_DEVID(dev) & 0xf) == 0xe))
2552: /* ULX machines are also considered ULT. */
2553: #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2554: (INTEL_DEVID(dev) & 0xf) == 0xe)
2555: #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2556: (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
1.4 riastrad 2557: #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1.12 riastrad 2558: (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
1.4 riastrad 2559: #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1.12 riastrad 2560: (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
1.4 riastrad 2561: /* ULX machines are also considered ULT. */
1.12 riastrad 2562: #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2563: INTEL_DEVID(dev) == 0x0A1E)
2564: #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2565: INTEL_DEVID(dev) == 0x1913 || \
2566: INTEL_DEVID(dev) == 0x1916 || \
2567: INTEL_DEVID(dev) == 0x1921 || \
2568: INTEL_DEVID(dev) == 0x1926)
2569: #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2570: INTEL_DEVID(dev) == 0x1915 || \
2571: INTEL_DEVID(dev) == 0x191E)
2572: #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2573: (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2574: #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2575: (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2576:
1.4 riastrad 2577: #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1.1 riastrad 2578:
1.12 riastrad 2579: #define SKL_REVID_A0 (0x0)
2580: #define SKL_REVID_B0 (0x1)
2581: #define SKL_REVID_C0 (0x2)
2582: #define SKL_REVID_D0 (0x3)
2583: #define SKL_REVID_E0 (0x4)
2584: #define SKL_REVID_F0 (0x5)
2585:
2586: #define BXT_REVID_A0 (0x0)
2587: #define BXT_REVID_B0 (0x3)
2588: #define BXT_REVID_C0 (0x9)
2589:
1.1 riastrad 2590: /*
2591: * The genX designation typically refers to the render engine, so render
2592: * capability related checks should use IS_GEN, while display and other checks
2593: * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2594: * chips, etc.).
2595: */
2596: #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2597: #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2598: #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2599: #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2600: #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2601: #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1.4 riastrad 2602: #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1.12 riastrad 2603: #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
1.1 riastrad 2604:
1.4 riastrad 2605: #define RENDER_RING (1<<RCS)
2606: #define BSD_RING (1<<VCS)
2607: #define BLT_RING (1<<BCS)
2608: #define VEBOX_RING (1<<VECS)
1.12 riastrad 2609: #define BSD2_RING (1<<VCS2)
2610: #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2611: #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2612: #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2613: #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2614: #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2615: #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2616: __I915__(dev)->ellc_size)
1.1 riastrad 2617: #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2618:
2619: #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1.12 riastrad 2620: #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2621: #define USES_PPGTT(dev) (i915.enable_ppgtt)
2622: #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2623: #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
1.1 riastrad 2624:
2625: #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2626: #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2627:
2628: /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2629: #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1.4 riastrad 2630: /*
2631: * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2632: * even when in MSI mode. This results in spurious interrupt warnings if the
2633: * legacy irq no. is shared with another device. The kernel then disables that
2634: * interrupt source and so prevents the other device from working properly.
2635: */
2636: #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2637: #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1.1 riastrad 2638:
2639: /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2640: * rows, which changed the alignment requirements and fence programming.
2641: */
2642: #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2643: IS_I915GM(dev)))
2644: #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2645: #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2646:
2647: #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2648: #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1.4 riastrad 2649: #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2650:
1.12 riastrad 2651: #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2652:
2653: #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2654: INTEL_INFO(dev)->gen >= 9)
1.1 riastrad 2655:
1.4 riastrad 2656: #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2657: #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1.12 riastrad 2658: #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2659: IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2660: IS_SKYLAKE(dev))
2661: #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2662: IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2663: IS_SKYLAKE(dev))
2664: #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2665: #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2666:
2667: #define HAS_CSR(dev) (IS_GEN9(dev))
2668:
2669: #define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
2670: #define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
2671:
2672: #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2673: INTEL_INFO(dev)->gen >= 8)
2674:
2675: #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2676: !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
1.1 riastrad 2677:
2678: #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2679: #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2680: #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2681: #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2682: #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2683: #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1.12 riastrad 2684: #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2685: #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2686: #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2687: #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
1.1 riastrad 2688:
1.12 riastrad 2689: #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2690: #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
1.1 riastrad 2691: #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1.12 riastrad 2692: #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
1.1 riastrad 2693: #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2694: #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1.4 riastrad 2695: #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1.1 riastrad 2696: #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2697:
1.12 riastrad 2698: #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2699:
1.4 riastrad 2700: /* DPF == dynamic parity feature */
2701: #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2702: #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1.1 riastrad 2703:
2704: #define GT_FREQUENCY_MULTIPLIER 50
1.12 riastrad 2705: #define GEN9_FREQ_SCALER 3
1.1 riastrad 2706:
2707: #include "i915_trace.h"
2708:
1.4 riastrad 2709: extern const struct drm_ioctl_desc i915_ioctls[];
1.1 riastrad 2710: extern int i915_max_ioctl;
2711:
1.12 riastrad 2712: extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2713: extern int i915_resume_switcheroo(struct drm_device *dev);
1.1 riastrad 2714:
1.6 riastrad 2715: extern int i915_drm_freeze(struct drm_device *dev);
2716: extern int i915_drm_thaw_early(struct drm_device *dev);
2717: extern int i915_drm_thaw(struct drm_device *dev);
2718:
1.4 riastrad 2719: /* i915_params.c */
2720: struct i915_params {
2721: int modeset;
2722: int panel_ignore_lid;
2723: int semaphores;
2724: int lvds_channel_mode;
2725: int panel_use_ssc;
2726: int vbt_sdvo_panel_type;
2727: int enable_rc6;
2728: int enable_fbc;
2729: int enable_ppgtt;
1.12 riastrad 2730: int enable_execlists;
1.4 riastrad 2731: int enable_psr;
2732: unsigned int preliminary_hw_support;
2733: int disable_power_well;
2734: int enable_ips;
2735: int invert_brightness;
2736: int enable_cmd_parser;
2737: /* leave bools at the end to not create holes */
2738: bool enable_hangcheck;
2739: bool fastboot;
2740: bool prefault_disable;
1.12 riastrad 2741: bool load_detect_test;
1.4 riastrad 2742: bool reset;
2743: bool disable_display;
1.12 riastrad 2744: bool disable_vtd_wa;
2745: bool enable_guc_submission;
2746: int guc_log_level;
2747: int use_mmio_flip;
2748: int mmio_debug;
2749: bool verbose_state_checks;
2750: bool nuclear_pageflip;
2751: int edp_vswing;
1.4 riastrad 2752: };
2753: extern struct i915_params i915 __read_mostly;
2754:
1.1 riastrad 2755: /* i915_dma.c */
2756: extern int i915_driver_load(struct drm_device *, unsigned long flags);
2757: extern int i915_driver_unload(struct drm_device *);
1.12 riastrad 2758: extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
1.1 riastrad 2759: extern void i915_driver_lastclose(struct drm_device * dev);
2760: extern void i915_driver_preclose(struct drm_device *dev,
1.12 riastrad 2761: struct drm_file *file);
1.1 riastrad 2762: extern void i915_driver_postclose(struct drm_device *dev,
1.12 riastrad 2763: struct drm_file *file);
1.1 riastrad 2764: #ifdef CONFIG_COMPAT
2765: extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2766: unsigned long arg);
2767: #endif
2768: extern int intel_gpu_reset(struct drm_device *dev);
1.12 riastrad 2769: extern bool intel_has_gpu_reset(struct drm_device *dev);
1.1 riastrad 2770: extern int i915_reset(struct drm_device *dev);
2771: extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2772: extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2773: extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2774: extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1.12 riastrad 2775: int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2776: void i915_firmware_load_error_print(const char *fw_path, int err);
1.1 riastrad 2777:
1.12 riastrad 2778: /* intel_hotplug.c */
2779: void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2780: void intel_hpd_init(struct drm_i915_private *dev_priv);
2781: void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2782: void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2783: bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
1.1 riastrad 2784:
2785: /* i915_irq.c */
1.4 riastrad 2786: void i915_queue_hangcheck(struct drm_device *dev);
2787: __printf(3, 4)
2788: void i915_handle_error(struct drm_device *dev, bool wedged,
2789: const char *fmt, ...);
1.1 riastrad 2790:
1.12 riastrad 2791: extern void intel_irq_init(struct drm_i915_private *dev_priv);
2792: int intel_irq_install(struct drm_i915_private *dev_priv);
2793: void intel_irq_uninstall(struct drm_i915_private *dev_priv);
1.1 riastrad 2794:
1.4 riastrad 2795: extern void intel_uncore_sanitize(struct drm_device *dev);
1.12 riastrad 2796: extern void intel_uncore_early_sanitize(struct drm_device *dev,
2797: bool restore_forcewake);
1.4 riastrad 2798: extern void intel_uncore_init(struct drm_device *dev);
2799: extern void intel_uncore_check_errors(struct drm_device *dev);
2800: extern void intel_uncore_fini(struct drm_device *dev);
1.6 riastrad 2801: extern void intel_uncore_destroy(struct drm_device *dev);
1.12 riastrad 2802: extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2803: const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2804: void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2805: enum forcewake_domains domains);
2806: void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2807: enum forcewake_domains domains);
2808: /* Like above but the caller must manage the uncore.lock itself.
2809: * Must be used with I915_READ_FW and friends.
2810: */
2811: void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2812: enum forcewake_domains domains);
2813: void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2814: enum forcewake_domains domains);
2815: void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2816: static inline bool intel_vgpu_active(struct drm_device *dev)
2817: {
2818: return to_i915(dev)->vgpu.active;
2819: }
1.1 riastrad 2820:
2821: void
1.9 matt 2822: i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
1.4 riastrad 2823: u32 status_mask);
1.1 riastrad 2824:
2825: void
1.9 matt 2826: i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
1.4 riastrad 2827: u32 status_mask);
1.1 riastrad 2828:
1.4 riastrad 2829: void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2830: void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
1.12 riastrad 2831: void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2832: uint32_t mask,
2833: uint32_t bits);
2834: void
2835: ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2836: void
2837: ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2838: void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2839: uint32_t interrupt_mask,
2840: uint32_t enabled_irq_mask);
2841: #define ibx_enable_display_interrupt(dev_priv, bits) \
2842: ibx_display_interrupt_update((dev_priv), (bits), (bits))
2843: #define ibx_disable_display_interrupt(dev_priv, bits) \
2844: ibx_display_interrupt_update((dev_priv), (bits), 0)
1.1 riastrad 2845:
2846: /* i915_gem.c */
2847: int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2848: struct drm_file *file_priv);
2849: int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2850: struct drm_file *file_priv);
2851: int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2852: struct drm_file *file_priv);
2853: int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2854: struct drm_file *file_priv);
2855: int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2856: struct drm_file *file_priv);
2857: int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2858: struct drm_file *file_priv);
2859: int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2860: struct drm_file *file_priv);
1.12 riastrad 2861: void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2862: struct drm_i915_gem_request *req);
2863: void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2864: int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2865: struct drm_i915_gem_execbuffer2 *args,
2866: struct list_head *vmas);
1.1 riastrad 2867: int i915_gem_execbuffer(struct drm_device *dev, void *data,
2868: struct drm_file *file_priv);
2869: int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2870: struct drm_file *file_priv);
2871: int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2872: struct drm_file *file_priv);
2873: int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2874: struct drm_file *file);
2875: int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2876: struct drm_file *file);
2877: int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2878: struct drm_file *file_priv);
2879: int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2880: struct drm_file *file_priv);
2881: int i915_gem_set_tiling(struct drm_device *dev, void *data,
2882: struct drm_file *file_priv);
2883: int i915_gem_get_tiling(struct drm_device *dev, void *data,
2884: struct drm_file *file_priv);
1.12 riastrad 2885: int i915_gem_init_userptr(struct drm_device *dev);
2886: int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2887: struct drm_file *file);
1.1 riastrad 2888: int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2889: struct drm_file *file_priv);
2890: int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2891: struct drm_file *file_priv);
2892: void i915_gem_load(struct drm_device *dev);
1.4 riastrad 2893: void *i915_gem_object_alloc(struct drm_device *dev);
2894: void i915_gem_object_free(struct drm_i915_gem_object *obj);
1.1 riastrad 2895: void i915_gem_object_init(struct drm_i915_gem_object *obj,
2896: const struct drm_i915_gem_object_ops *ops);
2897: struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2898: size_t size);
1.12 riastrad 2899: struct drm_i915_gem_object *i915_gem_object_create_from_data(
2900: struct drm_device *dev, const void *data, size_t size);
1.1 riastrad 2901: void i915_gem_free_object(struct drm_gem_object *obj);
1.4 riastrad 2902: void i915_gem_vma_destroy(struct i915_vma *vma);
2903:
1.12 riastrad 2904: /* Flags used by pin/bind&friends. */
2905: #define PIN_MAPPABLE (1<<0)
2906: #define PIN_NONBLOCK (1<<1)
2907: #define PIN_GLOBAL (1<<2)
2908: #define PIN_OFFSET_BIAS (1<<3)
2909: #define PIN_USER (1<<4)
2910: #define PIN_UPDATE (1<<5)
2911: #define PIN_ZONE_4G (1<<6)
2912: #define PIN_HIGH (1<<7)
1.4 riastrad 2913: #define PIN_OFFSET_MASK (~4095)
1.12 riastrad 2914: int __must_check
2915: i915_gem_object_pin(struct drm_i915_gem_object *obj,
2916: struct i915_address_space *vm,
2917: uint32_t alignment,
2918: uint64_t flags);
2919: int __must_check
2920: i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2921: const struct i915_ggtt_view *view,
2922: uint32_t alignment,
2923: uint64_t flags);
2924:
2925: int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2926: u32 flags);
2927: void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
1.4 riastrad 2928: int __must_check i915_vma_unbind(struct i915_vma *vma);
1.12 riastrad 2929: /*
2930: * BEWARE: Do not use the function below unless you can _absolutely_
2931: * _guarantee_ VMA in question is _not in use_ anywhere.
2932: */
2933: int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
1.4 riastrad 2934: int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2935: void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
1.1 riastrad 2936: void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2937:
1.4 riastrad 2938: int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2939: int *needs_clflush);
2940:
1.1 riastrad 2941: int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1.12 riastrad 2942:
1.2 riastrad 2943: #ifdef __NetBSD__ /* XXX */
2944: static inline struct page *
2945: i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2946: {
1.12 riastrad 2947: struct vm_page *page;
1.2 riastrad 2948:
1.12 riastrad 2949: if (obj->phys_handle) {
1.16 riastrad 2950: vaddr_t va = (vaddr_t)obj->phys_handle->vaddr;
1.12 riastrad 2951: paddr_t pa;
2952: if (!pmap_extract(pmap_kernel(), va + n*PAGE_SIZE, &pa))
2953: panic("i915 gem object phys-attached but not mapped:"
2954: " obj=%p pgno=%d va=%p", obj, n,
2955: obj->phys_handle->vaddr);
2956: page = PHYS_TO_VM_PAGE(pa);
2957: } else {
2958: /*
2959: * Pages must be pinned so that we need not hold the
2960: * lock to prevent them from disappearing.
2961: */
2962: KASSERT(obj->pages != NULL);
1.19 riastrad 2963: mutex_enter(obj->base.filp->vmobjlock);
2964: page = uvm_pagelookup(obj->base.filp, ptoa(n));
2965: mutex_exit(obj->base.filp->vmobjlock);
1.12 riastrad 2966: }
2967: KASSERT(page != NULL);
1.2 riastrad 2968: return container_of(page, struct page, p_vmp);
2969: }
2970: #else
1.12 riastrad 2971: static inline int __sg_page_count(struct scatterlist *sg)
1.1 riastrad 2972: {
1.12 riastrad 2973: return sg->length >> PAGE_SHIFT;
2974: }
1.4 riastrad 2975:
1.12 riastrad 2976: static inline struct page *
2977: i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2978: {
2979: if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2980: return NULL;
2981:
2982: if (n < obj->get_page.last) {
2983: obj->get_page.sg = obj->pages->sgl;
2984: obj->get_page.last = 0;
2985: }
2986:
2987: while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2988: obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2989: if (unlikely(sg_is_chain(obj->get_page.sg)))
2990: obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2991: }
1.4 riastrad 2992:
1.12 riastrad 2993: return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
1.1 riastrad 2994: }
1.2 riastrad 2995: #endif
1.12 riastrad 2996:
1.1 riastrad 2997: static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2998: {
2999: BUG_ON(obj->pages == NULL);
3000: obj->pages_pin_count++;
3001: }
3002: static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3003: {
3004: BUG_ON(obj->pages_pin_count == 0);
3005: obj->pages_pin_count--;
3006: }
3007:
3008: int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3009: int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1.12 riastrad 3010: struct intel_engine_cs *to,
3011: struct drm_i915_gem_request **to_req);
1.4 riastrad 3012: void i915_vma_move_to_active(struct i915_vma *vma,
1.12 riastrad 3013: struct drm_i915_gem_request *req);
1.1 riastrad 3014: int i915_gem_dumb_create(struct drm_file *file_priv,
3015: struct drm_device *dev,
3016: struct drm_mode_create_dumb *args);
3017: int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3018: uint32_t handle, uint64_t *offset);
3019: /**
3020: * Returns true if seq1 is later than seq2.
3021: */
3022: static inline bool
3023: i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3024: {
3025: return (int32_t)(seq1 - seq2) >= 0;
3026: }
3027:
1.12 riastrad 3028: static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3029: bool lazy_coherency)
1.1 riastrad 3030: {
1.12 riastrad 3031: u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3032: return i915_seqno_passed(seqno, req->previous_seqno);
1.1 riastrad 3033: }
3034:
1.12 riastrad 3035: static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3036: bool lazy_coherency)
1.1 riastrad 3037: {
1.12 riastrad 3038: u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3039: return i915_seqno_passed(seqno, req->seqno);
1.1 riastrad 3040: }
3041:
1.12 riastrad 3042: int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3043: int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3044:
1.4 riastrad 3045: struct drm_i915_gem_request *
1.12 riastrad 3046: i915_gem_find_active_request(struct intel_engine_cs *ring);
1.4 riastrad 3047:
3048: bool i915_gem_retire_requests(struct drm_device *dev);
1.12 riastrad 3049: void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
1.4 riastrad 3050: int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1.1 riastrad 3051: bool interruptible);
1.12 riastrad 3052:
1.4 riastrad 3053: static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3054: {
3055: return unlikely(atomic_read(&error->reset_counter)
3056: & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3057: }
3058:
3059: static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3060: {
3061: return atomic_read(&error->reset_counter) & I915_WEDGED;
3062: }
3063:
3064: static inline u32 i915_reset_count(struct i915_gpu_error *error)
3065: {
3066: return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3067: }
1.1 riastrad 3068:
1.12 riastrad 3069: static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3070: {
3071: return dev_priv->gpu_error.stop_rings == 0 ||
3072: dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3073: }
3074:
3075: static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3076: {
3077: return dev_priv->gpu_error.stop_rings == 0 ||
3078: dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3079: }
3080:
1.1 riastrad 3081: void i915_gem_reset(struct drm_device *dev);
1.4 riastrad 3082: bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
1.1 riastrad 3083: int __must_check i915_gem_init(struct drm_device *dev);
1.12 riastrad 3084: int i915_gem_init_rings(struct drm_device *dev);
1.1 riastrad 3085: int __must_check i915_gem_init_hw(struct drm_device *dev);
1.12 riastrad 3086: int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
1.1 riastrad 3087: void i915_gem_init_swizzling(struct drm_device *dev);
3088: void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3089: int __must_check i915_gpu_idle(struct drm_device *dev);
1.4 riastrad 3090: int __must_check i915_gem_suspend(struct drm_device *dev);
1.12 riastrad 3091: void __i915_add_request(struct drm_i915_gem_request *req,
3092: struct drm_i915_gem_object *batch_obj,
3093: bool flush_caches);
3094: #define i915_add_request(req) \
3095: __i915_add_request(req, NULL, true)
3096: #define i915_add_request_no_flush(req) \
3097: __i915_add_request(req, NULL, false)
3098: int __i915_wait_request(struct drm_i915_gem_request *req,
3099: unsigned reset_counter,
3100: bool interruptible,
3101: s64 *timeout,
3102: struct intel_rps_client *rps);
3103: int __must_check i915_wait_request(struct drm_i915_gem_request *req);
1.2 riastrad 3104: #ifdef __NetBSD__ /* XXX */
3105: int i915_gem_fault(struct uvm_faultinfo *, vaddr_t, struct vm_page **,
3106: int, int, vm_prot_t, int);
3107: #else
1.1 riastrad 3108: int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1.2 riastrad 3109: #endif
1.1 riastrad 3110: int __must_check
1.12 riastrad 3111: i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3112: bool readonly);
3113: int __must_check
1.1 riastrad 3114: i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3115: bool write);
3116: int __must_check
3117: i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3118: int __must_check
3119: i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3120: u32 alignment,
1.12 riastrad 3121: struct intel_engine_cs *pipelined,
3122: struct drm_i915_gem_request **pipelined_request,
3123: const struct i915_ggtt_view *view);
3124: void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3125: const struct i915_ggtt_view *view);
1.4 riastrad 3126: int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
1.1 riastrad 3127: int align);
1.4 riastrad 3128: int i915_gem_open(struct drm_device *dev, struct drm_file *file);
1.1 riastrad 3129: void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3130:
3131: uint32_t
1.4 riastrad 3132: i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3133: uint32_t
3134: i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3135: int tiling_mode, bool fenced);
1.1 riastrad 3136:
3137: int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3138: enum i915_cache_level cache_level);
3139:
3140: struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3141: struct dma_buf *dma_buf);
3142:
3143: struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3144: struct drm_gem_object *gem_obj, int flags);
3145:
1.12 riastrad 3146: u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3147: const struct i915_ggtt_view *view);
3148: u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3149: struct i915_address_space *vm);
3150: static inline u64
3151: i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3152: {
3153: return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3154: }
1.4 riastrad 3155:
3156: bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
1.12 riastrad 3157: bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3158: const struct i915_ggtt_view *view);
1.4 riastrad 3159: bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3160: struct i915_address_space *vm);
1.12 riastrad 3161:
1.4 riastrad 3162: unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3163: struct i915_address_space *vm);
1.12 riastrad 3164: struct i915_vma *
3165: i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3166: struct i915_address_space *vm);
3167: struct i915_vma *
3168: i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3169: const struct i915_ggtt_view *view);
3170:
1.4 riastrad 3171: struct i915_vma *
3172: i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3173: struct i915_address_space *vm);
1.12 riastrad 3174: struct i915_vma *
3175: i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3176: const struct i915_ggtt_view *view);
1.4 riastrad 3177:
1.12 riastrad 3178: static inline struct i915_vma *
3179: i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3180: {
3181: return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
1.4 riastrad 3182: }
1.12 riastrad 3183: bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
1.4 riastrad 3184:
3185: /* Some GGTT VM helpers */
1.12 riastrad 3186: #define i915_obj_to_ggtt(obj) \
1.4 riastrad 3187: (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3188: static inline bool i915_is_ggtt(struct i915_address_space *vm)
3189: {
3190: struct i915_address_space *ggtt =
3191: &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3192: return vm == ggtt;
3193: }
3194:
1.12 riastrad 3195: static inline struct i915_hw_ppgtt *
3196: i915_vm_to_ppgtt(struct i915_address_space *vm)
1.4 riastrad 3197: {
1.12 riastrad 3198: WARN_ON(i915_is_ggtt(vm));
3199:
3200: return container_of(vm, struct i915_hw_ppgtt, base);
1.4 riastrad 3201: }
3202:
1.12 riastrad 3203:
3204: static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
1.4 riastrad 3205: {
1.12 riastrad 3206: return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
1.4 riastrad 3207: }
3208:
3209: static inline unsigned long
3210: i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3211: {
1.12 riastrad 3212: return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
1.4 riastrad 3213: }
3214:
3215: static inline int __must_check
3216: i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3217: uint32_t alignment,
3218: unsigned flags)
3219: {
1.12 riastrad 3220: return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3221: alignment, flags | PIN_GLOBAL);
1.4 riastrad 3222: }
3223:
3224: static inline int
3225: i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3226: {
3227: return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3228: }
3229:
1.12 riastrad 3230: void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3231: const struct i915_ggtt_view *view);
3232: static inline void
3233: i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3234: {
3235: i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3236: }
3237:
3238: /* i915_gem_fence.c */
3239: int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3240: int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3241:
3242: bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3243: void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3244:
3245: void i915_gem_restore_fences(struct drm_device *dev);
3246:
3247: void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3248: void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3249: void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1.4 riastrad 3250:
1.1 riastrad 3251: /* i915_gem_context.c */
1.4 riastrad 3252: int __must_check i915_gem_context_init(struct drm_device *dev);
1.1 riastrad 3253: void i915_gem_context_fini(struct drm_device *dev);
1.4 riastrad 3254: void i915_gem_context_reset(struct drm_device *dev);
3255: int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
1.12 riastrad 3256: int i915_gem_context_enable(struct drm_i915_gem_request *req);
1.1 riastrad 3257: void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1.12 riastrad 3258: int i915_switch_context(struct drm_i915_gem_request *req);
3259: struct intel_context *
1.4 riastrad 3260: i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3261: void i915_gem_context_free(struct kref *ctx_ref);
1.12 riastrad 3262: struct drm_i915_gem_object *
3263: i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3264: static inline void i915_gem_context_reference(struct intel_context *ctx)
1.4 riastrad 3265: {
3266: kref_get(&ctx->ref);
3267: }
3268:
1.12 riastrad 3269: static inline void i915_gem_context_unreference(struct intel_context *ctx)
1.4 riastrad 3270: {
3271: kref_put(&ctx->ref, i915_gem_context_free);
3272: }
3273:
1.12 riastrad 3274: static inline bool i915_gem_context_is_default(const struct intel_context *c)
1.4 riastrad 3275: {
1.12 riastrad 3276: return c->user_handle == DEFAULT_CONTEXT_HANDLE;
1.4 riastrad 3277: }
3278:
1.1 riastrad 3279: int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3280: struct drm_file *file);
3281: int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3282: struct drm_file *file);
1.12 riastrad 3283: int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3284: struct drm_file *file_priv);
3285: int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3286: struct drm_file *file_priv);
1.1 riastrad 3287:
1.4 riastrad 3288: /* i915_gem_evict.c */
3289: int __must_check i915_gem_evict_something(struct drm_device *dev,
3290: struct i915_address_space *vm,
3291: int min_size,
3292: unsigned alignment,
3293: unsigned cache_level,
3294: unsigned long start,
3295: unsigned long end,
3296: unsigned flags);
3297: int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3298:
1.12 riastrad 3299: /* belongs in i915_gem_gtt.h */
1.1 riastrad 3300: static inline void i915_gem_chipset_flush(struct drm_device *dev)
3301: {
3302: if (INTEL_INFO(dev)->gen < 6)
3303: intel_gtt_chipset_flush();
3304: }
3305:
3306: /* i915_gem_stolen.c */
1.12 riastrad 3307: int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3308: struct drm_mm_node *node, u64 size,
3309: unsigned alignment);
3310: int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3311: struct drm_mm_node *node, u64 size,
3312: unsigned alignment, u64 start,
3313: u64 end);
3314: void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3315: struct drm_mm_node *node);
1.1 riastrad 3316: int i915_gem_init_stolen(struct drm_device *dev);
3317: void i915_gem_cleanup_stolen(struct drm_device *dev);
1.4 riastrad 3318: struct drm_i915_gem_object *
3319: i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3320: struct drm_i915_gem_object *
3321: i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3322: u32 stolen_offset,
3323: u32 gtt_offset,
3324: u32 size);
1.12 riastrad 3325:
3326: /* i915_gem_shrinker.c */
3327: unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3328: unsigned long target,
3329: unsigned flags);
3330: #define I915_SHRINK_PURGEABLE 0x1
3331: #define I915_SHRINK_UNBOUND 0x2
3332: #define I915_SHRINK_BOUND 0x4
3333: #define I915_SHRINK_ACTIVE 0x8
3334: unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3335: void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3336:
1.1 riastrad 3337:
3338: /* i915_gem_tiling.c */
1.4 riastrad 3339: static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3340: {
3341: struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3342:
3343: return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3344: obj->tiling_mode != I915_TILING_NONE;
3345: }
3346:
1.1 riastrad 3347: /* i915_gem_debug.c */
3348: #if WATCH_LISTS
3349: int i915_verify_lists(struct drm_device *dev);
3350: #else
3351: #define i915_verify_lists(dev) 0
3352: #endif
3353:
3354: /* i915_debugfs.c */
3355: int i915_debugfs_init(struct drm_minor *minor);
3356: void i915_debugfs_cleanup(struct drm_minor *minor);
1.4 riastrad 3357: #ifdef CONFIG_DEBUG_FS
1.12 riastrad 3358: int i915_debugfs_connector_add(struct drm_connector *connector);
1.4 riastrad 3359: void intel_display_crc_init(struct drm_device *dev);
3360: #else
1.12 riastrad 3361: static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3362: { return 0; }
1.4 riastrad 3363: static inline void intel_display_crc_init(struct drm_device *dev) {}
3364: #endif
3365:
3366: /* i915_gpu_error.c */
3367: __printf(2, 3)
3368: void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3369: int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3370: const struct i915_error_state_file_priv *error);
3371: int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
1.12 riastrad 3372: struct drm_i915_private *i915,
1.4 riastrad 3373: size_t count, loff_t pos);
3374: static inline void i915_error_state_buf_release(
3375: struct drm_i915_error_state_buf *eb)
3376: {
3377: kfree(eb->buf);
3378: }
3379: void i915_capture_error_state(struct drm_device *dev, bool wedge,
3380: const char *error_msg);
3381: void i915_error_state_get(struct drm_device *dev,
3382: struct i915_error_state_file_priv *error_priv);
3383: void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3384: void i915_destroy_error_state(struct drm_device *dev);
3385:
3386: void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
1.12 riastrad 3387: const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1.4 riastrad 3388:
3389: /* i915_cmd_parser.c */
1.12 riastrad 3390: int i915_cmd_parser_get_version(void);
3391: int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3392: void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3393: bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3394: int i915_parse_cmds(struct intel_engine_cs *ring,
1.4 riastrad 3395: struct drm_i915_gem_object *batch_obj,
1.12 riastrad 3396: struct drm_i915_gem_object *shadow_batch_obj,
1.4 riastrad 3397: u32 batch_start_offset,
1.12 riastrad 3398: u32 batch_len,
1.4 riastrad 3399: bool is_master);
1.1 riastrad 3400:
3401: /* i915_suspend.c */
3402: extern int i915_save_state(struct drm_device *dev);
3403: extern int i915_restore_state(struct drm_device *dev);
3404:
3405: /* i915_sysfs.c */
3406: void i915_setup_sysfs(struct drm_device *dev_priv);
3407: void i915_teardown_sysfs(struct drm_device *dev_priv);
3408:
3409: /* intel_i2c.c */
3410: extern int intel_setup_gmbus(struct drm_device *dev);
3411: extern void intel_teardown_gmbus(struct drm_device *dev);
1.12 riastrad 3412: extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3413: unsigned int pin);
1.1 riastrad 3414:
1.12 riastrad 3415: extern struct i2c_adapter *
3416: intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
1.1 riastrad 3417: extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3418: extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1.2 riastrad 3419: static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1.1 riastrad 3420: {
3421: return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3422: }
3423: extern void intel_i2c_reset(struct drm_device *dev);
3424:
1.12 riastrad 3425: /* intel_bios.c */
3426: bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3427:
1.1 riastrad 3428: /* intel_opregion.c */
1.10 nonaka 3429: #ifdef CONFIG_ACPI
1.8 riastrad 3430: extern int intel_opregion_setup(struct drm_device *dev);
1.1 riastrad 3431: extern void intel_opregion_init(struct drm_device *dev);
3432: extern void intel_opregion_fini(struct drm_device *dev);
3433: extern void intel_opregion_asle_intr(struct drm_device *dev);
1.4 riastrad 3434: extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3435: bool enable);
3436: extern int intel_opregion_notify_adapter(struct drm_device *dev,
3437: pci_power_t state);
1.1 riastrad 3438: #else
1.10 nonaka 3439: static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
1.1 riastrad 3440: static inline void intel_opregion_init(struct drm_device *dev) { return; }
3441: static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3442: static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1.4 riastrad 3443: static inline int
3444: intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3445: {
3446: return 0;
3447: }
3448: static inline int
3449: intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3450: {
3451: return 0;
3452: }
1.1 riastrad 3453: #endif
3454:
3455: /* intel_acpi.c */
3456: #ifdef CONFIG_ACPI
1.10 nonaka 3457: #ifdef __NetBSD__
3458: extern void intel_register_dsm_handler(struct drm_device *);
3459: #else
1.1 riastrad 3460: extern void intel_register_dsm_handler(void);
1.10 nonaka 3461: #endif
1.1 riastrad 3462: extern void intel_unregister_dsm_handler(void);
3463: #else
1.10 nonaka 3464: #ifdef __NetBSD__
3465: static inline void
3466: intel_register_dsm_handler(struct drm_device *dev)
3467: {
3468: return;
3469: }
3470: #else
1.1 riastrad 3471: static inline void intel_register_dsm_handler(void) { return; }
1.10 nonaka 3472: #endif
1.1 riastrad 3473: static inline void intel_unregister_dsm_handler(void) { return; }
3474: #endif /* CONFIG_ACPI */
3475:
3476: /* modesetting */
1.7 riastrad 3477: extern void i915_disable_vga(struct drm_device *dev);
1.1 riastrad 3478: extern void intel_modeset_init_hw(struct drm_device *dev);
3479: extern void intel_modeset_init(struct drm_device *dev);
3480: extern void intel_modeset_gem_init(struct drm_device *dev);
3481: extern void intel_modeset_cleanup(struct drm_device *dev);
1.4 riastrad 3482: extern void intel_connector_unregister(struct intel_connector *);
1.1 riastrad 3483: extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1.12 riastrad 3484: extern void intel_display_resume(struct drm_device *dev);
1.13 riastrad 3485: extern void i915_disable_vga(struct drm_device *dev);
1.4 riastrad 3486: extern void i915_redisable_vga(struct drm_device *dev);
3487: extern void i915_redisable_vga_power_on(struct drm_device *dev);
1.1 riastrad 3488: extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3489: extern void intel_init_pch_refclk(struct drm_device *dev);
1.12 riastrad 3490: extern void intel_set_rps(struct drm_device *dev, u8 val);
3491: extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3492: bool enable);
1.1 riastrad 3493: extern void intel_detect_pch(struct drm_device *dev);
3494: extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3495: extern int intel_enable_rc6(const struct drm_device *dev);
3496:
3497: extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3498: int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3499: struct drm_file *file);
1.4 riastrad 3500: int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3501: struct drm_file *file);
1.1 riastrad 3502:
3503: /* overlay */
3504: extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1.4 riastrad 3505: extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3506: struct intel_overlay_error_state *error);
1.1 riastrad 3507:
3508: extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1.4 riastrad 3509: extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
1.1 riastrad 3510: struct drm_device *dev,
3511: struct intel_display_error_state *error);
3512:
1.12 riastrad 3513: int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3514: int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
1.1 riastrad 3515:
1.4 riastrad 3516: /* intel_sideband.c */
1.12 riastrad 3517: u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3518: void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
1.4 riastrad 3519: u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3520: u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3521: void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3522: u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3523: void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3524: u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3525: void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3526: u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3527: void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3528: u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3529: void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
1.9 matt 3530: u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);
3531: void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);
1.4 riastrad 3532: u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3533: enum intel_sbi_destination destination);
3534: void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3535: enum intel_sbi_destination destination);
3536: u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3537: void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3538:
1.12 riastrad 3539: int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3540: int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
1.4 riastrad 3541:
3542: #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3543: #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3544:
3545: #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3546: #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3547: #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3548: #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3549:
3550: #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3551: #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3552: #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3553: #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3554:
3555: /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3556: * will be implemented using 2 32-bit writes in an arbitrary order with
3557: * an arbitrary delay between them. This can cause the hardware to
3558: * act upon the intermediate value, possibly leading to corruption and
3559: * machine death. You have been warned.
3560: */
3561: #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3562: #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3563:
3564: #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
1.12 riastrad 3565: u32 upper, lower, old_upper, loop = 0; \
3566: upper = I915_READ(upper_reg); \
3567: do { \
3568: old_upper = upper; \
3569: lower = I915_READ(lower_reg); \
3570: upper = I915_READ(upper_reg); \
3571: } while (upper != old_upper && loop++ < 2); \
3572: (u64)upper << 32 | lower; })
1.4 riastrad 3573:
3574: #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3575: #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3576:
1.12 riastrad 3577: /* These are untraced mmio-accessors that are only valid to be used inside
3578: * criticial sections inside IRQ handlers where forcewake is explicitly
3579: * controlled.
3580: * Think twice, and think again, before using these.
3581: * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3582: * intel_uncore_forcewake_irqunlock().
3583: */
1.17 riastrad 3584: #ifdef __NetBSD__
3585: #define I915_READ_FW(reg__) bus_space_read_4(dev_priv->regs_bst, dev_priv->regs_bsh, (reg__))
3586: #define I915_WRITE_FW(reg__, val__) bus_space_write_4(dev_priv->regs_bst, dev_priv->regs_bsh, (reg__), (val__))
3587: #else
1.12 riastrad 3588: #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3589: #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
1.17 riastrad 3590: #endif
1.12 riastrad 3591: #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3592:
1.4 riastrad 3593: /* "Broadcast RGB" property */
3594: #define INTEL_BROADCAST_RGB_AUTO 0
3595: #define INTEL_BROADCAST_RGB_FULL 1
3596: #define INTEL_BROADCAST_RGB_LIMITED 2
3597:
3598: static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3599: {
1.12 riastrad 3600: if (IS_VALLEYVIEW(dev))
3601: return VLV_VGACNTRL;
3602: else if (INTEL_INFO(dev)->gen >= 5)
1.4 riastrad 3603: return CPU_VGACNTRL;
3604: else
3605: return VGACNTRL;
3606: }
1.1 riastrad 3607:
1.4 riastrad 3608: static inline void __user *to_user_ptr(u64 address)
3609: {
3610: return (void __user *)(uintptr_t)address;
3611: }
1.1 riastrad 3612:
1.4 riastrad 3613: static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3614: {
3615: unsigned long j = msecs_to_jiffies(m);
1.1 riastrad 3616:
1.4 riastrad 3617: return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3618: }
1.1 riastrad 3619:
1.12 riastrad 3620: static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3621: {
3622: return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3623: }
3624:
1.4 riastrad 3625: static inline unsigned long
3626: timespec_to_jiffies_timeout(const struct timespec *value)
3627: {
3628: unsigned long j = timespec_to_jiffies(value);
1.1 riastrad 3629:
1.4 riastrad 3630: return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3631: }
1.1 riastrad 3632:
1.4 riastrad 3633: /*
3634: * If you need to wait X milliseconds between events A and B, but event B
3635: * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3636: * when event A happened, then just before event B you call this function and
3637: * pass the timestamp as the first argument, and X as the second argument.
3638: */
3639: static inline void
3640: wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3641: {
3642: unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
1.1 riastrad 3643:
1.4 riastrad 3644: /*
3645: * Don't re-read the value of "jiffies" every time since it may change
3646: * behind our back and break the math.
3647: */
3648: tmp_jiffies = jiffies;
3649: target_jiffies = timestamp_jiffies +
3650: msecs_to_jiffies_timeout(to_wait_ms);
3651:
3652: if (time_after(target_jiffies, tmp_jiffies)) {
3653: remaining_jiffies = target_jiffies - tmp_jiffies;
3654: while (remaining_jiffies)
3655: remaining_jiffies =
3656: schedule_timeout_uninterruptible(remaining_jiffies);
3657: }
3658: }
1.1 riastrad 3659:
1.12 riastrad 3660: static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3661: struct drm_i915_gem_request *req)
3662: {
3663: if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3664: i915_gem_request_assign(&ring->trace_irq_req, req);
3665: }
3666:
1.1 riastrad 3667: #endif
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