Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

===================================================================
RCS file: /ftp/cvs/cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h,v
rcsdiff: /ftp/cvs/cvsroot/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h,v: warning: Unknown phrases like `commitid ...;' are present.
retrieving revision 1.11.20.3
retrieving revision 1.12
diff -u -p -r1.11.20.3 -r1.12
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h	2020/04/13 08:04:57	1.11.20.3
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h	2018/08/27 04:58:23	1.12
@@ -1,4 +1,4 @@
-/*	$NetBSD: i915_drv.h,v 1.11.20.3 2020/04/13 08:04:57 martin Exp $	*/
+/*	$NetBSD: i915_drv.h,v 1.12 2018/08/27 04:58:23 riastradh Exp $	*/
 
 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  */
@@ -127,7 +127,7 @@ static inline const char *yesno(bool v)
 	return v ? "yes" : "no";
 }
 
-enum pipe {
+enum i915_pipe {
 	INVALID_PIPE = -1,
 	PIPE_A = 0,
 	PIPE_B,
@@ -475,10 +475,6 @@ struct opregion_asle;
 #endif
 
 struct intel_opregion {
-#ifdef __NetBSD__
-	bus_space_tag_t bst;
-	bus_space_handle_t bsh;
-#endif
 	struct opregion_header *header;
 	struct opregion_acpi *acpi;
 	struct opregion_swsci *swsci;
@@ -800,7 +796,6 @@ struct intel_csr {
 	func(is_valleyview) sep \
 	func(is_haswell) sep \
 	func(is_skylake) sep \
-	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
 	func(has_pipe_cxsr) sep \
@@ -921,12 +916,6 @@ struct intel_context {
 		int pin_count;
 	} engine[I915_NUM_RINGS];
 
-	/* jump_whitelist: Bit array for tracking cmds during cmdparsing */
-	unsigned long *jump_whitelist;
-
-	/* jump_whitelist_cmds: No of cmd slots available */
-	uint32_t jump_whitelist_cmds;
-
 	struct list_head link;
 };
 
@@ -1034,7 +1023,6 @@ enum intel_pch {
 	PCH_CPT,	/* Cougarpoint PCH */
 	PCH_LPT,	/* Lynxpoint PCH */
 	PCH_SPT,        /* Sunrisepoint PCH */
-	PCH_KBP,	/* Kabypoint PCH */
 	PCH_NOP,
 };
 
@@ -1050,11 +1038,6 @@ enum intel_sbi_destination {
 #define QUIRK_PIPEB_FORCE (1<<4)
 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 
-#ifdef __NetBSD__
-/* NetBSD hack to note version was called and thus mmap flags valid. */
-#define QUIRK_NETBSD_VERSION_CALLED (1ul<<31)
-#endif
-
 struct intel_fbdev;
 struct intel_fbc_work;
 
@@ -1195,7 +1178,6 @@ struct intel_gen6_power_mgmt {
 	bool client_boost;
 
 	bool enabled;
-	bool ctx_corrupted;
 	struct delayed_work delayed_resume_work;
 	unsigned boosts;
 
@@ -1431,7 +1413,7 @@ struct i915_gpu_error {
 	atomic_t reset_counter;
 
 #define I915_RESET_IN_PROGRESS_FLAG	1
-#define I915_WEDGED			(1UL << 31)
+#define I915_WEDGED			(1 << 31)
 
 	/**
 	 * Waitqueue to signal when the reset has completed. Used by clients
@@ -2044,12 +2026,10 @@ static inline struct drm_i915_private *t
 	return dev->dev_private;
 }
 
-#ifndef __NetBSD__
 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
 {
 	return to_i915(dev_get_drvdata(dev));
 }
-#endif
 
 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
 {
@@ -2195,9 +2175,10 @@ struct drm_i915_gem_object {
 	unsigned int pin_display;
 
 #ifdef __NetBSD__
-	struct pglist pageq;
-	bus_dmamap_t pages;	/* expedient misnomer */
-	struct sg_table *sg;	/* drm prime */
+	struct pglist igo_pageq;
+	bus_dma_segment_t *pages; /* `pages' is an expedient misnomer.  */
+	int igo_nsegs;
+	bus_dmamap_t igo_dmamap;
 #else
 	struct sg_table *pages;
 #endif
@@ -2519,9 +2500,9 @@ struct drm_i915_cmd_table {
 #define __I915__(p) ({ \
 	struct drm_i915_private *__p; \
 	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
-		__p = (struct drm_i915_private *)__UNCONST(p); \
+		__p = (struct drm_i915_private *)p; \
 	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
-		__p = to_i915((struct drm_device *)__UNCONST(p)); \
+		__p = to_i915((struct drm_device *)p); \
 	else \
 		BUILD_BUG(); \
 	__p; \
@@ -2530,16 +2511,6 @@ struct drm_i915_cmd_table {
 #define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
 #define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
 
-#define REVID_FOREVER	(0xff)
-
-/*
- * Return true if revision is in range [since,until] inclusive.
- *
- * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
- */
-#define IS_REVID(p, since, until) \
-	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-
 #define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
 #define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
 #define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
@@ -2563,12 +2534,10 @@ struct drm_i915_cmd_table {
 				 INTEL_DEVID(dev) == 0x015a)
 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
-#define IS_HASWELL(dev)		(INTEL_INFO(dev)->is_haswell)
+#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
-#define IS_SKYLAKE(dev)		(INTEL_INFO(dev)->is_skylake)
-#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
-#define IS_BROXTON(dev)		(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev) && \
-				 IS_GEN9(dev))
+#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
+#define IS_BROXTON(dev)	(!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
@@ -2596,14 +2565,6 @@ struct drm_i915_cmd_table {
 #define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
 				 INTEL_DEVID(dev) == 0x1915 || \
 				 INTEL_DEVID(dev) == 0x191E)
-#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
-				 INTEL_DEVID(dev) == 0x5913 || \
-				 INTEL_DEVID(dev) == 0x5916 || \
-				 INTEL_DEVID(dev) == 0x5921 || \
-				 INTEL_DEVID(dev) == 0x5926)
-#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
-				 INTEL_DEVID(dev) == 0x5915 || \
-				 INTEL_DEVID(dev) == 0x591E)
 #define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
 #define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
@@ -2618,23 +2579,10 @@ struct drm_i915_cmd_table {
 #define SKL_REVID_E0		(0x4)
 #define SKL_REVID_F0		(0x5)
 
-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
-
 #define BXT_REVID_A0		(0x0)
-#define BXT_REVID_A1		(0x1)
 #define BXT_REVID_B0		(0x3)
 #define BXT_REVID_C0		(0x9)
 
-#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
-
-#define KBL_REVID_A0		(0x0)
-#define KBL_REVID_B0		(0x1)
-#define KBL_REVID_C0		(0x2)
-#define KBL_REVID_D0		(0x3)
-#define KBL_REVID_E0		(0x4)
-
-#define IS_KBL_REVID(p, since, until) (IS_KABYLAKE(p) && IS_REVID(p, since, until))
-
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
@@ -2659,9 +2607,6 @@ struct drm_i915_cmd_table {
 #define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
 #define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
 #define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
-
-#define HAS_SECURE_BATCHES(dev_priv) (INTEL_INFO(dev_priv)->gen < 6)
-
 #define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
 #define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
 				 __I915__(dev)->ellc_size)
@@ -2676,18 +2621,8 @@ struct drm_i915_cmd_table {
 #define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
 
-/*
- * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
- * All later gens can run the final buffer from the ppgtt
- */
-#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN7(dev_priv)
-
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
-
-#define NEEDS_RC6_CTX_CORRUPTION_WA(dev)	\
-	(IS_BROADWELL(dev) || INTEL_INFO(dev)->gen == 9)
-
 /*
  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
  * even when in MSI mode. This results in spurious interrupt warnings if the
@@ -2744,12 +2679,10 @@ struct drm_i915_cmd_table {
 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
 #define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
-#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
-#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
@@ -2767,16 +2700,17 @@ struct drm_i915_cmd_table {
 #define GT_FREQUENCY_MULTIPLIER 50
 #define GEN9_FREQ_SCALER 3
 
+#include "i915_trace.h"
+
 extern const struct drm_ioctl_desc i915_ioctls[];
 extern int i915_max_ioctl;
 
 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 extern int i915_resume_switcheroo(struct drm_device *dev);
 
-extern int i915_drm_suspend(struct drm_device *dev);
-extern int i915_drm_suspend_late(struct drm_device *dev, bool hibernation);
-extern int i915_drm_resume_early(struct drm_device *dev);
-extern int i915_drm_resume(struct drm_device *dev);
+extern int i915_drm_freeze(struct drm_device *dev);
+extern int i915_drm_thaw_early(struct drm_device *dev);
+extern int i915_drm_thaw(struct drm_device *dev);
 
 /* i915_params.c */
 struct i915_params {
@@ -2860,6 +2794,7 @@ extern void intel_uncore_early_sanitize(
 extern void intel_uncore_init(struct drm_device *dev);
 extern void intel_uncore_check_errors(struct drm_device *dev);
 extern void intel_uncore_fini(struct drm_device *dev);
+extern void intel_uncore_destroy(struct drm_device *dev);
 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
@@ -2880,11 +2815,11 @@ static inline bool intel_vgpu_active(str
 }
 
 void
-i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
+i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
 		     u32 status_mask);
 
 void
-i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
+i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
 		      u32 status_mask);
 
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
@@ -3008,7 +2943,7 @@ i915_gem_object_get_page(struct drm_i915
 	struct vm_page *page;
 
 	if (obj->phys_handle) {
-		vaddr_t va = (vaddr_t)obj->phys_handle->vaddr;
+		char *va = obj->phys_handle->vaddr;
 		paddr_t pa;
 		if (!pmap_extract(pmap_kernel(), va + n*PAGE_SIZE, &pa))
 			panic("i915 gem object phys-attached but not mapped:"
@@ -3021,9 +2956,10 @@ i915_gem_object_get_page(struct drm_i915
 		 * lock to prevent them from disappearing.
 		 */
 		KASSERT(obj->pages != NULL);
-		rw_enter(obj->base.filp->vmobjlock, RW_WRITER);
-		page = uvm_pagelookup(obj->base.filp, ptoa(n));
-		rw_exit(obj->base.filp->vmobjlock);
+		mutex_enter(obj->base.gemo_shm_uao->vmobjlock);
+		struct vm_page *const page =
+		    uvm_pagelookup(obj->base.gemo_shm_uao, ptoa(n));
+		mutex_exit(obj->base.gemo_shm_uao->vmobjlock);
 	}
 	KASSERT(page != NULL);
 	return container_of(page, struct page, p_vmp);
@@ -3448,19 +3384,16 @@ void i915_get_extra_instdone(struct drm_
 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
 
 /* i915_cmd_parser.c */
-int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
+int i915_cmd_parser_get_version(void);
 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
-int i915_parse_cmds(struct intel_context *cxt,
-		    struct intel_engine_cs *ring,
+int i915_parse_cmds(struct intel_engine_cs *ring,
 		    struct drm_i915_gem_object *batch_obj,
-		    u64 user_batch_start,
+		    struct drm_i915_gem_object *shadow_batch_obj,
 		    u32 batch_start_offset,
 		    u32 batch_len,
-		    struct drm_i915_gem_object *shadow_batch_obj,
-		    u64 shadow_batch_start);
-
+		    bool is_master);
 
 /* i915_suspend.c */
 extern int i915_save_state(struct drm_device *dev);
@@ -3546,7 +3479,6 @@ extern void intel_modeset_cleanup(struct
 extern void intel_connector_unregister(struct intel_connector *);
 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 extern void intel_display_resume(struct drm_device *dev);
-extern void i915_disable_vga(struct drm_device *dev);
 extern void i915_redisable_vga(struct drm_device *dev);
 extern void i915_redisable_vga_power_on(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
@@ -3591,8 +3523,8 @@ u32 vlv_bunit_read(struct drm_i915_priva
 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
-void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
+u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);
 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
 		   enum intel_sbi_destination destination);
 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
@@ -3645,13 +3577,8 @@ int intel_freq_opcode(struct drm_i915_pr
  * Note: Should only be used between intel_uncore_forcewake_irqlock() and
  * intel_uncore_forcewake_irqunlock().
  */
-#ifdef __NetBSD__
-#define I915_READ_FW(reg__) bus_space_read_4(dev_priv->regs_bst, dev_priv->regs_bsh, (reg__))
-#define I915_WRITE_FW(reg__, val__) bus_space_write_4(dev_priv->regs_bst, dev_priv->regs_bsh, (reg__), (val__))
-#else
 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
-#endif
 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
 
 /* "Broadcast RGB" property */