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Diff for /src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h between version 1.1.1.1.2.18 and 1.1.1.2

version 1.1.1.1.2.18, 2014/01/21 20:49:01 version 1.1.1.2, 2014/07/16 19:35:25
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Line 30 
 #ifndef _I915_DRV_H_  #ifndef _I915_DRV_H_
 #define _I915_DRV_H_  #define _I915_DRV_H_
   
   #include <uapi/drm/i915_drm.h>
   
 #include "i915_reg.h"  #include "i915_reg.h"
 #include "intel_bios.h"  #include "intel_bios.h"
 #include "intel_ringbuffer.h"  #include "intel_ringbuffer.h"
Line 40 
Line 42 
 #include <linux/backlight.h>  #include <linux/backlight.h>
 #include <linux/intel-iommu.h>  #include <linux/intel-iommu.h>
 #include <linux/kref.h>  #include <linux/kref.h>
 #include <linux/completion.h>  #include <linux/pm_qos.h>
 #include <linux/shrinker.h>  
   
 /* General customization:  /* General customization:
  */   */
Line 53 
Line 54 
 #define DRIVER_DATE             "20080730"  #define DRIVER_DATE             "20080730"
   
 enum pipe {  enum pipe {
           INVALID_PIPE = -1,
         PIPE_A = 0,          PIPE_A = 0,
         PIPE_B,          PIPE_B,
         PIPE_C,          PIPE_C,
         I915_MAX_PIPES          _PIPE_EDP,
           I915_MAX_PIPES = _PIPE_EDP
 };  };
 #define pipe_name(p) ((p) + 'A')  #define pipe_name(p) ((p) + 'A')
   
Line 64  enum transcoder {
Line 67  enum transcoder {
         TRANSCODER_A = 0,          TRANSCODER_A = 0,
         TRANSCODER_B,          TRANSCODER_B,
         TRANSCODER_C,          TRANSCODER_C,
         TRANSCODER_EDP = 0xF,          TRANSCODER_EDP,
           I915_MAX_TRANSCODERS
 };  };
 #define transcoder_name(t) ((t) + 'A')  #define transcoder_name(t) ((t) + 'A')
   
Line 75  enum plane {
Line 79  enum plane {
 };  };
 #define plane_name(p) ((p) + 'A')  #define plane_name(p) ((p) + 'A')
   
   #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
   
 enum port {  enum port {
         PORT_A = 0,          PORT_A = 0,
         PORT_B,          PORT_B,
Line 85  enum port {
Line 91  enum port {
 };  };
 #define port_name(p) ((p) + 'A')  #define port_name(p) ((p) + 'A')
   
 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))  #define I915_NUM_PHYS_VLV 1
   
   enum dpio_channel {
           DPIO_CH0,
           DPIO_CH1
   };
   
   enum dpio_phy {
           DPIO_PHY0,
           DPIO_PHY1
   };
   
   enum intel_display_power_domain {
           POWER_DOMAIN_PIPE_A,
           POWER_DOMAIN_PIPE_B,
           POWER_DOMAIN_PIPE_C,
           POWER_DOMAIN_PIPE_A_PANEL_FITTER,
           POWER_DOMAIN_PIPE_B_PANEL_FITTER,
           POWER_DOMAIN_PIPE_C_PANEL_FITTER,
           POWER_DOMAIN_TRANSCODER_A,
           POWER_DOMAIN_TRANSCODER_B,
           POWER_DOMAIN_TRANSCODER_C,
           POWER_DOMAIN_TRANSCODER_EDP,
           POWER_DOMAIN_PORT_DDI_A_2_LANES,
           POWER_DOMAIN_PORT_DDI_A_4_LANES,
           POWER_DOMAIN_PORT_DDI_B_2_LANES,
           POWER_DOMAIN_PORT_DDI_B_4_LANES,
           POWER_DOMAIN_PORT_DDI_C_2_LANES,
           POWER_DOMAIN_PORT_DDI_C_4_LANES,
           POWER_DOMAIN_PORT_DDI_D_2_LANES,
           POWER_DOMAIN_PORT_DDI_D_4_LANES,
           POWER_DOMAIN_PORT_DSI,
           POWER_DOMAIN_PORT_CRT,
           POWER_DOMAIN_PORT_OTHER,
           POWER_DOMAIN_VGA,
           POWER_DOMAIN_AUDIO,
           POWER_DOMAIN_INIT,
   
           POWER_DOMAIN_NUM,
   };
   
   #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
   #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
                   ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
   #define POWER_DOMAIN_TRANSCODER(tran) \
           ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
            (tran) + POWER_DOMAIN_TRANSCODER_A)
   
   enum hpd_pin {
           HPD_NONE = 0,
           HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
           HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
           HPD_CRT,
           HPD_SDVO_B,
           HPD_SDVO_C,
           HPD_PORT_B,
           HPD_PORT_C,
           HPD_PORT_D,
           HPD_NUM_PINS
   };
   
   #define I915_GEM_GPU_DOMAINS \
           (I915_GEM_DOMAIN_RENDER | \
            I915_GEM_DOMAIN_SAMPLER | \
            I915_GEM_DOMAIN_COMMAND | \
            I915_GEM_DOMAIN_INSTRUCTION | \
            I915_GEM_DOMAIN_VERTEX)
   
 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)  #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
   #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
   
 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \  #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \          list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
                 if ((intel_encoder)->base.crtc == (__crtc))                  if ((intel_encoder)->base.crtc == (__crtc))
   
 struct intel_pch_pll {  #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
           list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
                   if ((intel_connector)->base.encoder == (__encoder))
   
   struct drm_i915_private;
   
   enum intel_dpll_id {
           DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
           /* real shared dpll ids must be >= 0 */
           DPLL_ID_PCH_PLL_A,
           DPLL_ID_PCH_PLL_B,
   };
   #define I915_NUM_PLLS 2
   
   struct intel_dpll_hw_state {
           uint32_t dpll;
           uint32_t dpll_md;
           uint32_t fp0;
           uint32_t fp1;
   };
   
   struct intel_shared_dpll {
         int refcount; /* count of number of CRTCs sharing this PLL */          int refcount; /* count of number of CRTCs sharing this PLL */
         int active; /* count of number of active CRTCs (i.e. DPMS on) */          int active; /* count of number of active CRTCs (i.e. DPMS on) */
         bool on; /* is the PLL actually active? Disabled during modeset */          bool on; /* is the PLL actually active? Disabled during modeset */
         int pll_reg;          const char *name;
         int fp0_reg;          /* should match the index in the dev_priv->shared_dplls array */
         int fp1_reg;          enum intel_dpll_id id;
 };          struct intel_dpll_hw_state hw_state;
 #define I915_NUM_PLLS 2          void (*mode_set)(struct drm_i915_private *dev_priv,
                            struct intel_shared_dpll *pll);
           void (*enable)(struct drm_i915_private *dev_priv,
                          struct intel_shared_dpll *pll);
           void (*disable)(struct drm_i915_private *dev_priv,
                           struct intel_shared_dpll *pll);
           bool (*get_hw_state)(struct drm_i915_private *dev_priv,
                                struct intel_shared_dpll *pll,
                                struct intel_dpll_hw_state *hw_state);
   };
   
   /* Used by dp and fdi links */
   struct intel_link_m_n {
           uint32_t        tu;
           uint32_t        gmch_m;
           uint32_t        gmch_n;
           uint32_t        link_m;
           uint32_t        link_n;
   };
   
   void intel_link_compute_m_n(int bpp, int nlanes,
                               int pixel_clock, int link_clock,
                               struct intel_link_m_n *m_n);
   
 struct intel_ddi_plls {  struct intel_ddi_plls {
         int spll_refcount;          int spll_refcount;
Line 123  struct intel_ddi_plls {
Line 239  struct intel_ddi_plls {
 #define DRIVER_MINOR            6  #define DRIVER_MINOR            6
 #define DRIVER_PATCHLEVEL       0  #define DRIVER_PATCHLEVEL       0
   
 #define WATCH_COHERENCY 0  
 #define WATCH_LISTS     0  #define WATCH_LISTS     0
 #define WATCH_GTT       0  #define WATCH_GTT       0
   
 #define I915_GEM_PHYS_CURSOR_0 1  
 #define I915_GEM_PHYS_CURSOR_1 2  
 #define I915_GEM_PHYS_OVERLAY_REGS 3  
 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)  
   
 struct drm_i915_gem_phys_object {  
         int id;  
         struct page **page_list;  
         drm_dma_handle_t *handle;  
         struct drm_i915_gem_object *cur_obj;  
 };  
   
 struct opregion_header;  struct opregion_header;
 struct opregion_acpi;  struct opregion_acpi;
 struct opregion_swsci;  struct opregion_swsci;
 struct opregion_asle;  struct opregion_asle;
 struct drm_i915_private;  
   
 #ifdef __NetBSD__               /* XXX acpi iomem */  
 #  include <linux/acpi_io.h>  
 #  define       __iomem                 __acpi_iomem  
 #endif  
   
 struct intel_opregion {  struct intel_opregion {
         struct opregion_header __iomem *header;          struct opregion_header __iomem *header;
         struct opregion_acpi __iomem *acpi;          struct opregion_acpi __iomem *acpi;
         struct opregion_swsci __iomem *swsci;          struct opregion_swsci __iomem *swsci;
           u32 swsci_gbda_sub_functions;
           u32 swsci_sbcb_sub_functions;
         struct opregion_asle __iomem *asle;          struct opregion_asle __iomem *asle;
         void __iomem *vbt;          void __iomem *vbt;
         u32 __iomem *lid_state;          u32 __iomem *lid_state;
           struct work_struct asle_work;
 };  };
 #define OPREGION_SIZE            (8*1024)  #define OPREGION_SIZE            (8*1024)
   
 #ifdef __NetBSD__               /* XXX acpi iomem */  
 #  undef        __iomem  
 #endif  
   
 struct intel_overlay;  struct intel_overlay;
 struct intel_overlay_error_state;  struct intel_overlay_error_state;
   
Line 172  struct drm_i915_master_private {
Line 268  struct drm_i915_master_private {
         struct _drm_i915_sarea *sarea_priv;          struct _drm_i915_sarea *sarea_priv;
 };  };
 #define I915_FENCE_REG_NONE -1  #define I915_FENCE_REG_NONE -1
 #define I915_MAX_NUM_FENCES 16  #define I915_MAX_NUM_FENCES 32
 /* 16 fences + sign bit for FENCE_REG_NONE */  /* 32 fences + sign bit for FENCE_REG_NONE */
 #define I915_MAX_NUM_FENCE_BITS 5  #define I915_MAX_NUM_FENCE_BITS 6
   
 struct drm_i915_fence_reg {  struct drm_i915_fence_reg {
         struct list_head lru_list;          struct list_head lru_list;
Line 195  struct intel_display_error_state;
Line 291  struct intel_display_error_state;
   
 struct drm_i915_error_state {  struct drm_i915_error_state {
         struct kref ref;          struct kref ref;
           struct timeval time;
   
           char error_msg[128];
           u32 reset_count;
           u32 suspend_count;
   
           /* Generic register state */
         u32 eir;          u32 eir;
         u32 pgtbl_er;          u32 pgtbl_er;
         u32 ier;          u32 ier;
         u32 ccid;          u32 ccid;
         u32 derrmr;          u32 derrmr;
         u32 forcewake;          u32 forcewake;
         bool waiting[I915_NUM_RINGS];  
         u32 pipestat[I915_MAX_PIPES];  
         u32 tail[I915_NUM_RINGS];  
         u32 head[I915_NUM_RINGS];  
         u32 ctl[I915_NUM_RINGS];  
         u32 ipeir[I915_NUM_RINGS];  
         u32 ipehr[I915_NUM_RINGS];  
         u32 instdone[I915_NUM_RINGS];  
         u32 acthd[I915_NUM_RINGS];  
         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];  
         u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];  
         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */  
         /* our own tracking of ring head and tail */  
         u32 cpu_ring_head[I915_NUM_RINGS];  
         u32 cpu_ring_tail[I915_NUM_RINGS];  
         u32 error; /* gen6+ */          u32 error; /* gen6+ */
         u32 err_int; /* gen7 */          u32 err_int; /* gen7 */
         u32 instpm[I915_NUM_RINGS];  
         u32 instps[I915_NUM_RINGS];  
         u32 extra_instdone[I915_NUM_INSTDONE_REG];  
         u32 seqno[I915_NUM_RINGS];  
         u64 bbaddr;  
         u32 fault_reg[I915_NUM_RINGS];  
         u32 done_reg;          u32 done_reg;
         u32 faddr[I915_NUM_RINGS];          u32 gac_eco;
           u32 gam_ecochk;
           u32 gab_ctl;
           u32 gfx_mode;
           u32 extra_instdone[I915_NUM_INSTDONE_REG];
           u32 pipestat[I915_MAX_PIPES];
         u64 fence[I915_MAX_NUM_FENCES];          u64 fence[I915_MAX_NUM_FENCES];
         struct timeval time;          struct intel_overlay_error_state *overlay;
           struct intel_display_error_state *display;
   
         struct drm_i915_error_ring {          struct drm_i915_error_ring {
                   bool valid;
                   /* Software tracked state */
                   bool waiting;
                   int hangcheck_score;
                   enum intel_ring_hangcheck_action hangcheck_action;
                   int num_requests;
   
                   /* our own tracking of ring head and tail */
                   u32 cpu_ring_head;
                   u32 cpu_ring_tail;
   
                   u32 semaphore_seqno[I915_NUM_RINGS - 1];
   
                   /* Register state */
                   u32 tail;
                   u32 head;
                   u32 ctl;
                   u32 hws;
                   u32 ipeir;
                   u32 ipehr;
                   u32 instdone;
                   u32 bbstate;
                   u32 instpm;
                   u32 instps;
                   u32 seqno;
                   u64 bbaddr;
                   u64 acthd;
                   u32 fault_reg;
                   u32 faddr;
                   u32 rc_psmi; /* sleep state */
                   u32 semaphore_mboxes[I915_NUM_RINGS - 1];
   
                 struct drm_i915_error_object {                  struct drm_i915_error_object {
                         int page_count;                          int page_count;
                         u32 gtt_offset;                          u32 gtt_offset;
                         u32 *pages[0];                          u32 *pages[0];
                 } *ringbuffer, *batchbuffer;                  } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
   
                 struct drm_i915_error_request {                  struct drm_i915_error_request {
                         long jiffies;                          long jiffies;
                         u32 seqno;                          u32 seqno;
                         u32 tail;                          u32 tail;
                 } *requests;                  } *requests;
                 int num_requests;  
                   struct {
                           u32 gfx_mode;
                           union {
                                   u64 pdp[4];
                                   u32 pp_dir_base;
                           };
                   } vm_info;
   
                   pid_t pid;
                   char comm[TASK_COMM_LEN];
         } ring[I915_NUM_RINGS];          } ring[I915_NUM_RINGS];
         struct drm_i915_error_buffer {          struct drm_i915_error_buffer {
                 u32 size;                  u32 size;
Line 254  struct drm_i915_error_state {
Line 386  struct drm_i915_error_state {
                 u32 dirty:1;                  u32 dirty:1;
                 u32 purgeable:1;                  u32 purgeable:1;
                 s32 ring:4;                  s32 ring:4;
                 u32 cache_level:2;                  u32 cache_level:3;
         } *active_bo, *pinned_bo;          } **active_bo, **pinned_bo;
         u32 active_bo_count, pinned_bo_count;  
         struct intel_overlay_error_state *overlay;          u32 *active_bo_count, *pinned_bo_count;
         struct intel_display_error_state *display;  
 };  };
   
   struct intel_connector;
   struct intel_crtc_config;
   struct intel_plane_config;
   struct intel_crtc;
   struct intel_limit;
   struct dpll;
   
 struct drm_i915_display_funcs {  struct drm_i915_display_funcs {
         bool (*fbc_enabled)(struct drm_device *dev);          bool (*fbc_enabled)(struct drm_device *dev);
         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);          void (*enable_fbc)(struct drm_crtc *crtc);
         void (*disable_fbc)(struct drm_device *dev);          void (*disable_fbc)(struct drm_device *dev);
         int (*get_display_clock_speed)(struct drm_device *dev);          int (*get_display_clock_speed)(struct drm_device *dev);
         int (*get_fifo_size)(struct drm_device *dev, int plane);          int (*get_fifo_size)(struct drm_device *dev, int plane);
         void (*update_wm)(struct drm_device *dev);          /**
         void (*update_sprite_wm)(struct drm_device *dev, int pipe,           * find_dpll() - Find the best values for the PLL
                                  uint32_t sprite_width, int pixel_size);           * @limit: limits for the PLL
         void (*update_linetime_wm)(struct drm_device *dev, int pipe,           * @crtc: current CRTC
                                  struct drm_display_mode *mode);           * @target: target frequency in kHz
            * @refclk: reference clock frequency in kHz
            * @match_clock: if provided, @best_clock P divider must
            *               match the P divider from @match_clock
            *               used for LVDS downclocking
            * @best_clock: best PLL values found
            *
            * Returns true on success, false on failure.
            */
           bool (*find_dpll)(const struct intel_limit *limit,
                             struct drm_crtc *crtc,
                             int target, int refclk,
                             struct dpll *match_clock,
                             struct dpll *best_clock);
           void (*update_wm)(struct drm_crtc *crtc);
           void (*update_sprite_wm)(struct drm_plane *plane,
                                    struct drm_crtc *crtc,
                                    uint32_t sprite_width, int pixel_size,
                                    bool enable, bool scaled);
         void (*modeset_global_resources)(struct drm_device *dev);          void (*modeset_global_resources)(struct drm_device *dev);
           /* Returns the active state of the crtc, and if the crtc is active,
            * fills out the pipe-config with the hw state. */
           bool (*get_pipe_config)(struct intel_crtc *,
                                   struct intel_crtc_config *);
           void (*get_plane_config)(struct intel_crtc *,
                                    struct intel_plane_config *);
         int (*crtc_mode_set)(struct drm_crtc *crtc,          int (*crtc_mode_set)(struct drm_crtc *crtc,
                              struct drm_display_mode *mode,  
                              struct drm_display_mode *adjusted_mode,  
                              int x, int y,                               int x, int y,
                              struct drm_framebuffer *old_fb);                               struct drm_framebuffer *old_fb);
         void (*crtc_enable)(struct drm_crtc *crtc);          void (*crtc_enable)(struct drm_crtc *crtc);
         void (*crtc_disable)(struct drm_crtc *crtc);          void (*crtc_disable)(struct drm_crtc *crtc);
         void (*off)(struct drm_crtc *crtc);          void (*off)(struct drm_crtc *crtc);
         void (*write_eld)(struct drm_connector *connector,          void (*write_eld)(struct drm_connector *connector,
                           struct drm_crtc *crtc);                            struct drm_crtc *crtc,
                             struct drm_display_mode *mode);
         void (*fdi_link_train)(struct drm_crtc *crtc);          void (*fdi_link_train)(struct drm_crtc *crtc);
         void (*init_clock_gating)(struct drm_device *dev);          void (*init_clock_gating)(struct drm_device *dev);
         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,          int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
                           struct drm_framebuffer *fb,                            struct drm_framebuffer *fb,
                           struct drm_i915_gem_object *obj);                            struct drm_i915_gem_object *obj,
         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,                            uint32_t flags);
                             int x, int y);          int (*update_primary_plane)(struct drm_crtc *crtc,
                                       struct drm_framebuffer *fb,
                                       int x, int y);
           void (*hpd_irq_setup)(struct drm_device *dev);
         /* clock updates for mode set */          /* clock updates for mode set */
         /* cursor updates */          /* cursor updates */
         /* render clock increase/decrease */          /* render clock increase/decrease */
         /* display clock increase/decrease */          /* display clock increase/decrease */
         /* pll clock increase/decrease */          /* pll clock increase/decrease */
   
           int (*setup_backlight)(struct intel_connector *connector);
           uint32_t (*get_backlight)(struct intel_connector *connector);
           void (*set_backlight)(struct intel_connector *connector,
                                 uint32_t level);
           void (*disable_backlight)(struct intel_connector *connector);
           void (*enable_backlight)(struct intel_connector *connector);
   };
   
   struct intel_uncore_funcs {
           void (*force_wake_get)(struct drm_i915_private *dev_priv,
                                                           int fw_engine);
           void (*force_wake_put)(struct drm_i915_private *dev_priv,
                                                           int fw_engine);
   
           uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
           uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
           uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
           uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
   
           void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
                                   uint8_t val, bool trace);
           void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
                                   uint16_t val, bool trace);
           void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
                                   uint32_t val, bool trace);
           void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
                                   uint64_t val, bool trace);
   };
   
   struct intel_uncore {
           spinlock_t lock; /** lock is also taken in irq contexts. */
   
           struct intel_uncore_funcs funcs;
   
           unsigned fifo_count;
           unsigned forcewake_count;
   
           unsigned fw_rendercount;
           unsigned fw_mediacount;
   
           struct timer_list force_wake_timer;
 };  };
   
 struct drm_i915_gt_funcs {  #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
         void (*force_wake_get)(struct drm_i915_private *dev_priv);          func(is_mobile) sep \
         void (*force_wake_put)(struct drm_i915_private *dev_priv);          func(is_i85x) sep \
 };          func(is_i915g) sep \
           func(is_i945gm) sep \
 #define DEV_INFO_FLAGS \          func(is_g33) sep \
         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \          func(need_gfx_hws) sep \
         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \          func(is_g4x) sep \
         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \          func(is_pineview) sep \
         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \          func(is_broadwater) sep \
         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \          func(is_crestline) sep \
         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \          func(is_ivybridge) sep \
         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \          func(is_valleyview) sep \
         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \          func(is_haswell) sep \
         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \          func(is_preliminary) sep \
         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \          func(has_fbc) sep \
         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \          func(has_pipe_cxsr) sep \
         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \          func(has_hotplug) sep \
         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \          func(cursor_needs_physical) sep \
         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \          func(has_overlay) sep \
         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \          func(overlay_needs_physical) sep \
         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \          func(supports_tv) sep \
         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \          func(has_llc) sep \
         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \          func(has_ddi) sep \
         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \          func(has_fpga_dbg)
         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \  
         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \  #define DEFINE_FLAG(name) u8 name:1
         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \  #define SEP_SEMICOLON ;
         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \  
         DEV_INFO_FLAG(has_llc)  
   
 struct intel_device_info {  struct intel_device_info {
           u32 display_mmio_offset;
           u8 num_pipes:3;
           u8 num_sprites[I915_MAX_PIPES];
         u8 gen;          u8 gen;
         u8 is_mobile:1;          u8 ring_mask; /* Rings supported by the HW */
         u8 is_i85x:1;          DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
         u8 is_i915g:1;          /* Register offsets for the various display pipes and transcoders */
         u8 is_i945gm:1;          int pipe_offsets[I915_MAX_TRANSCODERS];
         u8 is_g33:1;          int trans_offsets[I915_MAX_TRANSCODERS];
         u8 need_gfx_hws:1;          int dpll_offsets[I915_MAX_PIPES];
         u8 is_g4x:1;          int dpll_md_offsets[I915_MAX_PIPES];
         u8 is_pineview:1;          int palette_offsets[I915_MAX_PIPES];
         u8 is_broadwater:1;  
         u8 is_crestline:1;  
         u8 is_ivybridge:1;  
         u8 is_valleyview:1;  
         u8 has_force_wake:1;  
         u8 is_haswell:1;  
         u8 has_fbc:1;  
         u8 has_pipe_cxsr:1;  
         u8 has_hotplug:1;  
         u8 cursor_needs_physical:1;  
         u8 has_overlay:1;  
         u8 overlay_needs_physical:1;  
         u8 supports_tv:1;  
         u8 has_bsd_ring:1;  
         u8 has_blt_ring:1;  
         u8 has_llc:1;  
 };  };
   
 #define I915_PPGTT_PD_ENTRIES 512  #undef DEFINE_FLAG
 #define I915_PPGTT_PT_ENTRIES 1024  #undef SEP_SEMICOLON
 struct i915_hw_ppgtt {  
   enum i915_cache_level {
           I915_CACHE_NONE = 0,
           I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
           I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
                                 caches, eg sampler/render caches, and the
                                 large Last-Level-Cache. LLC is coherent with
                                 the CPU, but L3 is only visible to the GPU. */
           I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
   };
   
   typedef uint32_t gen6_gtt_pte_t;
   
   /**
    * A VMA represents a GEM BO that is bound into an address space. Therefore, a
    * VMA's presence cannot be guaranteed before binding, or after unbinding the
    * object into/from the address space.
    *
    * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
    * will always be <= an objects lifetime. So object refcounting should cover us.
    */
   struct i915_vma {
           struct drm_mm_node node;
           struct drm_i915_gem_object *obj;
           struct i915_address_space *vm;
   
           /** This object's place on the active/inactive lists */
           struct list_head mm_list;
   
           struct list_head vma_link; /* Link in the object's VMA list */
   
           /** This vma's place in the batchbuffer or on the eviction list */
           struct list_head exec_list;
   
           /**
            * Used for performing relocations during execbuffer insertion.
            */
           struct hlist_node exec_node;
           unsigned long exec_handle;
           struct drm_i915_gem_exec_object2 *exec_entry;
   
           /**
            * How many users have pinned this object in GTT space. The following
            * users can each hold at most one reference: pwrite/pread, pin_ioctl
            * (via user_pin_count), execbuffer (objects are not allowed multiple
            * times for the same batchbuffer), and the framebuffer code. When
            * switching/pageflipping, the framebuffer code has at most two buffers
            * pinned per crtc.
            *
            * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
            * bits with absolutely no headroom. So use 4 bits. */
           unsigned int pin_count:4;
   #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
   
           /** Unmap an object from an address space. This usually consists of
            * setting the valid PTE entries to a reserved scratch page. */
           void (*unbind_vma)(struct i915_vma *vma);
           /* Map an object into an address space with the given cache flags. */
   #define GLOBAL_BIND (1<<0)
           void (*bind_vma)(struct i915_vma *vma,
                            enum i915_cache_level cache_level,
                            u32 flags);
   };
   
   struct i915_address_space {
           struct drm_mm mm;
         struct drm_device *dev;          struct drm_device *dev;
         unsigned num_pd_entries;          struct list_head global_link;
         struct page **pt_pages;          unsigned long start;            /* Start offset always 0 for dri2 */
         uint32_t pd_offset;          size_t total;           /* size addr space maps (ex. 2GB for ggtt) */
         dma_addr_t *pt_dma_addr;  
         dma_addr_t scratch_page_dma_addr;          struct {
                   dma_addr_t addr;
                   struct page *page;
           } scratch;
   
           /**
            * List of objects currently involved in rendering.
            *
            * Includes buffers having the contents of their GPU caches
            * flushed, not necessarily primitives.  last_rendering_seqno
            * represents when the rendering involved will be completed.
            *
            * A reference is held on the buffer while on this list.
            */
           struct list_head active_list;
   
           /**
            * LRU list of objects which are not in the ringbuffer and
            * are ready to unbind, but are still in the GTT.
            *
            * last_rendering_seqno is 0 while an object is in this list.
            *
            * A reference is not held on the buffer while on this list,
            * as merely being GTT-bound shouldn't prevent its being
            * freed, and we'll pull it off the list in the free path.
            */
           struct list_head inactive_list;
   
           /* FIXME: Need a more generic return type */
           gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
                                        enum i915_cache_level level,
                                        bool valid); /* Create a valid PTE */
           void (*clear_range)(struct i915_address_space *vm,
                               uint64_t start,
                               uint64_t length,
                               bool use_scratch);
           void (*insert_entries)(struct i915_address_space *vm,
                                  struct sg_table *st,
                                  uint64_t start,
                                  enum i915_cache_level cache_level);
           void (*cleanup)(struct i915_address_space *vm);
   };
   
   /* The Graphics Translation Table is the way in which GEN hardware translates a
    * Graphics Virtual Address into a Physical Address. In addition to the normal
    * collateral associated with any va->pa translations GEN hardware also has a
    * portion of the GTT which can be mapped by the CPU and remain both coherent
    * and correct (in cases like swizzling). That region is referred to as GMADR in
    * the spec.
    */
   struct i915_gtt {
           struct i915_address_space base;
           size_t stolen_size;             /* Total size of stolen memory */
   
           unsigned long mappable_end;     /* End offset that we can CPU map */
           struct io_mapping *mappable;    /* Mapping to our CPU mappable region */
           phys_addr_t mappable_base;      /* PA of our GMADR */
   
           /** "Graphics Stolen Memory" holds the global PTEs */
           void __iomem *gsm;
   
           bool do_idle_maps;
   
           int mtrr;
   
           /* global gtt ops */
           int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
                             size_t *stolen, phys_addr_t *mappable_base,
                             unsigned long *mappable_end);
 };  };
   #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
   
   #define GEN8_LEGACY_PDPS 4
   struct i915_hw_ppgtt {
           struct i915_address_space base;
           struct kref ref;
           struct drm_mm_node node;
           unsigned num_pd_entries;
           unsigned num_pd_pages; /* gen8+ */
           union {
                   struct page **pt_pages;
                   struct page **gen8_pt_pages[GEN8_LEGACY_PDPS];
           };
           struct page *pd_pages;
           union {
                   uint32_t pd_offset;
                   dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS];
           };
           union {
                   dma_addr_t *pt_dma_addr;
                   dma_addr_t *gen8_pt_dma_addr[4];
           };
   
           struct i915_hw_context *ctx;
   
           int (*enable)(struct i915_hw_ppgtt *ppgtt);
           int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
                            struct intel_ring_buffer *ring,
                            bool synchronous);
           void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
   };
   
   struct i915_ctx_hang_stats {
           /* This context had batch pending when hang was declared */
           unsigned batch_pending;
   
           /* This context had batch active when hang was declared */
           unsigned batch_active;
   
           /* Time when this context was last blamed for a GPU reset */
           unsigned long guilty_ts;
   
           /* This context is banned to submit more work */
           bool banned;
   };
   
 /* This must match up with the value previously used for execbuf2.rsvd1. */  /* This must match up with the value previously used for execbuf2.rsvd1. */
 #define DEFAULT_CONTEXT_ID 0  #define DEFAULT_CONTEXT_ID 0
 struct i915_hw_context {  struct i915_hw_context {
           struct kref ref;
         int id;          int id;
         bool is_initialized;          bool is_initialized;
           uint8_t remap_slice;
         struct drm_i915_file_private *file_priv;          struct drm_i915_file_private *file_priv;
         struct intel_ring_buffer *ring;          struct intel_ring_buffer *last_ring;
         struct drm_i915_gem_object *obj;          struct drm_i915_gem_object *obj;
           struct i915_ctx_hang_stats hang_stats;
           struct i915_address_space *vm;
   
           struct list_head link;
 };  };
   
 enum no_fbc_reason {  struct i915_fbc {
         FBC_NO_OUTPUT, /* no outputs enabled to compress */          unsigned long size;
         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */          unsigned int fb_id;
         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */          enum plane plane;
         FBC_MODE_TOO_LARGE, /* mode too large for compression */          int y;
         FBC_BAD_PLANE, /* fbc not supported on plane */  
         FBC_NOT_TILED, /* buffer not tiled */          struct drm_mm_node *compressed_fb;
         FBC_MULTIPLE_PIPES, /* more than one pipe active */          struct drm_mm_node *compressed_llb;
         FBC_MODULE_PARAM,  
           struct intel_fbc_work {
                   struct delayed_work work;
                   struct drm_crtc *crtc;
                   struct drm_framebuffer *fb;
           } *fbc_work;
   
           enum no_fbc_reason {
                   FBC_OK, /* FBC is enabled */
                   FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
                   FBC_NO_OUTPUT, /* no outputs enabled to compress */
                   FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
                   FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
                   FBC_MODE_TOO_LARGE, /* mode too large for compression */
                   FBC_BAD_PLANE, /* fbc not supported on plane */
                   FBC_NOT_TILED, /* buffer not tiled */
                   FBC_MULTIPLE_PIPES, /* more than one pipe active */
                   FBC_MODULE_PARAM,
                   FBC_CHIP_DEFAULT, /* disabled by default on this chip */
           } no_fbc_reason;
   };
   
   struct i915_psr {
           bool sink_support;
           bool source_ok;
 };  };
   
 enum intel_pch {  enum intel_pch {
Line 394  enum intel_pch {
Line 792  enum intel_pch {
         PCH_IBX,        /* Ibexpeak PCH */          PCH_IBX,        /* Ibexpeak PCH */
         PCH_CPT,        /* Cougarpoint PCH */          PCH_CPT,        /* Cougarpoint PCH */
         PCH_LPT,        /* Lynxpoint PCH */          PCH_LPT,        /* Lynxpoint PCH */
           PCH_NOP,
 };  };
   
 enum intel_sbi_destination {  enum intel_sbi_destination {
Line 455  struct i915_suspend_saved_registers {
Line 854  struct i915_suspend_saved_registers {
         u32 saveBLC_HIST_CTL;          u32 saveBLC_HIST_CTL;
         u32 saveBLC_PWM_CTL;          u32 saveBLC_PWM_CTL;
         u32 saveBLC_PWM_CTL2;          u32 saveBLC_PWM_CTL2;
           u32 saveBLC_HIST_CTL_B;
         u32 saveBLC_CPU_PWM_CTL;          u32 saveBLC_CPU_PWM_CTL;
         u32 saveBLC_CPU_PWM_CTL2;          u32 saveBLC_CPU_PWM_CTL2;
         u32 saveFPB0;          u32 saveFPB0;
Line 500  struct i915_suspend_saved_registers {
Line 900  struct i915_suspend_saved_registers {
         u32 savePFIT_CONTROL;          u32 savePFIT_CONTROL;
         u32 save_palette_a[256];          u32 save_palette_a[256];
         u32 save_palette_b[256];          u32 save_palette_b[256];
         u32 saveDPFC_CB_BASE;  
         u32 saveFBC_CFB_BASE;  
         u32 saveFBC_LL_BASE;  
         u32 saveFBC_CONTROL;          u32 saveFBC_CONTROL;
         u32 saveFBC_CONTROL2;  
         u32 saveIER;          u32 saveIER;
         u32 saveIIR;          u32 saveIIR;
         u32 saveIMR;          u32 saveIMR;
Line 570  struct i915_suspend_saved_registers {
Line 966  struct i915_suspend_saved_registers {
 };  };
   
 struct intel_gen6_power_mgmt {  struct intel_gen6_power_mgmt {
           /* work and pm_iir are protected by dev_priv->irq_lock */
         struct work_struct work;          struct work_struct work;
         u32 pm_iir;          u32 pm_iir;
         /* lock - irqsave spinlock that protectects the work_struct and  
          * pm_iir. */  
         spinlock_t lock;  
   
         /* The below variables an all the rps hw state are protected by          /* Frequencies are stored in potentially platform dependent multiples.
          * dev->struct mutext. */           * In other words, *_freq needs to be multiplied by X to be interesting.
         u8 cur_delay;           * Soft limits are those which are used for the dynamic reclocking done
         u8 min_delay;           * by the driver (raise frequencies under heavy loads, and lower for
         u8 max_delay;           * lighter loads). Hard limits are those imposed by the hardware.
            *
            * A distinction is made for overclocking, which is never enabled by
            * default, and is considered to be above the hard limit if it's
            * possible at all.
            */
           u8 cur_freq;            /* Current frequency (cached, may not == HW) */
           u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
           u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
           u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
           u8 min_freq;            /* AKA RPn. Minimum frequency */
           u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
           u8 rp1_freq;            /* "less than" RP0 power/freqency */
           u8 rp0_freq;            /* Non-overclocked max frequency. */
   
           int last_adj;
           enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
   
           bool enabled;
         struct delayed_work delayed_resume_work;          struct delayed_work delayed_resume_work;
   
         /*          /*
Line 591  struct intel_gen6_power_mgmt {
Line 1002  struct intel_gen6_power_mgmt {
         struct mutex hw_lock;          struct mutex hw_lock;
 };  };
   
   /* defined intel_pm.c */
   extern spinlock_t mchdev_lock;
   
 struct intel_ilk_power_mgmt {  struct intel_ilk_power_mgmt {
         u8 cur_delay;          u8 cur_delay;
         u8 min_delay;          u8 min_delay;
Line 613  struct intel_ilk_power_mgmt {
Line 1027  struct intel_ilk_power_mgmt {
         struct drm_i915_gem_object *renderctx;          struct drm_i915_gem_object *renderctx;
 };  };
   
   struct drm_i915_private;
   struct i915_power_well;
   
   struct i915_power_well_ops {
           /*
            * Synchronize the well's hw state to match the current sw state, for
            * example enable/disable it based on the current refcount. Called
            * during driver init and resume time, possibly after first calling
            * the enable/disable handlers.
            */
           void (*sync_hw)(struct drm_i915_private *dev_priv,
                           struct i915_power_well *power_well);
           /*
            * Enable the well and resources that depend on it (for example
            * interrupts located on the well). Called after the 0->1 refcount
            * transition.
            */
           void (*enable)(struct drm_i915_private *dev_priv,
                          struct i915_power_well *power_well);
           /*
            * Disable the well and resources that depend on it. Called after
            * the 1->0 refcount transition.
            */
           void (*disable)(struct drm_i915_private *dev_priv,
                           struct i915_power_well *power_well);
           /* Returns the hw enabled state. */
           bool (*is_enabled)(struct drm_i915_private *dev_priv,
                              struct i915_power_well *power_well);
   };
   
   /* Power well structure for haswell */
   struct i915_power_well {
           const char *name;
           bool always_on;
           /* power well enable/disable usage count */
           int count;
           unsigned long domains;
           unsigned long data;
           const struct i915_power_well_ops *ops;
   };
   
   struct i915_power_domains {
           /*
            * Power wells needed for initialization at driver init and suspend
            * time are on. They are kept on until after the first modeset.
            */
           bool init_power_on;
           int power_well_count;
   
           struct mutex lock;
           int domain_use_count[POWER_DOMAIN_NUM];
           struct i915_power_well *power_wells;
   };
   
 struct i915_dri1_state {  struct i915_dri1_state {
         unsigned allow_batchbuffer : 1;          unsigned allow_batchbuffer : 1;
 #ifdef __NetBSD__  
         struct drm_local_map gfx_hws_cpu_map;  
 #else  
         u32 __iomem *gfx_hws_cpu_addr;          u32 __iomem *gfx_hws_cpu_addr;
 #endif  
   
         unsigned int cpp;          unsigned int cpp;
         int back_offset;          int back_offset;
Line 630  struct i915_dri1_state {
Line 1094  struct i915_dri1_state {
         uint32_t counter;          uint32_t counter;
 };  };
   
   struct i915_ums_state {
           /**
            * Flag if the X Server, and thus DRM, is not currently in
            * control of the device.
            *
            * This is set between LeaveVT and EnterVT.  It needs to be
            * replaced with a semaphore.  It also needs to be
            * transitioned away from for kernel modesetting.
            */
           int mm_suspended;
   };
   
   #define MAX_L3_SLICES 2
 struct intel_l3_parity {  struct intel_l3_parity {
         u32 *remap_info;          u32 *remap_info[MAX_L3_SLICES];
         struct work_struct error_work;          struct work_struct error_work;
           int which_slice;
   };
   
   struct i915_gem_mm {
           /** Memory allocator for GTT stolen memory */
           struct drm_mm stolen;
           /** List of all objects in gtt_space. Used to restore gtt
            * mappings on resume */
           struct list_head bound_list;
           /**
            * List of objects which are not bound to the GTT (thus
            * are idle and not used by the GPU) but still have
            * (presumably uncached) pages still attached.
            */
           struct list_head unbound_list;
   
           /** Usable portion of the GTT for GEM */
           unsigned long stolen_base; /* limited to low memory (32-bit) */
   
           /** PPGTT used for aliasing the PPGTT with the GTT */
           struct i915_hw_ppgtt *aliasing_ppgtt;
   
           struct shrinker inactive_shrinker;
           bool shrinker_no_lock_stealing;
   
           /** LRU list of objects with fence regs on them. */
           struct list_head fence_list;
   
           /**
            * We leave the user IRQ off as much as possible,
            * but this means that requests will finish and never
            * be retired once the system goes idle. Set a timer to
            * fire periodically while the ring is running. When it
            * fires, go retire requests.
            */
           struct delayed_work retire_work;
   
           /**
            * When we detect an idle GPU, we want to turn on
            * powersaving features. So once we see that there
            * are no more requests outstanding and no more
            * arrive within a small period of time, we fire
            * off the idle_work.
            */
           struct delayed_work idle_work;
   
           /**
            * Are we in a non-interruptible section of code like
            * modesetting?
            */
           bool interruptible;
   
           /**
            * Is the GPU currently considered idle, or busy executing userspace
            * requests?  Whilst idle, we attempt to power down the hardware and
            * display clocks. In order to reduce the effect on performance, there
            * is a slight delay before we do so.
            */
           bool busy;
   
           /** Bit 6 swizzling required for X tiling */
           uint32_t bit_6_swizzle_x;
           /** Bit 6 swizzling required for Y tiling */
           uint32_t bit_6_swizzle_y;
   
           /* accounting, useful for userland debugging */
           spinlock_t object_stat_lock;
           size_t object_memory;
           u32 object_count;
   };
   
   struct drm_i915_error_state_buf {
           unsigned bytes;
           unsigned size;
           int err;
           u8 *buf;
           loff_t start;
           loff_t pos;
   };
   
   struct i915_error_state_file_priv {
           struct drm_device *dev;
           struct drm_i915_error_state *error;
   };
   
   struct i915_gpu_error {
           /* For hangcheck timer */
   #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
   #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
           /* Hang gpu twice in this window and your context gets banned */
   #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
   
           struct timer_list hangcheck_timer;
   
           /* For reset and error_state handling. */
           spinlock_t lock;
           /* Protected by the above dev->gpu_error.lock. */
           struct drm_i915_error_state *first_error;
           struct work_struct work;
   
   
           unsigned long missed_irq_rings;
   
           /**
            * State variable controlling the reset flow and count
            *
            * This is a counter which gets incremented when reset is triggered,
            * and again when reset has been handled. So odd values (lowest bit set)
            * means that reset is in progress and even values that
            * (reset_counter >> 1):th reset was successfully completed.
            *
            * If reset is not completed succesfully, the I915_WEDGE bit is
            * set meaning that hardware is terminally sour and there is no
            * recovery. All waiters on the reset_queue will be woken when
            * that happens.
            *
            * This counter is used by the wait_seqno code to notice that reset
            * event happened and it needs to restart the entire ioctl (since most
            * likely the seqno it waited for won't ever signal anytime soon).
            *
            * This is important for lock-free wait paths, where no contended lock
            * naturally enforces the correct ordering between the bail-out of the
            * waiter and the gpu reset work code.
            */
           atomic_t reset_counter;
   
   #define I915_RESET_IN_PROGRESS_FLAG     1
   #define I915_WEDGED                     (1 << 31)
   
           /**
            * Waitqueue to signal when the reset has completed. Used by clients
            * that wait for dev_priv->mm.wedged to settle.
            */
           wait_queue_head_t reset_queue;
   
           /* For gpu hang simulation. */
           unsigned int stop_rings;
   
           /* For missed irq/seqno simulation. */
           unsigned int test_irq_rings;
   };
   
   enum modeset_restore {
           MODESET_ON_LID_OPEN,
           MODESET_DONE,
           MODESET_SUSPENDED,
   };
   
   struct ddi_vbt_port_info {
           uint8_t hdmi_level_shift;
   
           uint8_t supports_dvi:1;
           uint8_t supports_hdmi:1;
           uint8_t supports_dp:1;
   };
   
   struct intel_vbt_data {
           struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
           struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
   
           /* Feature bits */
           unsigned int int_tv_support:1;
           unsigned int lvds_dither:1;
           unsigned int lvds_vbt:1;
           unsigned int int_crt_support:1;
           unsigned int lvds_use_ssc:1;
           unsigned int display_clock_mode:1;
           unsigned int fdi_rx_polarity_inverted:1;
           int lvds_ssc_freq;
           unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
   
           /* eDP */
           int edp_rate;
           int edp_lanes;
           int edp_preemphasis;
           int edp_vswing;
           bool edp_initialized;
           bool edp_support;
           int edp_bpp;
           struct edp_power_seq edp_pps;
   
           struct {
                   u16 pwm_freq_hz;
                   bool present;
                   bool active_low_pwm;
           } backlight;
   
           /* MIPI DSI */
           struct {
                   u16 panel_id;
           } dsi;
   
           int crt_ddc_pin;
   
           int child_dev_num;
           union child_device_config *child_dev;
   
           struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
   };
   
   enum intel_ddb_partitioning {
           INTEL_DDB_PART_1_2,
           INTEL_DDB_PART_5_6, /* IVB+ */
   };
   
   struct intel_wm_level {
           bool enable;
           uint32_t pri_val;
           uint32_t spr_val;
           uint32_t cur_val;
           uint32_t fbc_val;
   };
   
   struct ilk_wm_values {
           uint32_t wm_pipe[3];
           uint32_t wm_lp[3];
           uint32_t wm_lp_spr[3];
           uint32_t wm_linetime[3];
           bool enable_fbc_wm;
           enum intel_ddb_partitioning partitioning;
   };
   
   /*
    * This struct helps tracking the state needed for runtime PM, which puts the
    * device in PCI D3 state. Notice that when this happens, nothing on the
    * graphics device works, even register access, so we don't get interrupts nor
    * anything else.
    *
    * Every piece of our code that needs to actually touch the hardware needs to
    * either call intel_runtime_pm_get or call intel_display_power_get with the
    * appropriate power domain.
    *
    * Our driver uses the autosuspend delay feature, which means we'll only really
    * suspend if we stay with zero refcount for a certain amount of time. The
    * default value is currently very conservative (see intel_init_runtime_pm), but
    * it can be changed with the standard runtime PM files from sysfs.
    *
    * The irqs_disabled variable becomes true exactly after we disable the IRQs and
    * goes back to false exactly before we reenable the IRQs. We use this variable
    * to check if someone is trying to enable/disable IRQs while they're supposed
    * to be disabled. This shouldn't happen and we'll print some error messages in
    * case it happens, but if it actually happens we'll also update the variables
    * inside struct regsave so when we restore the IRQs they will contain the
    * latest expected values.
    *
    * For more, read the Documentation/power/runtime_pm.txt.
    */
   struct i915_runtime_pm {
           bool suspended;
           bool irqs_disabled;
   
           struct {
                   uint32_t deimr;
                   uint32_t sdeimr;
                   uint32_t gtimr;
                   uint32_t gtier;
                   uint32_t gen6_pmimr;
           } regsave;
   };
   
   enum intel_pipe_crc_source {
           INTEL_PIPE_CRC_SOURCE_NONE,
           INTEL_PIPE_CRC_SOURCE_PLANE1,
           INTEL_PIPE_CRC_SOURCE_PLANE2,
           INTEL_PIPE_CRC_SOURCE_PF,
           INTEL_PIPE_CRC_SOURCE_PIPE,
           /* TV/DP on pre-gen5/vlv can't use the pipe source. */
           INTEL_PIPE_CRC_SOURCE_TV,
           INTEL_PIPE_CRC_SOURCE_DP_B,
           INTEL_PIPE_CRC_SOURCE_DP_C,
           INTEL_PIPE_CRC_SOURCE_DP_D,
           INTEL_PIPE_CRC_SOURCE_AUTO,
           INTEL_PIPE_CRC_SOURCE_MAX,
   };
   
   struct intel_pipe_crc_entry {
           uint32_t frame;
           uint32_t crc[5];
   };
   
   #define INTEL_PIPE_CRC_ENTRIES_NR       128
   struct intel_pipe_crc {
           spinlock_t lock;
           bool opened;            /* exclusive access to the result file */
           struct intel_pipe_crc_entry *entries;
           enum intel_pipe_crc_source source;
           int head, tail;
           wait_queue_head_t wq;
 };  };
   
 typedef struct drm_i915_private {  typedef struct drm_i915_private {
         struct drm_device *dev;          struct drm_device *dev;
           struct kmem_cache *slab;
   
         const struct intel_device_info *info;          const struct intel_device_info info;
   
         int relative_constants_mode;          int relative_constants_mode;
   
 #ifdef __NetBSD__  
         struct drm_local_map *regs_map;  
 #else  
         void __iomem *regs;          void __iomem *regs;
 #endif  
   
         struct drm_i915_gt_funcs gt;          struct intel_uncore uncore;
         /** gt_fifo_count and the subsequent register write are synchronized  
          * with dev->struct_mutex. */  
         unsigned gt_fifo_count;  
         /** forcewake_count is protected by gt_lock */  
         unsigned forcewake_count;  
         /** gt_lock is also taken in irq contexts. */  
         struct spinlock gt_lock;  
   
         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];          struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
   
   
         /** gmbus_mutex protects against concurrent usage of the single hw gmbus          /** gmbus_mutex protects against concurrent usage of the single hw gmbus
          * controller on different i2c buses. */           * controller on different i2c buses. */
         struct mutex gmbus_mutex;          struct mutex gmbus_mutex;
Line 668  typedef struct drm_i915_private {
Line 1424  typedef struct drm_i915_private {
          */           */
         uint32_t gpio_mmio_base;          uint32_t gpio_mmio_base;
   
           wait_queue_head_t gmbus_wait_queue;
   
         struct pci_dev *bridge_dev;          struct pci_dev *bridge_dev;
         struct intel_ring_buffer ring[I915_NUM_RINGS];          struct intel_ring_buffer ring[I915_NUM_RINGS];
         uint32_t next_seqno;          uint32_t last_seqno, next_seqno;
   
         drm_dma_handle_t *status_page_dmah;          drm_dma_handle_t *status_page_dmah;
         struct resource mch_res;          struct resource mch_res;
   
         atomic_t irq_received;  
   
         /* protects the irq masks */          /* protects the irq masks */
         spinlock_t irq_lock;          spinlock_t irq_lock;
   
           bool display_irqs_enabled;
   
           /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
           struct pm_qos_request pm_qos;
   
         /* DPIO indirect register protection */          /* DPIO indirect register protection */
         spinlock_t dpio_lock;          struct mutex dpio_lock;
   
         /** Cached value of IMR to avoid reads in updating the bitfield */          /** Cached value of IMR to avoid reads in updating the bitfield */
         u32 pipestat[2];          union {
         u32 irq_mask;                  u32 irq_mask;
                   u32 de_irq_mask[I915_MAX_PIPES];
           };
         u32 gt_irq_mask;          u32 gt_irq_mask;
         u32 pch_irq_mask;          u32 pm_irq_mask;
           u32 pm_rps_events;
           u32 pipestat_irq_mask[I915_MAX_PIPES];
   
         u32 hotplug_supported_mask;  
         struct work_struct hotplug_work;          struct work_struct hotplug_work;
           bool enable_hotplug_processing;
           struct {
                   unsigned long hpd_last_jiffies;
                   int hpd_cnt;
                   enum {
                           HPD_ENABLED = 0,
                           HPD_DISABLED = 1,
                           HPD_MARK_DISABLED = 2
                   } hpd_mark;
           } hpd_stats[HPD_NUM_PINS];
           u32 hpd_event_bits;
           struct timer_list hotplug_reenable_timer;
   
         int num_pipe;          struct i915_fbc fbc;
         int num_pch_pll;  
   
         /* For hangcheck timer */  
 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */  
 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)  
         struct timer_list hangcheck_timer;  
         int hangcheck_count;  
         uint32_t last_acthd[I915_NUM_RINGS];  
         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];  
   
         unsigned int stop_rings;  
   
         unsigned long cfb_size;  
         unsigned int cfb_fb;  
         enum plane cfb_plane;  
         int cfb_y;  
         struct intel_fbc_work *fbc_work;  
   
         struct intel_opregion opregion;          struct intel_opregion opregion;
           struct intel_vbt_data vbt;
   
         /* overlay */          /* overlay */
         struct intel_overlay *overlay;          struct intel_overlay *overlay;
         bool sprite_scaling_enabled;  
           /* backlight registers and fields in struct intel_panel */
         /* LVDS info */          spinlock_t backlight_lock;
         int backlight_level;  /* restore backlight to this value */  
         bool backlight_enabled;          /* LVDS info */
         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */  
         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */  
   
         /* Feature bits from the VBIOS */  
         unsigned int int_tv_support:1;  
         unsigned int lvds_dither:1;  
         unsigned int lvds_vbt:1;  
         unsigned int int_crt_support:1;  
         unsigned int lvds_use_ssc:1;  
         unsigned int display_clock_mode:1;  
         int lvds_ssc_freq;  
         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */  
         unsigned int lvds_val; /* used for checking LVDS channel mode */  
         struct {  
                 int rate;  
                 int lanes;  
                 int preemphasis;  
                 int vswing;  
   
                 bool initialized;  
                 bool support;  
                 int bpp;  
                 struct edp_power_seq pps;  
         } edp;  
         bool no_aux_handshake;          bool no_aux_handshake;
   
         int crt_ddc_pin;  
         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */          struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */          int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
         int num_fence_regs; /* 8 on pre-965, 16 otherwise */          int num_fence_regs; /* 8 on pre-965, 16 otherwise */
   
         unsigned int fsb_freq, mem_freq, is_ddr3;          unsigned int fsb_freq, mem_freq, is_ddr3;
   
         spinlock_t error_lock;          /**
         /* Protected by dev->error_lock. */           * wq - Driver workqueue for GEM.
         struct drm_i915_error_state *first_error;           *
         struct work_struct error_work;           * NOTE: Work items scheduled here are not allowed to grab any modeset
         struct completion error_completion;           * locks, for otherwise the flushing done in the pageflip code will
            * result in deadlocks.
            */
         struct workqueue_struct *wq;          struct workqueue_struct *wq;
   
         /* Display functions */          /* Display functions */
Line 769  typedef struct drm_i915_private {
Line 1505  typedef struct drm_i915_private {
   
         unsigned long quirks;          unsigned long quirks;
   
         /* Register state */          enum modeset_restore modeset_restore;
         bool modeset_on_lid;          struct mutex modeset_restore_lock;
   
         struct {  
                 /** Bridge to intel-gtt-ko */  
                 struct intel_gtt *gtt;  
                 /** Memory allocator for GTT stolen memory */  
                 struct drm_mm stolen;  
                 /** Memory allocator for GTT */  
                 struct drm_mm gtt_space;  
                 /** List of all objects in gtt_space. Used to restore gtt  
                  * mappings on resume */  
                 struct list_head bound_list;  
                 /**  
                  * List of objects which are not bound to the GTT (thus  
                  * are idle and not used by the GPU) but still have  
                  * (presumably uncached) pages still attached.  
                  */  
                 struct list_head unbound_list;  
   
                 /** Usable portion of the GTT for GEM */  
                 unsigned long gtt_start;  
                 unsigned long gtt_mappable_end;  
                 unsigned long gtt_end;  
   
                 struct io_mapping *gtt_mapping;  
                 phys_addr_t gtt_base_addr;  
                 int gtt_mtrr;  
   
                 /** PPGTT used for aliasing the PPGTT with the GTT */  
                 struct i915_hw_ppgtt *aliasing_ppgtt;  
   
                 struct shrinker inactive_shrinker;  
                 bool shrinker_no_lock_stealing;  
   
                 /**  
                  * List of objects currently involved in rendering.  
                  *  
                  * Includes buffers having the contents of their GPU caches  
                  * flushed, not necessarily primitives.  last_rendering_seqno  
                  * represents when the rendering involved will be completed.  
                  *  
                  * A reference is held on the buffer while on this list.  
                  */  
                 struct list_head active_list;  
   
                 /**  
                  * LRU list of objects which are not in the ringbuffer and  
                  * are ready to unbind, but are still in the GTT.  
                  *  
                  * last_rendering_seqno is 0 while an object is in this list.  
                  *  
                  * A reference is not held on the buffer while on this list,  
                  * as merely being GTT-bound shouldn't prevent its being  
                  * freed, and we'll pull it off the list in the free path.  
                  */  
                 struct list_head inactive_list;  
   
                 /** LRU list of objects with fence regs on them. */  
                 struct list_head fence_list;  
   
                 /**  
                  * We leave the user IRQ off as much as possible,  
                  * but this means that requests will finish and never  
                  * be retired once the system goes idle. Set a timer to  
                  * fire periodically while the ring is running. When it  
                  * fires, go retire requests.  
                  */  
                 struct delayed_work retire_work;  
   
                 /**  
                  * Are we in a non-interruptible section of code like  
                  * modesetting?  
                  */  
                 bool interruptible;  
   
                 /**  
                  * Flag if the X Server, and thus DRM, is not currently in  
                  * control of the device.  
                  *  
                  * This is set between LeaveVT and EnterVT.  It needs to be  
                  * replaced with a semaphore.  It also needs to be  
                  * transitioned away from for kernel modesetting.  
                  */  
                 int suspended;  
   
                 /**          struct list_head vm_list; /* Global list of all address spaces */
                  * Flag if the hardware appears to be wedged.          struct i915_gtt gtt; /* VMA representing the global address space */
                  *  
                  * This is set when attempts to idle the device timeout.  
                  * It prevents command submission from occurring and makes  
                  * every pending request fail  
                  */  
                 atomic_t wedged;  
   
                 /** Bit 6 swizzling required for X tiling */          struct i915_gem_mm mm;
                 uint32_t bit_6_swizzle_x;  
                 /** Bit 6 swizzling required for Y tiling */  
                 uint32_t bit_6_swizzle_y;  
   
                 /* storage for physical objects */  
                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];  
   
                 /* accounting, useful for userland debugging */  
                 size_t gtt_total;  
                 size_t mappable_gtt_total;  
                 size_t object_memory;  
                 u32 object_count;  
         } mm;  
   
         /* Kernel Modesetting */          /* Kernel Modesetting */
   
         struct sdvo_device_mapping sdvo_mappings[2];          struct sdvo_device_mapping sdvo_mappings[2];
         /* indicate whether the LVDS_BORDER should be enabled or not */  
         unsigned int lvds_border_bits;          struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
         /* Panel fitter placement and size for Ironlake+ */          struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
         u32 pch_pf_pos, pch_pf_size;  
   
         struct drm_crtc *plane_to_crtc_mapping[3];  
         struct drm_crtc *pipe_to_crtc_mapping[3];  
 #ifdef __NetBSD__  
         /* XXX The locking scheme looks broken.  This mutex is a stop-gap.  */  
         struct mutex pending_flip_lock;  
         drm_waitqueue_t pending_flip_queue;  
 #else  
         wait_queue_head_t pending_flip_queue;          wait_queue_head_t pending_flip_queue;
   
   #ifdef CONFIG_DEBUG_FS
           struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
 #endif  #endif
   
         struct intel_pch_pll pch_plls[I915_NUM_PLLS];          int num_shared_dpll;
           struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
         struct intel_ddi_plls ddi_plls;          struct intel_ddi_plls ddi_plls;
           int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
   
         /* Reclocking support */          /* Reclocking support */
         bool render_reclock_avail;          bool render_reclock_avail;
Line 906  typedef struct drm_i915_private {
Line 1536  typedef struct drm_i915_private {
         /* indicates the reduced downclock for LVDS*/          /* indicates the reduced downclock for LVDS*/
         int lvds_downclock;          int lvds_downclock;
         u16 orig_clock;          u16 orig_clock;
         int child_dev_num;  
         struct child_device_config *child_dev;  
   
         bool mchbar_need_disable;          bool mchbar_need_disable;
   
         struct intel_l3_parity l3_parity;          struct intel_l3_parity l3_parity;
   
           /* Cannot be determined by PCIID. You must always read a register. */
           size_t ellc_size;
   
         /* gen6+ rps state */          /* gen6+ rps state */
         struct intel_gen6_power_mgmt rps;          struct intel_gen6_power_mgmt rps;
   
Line 920  typedef struct drm_i915_private {
Line 1551  typedef struct drm_i915_private {
          * mchdev_lock in intel_pm.c */           * mchdev_lock in intel_pm.c */
         struct intel_ilk_power_mgmt ips;          struct intel_ilk_power_mgmt ips;
   
         enum no_fbc_reason no_fbc_reason;          struct i915_power_domains power_domains;
   
         struct drm_mm_node *compressed_fb;          struct i915_psr psr;
         struct drm_mm_node *compressed_llb;  
   
 #ifdef __NetBSD__          struct i915_gpu_error gpu_error;
         time_t last_gpu_reset;  
 #else          struct drm_i915_gem_object *vlv_pctx;
         unsigned long last_gpu_reset;  
 #endif  
   
   #ifdef CONFIG_DRM_I915_FBDEV
         /* list of fbdev register on this device */          /* list of fbdev register on this device */
         struct intel_fbdev *fbdev;          struct intel_fbdev *fbdev;
   #endif
   
         /*          /*
          * The console may be contended at resume, but we don't           * The console may be contended at resume, but we don't
Line 940  typedef struct drm_i915_private {
Line 1570  typedef struct drm_i915_private {
          */           */
         struct work_struct console_resume_work;          struct work_struct console_resume_work;
   
         struct backlight_device *backlight;  
   
         struct drm_property *broadcast_rgb_property;          struct drm_property *broadcast_rgb_property;
         struct drm_property *force_audio_property;          struct drm_property *force_audio_property;
   
         bool hw_contexts_disabled;  
         uint32_t hw_context_size;          uint32_t hw_context_size;
           struct list_head context_list;
   
         bool fdi_rx_polarity_reversed;          u32 fdi_rx_config;
   
           u32 suspend_count;
         struct i915_suspend_saved_registers regfile;          struct i915_suspend_saved_registers regfile;
   
           struct {
                   /*
                    * Raw watermark latency values:
                    * in 0.1us units for WM0,
                    * in 0.5us units for WM1+.
                    */
                   /* primary */
                   uint16_t pri_latency[5];
                   /* sprite */
                   uint16_t spr_latency[5];
                   /* cursor */
                   uint16_t cur_latency[5];
   
                   /* current hardware state */
                   struct ilk_wm_values hw;
           } wm;
   
           struct i915_runtime_pm pm;
   
         /* Old dri1 support infrastructure, beware the dragons ya fools entering          /* Old dri1 support infrastructure, beware the dragons ya fools entering
          * here! */           * here! */
         struct i915_dri1_state dri1;          struct i915_dri1_state dri1;
           /* Old ums support infrastructure, same warning applies. */
           struct i915_ums_state ums;
 } drm_i915_private_t;  } drm_i915_private_t;
   
   static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
   {
           return dev->dev_private;
   }
   
 /* Iterate over initialised rings */  /* Iterate over initialised rings */
 #define for_each_ring(ring__, dev_priv__, i__) \  #define for_each_ring(ring__, dev_priv__, i__) \
         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \          for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
Line 969  enum hdmi_force_audio {
Line 1624  enum hdmi_force_audio {
         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */          HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 };  };
   
 enum i915_cache_level {  #define I915_GTT_OFFSET_NONE ((u32)-1)
         I915_CACHE_NONE = 0,  
         I915_CACHE_LLC,  
         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */  
 };  
   
 struct drm_i915_gem_object_ops {  struct drm_i915_gem_object_ops {
         /* Interface between the GEM object and its backing storage.          /* Interface between the GEM object and its backing storage.
Line 998  struct drm_i915_gem_object {
Line 1649  struct drm_i915_gem_object {
   
         const struct drm_i915_gem_object_ops *ops;          const struct drm_i915_gem_object_ops *ops;
   
         /** Current space allocated to this object in the GTT, if any. */          /** List of VMAs backed by this object */
         struct drm_mm_node *gtt_space;          struct list_head vma_list;
         struct list_head gtt_list;  
           /** Stolen memory for this object, instead of being backed by shmem. */
           struct drm_mm_node *stolen;
           struct list_head global_list;
   
         /** This object's place on the active/inactive lists */  
         struct list_head ring_list;          struct list_head ring_list;
         struct list_head mm_list;          /** Used in execbuf to temporarily hold a ref */
         /** This object's place in the batchbuffer or on the eviction list */          struct list_head obj_exec_link;
         struct list_head exec_list;  
   
         /**          /**
          * This is set if the object is on the active lists (has pending           * This is set if the object is on the active lists (has pending
Line 1046  struct drm_i915_gem_object {
Line 1698  struct drm_i915_gem_object {
          */           */
         unsigned int fence_dirty:1;          unsigned int fence_dirty:1;
   
         /** How many users have pinned this object in GTT space. The following  
          * users can each hold at most one reference: pwrite/pread, pin_ioctl  
          * (via user_pin_count), execbuffer (objects are not allowed multiple  
          * times for the same batchbuffer), and the framebuffer code. When  
          * switching/pageflipping, the framebuffer code has at most two buffers  
          * pinned per crtc.  
          *  
          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3  
          * bits with absolutely no headroom. So use 4 bits. */  
         unsigned int pin_count:4;  
 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf  
   
         /**          /**
          * Is the object at the current location in the gtt mappable and           * Is the object at the current location in the gtt mappable and
          * fenceable? Used to avoid costly recalculations.           * fenceable? Used to avoid costly recalculations.
Line 1071  struct drm_i915_gem_object {
Line 1711  struct drm_i915_gem_object {
          */           */
         unsigned int fault_mappable:1;          unsigned int fault_mappable:1;
         unsigned int pin_mappable:1;          unsigned int pin_mappable:1;
           unsigned int pin_display:1;
   
         /*          /*
          * Is the GPU currently using a fence to access this buffer,           * Is the GPU currently using a fence to access this buffer,
Line 1078  struct drm_i915_gem_object {
Line 1719  struct drm_i915_gem_object {
         unsigned int pending_fenced_gpu_access:1;          unsigned int pending_fenced_gpu_access:1;
         unsigned int fenced_gpu_access:1;          unsigned int fenced_gpu_access:1;
   
         unsigned int cache_level:2;          unsigned int cache_level:3;
   
         unsigned int has_aliasing_ppgtt_mapping:1;          unsigned int has_aliasing_ppgtt_mapping:1;
         unsigned int has_global_gtt_mapping:1;          unsigned int has_global_gtt_mapping:1;
         unsigned int has_dma_mapping:1;          unsigned int has_dma_mapping:1;
   
 #ifdef __NetBSD__  
         struct pglist igo_pageq;  
         bus_dma_segment_t *pages; /* `pages' is an expedient misnomer.  */  
         int igo_nsegs;  
         bus_dmamap_t igo_dmamap;  
 #else  
         struct sg_table *pages;          struct sg_table *pages;
 #endif  
         int pages_pin_count;          int pages_pin_count;
   
         /* prime dma-buf support */          /* prime dma-buf support */
         void *dma_buf_vmapping;          void *dma_buf_vmapping;
         int vmapping_count;          int vmapping_count;
   
         /**  
          * Used for performing relocations during execbuffer insertion.  
          */  
         struct hlist_node exec_node;  
         unsigned long exec_handle;  
         struct drm_i915_gem_exec_object2 *exec_entry;  
   
         /**  
          * Current offset of the object in GTT space.  
          *  
          * This is the same as gtt_space->start  
          */  
         uint32_t gtt_offset;  
   
         struct intel_ring_buffer *ring;          struct intel_ring_buffer *ring;
   
         /** Breadcrumb of last rendering to the buffer. */          /** Breadcrumb of last rendering to the buffer. */
Line 1123  struct drm_i915_gem_object {
Line 1743  struct drm_i915_gem_object {
         /** Current tiling stride for the object, if it's tiled. */          /** Current tiling stride for the object, if it's tiled. */
         uint32_t stride;          uint32_t stride;
   
           /** References from framebuffers, locks out tiling changes. */
           unsigned long framebuffer_references;
   
         /** Record of address bit 17 of each page at last unbind. */          /** Record of address bit 17 of each page at last unbind. */
         unsigned long *bit_17;          unsigned long *bit_17;
   
         /** User space pin count and filp owning the pin */          /** User space pin count and filp owning the pin */
         uint32_t user_pin_count;          unsigned long user_pin_count;
         struct drm_file *pin_filp;          struct drm_file *pin_filp;
   
         /** for phy allocated objects */          /** for phy allocated objects */
         struct drm_i915_gem_phys_object *phys_obj;          drm_dma_handle_t *phys_handle;
   
         /**  
          * Number of crtcs where this object is currently the fb, but  
          * will be page flipped away on the next vblank.  When it  
          * reaches 0, dev_priv->pending_flip_queue will be woken up.  
          */  
         atomic_t pending_flip;  
 };  };
 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)  
   
 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)  #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
   
Line 1161  struct drm_i915_gem_request {
Line 1776  struct drm_i915_gem_request {
         /** GEM sequence number associated with this request. */          /** GEM sequence number associated with this request. */
         uint32_t seqno;          uint32_t seqno;
   
         /** Postion in the ringbuffer of the end of the request */          /** Position in the ringbuffer of the start of the request */
           u32 head;
   
           /** Position in the ringbuffer of the end of the request */
         u32 tail;          u32 tail;
   
           /** Context related to this request */
           struct i915_hw_context *ctx;
   
           /** Batch buffer related to this request if any */
           struct drm_i915_gem_object *batch_obj;
   
         /** Time at which this request was emitted, in jiffies. */          /** Time at which this request was emitted, in jiffies. */
         unsigned long emitted_jiffies;          unsigned long emitted_jiffies;
   
Line 1176  struct drm_i915_gem_request {
Line 1800  struct drm_i915_gem_request {
 };  };
   
 struct drm_i915_file_private {  struct drm_i915_file_private {
           struct drm_i915_private *dev_priv;
           struct drm_file *file;
   
         struct {          struct {
                 struct spinlock lock;                  spinlock_t lock;
                 struct list_head request_list;                  struct list_head request_list;
                   struct delayed_work idle_work;
         } mm;          } mm;
         struct idr context_idr;          struct idr context_idr;
   
           struct i915_hw_context *private_default_ctx;
           atomic_t rps_wait_boost;
   };
   
   /*
    * A command that requires special handling by the command parser.
    */
   struct drm_i915_cmd_descriptor {
           /*
            * Flags describing how the command parser processes the command.
            *
            * CMD_DESC_FIXED: The command has a fixed length if this is set,
            *                 a length mask if not set
            * CMD_DESC_SKIP: The command is allowed but does not follow the
            *                standard length encoding for the opcode range in
            *                which it falls
            * CMD_DESC_REJECT: The command is never allowed
            * CMD_DESC_REGISTER: The command should be checked against the
            *                    register whitelist for the appropriate ring
            * CMD_DESC_MASTER: The command is allowed if the submitting process
            *                  is the DRM master
            */
           u32 flags;
   #define CMD_DESC_FIXED    (1<<0)
   #define CMD_DESC_SKIP     (1<<1)
   #define CMD_DESC_REJECT   (1<<2)
   #define CMD_DESC_REGISTER (1<<3)
   #define CMD_DESC_BITMASK  (1<<4)
   #define CMD_DESC_MASTER   (1<<5)
   
           /*
            * The command's unique identification bits and the bitmask to get them.
            * This isn't strictly the opcode field as defined in the spec and may
            * also include type, subtype, and/or subop fields.
            */
           struct {
                   u32 value;
                   u32 mask;
           } cmd;
   
           /*
            * The command's length. The command is either fixed length (i.e. does
            * not include a length field) or has a length field mask. The flag
            * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
            * a length mask. All command entries in a command table must include
            * length information.
            */
           union {
                   u32 fixed;
                   u32 mask;
           } length;
   
           /*
            * Describes where to find a register address in the command to check
            * against the ring's register whitelist. Only valid if flags has the
            * CMD_DESC_REGISTER bit set.
            */
           struct {
                   u32 offset;
                   u32 mask;
           } reg;
   
   #define MAX_CMD_DESC_BITMASKS 3
           /*
            * Describes command checks where a particular dword is masked and
            * compared against an expected value. If the command does not match
            * the expected value, the parser rejects it. Only valid if flags has
            * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
            * are valid.
            */
           struct {
                   u32 offset;
                   u32 mask;
                   u32 expected;
           } bits[MAX_CMD_DESC_BITMASKS];
   };
   
   /*
    * A table of commands requiring special handling by the command parser.
    *
    * Each ring has an array of tables. Each table consists of an array of command
    * descriptors, which must be sorted with command opcodes in ascending order.
    */
   struct drm_i915_cmd_table {
           const struct drm_i915_cmd_descriptor *table;
           int count;
 };  };
   
 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)  #define INTEL_INFO(dev) (&to_i915(dev)->info)
   
 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)  #define IS_I830(dev)            ((dev)->pdev->device == 0x3577)
 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)  #define IS_845G(dev)            ((dev)->pdev->device == 0x2562)
 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)  #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)  #define IS_I865G(dev)           ((dev)->pdev->device == 0x2572)
 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)  #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)  #define IS_I915GM(dev)          ((dev)->pdev->device == 0x2592)
 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)  #define IS_I945G(dev)           ((dev)->pdev->device == 0x2772)
 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)  #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)  #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)  #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)  #define IS_GM45(dev)            ((dev)->pdev->device == 0x2A42)
 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)  #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)  #define IS_PINEVIEW_G(dev)      ((dev)->pdev->device == 0xa001)
 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)  #define IS_PINEVIEW_M(dev)      ((dev)->pdev->device == 0xa011)
 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)  #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)  #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)  #define IS_IRONLAKE_M(dev)      ((dev)->pdev->device == 0x0046)
 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)  
 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)  #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
 #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \  #define IS_IVB_GT1(dev)         ((dev)->pdev->device == 0x0156 || \
                                  (dev)->pci_device == 0x0152 || \                                   (dev)->pdev->device == 0x0152 || \
                                  (dev)->pci_device == 0x015a)                                   (dev)->pdev->device == 0x015a)
 #define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \  #define IS_SNB_GT1(dev)         ((dev)->pdev->device == 0x0102 || \
                                  (dev)->pci_device == 0x0106 || \                                   (dev)->pdev->device == 0x0106 || \
                                  (dev)->pci_device == 0x010A)                                   (dev)->pdev->device == 0x010A)
 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)  #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)  #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
   #define IS_BROADWELL(dev)       (INTEL_INFO(dev)->gen == 8)
 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)  #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
 #define IS_ULT(dev)             (IS_HASWELL(dev) && \  #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
                                  ((dev)->pci_device & 0xFF00) == 0x0A00)                                   ((dev)->pdev->device & 0xFF00) == 0x0C00)
   #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
                                    (((dev)->pdev->device & 0xf) == 0x2  || \
                                    ((dev)->pdev->device & 0xf) == 0x6 || \
                                    ((dev)->pdev->device & 0xf) == 0xe))
   #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
                                    ((dev)->pdev->device & 0xFF00) == 0x0A00)
   #define IS_ULT(dev)             (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
   #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
                                    ((dev)->pdev->device & 0x00F0) == 0x0020)
   /* ULX machines are also considered ULT. */
   #define IS_HSW_ULX(dev)         ((dev)->pdev->device == 0x0A0E || \
                                    (dev)->pdev->device == 0x0A1E)
   #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
   
 /*  /*
  * The genX designation typically refers to the render engine, so render   * The genX designation typically refers to the render engine, so render
Line 1228  struct drm_i915_file_private {
Line 1956  struct drm_i915_file_private {
 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)  #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)  #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)  #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
   #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
   
 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)  #define RENDER_RING             (1<<RCS)
 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)  #define BSD_RING                (1<<VCS)
   #define BLT_RING                (1<<BCS)
   #define VEBOX_RING              (1<<VECS)
   #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
   #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
   #define HAS_VEBOX(dev)            (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)  #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
   #define HAS_WT(dev)            (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)  #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
   
 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)  #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))  #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
   #define HAS_PPGTT(dev)          (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
                                    && !IS_BROADWELL(dev))
   #define USES_PPGTT(dev)         intel_enable_ppgtt(dev, false)
   #define USES_FULL_PPGTT(dev)    intel_enable_ppgtt(dev, true)
   
 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)  #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)  #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
   
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */  /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))  #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
   /*
    * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
    * even when in MSI mode. This results in spurious interrupt warnings if the
    * legacy irq no. is shared with another device. The kernel then disables that
    * interrupt source and so prevents the other device from working properly.
    */
   #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
   #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
   
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.   * rows, which changed the alignment requirements and fence programming.
Line 1251  struct drm_i915_file_private {
Line 1998  struct drm_i915_file_private {
 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))  #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))  #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))  #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))  
 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)  #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)  #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
 /* dsparb controlled by hw only */  
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))  
   
 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)  #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)  #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)  #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
   
   #define HAS_IPS(dev)            (IS_ULT(dev) || IS_BROADWELL(dev))
   
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)  #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
   #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
   #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
   #define HAS_PC8(dev)            (IS_HASWELL(dev)) /* XXX HSW:ULX */
   #define HAS_RUNTIME_PM(dev)     (IS_HASWELL(dev))
   
 #define INTEL_PCH_DEVICE_ID_MASK                0xff00  #define INTEL_PCH_DEVICE_ID_MASK                0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00  #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
Line 1270  struct drm_i915_file_private {
Line 2020  struct drm_i915_file_private {
 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00  #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00  #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
   
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)  #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)  #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)  #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)  #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
   #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)  #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
   
 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)  /* DPF == dynamic parity feature */
   #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))  #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
   
 #define GT_FREQUENCY_MULTIPLIER 50  #define GT_FREQUENCY_MULTIPLIER 50
   
 #include "i915_trace.h"  #include "i915_trace.h"
   
 /**  extern const struct drm_ioctl_desc i915_ioctls[];
  * RC6 is a special power stage which allows the GPU to enter an very  
  * low-voltage mode when idle, using down to 0V while at this stage.  This  
  * stage is entered automatically when the GPU is idle when RC6 support is  
  * enabled, and as soon as new workload arises GPU wakes up automatically as well.  
  *  
  * There are different RC6 modes available in Intel GPU, which differentiate  
  * among each other with the latency required to enter and leave RC6 and  
  * voltage consumed by the GPU in different states.  
  *  
  * The combination of the following flags define which states GPU is allowed  
  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and  
  * RC6pp is deepest RC6. Their support by hardware varies according to the  
  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one  
  * which brings the most power savings; deeper states save more power, but  
  * require higher latency to switch to and wake up.  
  */  
 #define INTEL_RC6_ENABLE                        (1<<0)  
 #define INTEL_RC6p_ENABLE                       (1<<1)  
 #define INTEL_RC6pp_ENABLE                      (1<<2)  
   
 extern struct drm_ioctl_desc i915_ioctls[];  
 extern int i915_max_ioctl;  extern int i915_max_ioctl;
 extern unsigned int i915_fbpercrtc __always_unused;  
 extern int i915_panel_ignore_lid __read_mostly;  
 extern unsigned int i915_powersave __read_mostly;  
 extern int i915_semaphores __read_mostly;  
 extern unsigned int i915_lvds_downclock __read_mostly;  
 extern int i915_lvds_channel_mode __read_mostly;  
 extern int i915_panel_use_ssc __read_mostly;  
 extern int i915_vbt_sdvo_panel_type __read_mostly;  
 extern int i915_enable_rc6 __read_mostly;  
 extern int i915_enable_fbc __read_mostly;  
 extern bool i915_enable_hangcheck __read_mostly;  
 extern int i915_enable_ppgtt __read_mostly;  
 extern unsigned int i915_preliminary_hw_support __read_mostly;  
   
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);  extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 extern int i915_resume(struct drm_device *dev);  extern int i915_resume(struct drm_device *dev);
 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);  extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);  extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
   
   /* i915_params.c */
   struct i915_params {
           int modeset;
           int panel_ignore_lid;
           unsigned int powersave;
           int semaphores;
           unsigned int lvds_downclock;
           int lvds_channel_mode;
           int panel_use_ssc;
           int vbt_sdvo_panel_type;
           int enable_rc6;
           int enable_fbc;
           int enable_ppgtt;
           int enable_psr;
           unsigned int preliminary_hw_support;
           int disable_power_well;
           int enable_ips;
           int invert_brightness;
           int enable_cmd_parser;
           /* leave bools at the end to not create holes */
           bool enable_hangcheck;
           bool fastboot;
           bool prefault_disable;
           bool reset;
           bool disable_display;
   };
   extern struct i915_params i915 __read_mostly;
   
                                 /* i915_dma.c */                                  /* i915_dma.c */
 void i915_update_dri1_breadcrumb(struct drm_device *dev);  void i915_update_dri1_breadcrumb(struct drm_device *dev);
 extern void i915_kernel_lost_context(struct drm_device * dev);  extern void i915_kernel_lost_context(struct drm_device * dev);
Line 1355  extern void i915_update_gfx_val(struct d
Line 2100  extern void i915_update_gfx_val(struct d
 extern void intel_console_resume(struct work_struct *work);  extern void intel_console_resume(struct work_struct *work);
   
 /* i915_irq.c */  /* i915_irq.c */
 void i915_hangcheck_elapsed(unsigned long data);  void i915_queue_hangcheck(struct drm_device *dev);
 void i915_handle_error(struct drm_device *dev, bool wedged);  __printf(3, 4)
   void i915_handle_error(struct drm_device *dev, bool wedged,
                          const char *fmt, ...);
   
   void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
                                                           int new_delay);
 extern void intel_irq_init(struct drm_device *dev);  extern void intel_irq_init(struct drm_device *dev);
 extern void intel_gt_init(struct drm_device *dev);  extern void intel_hpd_init(struct drm_device *dev);
 #ifdef __NetBSD__               /* XXX gt fini */  
 extern void intel_gt_fini(struct drm_device *dev);  
 #endif  
 extern void intel_gt_reset(struct drm_device *dev);  
   
 void i915_error_state_free(struct kref *error_ref);  extern void intel_uncore_sanitize(struct drm_device *dev);
   extern void intel_uncore_early_sanitize(struct drm_device *dev);
   extern void intel_uncore_init(struct drm_device *dev);
   extern void intel_uncore_check_errors(struct drm_device *dev);
   extern void intel_uncore_fini(struct drm_device *dev);
   
 void  void
 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);  i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
                        u32 status_mask);
   
 void  void
 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);  i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
                         u32 status_mask);
 void intel_enable_asle(struct drm_device *dev);  
   
 #ifdef CONFIG_DEBUG_FS  
 extern void i915_destroy_error_state(struct drm_device *dev);  
 #else  
 #define i915_destroy_error_state(x)  
 #endif  
   
   void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
   void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
   
 /* i915_gem.c */  /* i915_gem.c */
 int i915_gem_init_ioctl(struct drm_device *dev, void *data,  int i915_gem_init_ioctl(struct drm_device *dev, void *data,
Line 1430  int i915_gem_get_aperture_ioctl(struct d
Line 2175  int i915_gem_get_aperture_ioctl(struct d
 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,  int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
                         struct drm_file *file_priv);                          struct drm_file *file_priv);
 void i915_gem_load(struct drm_device *dev);  void i915_gem_load(struct drm_device *dev);
 int i915_gem_init_object(struct drm_gem_object *obj);  void *i915_gem_object_alloc(struct drm_device *dev);
   void i915_gem_object_free(struct drm_i915_gem_object *obj);
 void i915_gem_object_init(struct drm_i915_gem_object *obj,  void i915_gem_object_init(struct drm_i915_gem_object *obj,
                          const struct drm_i915_gem_object_ops *ops);                           const struct drm_i915_gem_object_ops *ops);
 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,  struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
                                                   size_t size);                                                    size_t size);
   void i915_init_vm(struct drm_i915_private *dev_priv,
                     struct i915_address_space *vm);
 void i915_gem_free_object(struct drm_gem_object *obj);  void i915_gem_free_object(struct drm_gem_object *obj);
   void i915_gem_vma_destroy(struct i915_vma *vma);
   
   #define PIN_MAPPABLE 0x1
   #define PIN_NONBLOCK 0x2
   #define PIN_GLOBAL 0x4
   #define PIN_OFFSET_BIAS 0x8
   #define PIN_OFFSET_MASK (~4095)
 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,  int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
                                        struct i915_address_space *vm,
                                      uint32_t alignment,                                       uint32_t alignment,
                                      bool map_and_fenceable,                                       uint64_t flags);
                                      bool nonblocking);  int __must_check i915_vma_unbind(struct i915_vma *vma);
 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);  int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);  void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);  void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
 void i915_gem_lastclose(struct drm_device *dev);  void i915_gem_lastclose(struct drm_device *dev);
   
   int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
                                       int *needs_clflush);
   
 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);  int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
 #ifdef __NetBSD__               /* XXX */  static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
 static inline struct page *  
 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)  
 {  {
           struct sg_page_iter sg_iter;
   
         /*          for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
          * Pages must be pinned so that we need not hold the lock to                  return sg_page_iter_page(&sg_iter);
          * prevent them from disappearing.  
          */  
         KASSERT(obj->pages != NULL);  
         mutex_enter(obj->base.gemo_shm_uao->vmobjlock);  
         struct vm_page *const page = uvm_pagelookup(obj->base.gemo_shm_uao,  
             ptoa(n));  
         mutex_exit(obj->base.gemo_shm_uao->vmobjlock);  
   
         return container_of(page, struct page, p_vmp);          return NULL;
 }  
 #else  
 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)  
 {  
         struct scatterlist *sg = obj->pages->sgl;  
         int nents = obj->pages->nents;  
         while (nents > SG_MAX_SINGLE_ALLOC) {  
                 if (n < SG_MAX_SINGLE_ALLOC - 1)  
                         break;  
   
                 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);  
                 n -= SG_MAX_SINGLE_ALLOC - 1;  
                 nents -= SG_MAX_SINGLE_ALLOC - 1;  
         }  
         return sg_page(sg+n);  
 }  }
 #endif  
 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)  static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
 {  {
         BUG_ON(obj->pages == NULL);          BUG_ON(obj->pages == NULL);
Line 1493  static inline void i915_gem_object_unpin
Line 2228  static inline void i915_gem_object_unpin
 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);  int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
 int i915_gem_object_sync(struct drm_i915_gem_object *obj,  int i915_gem_object_sync(struct drm_i915_gem_object *obj,
                          struct intel_ring_buffer *to);                           struct intel_ring_buffer *to);
 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,  void i915_vma_move_to_active(struct i915_vma *vma,
                                     struct intel_ring_buffer *ring);                               struct intel_ring_buffer *ring);
   
 int i915_gem_dumb_create(struct drm_file *file_priv,  int i915_gem_dumb_create(struct drm_file *file_priv,
                          struct drm_device *dev,                           struct drm_device *dev,
                          struct drm_mode_create_dumb *args);                           struct drm_mode_create_dumb *args);
 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,  int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
                       uint32_t handle, uint64_t *offset);                        uint32_t handle, uint64_t *offset);
 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,  
                           uint32_t handle);  
 /**  /**
  * Returns true if seq1 is later than seq2.   * Returns true if seq1 is later than seq2.
  */   */
Line 1512  i915_seqno_passed(uint32_t seq1, uint32_
Line 2244  i915_seqno_passed(uint32_t seq1, uint32_
         return (int32_t)(seq1 - seq2) >= 0;          return (int32_t)(seq1 - seq2) >= 0;
 }  }
   
 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);  int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
   int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);  int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);  int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
   
Line 1533  i915_gem_object_unpin_fence(struct drm_i
Line 2265  i915_gem_object_unpin_fence(struct drm_i
 {  {
         if (obj->fence_reg != I915_FENCE_REG_NONE) {          if (obj->fence_reg != I915_FENCE_REG_NONE) {
                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;                  struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
                   WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
                 dev_priv->fence_regs[obj->fence_reg].pin_count--;                  dev_priv->fence_regs[obj->fence_reg].pin_count--;
         }          }
 }  }
   
 void i915_gem_retire_requests(struct drm_device *dev);  struct drm_i915_gem_request *
 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);  i915_gem_find_active_request(struct intel_ring_buffer *ring);
 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,  
   bool i915_gem_retire_requests(struct drm_device *dev);
   int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
                                       bool interruptible);                                        bool interruptible);
   static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
   {
           return unlikely(atomic_read(&error->reset_counter)
                           & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
   }
   
   static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
   {
           return atomic_read(&error->reset_counter) & I915_WEDGED;
   }
   
   static inline u32 i915_reset_count(struct i915_gpu_error *error)
   {
           return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
   }
   
 void i915_gem_reset(struct drm_device *dev);  void i915_gem_reset(struct drm_device *dev);
 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);  bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,  
                                             uint32_t read_domains,  
                                             uint32_t write_domain);  
 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);  int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_init(struct drm_device *dev);  int __must_check i915_gem_init(struct drm_device *dev);
 int __must_check i915_gem_init_hw(struct drm_device *dev);  int __must_check i915_gem_init_hw(struct drm_device *dev);
 void i915_gem_l3_remap(struct drm_device *dev);  int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
 void i915_gem_init_swizzling(struct drm_device *dev);  void i915_gem_init_swizzling(struct drm_device *dev);
 void i915_gem_init_ppgtt(struct drm_device *dev);  
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);  void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 int __must_check i915_gpu_idle(struct drm_device *dev);  int __must_check i915_gpu_idle(struct drm_device *dev);
 int __must_check i915_gem_idle(struct drm_device *dev);  int __must_check i915_gem_suspend(struct drm_device *dev);
 int i915_add_request(struct intel_ring_buffer *ring,  int __i915_add_request(struct intel_ring_buffer *ring,
                      struct drm_file *file,                         struct drm_file *file,
                      u32 *seqno);                         struct drm_i915_gem_object *batch_obj,
                          u32 *seqno);
   #define i915_add_request(ring, seqno) \
           __i915_add_request(ring, NULL, NULL, seqno)
 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,  int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
                                  uint32_t seqno);                                   uint32_t seqno);
 #ifdef __NetBSD__               /* XXX */  
 int i915_gem_fault(struct uvm_faultinfo *, vaddr_t, struct vm_page **,  
     int, int, vm_prot_t, int);  
 #else  
 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);  int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 #endif  
 int __must_check  int __must_check
 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,  i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
                                   bool write);                                    bool write);
Line 1576  int __must_check
Line 2320  int __must_check
 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,  i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
                                      u32 alignment,                                       u32 alignment,
                                      struct intel_ring_buffer *pipelined);                                       struct intel_ring_buffer *pipelined);
 int i915_gem_attach_phys_object(struct drm_device *dev,  void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
                                 struct drm_i915_gem_object *obj,  int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
                                 int id,  
                                 int align);                                  int align);
 void i915_gem_detach_phys_object(struct drm_device *dev,  int i915_gem_open(struct drm_device *dev, struct drm_file *file);
                                  struct drm_i915_gem_object *obj);  
 void i915_gem_free_all_phys_object(struct drm_device *dev);  
 void i915_gem_release(struct drm_device *dev, struct drm_file *file);  void i915_gem_release(struct drm_device *dev, struct drm_file *file);
   
 uint32_t  uint32_t
 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,  i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
                                     uint32_t size,  uint32_t
                                     int tiling_mode);  i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
                               int tiling_mode, bool fenced);
   
 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,  int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
                                     enum i915_cache_level cache_level);                                      enum i915_cache_level cache_level);
Line 1599  struct drm_gem_object *i915_gem_prime_im
Line 2341  struct drm_gem_object *i915_gem_prime_im
 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,  struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
                                 struct drm_gem_object *gem_obj, int flags);                                  struct drm_gem_object *gem_obj, int flags);
   
   void i915_gem_restore_fences(struct drm_device *dev);
   
   unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
                                     struct i915_address_space *vm);
   bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
   bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
                           struct i915_address_space *vm);
   unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
                                   struct i915_address_space *vm);
   struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
                                        struct i915_address_space *vm);
   struct i915_vma *
   i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
                                     struct i915_address_space *vm);
   
   struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
   static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
           struct i915_vma *vma;
           list_for_each_entry(vma, &obj->vma_list, vma_link)
                   if (vma->pin_count > 0)
                           return true;
           return false;
   }
   
   /* Some GGTT VM helpers */
   #define obj_to_ggtt(obj) \
           (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
   static inline bool i915_is_ggtt(struct i915_address_space *vm)
   {
           struct i915_address_space *ggtt =
                   &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
           return vm == ggtt;
   }
   
   static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
   {
           return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
   }
   
   static inline unsigned long
   i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
   {
           return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
   }
   
   static inline unsigned long
   i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
   {
           return i915_gem_obj_size(obj, obj_to_ggtt(obj));
   }
   
   static inline int __must_check
   i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
                         uint32_t alignment,
                         unsigned flags)
   {
           return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
   }
   
   static inline int
   i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
   {
           return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
   }
   
   void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
   
 /* i915_gem_context.c */  /* i915_gem_context.c */
 void i915_gem_context_init(struct drm_device *dev);  #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
   int __must_check i915_gem_context_init(struct drm_device *dev);
 void i915_gem_context_fini(struct drm_device *dev);  void i915_gem_context_fini(struct drm_device *dev);
   void i915_gem_context_reset(struct drm_device *dev);
   int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
   int i915_gem_context_enable(struct drm_i915_private *dev_priv);
 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);  void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
 int i915_switch_context(struct intel_ring_buffer *ring,  int i915_switch_context(struct intel_ring_buffer *ring,
                         struct drm_file *file, int to_id);                          struct i915_hw_context *to);
   struct i915_hw_context *
   i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
   void i915_gem_context_free(struct kref *ctx_ref);
   static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
   {
           kref_get(&ctx->ref);
   }
   
   static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
   {
           kref_put(&ctx->ref, i915_gem_context_free);
   }
   
   static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
   {
           return c->id == DEFAULT_CONTEXT_ID;
   }
   
 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,  int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
                                   struct drm_file *file);                                    struct drm_file *file);
 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,  int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
                                    struct drm_file *file);                                     struct drm_file *file);
   
 /* i915_gem_gtt.c */  /* i915_gem_evict.c */
 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);  int __must_check i915_gem_evict_something(struct drm_device *dev,
 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);                                            struct i915_address_space *vm,
 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,                                            int min_size,
                             struct drm_i915_gem_object *obj,                                            unsigned alignment,
                             enum i915_cache_level cache_level);                                            unsigned cache_level,
 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,                                            unsigned long start,
                               struct drm_i915_gem_object *obj);                                            unsigned long end,
                                             unsigned flags);
   int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
   int i915_gem_evict_everything(struct drm_device *dev);
   
   /* i915_gem_gtt.c */
   void i915_check_and_clear_faults(struct drm_device *dev);
   void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);  void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);  int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,  
                                 enum i915_cache_level cache_level);  
 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);  
 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);  void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
 void i915_gem_init_global_gtt(struct drm_device *dev,  void i915_gem_init_global_gtt(struct drm_device *dev);
                               unsigned long start,  void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
                               unsigned long mappable_end,                                 unsigned long mappable_end, unsigned long end);
                               unsigned long end);  
 #ifdef __NetBSD__               /* XXX fini global gtt */  
 void i915_gem_fini_global_gtt(struct drm_device *dev);  
 #endif  
 int i915_gem_gtt_init(struct drm_device *dev);  int i915_gem_gtt_init(struct drm_device *dev);
 void i915_gem_gtt_fini(struct drm_device *dev);  
 static inline void i915_gem_chipset_flush(struct drm_device *dev)  static inline void i915_gem_chipset_flush(struct drm_device *dev)
 {  {
         if (INTEL_INFO(dev)->gen < 6)          if (INTEL_INFO(dev)->gen < 6)
                 intel_gtt_chipset_flush();                  intel_gtt_chipset_flush();
 }  }
   int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
   bool intel_enable_ppgtt(struct drm_device *dev, bool full);
 /* i915_gem_evict.c */  
 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,  
                                           unsigned alignment,  
                                           unsigned cache_level,  
                                           bool mappable,  
                                           bool nonblock);  
 int i915_gem_evict_everything(struct drm_device *dev);  
   
 /* i915_gem_stolen.c */  /* i915_gem_stolen.c */
 int i915_gem_init_stolen(struct drm_device *dev);  int i915_gem_init_stolen(struct drm_device *dev);
   int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
   void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
 void i915_gem_cleanup_stolen(struct drm_device *dev);  void i915_gem_cleanup_stolen(struct drm_device *dev);
   struct drm_i915_gem_object *
   i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
   struct drm_i915_gem_object *
   i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
                                                  u32 stolen_offset,
                                                  u32 gtt_offset,
                                                  u32 size);
   void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
   
 /* i915_gem_tiling.c */  /* i915_gem_tiling.c */
   static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
   {
           struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
   
           return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
                   obj->tiling_mode != I915_TILING_NONE;
   }
   
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);  void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);  void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);  void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
   
 /* i915_gem_debug.c */  /* i915_gem_debug.c */
 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,  
                           const char *where, uint32_t mark);  
 #if WATCH_LISTS  #if WATCH_LISTS
 int i915_verify_lists(struct drm_device *dev);  int i915_verify_lists(struct drm_device *dev);
 #else  #else
 #define i915_verify_lists(dev) 0  #define i915_verify_lists(dev) 0
 #endif  #endif
 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,  
                                      int handle);  
 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,  
                           const char *where, uint32_t mark);  
   
 /* i915_debugfs.c */  /* i915_debugfs.c */
 int i915_debugfs_init(struct drm_minor *minor);  int i915_debugfs_init(struct drm_minor *minor);
 void i915_debugfs_cleanup(struct drm_minor *minor);  void i915_debugfs_cleanup(struct drm_minor *minor);
   #ifdef CONFIG_DEBUG_FS
   void intel_display_crc_init(struct drm_device *dev);
   #else
   static inline void intel_display_crc_init(struct drm_device *dev) {}
   #endif
   
 /* i915_suspend.c */  /* i915_gpu_error.c */
 extern int i915_save_state(struct drm_device *dev);  __printf(2, 3)
 extern int i915_restore_state(struct drm_device *dev);  void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
   int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
                               const struct i915_error_state_file_priv *error);
   int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
                                 size_t count, loff_t pos);
   static inline void i915_error_state_buf_release(
           struct drm_i915_error_state_buf *eb)
   {
           kfree(eb->buf);
   }
   void i915_capture_error_state(struct drm_device *dev, bool wedge,
                                 const char *error_msg);
   void i915_error_state_get(struct drm_device *dev,
                             struct i915_error_state_file_priv *error_priv);
   void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
   void i915_destroy_error_state(struct drm_device *dev);
   
   void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
   const char *i915_cache_level_str(int type);
   
   /* i915_cmd_parser.c */
   void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
   bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
   int i915_parse_cmds(struct intel_ring_buffer *ring,
                       struct drm_i915_gem_object *batch_obj,
                       u32 batch_start_offset,
                       bool is_master);
   
 /* i915_suspend.c */  /* i915_suspend.c */
 extern int i915_save_state(struct drm_device *dev);  extern int i915_save_state(struct drm_device *dev);
 extern int i915_restore_state(struct drm_device *dev);  extern int i915_restore_state(struct drm_device *dev);
   
   /* i915_ums.c */
   void i915_save_display_reg(struct drm_device *dev);
   void i915_restore_display_reg(struct drm_device *dev);
   
 /* i915_sysfs.c */  /* i915_sysfs.c */
 void i915_setup_sysfs(struct drm_device *dev_priv);  void i915_setup_sysfs(struct drm_device *dev_priv);
 void i915_teardown_sysfs(struct drm_device *dev_priv);  void i915_teardown_sysfs(struct drm_device *dev_priv);
Line 1690  void i915_teardown_sysfs(struct drm_devi
Line 2559  void i915_teardown_sysfs(struct drm_devi
 /* intel_i2c.c */  /* intel_i2c.c */
 extern int intel_setup_gmbus(struct drm_device *dev);  extern int intel_setup_gmbus(struct drm_device *dev);
 extern void intel_teardown_gmbus(struct drm_device *dev);  extern void intel_teardown_gmbus(struct drm_device *dev);
 #ifdef __NetBSD__  
 static inline bool intel_gmbus_is_port_valid(unsigned port)  static inline bool intel_gmbus_is_port_valid(unsigned port)
 #else  
 extern inline bool intel_gmbus_is_port_valid(unsigned port)  
 #endif  
 {  {
         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);          return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
 }  }
Line 1703  extern struct i2c_adapter *intel_gmbus_g
Line 2568  extern struct i2c_adapter *intel_gmbus_g
                 struct drm_i915_private *dev_priv, unsigned port);                  struct drm_i915_private *dev_priv, unsigned port);
 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);  extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);  extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
 #ifdef __NetBSD__  
 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)  static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
 #else  
 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)  
 #endif  
 {  {
         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;          return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
 }  }
 extern void intel_i2c_reset(struct drm_device *dev);  extern void intel_i2c_reset(struct drm_device *dev);
   
 /* intel_opregion.c */  /* intel_opregion.c */
 extern int intel_opregion_setup(struct drm_device *dev);  struct intel_encoder;
 #ifdef CONFIG_ACPI  #ifdef CONFIG_ACPI
   extern int intel_opregion_setup(struct drm_device *dev);
 extern void intel_opregion_init(struct drm_device *dev);  extern void intel_opregion_init(struct drm_device *dev);
 extern void intel_opregion_fini(struct drm_device *dev);  extern void intel_opregion_fini(struct drm_device *dev);
 extern void intel_opregion_asle_intr(struct drm_device *dev);  extern void intel_opregion_asle_intr(struct drm_device *dev);
 extern void intel_opregion_gse_intr(struct drm_device *dev);  extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
 extern void intel_opregion_enable_asle(struct drm_device *dev);                                           bool enable);
   extern int intel_opregion_notify_adapter(struct drm_device *dev,
                                            pci_power_t state);
 #else  #else
   static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
 static inline void intel_opregion_init(struct drm_device *dev) { return; }  static inline void intel_opregion_init(struct drm_device *dev) { return; }
 static inline void intel_opregion_fini(struct drm_device *dev) { return; }  static inline void intel_opregion_fini(struct drm_device *dev) { return; }
 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }  static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }  static inline int
 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }  intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
   {
           return 0;
   }
   static inline int
   intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
   {
           return 0;
   }
 #endif  #endif
   
 /* intel_acpi.c */  /* intel_acpi.c */
Line 1740  static inline void intel_unregister_dsm_
Line 2613  static inline void intel_unregister_dsm_
   
 /* modesetting */  /* modesetting */
 extern void intel_modeset_init_hw(struct drm_device *dev);  extern void intel_modeset_init_hw(struct drm_device *dev);
   extern void intel_modeset_suspend_hw(struct drm_device *dev);
 extern void intel_modeset_init(struct drm_device *dev);  extern void intel_modeset_init(struct drm_device *dev);
 extern void intel_modeset_gem_init(struct drm_device *dev);  extern void intel_modeset_gem_init(struct drm_device *dev);
 extern void intel_modeset_cleanup(struct drm_device *dev);  extern void intel_modeset_cleanup(struct drm_device *dev);
   extern void intel_connector_unregister(struct intel_connector *);
 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);  extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 extern void intel_modeset_setup_hw_state(struct drm_device *dev,  extern void intel_modeset_setup_hw_state(struct drm_device *dev,
                                          bool force_restore);                                           bool force_restore);
   extern void i915_redisable_vga(struct drm_device *dev);
   extern void i915_redisable_vga_power_on(struct drm_device *dev);
 extern bool intel_fbc_enabled(struct drm_device *dev);  extern bool intel_fbc_enabled(struct drm_device *dev);
 extern void intel_disable_fbc(struct drm_device *dev);  extern void intel_disable_fbc(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);  extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);  extern void intel_init_pch_refclk(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);  extern void gen6_set_rps(struct drm_device *dev, u8 val);
   extern void valleyview_set_rps(struct drm_device *dev, u8 val);
   extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
   extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
 extern void intel_detect_pch(struct drm_device *dev);  extern void intel_detect_pch(struct drm_device *dev);
 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);  extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 extern int intel_enable_rc6(const struct drm_device *dev);  extern int intel_enable_rc6(const struct drm_device *dev);
Line 1758  extern int intel_enable_rc6(const struct
Line 2638  extern int intel_enable_rc6(const struct
 extern bool i915_semaphore_is_enabled(struct drm_device *dev);  extern bool i915_semaphore_is_enabled(struct drm_device *dev);
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,  int i915_reg_read_ioctl(struct drm_device *dev, void *data,
                         struct drm_file *file);                          struct drm_file *file);
   int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
                                  struct drm_file *file);
   
 /* overlay */  /* overlay */
 #ifdef CONFIG_DEBUG_FS  
 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);  extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);  extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
                                               struct intel_overlay_error_state *error);
   
 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);  extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
 extern void intel_display_print_error_state(struct seq_file *m,  extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
                                             struct drm_device *dev,                                              struct drm_device *dev,
                                             struct intel_display_error_state *error);                                              struct intel_display_error_state *error);
 #endif  
   
 /* On SNB platform, before reading ring registers forcewake bit  /* On SNB platform, before reading ring registers forcewake bit
  * must be set to prevent GT core from power down and stale values being   * must be set to prevent GT core from power down and stale values being
  * returned.   * returned.
  */   */
 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);  void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);  void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);  void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
   
 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);  int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);  int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
   
 #define __i915_read(x, y) \  /* intel_sideband.c */
         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);  u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
   void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
 __i915_read(8, b)  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
 __i915_read(16, w)  u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
 __i915_read(32, l)  void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 __i915_read(64, q)  u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
 #undef __i915_read  void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
   u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
 #define __i915_write(x, y) \  void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);  u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
   void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 __i915_write(8, b)  u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
 __i915_write(16, w)  void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 __i915_write(32, l)  u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
 __i915_write(64, q)  void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
 #undef __i915_write  u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
                      enum intel_sbi_destination destination);
 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))  void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))                       enum intel_sbi_destination destination);
   u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))  
 #ifdef __NetBSD__  int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
 #define I915_READ16_NOTRACE(reg)        DRM_READ16(dev_priv->regs_map, (reg))  int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
 #define I915_WRITE16_NOTRACE(reg, val)  DRM_WRITE16(dev_priv->regs_map, (reg), (val))  
 #else  void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))  void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))  
 #endif  #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
           (((reg) >= 0x2000 && (reg) < 0x4000) ||\
 #define I915_READ(reg)          i915_read32(dev_priv, (reg))          ((reg) >= 0x5000 && (reg) < 0x8000) ||\
 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))          ((reg) >= 0xB000 && (reg) < 0x12000) ||\
 #ifdef __NetBSD__          ((reg) >= 0x2E000 && (reg) < 0x30000))
 #define I915_READ_NOTRACE(reg)          DRM_READ32(dev_priv->regs_map, (reg))  
 #define I915_WRITE_NOTRACE(reg, val)    DRM_WRITE32(dev_priv->regs_map, (reg), (val))  #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
 #else          (((reg) >= 0x12000 && (reg) < 0x14000) ||\
 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))          ((reg) >= 0x22000 && (reg) < 0x24000) ||\
 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))          ((reg) >= 0x30000 && (reg) < 0x40000))
 #endif  
   #define FORCEWAKE_RENDER        (1 << 0)
   #define FORCEWAKE_MEDIA         (1 << 1)
   #define FORCEWAKE_ALL           (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
   
   
   #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
   #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
   
   #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
   #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
   #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
   #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
   
   #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
   #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
   #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
   #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
   
   /* Be very careful with read/write 64-bit values. On 32-bit machines, they
    * will be implemented using 2 32-bit writes in an arbitrary order with
    * an arbitrary delay between them. This can cause the hardware to
    * act upon the intermediate value, possibly leading to corruption and
    * machine death. You have been warned.
    */
   #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
   #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
   
 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))  #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))                  u32 upper = I915_READ(upper_reg);                       \
                   u32 lower = I915_READ(lower_reg);                       \
                   u32 tmp = I915_READ(upper_reg);                         \
                   if (upper != tmp) {                                     \
                           upper = tmp;                                    \
                           lower = I915_READ(lower_reg);                   \
                           WARN_ON(I915_READ(upper_reg) != upper);         \
                   }                                                       \
                   (u64)upper << 32 | lower; })
   
 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)  #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)  #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
   
   /* "Broadcast RGB" property */
   #define INTEL_BROADCAST_RGB_AUTO 0
   #define INTEL_BROADCAST_RGB_FULL 1
   #define INTEL_BROADCAST_RGB_LIMITED 2
   
   static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
   {
           if (HAS_PCH_SPLIT(dev))
                   return CPU_VGACNTRL;
           else if (IS_VALLEYVIEW(dev))
                   return VLV_VGACNTRL;
           else
                   return VGACNTRL;
   }
   
   static inline void __user *to_user_ptr(u64 address)
   {
           return (void __user *)(uintptr_t)address;
   }
   
   static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
   {
           unsigned long j = msecs_to_jiffies(m);
   
           return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
   }
   
   static inline unsigned long
   timespec_to_jiffies_timeout(const struct timespec *value)
   {
           unsigned long j = timespec_to_jiffies(value);
   
           return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
   }
   
   /*
    * If you need to wait X milliseconds between events A and B, but event B
    * doesn't happen exactly after event A, you record the timestamp (jiffies) of
    * when event A happened, then just before event B you call this function and
    * pass the timestamp as the first argument, and X as the second argument.
    */
   static inline void
   wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
   {
           unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
   
           /*
            * Don't re-read the value of "jiffies" every time since it may change
            * behind our back and break the math.
            */
           tmp_jiffies = jiffies;
           target_jiffies = timestamp_jiffies +
                            msecs_to_jiffies_timeout(to_wait_ms);
   
           if (time_after(target_jiffies, tmp_jiffies)) {
                   remaining_jiffies = target_jiffies - tmp_jiffies;
                   while (remaining_jiffies)
                           remaining_jiffies =
                               schedule_timeout_uninterruptible(remaining_jiffies);
           }
   }
   
 #endif  #endif
Legend:
Removed from v.1.1.1.1.2.18  
changed lines
  Added in v.1.1.1.2
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