Annotation of src/sys/dev/usb/xhci.c, Revision 1.86.2.7
1.86.2.7! pgoyette 1: /* $NetBSD: xhci.c,v 1.99 2018/09/16 20:21:56 mrg Exp $ */
1.1 jakllsch 2:
3: /*
4: * Copyright (c) 2013 Jonathan A. Kollasch
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17: * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20: * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23: * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27: */
28:
1.34 skrll 29: /*
1.41 skrll 30: * USB rev 2.0 and rev 3.1 specification
31: * http://www.usb.org/developers/docs/
1.34 skrll 32: * xHCI rev 1.1 specification
1.41 skrll 33: * http://www.intel.com/technology/usb/spec.htm
1.34 skrll 34: */
35:
1.1 jakllsch 36: #include <sys/cdefs.h>
1.86.2.7! pgoyette 37: __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.99 2018/09/16 20:21:56 mrg Exp $");
1.27 skrll 38:
1.46 pooka 39: #ifdef _KERNEL_OPT
1.27 skrll 40: #include "opt_usb.h"
1.46 pooka 41: #endif
1.1 jakllsch 42:
43: #include <sys/param.h>
44: #include <sys/systm.h>
45: #include <sys/kernel.h>
46: #include <sys/kmem.h>
47: #include <sys/device.h>
48: #include <sys/select.h>
49: #include <sys/proc.h>
50: #include <sys/queue.h>
51: #include <sys/mutex.h>
52: #include <sys/condvar.h>
53: #include <sys/bus.h>
54: #include <sys/cpu.h>
1.27 skrll 55: #include <sys/sysctl.h>
1.1 jakllsch 56:
57: #include <machine/endian.h>
58:
59: #include <dev/usb/usb.h>
60: #include <dev/usb/usbdi.h>
61: #include <dev/usb/usbdivar.h>
1.34 skrll 62: #include <dev/usb/usbdi_util.h>
1.27 skrll 63: #include <dev/usb/usbhist.h>
1.1 jakllsch 64: #include <dev/usb/usb_mem.h>
65: #include <dev/usb/usb_quirks.h>
66:
67: #include <dev/usb/xhcireg.h>
68: #include <dev/usb/xhcivar.h>
1.34 skrll 69: #include <dev/usb/usbroothub.h>
1.1 jakllsch 70:
1.27 skrll 71:
72: #ifdef USB_DEBUG
73: #ifndef XHCI_DEBUG
74: #define xhcidebug 0
1.34 skrll 75: #else /* !XHCI_DEBUG */
1.79 christos 76: #define HEXDUMP(a, b, c) \
77: do { \
78: if (xhcidebug > 0) \
1.80 christos 79: hexdump(printf, a, b, c); \
1.79 christos 80: } while (/*CONSTCOND*/0)
1.27 skrll 81: static int xhcidebug = 0;
82:
83: SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup")
84: {
85: int err;
86: const struct sysctlnode *rnode;
87: const struct sysctlnode *cnode;
88:
89: err = sysctl_createv(clog, 0, NULL, &rnode,
90: CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci",
91: SYSCTL_DESCR("xhci global controls"),
92: NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
93:
94: if (err)
95: goto fail;
96:
97: /* control debugging printfs */
98: err = sysctl_createv(clog, 0, &rnode, &cnode,
99: CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
100: "debug", SYSCTL_DESCR("Enable debugging output"),
101: NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL);
102: if (err)
103: goto fail;
104:
105: return;
106: fail:
107: aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
108: }
109:
1.34 skrll 110: #endif /* !XHCI_DEBUG */
1.27 skrll 111: #endif /* USB_DEBUG */
112:
1.79 christos 113: #ifndef HEXDUMP
114: #define HEXDUMP(a, b, c)
115: #endif
116:
1.27 skrll 117: #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D)
118: #define XHCIHIST_FUNC() USBHIST_FUNC()
119: #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug)
1.1 jakllsch 120:
121: #define XHCI_DCI_SLOT 0
122: #define XHCI_DCI_EP_CONTROL 1
123:
124: #define XHCI_ICI_INPUT_CONTROL 0
125:
126: struct xhci_pipe {
127: struct usbd_pipe xp_pipe;
1.34 skrll 128: struct usb_task xp_async_task;
1.1 jakllsch 129: };
130:
131: #define XHCI_COMMAND_RING_TRBS 256
132: #define XHCI_EVENT_RING_TRBS 256
133: #define XHCI_EVENT_RING_SEGMENTS 1
134: #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT
135:
1.34 skrll 136: static usbd_status xhci_open(struct usbd_pipe *);
137: static void xhci_close_pipe(struct usbd_pipe *);
1.1 jakllsch 138: static int xhci_intr1(struct xhci_softc * const);
139: static void xhci_softintr(void *);
140: static void xhci_poll(struct usbd_bus *);
1.34 skrll 141: static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int);
142: static void xhci_freex(struct usbd_bus *, struct usbd_xfer *);
1.1 jakllsch 143: static void xhci_get_lock(struct usbd_bus *, kmutex_t **);
1.34 skrll 144: static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int,
1.1 jakllsch 145: struct usbd_port *);
1.34 skrll 146: static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
147: void *, int);
1.1 jakllsch 148:
1.34 skrll 149: static usbd_status xhci_configure_endpoint(struct usbd_pipe *);
150: //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *);
151: static usbd_status xhci_reset_endpoint(struct usbd_pipe *);
152: static usbd_status xhci_stop_endpoint(struct usbd_pipe *);
1.1 jakllsch 153:
1.55 skrll 154: static void xhci_host_dequeue(struct xhci_ring * const);
1.34 skrll 155: static usbd_status xhci_set_dequeue(struct usbd_pipe *);
1.1 jakllsch 156:
157: static usbd_status xhci_do_command(struct xhci_softc * const,
158: struct xhci_trb * const, int);
1.34 skrll 159: static usbd_status xhci_do_command_locked(struct xhci_softc * const,
160: struct xhci_trb * const, int);
1.48 skrll 161: static usbd_status xhci_init_slot(struct usbd_device *, uint32_t);
162: static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int);
1.51 skrll 163: static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool);
1.1 jakllsch 164: static usbd_status xhci_enable_slot(struct xhci_softc * const,
165: uint8_t * const);
1.34 skrll 166: static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t);
1.1 jakllsch 167: static usbd_status xhci_address_device(struct xhci_softc * const,
168: uint64_t, uint8_t, bool);
1.34 skrll 169: static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int);
1.1 jakllsch 170: static usbd_status xhci_update_ep0_mps(struct xhci_softc * const,
171: struct xhci_slot * const, u_int);
172: static usbd_status xhci_ring_init(struct xhci_softc * const,
173: struct xhci_ring * const, size_t, size_t);
174: static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const);
175:
1.51 skrll 176: static void xhci_setup_ctx(struct usbd_pipe *);
177: static void xhci_setup_route(struct usbd_pipe *, uint32_t *);
178: static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *);
179: static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *);
180: static uint32_t xhci_bival2ival(uint32_t, uint32_t);
181:
1.34 skrll 182: static void xhci_noop(struct usbd_pipe *);
1.1 jakllsch 183:
1.34 skrll 184: static usbd_status xhci_root_intr_transfer(struct usbd_xfer *);
185: static usbd_status xhci_root_intr_start(struct usbd_xfer *);
186: static void xhci_root_intr_abort(struct usbd_xfer *);
187: static void xhci_root_intr_close(struct usbd_pipe *);
188: static void xhci_root_intr_done(struct usbd_xfer *);
189:
190: static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *);
191: static usbd_status xhci_device_ctrl_start(struct usbd_xfer *);
192: static void xhci_device_ctrl_abort(struct usbd_xfer *);
193: static void xhci_device_ctrl_close(struct usbd_pipe *);
194: static void xhci_device_ctrl_done(struct usbd_xfer *);
195:
196: static usbd_status xhci_device_intr_transfer(struct usbd_xfer *);
197: static usbd_status xhci_device_intr_start(struct usbd_xfer *);
198: static void xhci_device_intr_abort(struct usbd_xfer *);
199: static void xhci_device_intr_close(struct usbd_pipe *);
200: static void xhci_device_intr_done(struct usbd_xfer *);
201:
202: static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *);
203: static usbd_status xhci_device_bulk_start(struct usbd_xfer *);
204: static void xhci_device_bulk_abort(struct usbd_xfer *);
205: static void xhci_device_bulk_close(struct usbd_pipe *);
206: static void xhci_device_bulk_done(struct usbd_xfer *);
1.1 jakllsch 207:
208: static void xhci_timeout(void *);
209: static void xhci_timeout_task(void *);
210:
211: static const struct usbd_bus_methods xhci_bus_methods = {
1.34 skrll 212: .ubm_open = xhci_open,
213: .ubm_softint = xhci_softintr,
214: .ubm_dopoll = xhci_poll,
215: .ubm_allocx = xhci_allocx,
216: .ubm_freex = xhci_freex,
217: .ubm_getlock = xhci_get_lock,
218: .ubm_newdev = xhci_new_device,
219: .ubm_rhctrl = xhci_roothub_ctrl,
1.1 jakllsch 220: };
221:
222: static const struct usbd_pipe_methods xhci_root_intr_methods = {
1.34 skrll 223: .upm_transfer = xhci_root_intr_transfer,
224: .upm_start = xhci_root_intr_start,
225: .upm_abort = xhci_root_intr_abort,
226: .upm_close = xhci_root_intr_close,
227: .upm_cleartoggle = xhci_noop,
228: .upm_done = xhci_root_intr_done,
1.1 jakllsch 229: };
230:
231:
232: static const struct usbd_pipe_methods xhci_device_ctrl_methods = {
1.34 skrll 233: .upm_transfer = xhci_device_ctrl_transfer,
234: .upm_start = xhci_device_ctrl_start,
235: .upm_abort = xhci_device_ctrl_abort,
236: .upm_close = xhci_device_ctrl_close,
237: .upm_cleartoggle = xhci_noop,
238: .upm_done = xhci_device_ctrl_done,
1.1 jakllsch 239: };
240:
241: static const struct usbd_pipe_methods xhci_device_isoc_methods = {
1.34 skrll 242: .upm_cleartoggle = xhci_noop,
1.1 jakllsch 243: };
244:
245: static const struct usbd_pipe_methods xhci_device_bulk_methods = {
1.34 skrll 246: .upm_transfer = xhci_device_bulk_transfer,
247: .upm_start = xhci_device_bulk_start,
248: .upm_abort = xhci_device_bulk_abort,
249: .upm_close = xhci_device_bulk_close,
250: .upm_cleartoggle = xhci_noop,
251: .upm_done = xhci_device_bulk_done,
1.1 jakllsch 252: };
253:
254: static const struct usbd_pipe_methods xhci_device_intr_methods = {
1.34 skrll 255: .upm_transfer = xhci_device_intr_transfer,
256: .upm_start = xhci_device_intr_start,
257: .upm_abort = xhci_device_intr_abort,
258: .upm_close = xhci_device_intr_close,
259: .upm_cleartoggle = xhci_noop,
260: .upm_done = xhci_device_intr_done,
1.1 jakllsch 261: };
262:
263: static inline uint32_t
1.34 skrll 264: xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset)
265: {
266: return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
267: }
268:
269: static inline uint32_t
1.1 jakllsch 270: xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset)
271: {
272: return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset);
273: }
274:
1.34 skrll 275: static inline void
276: xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset,
277: uint32_t value)
278: {
279: bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value);
280: }
281:
1.4 apb 282: #if 0 /* unused */
1.1 jakllsch 283: static inline void
284: xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset,
285: uint32_t value)
286: {
287: bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value);
288: }
1.4 apb 289: #endif /* unused */
1.1 jakllsch 290:
291: static inline uint32_t
292: xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset)
293: {
294: return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset);
295: }
296:
297: static inline uint32_t
298: xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset)
299: {
300: return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
301: }
302:
303: static inline void
304: xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset,
305: uint32_t value)
306: {
307: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
308: }
309:
310: static inline uint64_t
311: xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset)
312: {
313: uint64_t value;
314:
315: if (sc->sc_ac64) {
316: #ifdef XHCI_USE_BUS_SPACE_8
317: value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset);
318: #else
319: value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
320: value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh,
321: offset + 4) << 32;
322: #endif
323: } else {
324: value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
325: }
326:
327: return value;
328: }
329:
330: static inline void
331: xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset,
332: uint64_t value)
333: {
334: if (sc->sc_ac64) {
335: #ifdef XHCI_USE_BUS_SPACE_8
336: bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value);
337: #else
338: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0,
339: (value >> 0) & 0xffffffff);
340: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4,
341: (value >> 32) & 0xffffffff);
342: #endif
343: } else {
344: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
345: }
346: }
347:
348: static inline uint32_t
349: xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset)
350: {
351: return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
352: }
353:
354: static inline void
355: xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset,
356: uint32_t value)
357: {
358: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
359: }
360:
1.4 apb 361: #if 0 /* unused */
1.1 jakllsch 362: static inline uint64_t
363: xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset)
364: {
365: uint64_t value;
366:
367: if (sc->sc_ac64) {
368: #ifdef XHCI_USE_BUS_SPACE_8
369: value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset);
370: #else
371: value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
372: value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh,
373: offset + 4) << 32;
374: #endif
375: } else {
376: value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
377: }
378:
379: return value;
380: }
1.4 apb 381: #endif /* unused */
1.1 jakllsch 382:
383: static inline void
384: xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset,
385: uint64_t value)
386: {
387: if (sc->sc_ac64) {
388: #ifdef XHCI_USE_BUS_SPACE_8
389: bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value);
390: #else
391: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0,
392: (value >> 0) & 0xffffffff);
393: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4,
394: (value >> 32) & 0xffffffff);
395: #endif
396: } else {
397: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
398: }
399: }
400:
1.4 apb 401: #if 0 /* unused */
1.1 jakllsch 402: static inline uint32_t
403: xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset)
404: {
405: return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset);
406: }
1.4 apb 407: #endif /* unused */
1.1 jakllsch 408:
409: static inline void
410: xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset,
411: uint32_t value)
412: {
413: bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value);
414: }
415:
416: /* --- */
417:
418: static inline uint8_t
419: xhci_ep_get_type(usb_endpoint_descriptor_t * const ed)
420: {
1.34 skrll 421: u_int eptype = 0;
1.1 jakllsch 422:
423: switch (UE_GET_XFERTYPE(ed->bmAttributes)) {
424: case UE_CONTROL:
425: eptype = 0x0;
426: break;
427: case UE_ISOCHRONOUS:
428: eptype = 0x1;
429: break;
430: case UE_BULK:
431: eptype = 0x2;
432: break;
433: case UE_INTERRUPT:
434: eptype = 0x3;
435: break;
436: }
437:
438: if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
439: (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
440: return eptype | 0x4;
441: else
442: return eptype;
443: }
444:
445: static u_int
446: xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed)
447: {
448: /* xHCI 1.0 section 4.5.1 */
449: u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress);
450: u_int in = 0;
451:
452: if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
453: (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
454: in = 1;
455:
456: return epaddr * 2 + in;
457: }
458:
459: static inline u_int
460: xhci_dci_to_ici(const u_int i)
461: {
462: return i + 1;
463: }
464:
465: static inline void *
466: xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs,
467: const u_int dci)
468: {
469: return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
470: }
471:
1.4 apb 472: #if 0 /* unused */
1.1 jakllsch 473: static inline bus_addr_t
474: xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs,
475: const u_int dci)
476: {
477: return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
478: }
1.4 apb 479: #endif /* unused */
1.1 jakllsch 480:
481: static inline void *
482: xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs,
483: const u_int ici)
484: {
485: return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
486: }
487:
488: static inline bus_addr_t
489: xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs,
490: const u_int ici)
491: {
492: return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
493: }
494:
495: static inline struct xhci_trb *
496: xhci_ring_trbv(struct xhci_ring * const xr, u_int idx)
497: {
498: return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
499: }
500:
501: static inline bus_addr_t
502: xhci_ring_trbp(struct xhci_ring * const xr, u_int idx)
503: {
504: return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
505: }
506:
507: static inline void
508: xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
509: uint32_t control)
510: {
1.34 skrll 511: trb->trb_0 = htole64(parameter);
512: trb->trb_2 = htole32(status);
513: trb->trb_3 = htole32(control);
1.1 jakllsch 514: }
515:
1.40 skrll 516: static int
517: xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx)
518: {
519: /* base address of TRBs */
520: bus_addr_t trbp = xhci_ring_trbp(xr, 0);
521:
522: /* trb_0 range sanity check */
523: if (trb_0 == 0 || trb_0 < trbp ||
524: (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 ||
525: (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) {
526: return 1;
527: }
528: *idx = (trb_0 - trbp) / sizeof(struct xhci_trb);
529: return 0;
530: }
531:
1.63 skrll 532: static unsigned int
533: xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs,
534: u_int dci)
535: {
536: uint32_t *cp;
537:
538: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
539: cp = xhci_slot_get_dcv(sc, xs, dci);
540: return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0]));
541: }
542:
1.68 skrll 543: static inline unsigned int
544: xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport)
545: {
546: const unsigned int port = ctlrport - 1;
547: const uint8_t bit = __BIT(port % NBBY);
548:
549: return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit);
550: }
551:
552: /*
553: * Return the roothub port for a controller port. Both are 1..n.
554: */
555: static inline unsigned int
556: xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport)
557: {
558:
559: return sc->sc_ctlrportmap[ctrlport - 1];
560: }
561:
562: /*
563: * Return the controller port for a bus roothub port. Both are 1..n.
564: */
565: static inline unsigned int
566: xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn,
567: unsigned int rhport)
568: {
569:
570: return sc->sc_rhportmap[bn][rhport - 1];
571: }
572:
1.1 jakllsch 573: /* --- */
574:
575: void
576: xhci_childdet(device_t self, device_t child)
577: {
578: struct xhci_softc * const sc = device_private(self);
579:
1.84 msaitoh 580: KASSERT((sc->sc_child == child) || (sc->sc_child2 == child));
581: if (child == sc->sc_child2)
582: sc->sc_child2 = NULL;
583: else if (child == sc->sc_child)
1.1 jakllsch 584: sc->sc_child = NULL;
585: }
586:
587: int
588: xhci_detach(struct xhci_softc *sc, int flags)
589: {
590: int rv = 0;
591:
1.68 skrll 592: if (sc->sc_child2 != NULL) {
593: rv = config_detach(sc->sc_child2, flags);
594: if (rv != 0)
595: return rv;
1.86.2.2 pgoyette 596: KASSERT(sc->sc_child2 == NULL);
1.68 skrll 597: }
598:
599: if (sc->sc_child != NULL) {
1.1 jakllsch 600: rv = config_detach(sc->sc_child, flags);
1.68 skrll 601: if (rv != 0)
602: return rv;
1.86.2.2 pgoyette 603: KASSERT(sc->sc_child == NULL);
1.68 skrll 604: }
1.1 jakllsch 605:
606: /* XXX unconfigure/free slots */
607:
608: /* verify: */
609: xhci_rt_write_4(sc, XHCI_IMAN(0), 0);
610: xhci_op_write_4(sc, XHCI_USBCMD, 0);
611: /* do we need to wait for stop? */
612:
613: xhci_op_write_8(sc, XHCI_CRCR, 0);
614: xhci_ring_free(sc, &sc->sc_cr);
615: cv_destroy(&sc->sc_command_cv);
1.68 skrll 616: cv_destroy(&sc->sc_cmdbusy_cv);
1.1 jakllsch 617:
618: xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0);
619: xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0);
620: xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY);
621: xhci_ring_free(sc, &sc->sc_er);
622:
623: usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
624:
625: xhci_op_write_8(sc, XHCI_DCBAAP, 0);
626: usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
627:
628: kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots);
629:
1.82 skrll 630: kmem_free(sc->sc_ctlrportbus,
1.70 skrll 631: howmany(sc->sc_maxports * sizeof(uint8_t), NBBY));
1.68 skrll 632: kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int));
633:
634: for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
635: kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int));
636: }
637:
1.1 jakllsch 638: mutex_destroy(&sc->sc_lock);
639: mutex_destroy(&sc->sc_intr_lock);
640:
641: pool_cache_destroy(sc->sc_xferpool);
642:
643: return rv;
644: }
645:
646: int
647: xhci_activate(device_t self, enum devact act)
648: {
649: struct xhci_softc * const sc = device_private(self);
650:
651: switch (act) {
652: case DVACT_DEACTIVATE:
653: sc->sc_dying = true;
654: return 0;
655: default:
656: return EOPNOTSUPP;
657: }
658: }
659:
660: bool
661: xhci_suspend(device_t dv, const pmf_qual_t *qual)
662: {
663: return false;
664: }
665:
666: bool
667: xhci_resume(device_t dv, const pmf_qual_t *qual)
668: {
669: return false;
670: }
671:
672: bool
673: xhci_shutdown(device_t self, int flags)
674: {
675: return false;
676: }
677:
1.40 skrll 678: static int
679: xhci_hc_reset(struct xhci_softc * const sc)
680: {
681: uint32_t usbcmd, usbsts;
682: int i;
683:
684: /* Check controller not ready */
1.42 skrll 685: for (i = 0; i < XHCI_WAIT_CNR; i++) {
1.40 skrll 686: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
687: if ((usbsts & XHCI_STS_CNR) == 0)
688: break;
689: usb_delay_ms(&sc->sc_bus, 1);
690: }
1.42 skrll 691: if (i >= XHCI_WAIT_CNR) {
1.40 skrll 692: aprint_error_dev(sc->sc_dev, "controller not ready timeout\n");
693: return EIO;
694: }
695:
696: /* Halt controller */
697: usbcmd = 0;
698: xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
699: usb_delay_ms(&sc->sc_bus, 1);
700:
701: /* Reset controller */
702: usbcmd = XHCI_CMD_HCRST;
703: xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
1.42 skrll 704: for (i = 0; i < XHCI_WAIT_HCRST; i++) {
1.76 msaitoh 705: /*
706: * Wait 1ms first. Existing Intel xHCI requies 1ms delay to
707: * prevent system hang (Errata).
708: */
709: usb_delay_ms(&sc->sc_bus, 1);
1.40 skrll 710: usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
711: if ((usbcmd & XHCI_CMD_HCRST) == 0)
712: break;
713: }
1.42 skrll 714: if (i >= XHCI_WAIT_HCRST) {
1.40 skrll 715: aprint_error_dev(sc->sc_dev, "host controller reset timeout\n");
716: return EIO;
717: }
718:
719: /* Check controller not ready */
1.42 skrll 720: for (i = 0; i < XHCI_WAIT_CNR; i++) {
1.40 skrll 721: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
722: if ((usbsts & XHCI_STS_CNR) == 0)
723: break;
724: usb_delay_ms(&sc->sc_bus, 1);
725: }
1.42 skrll 726: if (i >= XHCI_WAIT_CNR) {
1.40 skrll 727: aprint_error_dev(sc->sc_dev,
728: "controller not ready timeout after reset\n");
729: return EIO;
730: }
731:
732: return 0;
733: }
734:
1.1 jakllsch 735:
1.68 skrll 736: /* 7.2 xHCI Support Protocol Capability */
737: static void
738: xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp)
739: {
740: /* XXX Cache this lot */
741:
742: const uint32_t w0 = xhci_read_4(sc, ecp);
743: const uint32_t w4 = xhci_read_4(sc, ecp + 4);
744: const uint32_t w8 = xhci_read_4(sc, ecp + 8);
745: const uint32_t wc = xhci_read_4(sc, ecp + 0xc);
746:
747: aprint_debug_dev(sc->sc_dev,
748: " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc);
749:
750: if (w4 != XHCI_XECP_USBID)
751: return;
752:
753: const int major = XHCI_XECP_SP_W0_MAJOR(w0);
754: const int minor = XHCI_XECP_SP_W0_MINOR(w0);
755: const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8);
756: const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8);
757:
758: const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16));
759: switch (mm) {
760: case 0x0200:
761: case 0x0300:
762: case 0x0301:
763: aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n",
764: major == 3 ? "ss" : "hs", cpo, cpo + cpc -1);
765: break;
766: default:
767: aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n",
768: major, minor);
769: return;
770: }
771:
772: const size_t bus = (major == 3) ? 0 : 1;
773:
774: /* Index arrays with 0..n-1 where ports are numbered 1..n */
775: for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) {
776: if (sc->sc_ctlrportmap[cp] != 0) {
777: aprint_error_dev(sc->sc_dev, "contoller port %zu "
778: "already assigned", cp);
779: continue;
780: }
781:
782: sc->sc_ctlrportbus[cp / NBBY] |=
783: bus == 0 ? 0 : __BIT(cp % NBBY);
784:
785: const size_t rhp = sc->sc_rhportcount[bus]++;
786:
787: KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0,
788: "bus %zu rhp %zu is %d", bus, rhp,
789: sc->sc_rhportmap[bus][rhp]);
790:
791: sc->sc_rhportmap[bus][rhp] = cp + 1;
792: sc->sc_ctlrportmap[cp] = rhp + 1;
793: }
794: }
795:
1.40 skrll 796: /* Process extended capabilities */
797: static void
798: xhci_ecp(struct xhci_softc *sc, uint32_t hcc)
799: {
800: XHCIHIST_FUNC(); XHCIHIST_CALLED();
801:
1.68 skrll 802: bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4;
1.40 skrll 803: while (ecp != 0) {
1.68 skrll 804: uint32_t ecr = xhci_read_4(sc, ecp);
1.69 skrll 805: aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr);
1.40 skrll 806: switch (XHCI_XECP_ID(ecr)) {
807: case XHCI_ID_PROTOCOLS: {
1.68 skrll 808: xhci_id_protocols(sc, ecp);
1.40 skrll 809: break;
810: }
811: case XHCI_ID_USB_LEGACY: {
812: uint8_t bios_sem;
813:
814: /* Take host controller ownership from BIOS */
815: bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM);
816: if (bios_sem) {
817: /* sets xHCI to be owned by OS */
818: xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1);
819: aprint_debug_dev(sc->sc_dev,
820: "waiting for BIOS to give up control\n");
821: for (int i = 0; i < 5000; i++) {
822: bios_sem = xhci_read_1(sc, ecp +
823: XHCI_XECP_BIOS_SEM);
824: if (bios_sem == 0)
825: break;
826: DELAY(1000);
827: }
828: if (bios_sem) {
829: aprint_error_dev(sc->sc_dev,
830: "timed out waiting for BIOS\n");
831: }
832: }
833: break;
834: }
835: default:
836: break;
837: }
838: ecr = xhci_read_4(sc, ecp);
839: if (XHCI_XECP_NEXT(ecr) == 0) {
840: ecp = 0;
841: } else {
842: ecp += XHCI_XECP_NEXT(ecr) * 4;
843: }
844: }
845: }
846:
1.34 skrll 847: #define XHCI_HCCPREV1_BITS \
848: "\177\020" /* New bitmask */ \
849: "f\020\020XECP\0" \
850: "f\014\4MAXPSA\0" \
851: "b\013CFC\0" \
852: "b\012SEC\0" \
853: "b\011SBD\0" \
854: "b\010FSE\0" \
855: "b\7NSS\0" \
856: "b\6LTC\0" \
857: "b\5LHRC\0" \
858: "b\4PIND\0" \
859: "b\3PPC\0" \
860: "b\2CZC\0" \
861: "b\1BNC\0" \
862: "b\0AC64\0" \
863: "\0"
864: #define XHCI_HCCV1_x_BITS \
865: "\177\020" /* New bitmask */ \
866: "f\020\020XECP\0" \
867: "f\014\4MAXPSA\0" \
868: "b\013CFC\0" \
869: "b\012SEC\0" \
870: "b\011SPC\0" \
871: "b\010PAE\0" \
872: "b\7NSS\0" \
873: "b\6LTC\0" \
874: "b\5LHRC\0" \
875: "b\4PIND\0" \
876: "b\3PPC\0" \
877: "b\2CSZ\0" \
878: "b\1BNC\0" \
879: "b\0AC64\0" \
880: "\0"
1.1 jakllsch 881:
1.86.2.5 pgoyette 882: #define XHCI_HCC2_BITS \
883: "\177\020" /* New bitmask */ \
884: "b\7ETC_TSC\0" \
885: "b\6ETC\0" \
886: "b\5CIC\0" \
887: "b\4LEC\0" \
888: "b\3CTC\0" \
889: "b\2FSC\0" \
890: "b\1CMC\0" \
891: "b\0U3C\0" \
892: "\0"
893:
1.74 jmcneill 894: void
895: xhci_start(struct xhci_softc *sc)
896: {
897: xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA);
898: if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0)
899: /* Intel xhci needs interrupt rate moderated. */
900: xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP);
901: else
902: xhci_rt_write_4(sc, XHCI_IMOD(0), 0);
903: aprint_debug_dev(sc->sc_dev, "current IMOD %u\n",
904: xhci_rt_read_4(sc, XHCI_IMOD(0)));
905:
906: xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */
907: aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n",
908: xhci_op_read_4(sc, XHCI_USBCMD));
909: }
910:
1.15 skrll 911: int
1.1 jakllsch 912: xhci_init(struct xhci_softc *sc)
913: {
914: bus_size_t bsz;
1.86.2.5 pgoyette 915: uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff, hcc2;
1.40 skrll 916: uint32_t pagesize, config;
917: int i = 0;
1.1 jakllsch 918: uint16_t hciversion;
919: uint8_t caplength;
920:
1.27 skrll 921: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 922:
1.68 skrll 923: /* Set up the bus struct for the usb 3 and usb 2 buses */
924: sc->sc_bus.ub_methods = &xhci_bus_methods;
925: sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe);
1.34 skrll 926: sc->sc_bus.ub_usedma = true;
1.68 skrll 927: sc->sc_bus.ub_hcpriv = sc;
928:
929: sc->sc_bus2.ub_methods = &xhci_bus_methods;
930: sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe);
931: sc->sc_bus2.ub_revision = USBREV_2_0;
932: sc->sc_bus2.ub_usedma = true;
933: sc->sc_bus2.ub_hcpriv = sc;
934: sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag;
1.1 jakllsch 935:
936: cap = xhci_read_4(sc, XHCI_CAPLENGTH);
937: caplength = XHCI_CAP_CAPLENGTH(cap);
938: hciversion = XHCI_CAP_HCIVERSION(cap);
939:
1.34 skrll 940: if (hciversion < XHCI_HCIVERSION_0_96 ||
1.86.2.6 pgoyette 941: hciversion >= 0x0200) {
1.1 jakllsch 942: aprint_normal_dev(sc->sc_dev,
943: "xHCI version %x.%x not known to be supported\n",
944: (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
945: } else {
946: aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n",
947: (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
948: }
949:
950: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength,
951: &sc->sc_cbh) != 0) {
952: aprint_error_dev(sc->sc_dev, "capability subregion failure\n");
1.15 skrll 953: return ENOMEM;
1.1 jakllsch 954: }
955:
956: hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1);
957: sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1);
958: sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1);
959: sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1);
960: hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2);
1.34 skrll 961: hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3);
962: aprint_debug_dev(sc->sc_dev,
963: "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3);
964:
1.1 jakllsch 965: hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS);
966: sc->sc_ac64 = XHCI_HCC_AC64(hcc);
967: sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32;
968:
1.34 skrll 969: char sbuf[128];
970: if (hciversion < XHCI_HCIVERSION_1_0)
971: snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc);
972: else
973: snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc);
974: aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf);
1.12 jakllsch 975: aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4);
1.86.2.5 pgoyette 976: if (hciversion >= XHCI_HCIVERSION_1_1) {
977: hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2);
978: snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, hcc2);
979: aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf);
980: }
1.34 skrll 981:
1.68 skrll 982: /* default all ports to bus 0, i.e. usb 3 */
1.70 skrll 983: sc->sc_ctlrportbus = kmem_zalloc(
984: howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP);
1.68 skrll 985: sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
986:
987: /* controller port to bus roothub port map */
988: for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
989: sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
990: }
991:
992: /*
993: * Process all Extended Capabilities
994: */
1.40 skrll 995: xhci_ecp(sc, hcc);
1.1 jakllsch 996:
1.68 skrll 997: bsz = XHCI_PORTSC(sc->sc_maxports);
1.1 jakllsch 998: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz,
999: &sc->sc_obh) != 0) {
1000: aprint_error_dev(sc->sc_dev, "operational subregion failure\n");
1.15 skrll 1001: return ENOMEM;
1.1 jakllsch 1002: }
1003:
1004: dboff = xhci_cap_read_4(sc, XHCI_DBOFF);
1005: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff,
1006: sc->sc_maxslots * 4, &sc->sc_dbh) != 0) {
1007: aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n");
1.15 skrll 1008: return ENOMEM;
1.1 jakllsch 1009: }
1010:
1011: rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF);
1012: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff,
1013: sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) {
1014: aprint_error_dev(sc->sc_dev, "runtime subregion failure\n");
1.15 skrll 1015: return ENOMEM;
1.1 jakllsch 1016: }
1017:
1.40 skrll 1018: int rv;
1019: rv = xhci_hc_reset(sc);
1020: if (rv != 0) {
1021: return rv;
1.37 skrll 1022: }
1.1 jakllsch 1023:
1.34 skrll 1024: if (sc->sc_vendor_init)
1025: sc->sc_vendor_init(sc);
1026:
1.1 jakllsch 1027: pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE);
1.12 jakllsch 1028: aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize);
1.1 jakllsch 1029: pagesize = ffs(pagesize);
1.37 skrll 1030: if (pagesize == 0) {
1031: aprint_error_dev(sc->sc_dev, "pagesize is 0\n");
1.15 skrll 1032: return EIO;
1.37 skrll 1033: }
1.1 jakllsch 1034: sc->sc_pgsz = 1 << (12 + (pagesize - 1));
1.12 jakllsch 1035: aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz);
1036: aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n",
1.1 jakllsch 1037: (uint32_t)sc->sc_maxslots);
1.34 skrll 1038: aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports);
1.1 jakllsch 1039:
1.5 matt 1040: usbd_status err;
1041:
1042: sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2);
1.12 jakllsch 1043: aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf);
1.5 matt 1044: if (sc->sc_maxspbuf != 0) {
1045: err = usb_allocmem(&sc->sc_bus,
1046: sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t),
1047: &sc->sc_spbufarray_dma);
1.37 skrll 1048: if (err) {
1049: aprint_error_dev(sc->sc_dev,
1050: "spbufarray init fail, err %d\n", err);
1051: return ENOMEM;
1052: }
1.30 skrll 1053:
1.36 skrll 1054: sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) *
1055: sc->sc_maxspbuf, KM_SLEEP);
1.5 matt 1056: uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0);
1057: for (i = 0; i < sc->sc_maxspbuf; i++) {
1058: usb_dma_t * const dma = &sc->sc_spbuf_dma[i];
1059: /* allocate contexts */
1060: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz,
1061: sc->sc_pgsz, dma);
1.37 skrll 1062: if (err) {
1063: aprint_error_dev(sc->sc_dev,
1064: "spbufarray_dma init fail, err %d\n", err);
1065: rv = ENOMEM;
1066: goto bad1;
1067: }
1.5 matt 1068: spbufarray[i] = htole64(DMAADDR(dma, 0));
1069: usb_syncmem(dma, 0, sc->sc_pgsz,
1070: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1071: }
1072:
1.30 skrll 1073: usb_syncmem(&sc->sc_spbufarray_dma, 0,
1.5 matt 1074: sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE);
1075: }
1076:
1.1 jakllsch 1077: config = xhci_op_read_4(sc, XHCI_CONFIG);
1078: config &= ~0xFF;
1079: config |= sc->sc_maxslots & 0xFF;
1080: xhci_op_write_4(sc, XHCI_CONFIG, config);
1081:
1082: err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS,
1083: XHCI_COMMAND_RING_SEGMENTS_ALIGN);
1084: if (err) {
1.37 skrll 1085: aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n",
1086: err);
1087: rv = ENOMEM;
1088: goto bad1;
1.1 jakllsch 1089: }
1090:
1091: err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS,
1092: XHCI_EVENT_RING_SEGMENTS_ALIGN);
1093: if (err) {
1.37 skrll 1094: aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n",
1095: err);
1096: rv = ENOMEM;
1097: goto bad2;
1.1 jakllsch 1098: }
1099:
1.16 skrll 1100: usb_dma_t *dma;
1101: size_t size;
1102: size_t align;
1103:
1104: dma = &sc->sc_eventst_dma;
1105: size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE,
1106: XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN);
1.37 skrll 1107: KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size);
1.16 skrll 1108: align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN;
1109: err = usb_allocmem(&sc->sc_bus, size, align, dma);
1.37 skrll 1110: if (err) {
1111: aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n",
1112: err);
1113: rv = ENOMEM;
1114: goto bad3;
1115: }
1.16 skrll 1116:
1117: memset(KERNADDR(dma, 0), 0, size);
1118: usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
1.37 skrll 1119: aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n",
1.16 skrll 1120: (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0),
1121: KERNADDR(&sc->sc_eventst_dma, 0),
1.34 skrll 1122: sc->sc_eventst_dma.udma_block->size);
1.16 skrll 1123:
1124: dma = &sc->sc_dcbaa_dma;
1125: size = (1 + sc->sc_maxslots) * sizeof(uint64_t);
1.37 skrll 1126: KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size);
1.16 skrll 1127: align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN;
1128: err = usb_allocmem(&sc->sc_bus, size, align, dma);
1.37 skrll 1129: if (err) {
1130: aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err);
1131: rv = ENOMEM;
1132: goto bad4;
1133: }
1134: aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n",
1135: (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0),
1136: KERNADDR(&sc->sc_dcbaa_dma, 0),
1137: sc->sc_dcbaa_dma.udma_block->size);
1.16 skrll 1138:
1139: memset(KERNADDR(dma, 0), 0, size);
1140: if (sc->sc_maxspbuf != 0) {
1141: /*
1142: * DCBA entry 0 hold the scratchbuf array pointer.
1143: */
1144: *(uint64_t *)KERNADDR(dma, 0) =
1145: htole64(DMAADDR(&sc->sc_spbufarray_dma, 0));
1.1 jakllsch 1146: }
1.16 skrll 1147: usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 1148:
1149: sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots,
1150: KM_SLEEP);
1.37 skrll 1151: if (sc->sc_slots == NULL) {
1152: aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err);
1153: rv = ENOMEM;
1154: goto bad;
1155: }
1156:
1157: sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0,
1158: "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
1159: if (sc->sc_xferpool == NULL) {
1160: aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n",
1161: err);
1162: rv = ENOMEM;
1163: goto bad;
1164: }
1.1 jakllsch 1165:
1166: cv_init(&sc->sc_command_cv, "xhcicmd");
1.68 skrll 1167: cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq");
1.34 skrll 1168: mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1169: mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
1170:
1.1 jakllsch 1171: struct xhci_erste *erst;
1172: erst = KERNADDR(&sc->sc_eventst_dma, 0);
1173: erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0));
1.52 skrll 1174: erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb);
1.1 jakllsch 1175: erst[0].erste_3 = htole32(0);
1176: usb_syncmem(&sc->sc_eventst_dma, 0,
1177: XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE);
1178:
1179: xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS);
1180: xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0));
1181: xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) |
1182: XHCI_ERDP_LO_BUSY);
1183: xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0));
1184: xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) |
1185: sc->sc_cr.xr_cs);
1186:
1.79 christos 1187: HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0),
1.1 jakllsch 1188: XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS);
1189:
1.74 jmcneill 1190: if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0)
1191: xhci_start(sc);
1.1 jakllsch 1192:
1.37 skrll 1193: return 0;
1194:
1195: bad:
1196: if (sc->sc_xferpool) {
1197: pool_cache_destroy(sc->sc_xferpool);
1198: sc->sc_xferpool = NULL;
1199: }
1200:
1201: if (sc->sc_slots) {
1202: kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) *
1203: sc->sc_maxslots);
1204: sc->sc_slots = NULL;
1205: }
1206:
1207: usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
1208: bad4:
1209: usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
1210: bad3:
1211: xhci_ring_free(sc, &sc->sc_er);
1212: bad2:
1213: xhci_ring_free(sc, &sc->sc_cr);
1214: i = sc->sc_maxspbuf;
1215: bad1:
1216: for (int j = 0; j < i; j++)
1217: usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]);
1218: usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma);
1219:
1220: return rv;
1.1 jakllsch 1221: }
1222:
1.73 skrll 1223: static inline bool
1224: xhci_polling_p(struct xhci_softc * const sc)
1225: {
1226: return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling;
1227: }
1228:
1.1 jakllsch 1229: int
1230: xhci_intr(void *v)
1231: {
1232: struct xhci_softc * const sc = v;
1.25 skrll 1233: int ret = 0;
1.1 jakllsch 1234:
1.27 skrll 1235: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1236:
1.25 skrll 1237: if (sc == NULL)
1.1 jakllsch 1238: return 0;
1239:
1.25 skrll 1240: mutex_spin_enter(&sc->sc_intr_lock);
1241:
1242: if (sc->sc_dying || !device_has_power(sc->sc_dev))
1243: goto done;
1244:
1.1 jakllsch 1245: /* If we get an interrupt while polling, then just ignore it. */
1.73 skrll 1246: if (xhci_polling_p(sc)) {
1.1 jakllsch 1247: #ifdef DIAGNOSTIC
1.27 skrll 1248: DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1.1 jakllsch 1249: #endif
1.25 skrll 1250: goto done;
1.1 jakllsch 1251: }
1252:
1.25 skrll 1253: ret = xhci_intr1(sc);
1.73 skrll 1254: if (ret) {
1.86.2.3 pgoyette 1255: KASSERT(sc->sc_child || sc->sc_child2);
1256:
1257: /*
1258: * One of child busses could be already detached. It doesn't
1259: * matter on which of the two the softintr is scheduled.
1260: */
1261: if (sc->sc_child)
1262: usb_schedsoftintr(&sc->sc_bus);
1263: else
1264: usb_schedsoftintr(&sc->sc_bus2);
1.73 skrll 1265: }
1.25 skrll 1266: done:
1267: mutex_spin_exit(&sc->sc_intr_lock);
1268: return ret;
1.1 jakllsch 1269: }
1270:
1271: int
1272: xhci_intr1(struct xhci_softc * const sc)
1273: {
1274: uint32_t usbsts;
1275: uint32_t iman;
1276:
1.27 skrll 1277: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1278:
1.1 jakllsch 1279: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.75 pgoyette 1280: DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0);
1.86.2.3 pgoyette 1281: if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD |
1282: XHCI_STS_HCE)) == 0) {
1283: DPRINTFN(16, "ignored intr not for %s",
1.86.2.6 pgoyette 1284: (uintptr_t)device_xname(sc->sc_dev), 0, 0, 0);
1.1 jakllsch 1285: return 0;
1286: }
1.86.2.3 pgoyette 1287:
1288: /*
1289: * Clear EINT and other transient flags, to not misenterpret
1290: * next shared interrupt. Also, to avoid race, EINT must be cleared
1291: * before XHCI_IMAN_INTR_PEND is cleared.
1292: */
1293: xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0);
1294:
1295: #ifdef XHCI_DEBUG
1.1 jakllsch 1296: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.75 pgoyette 1297: DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0);
1.86.2.3 pgoyette 1298: #endif
1.1 jakllsch 1299:
1300: iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1.75 pgoyette 1301: DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0);
1.34 skrll 1302: iman |= XHCI_IMAN_INTR_PEND;
1.1 jakllsch 1303: xhci_rt_write_4(sc, XHCI_IMAN(0), iman);
1.86.2.3 pgoyette 1304:
1305: #ifdef XHCI_DEBUG
1.1 jakllsch 1306: iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1.75 pgoyette 1307: DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0);
1.1 jakllsch 1308: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.75 pgoyette 1309: DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0);
1.86.2.3 pgoyette 1310: #endif
1.1 jakllsch 1311:
1312: return 1;
1313: }
1314:
1.34 skrll 1315: /*
1316: * 3 port speed types used in USB stack
1317: *
1318: * usbdi speed
1319: * definition: USB_SPEED_* in usb.h
1320: * They are used in struct usbd_device in USB stack.
1321: * ioctl interface uses these values too.
1322: * port_status speed
1323: * definition: UPS_*_SPEED in usb.h
1324: * They are used in usb_port_status_t and valid only for USB 2.0.
1325: * Speed value is always 0 for Super Speed or more, and dwExtPortStatus
1326: * of usb_port_status_ext_t indicates port speed.
1327: * Note that some 3.0 values overlap with 2.0 values.
1328: * (e.g. 0x200 means UPS_POER_POWER_SS in SS and
1329: * means UPS_LOW_SPEED in HS.)
1330: * port status returned from hub also uses these values.
1331: * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed
1332: * or more.
1333: * xspeed:
1334: * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1)
1335: * They are used in only slot context and PORTSC reg of xhci.
1336: * The difference between usbdi speed and xspeed is
1337: * that FS and LS values are swapped.
1338: */
1339:
1340: /* convert usbdi speed to xspeed */
1341: static int
1342: xhci_speed2xspeed(int speed)
1343: {
1344: switch (speed) {
1345: case USB_SPEED_LOW: return 2;
1346: case USB_SPEED_FULL: return 1;
1347: default: return speed;
1348: }
1349: }
1350:
1351: #if 0
1352: /* convert xspeed to usbdi speed */
1353: static int
1354: xhci_xspeed2speed(int xspeed)
1355: {
1356: switch (xspeed) {
1357: case 1: return USB_SPEED_FULL;
1358: case 2: return USB_SPEED_LOW;
1359: default: return xspeed;
1360: }
1361: }
1362: #endif
1363:
1364: /* convert xspeed to port status speed */
1365: static int
1366: xhci_xspeed2psspeed(int xspeed)
1367: {
1368: switch (xspeed) {
1369: case 0: return 0;
1370: case 1: return UPS_FULL_SPEED;
1371: case 2: return UPS_LOW_SPEED;
1372: case 3: return UPS_HIGH_SPEED;
1373: default: return UPS_OTHER_SPEED;
1374: }
1375: }
1376:
1377: /*
1.54 skrll 1378: * Construct input contexts and issue TRB to open pipe.
1.34 skrll 1379: */
1.1 jakllsch 1380: static usbd_status
1.34 skrll 1381: xhci_configure_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1382: {
1.34 skrll 1383: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1384: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1.81 hannken 1385: #ifdef USB_DEBUG
1.34 skrll 1386: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.79 christos 1387: #endif
1.1 jakllsch 1388: struct xhci_trb trb;
1389: usbd_status err;
1390:
1.27 skrll 1391: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1392: DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx",
1.34 skrll 1393: xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress,
1394: pipe->up_endpoint->ue_edesc->bmAttributes);
1.1 jakllsch 1395:
1396: /* XXX ensure input context is available? */
1397:
1398: memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz);
1399:
1.51 skrll 1400: /* set up context */
1401: xhci_setup_ctx(pipe);
1.1 jakllsch 1402:
1.79 christos 1403: HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0),
1.1 jakllsch 1404: sc->sc_ctxsz * 1);
1.79 christos 1405: HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs,
1.1 jakllsch 1406: xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1);
1407:
1408: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1409: trb.trb_2 = 0;
1410: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1411: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1412:
1413: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1414:
1415: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1.79 christos 1416: HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci),
1.1 jakllsch 1417: sc->sc_ctxsz * 1);
1418:
1419: return err;
1420: }
1421:
1.34 skrll 1422: #if 0
1.1 jakllsch 1423: static usbd_status
1.34 skrll 1424: xhci_unconfigure_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1425: {
1.27 skrll 1426: #ifdef USB_DEBUG
1.34 skrll 1427: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1.27 skrll 1428: #endif
1429:
1430: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1431: DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0);
1.27 skrll 1432:
1.1 jakllsch 1433: return USBD_NORMAL_COMPLETION;
1434: }
1.34 skrll 1435: #endif
1.1 jakllsch 1436:
1.34 skrll 1437: /* 4.6.8, 6.4.3.7 */
1.1 jakllsch 1438: static usbd_status
1.63 skrll 1439: xhci_reset_endpoint_locked(struct usbd_pipe *pipe)
1.1 jakllsch 1440: {
1.34 skrll 1441: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1442: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1443: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1444: struct xhci_trb trb;
1445: usbd_status err;
1446:
1.27 skrll 1447: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1448: DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1.34 skrll 1449:
1.63 skrll 1450: KASSERT(mutex_owned(&sc->sc_lock));
1451:
1.1 jakllsch 1452: trb.trb_0 = 0;
1453: trb.trb_2 = 0;
1454: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1455: XHCI_TRB_3_EP_SET(dci) |
1456: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP);
1457:
1.63 skrll 1458: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.1 jakllsch 1459:
1460: return err;
1461: }
1462:
1.63 skrll 1463: static usbd_status
1464: xhci_reset_endpoint(struct usbd_pipe *pipe)
1465: {
1466: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1467:
1468: mutex_enter(&sc->sc_lock);
1469: usbd_status ret = xhci_reset_endpoint_locked(pipe);
1470: mutex_exit(&sc->sc_lock);
1471:
1472: return ret;
1473: }
1474:
1.34 skrll 1475: /*
1476: * 4.6.9, 6.4.3.8
1477: * Stop execution of TDs on xfer ring.
1478: * Should be called with sc_lock held.
1479: */
1.1 jakllsch 1480: static usbd_status
1.34 skrll 1481: xhci_stop_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1482: {
1.34 skrll 1483: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1484: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1.1 jakllsch 1485: struct xhci_trb trb;
1486: usbd_status err;
1.34 skrll 1487: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1488:
1.27 skrll 1489: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1490: DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1.34 skrll 1491:
1492: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1493:
1494: trb.trb_0 = 0;
1495: trb.trb_2 = 0;
1496: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1497: XHCI_TRB_3_EP_SET(dci) |
1498: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP);
1499:
1.34 skrll 1500: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.1 jakllsch 1501:
1502: return err;
1503: }
1504:
1.34 skrll 1505: /*
1506: * Set TR Dequeue Pointer.
1.54 skrll 1507: * xHCI 1.1 4.6.10 6.4.3.9
1508: * Purge all of the TRBs on ring and reinitialize ring.
1509: * Set TR dequeue Pointr to 0 and Cycle State to 1.
1510: * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE
1511: * error will be generated.
1.34 skrll 1512: */
1.1 jakllsch 1513: static usbd_status
1.63 skrll 1514: xhci_set_dequeue_locked(struct usbd_pipe *pipe)
1.1 jakllsch 1515: {
1.34 skrll 1516: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1517: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1518: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1519: struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr;
1520: struct xhci_trb trb;
1521: usbd_status err;
1522:
1.27 skrll 1523: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1524: DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1.1 jakllsch 1525:
1.63 skrll 1526: KASSERT(mutex_owned(&sc->sc_lock));
1527:
1.56 skrll 1528: xhci_host_dequeue(xr);
1.1 jakllsch 1529:
1.34 skrll 1530: /* set DCS */
1.1 jakllsch 1531: trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */
1532: trb.trb_2 = 0;
1533: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1534: XHCI_TRB_3_EP_SET(dci) |
1535: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE);
1536:
1.63 skrll 1537: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.1 jakllsch 1538:
1539: return err;
1540: }
1541:
1.63 skrll 1542: static usbd_status
1543: xhci_set_dequeue(struct usbd_pipe *pipe)
1544: {
1545: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1546:
1547: mutex_enter(&sc->sc_lock);
1548: usbd_status ret = xhci_set_dequeue_locked(pipe);
1549: mutex_exit(&sc->sc_lock);
1550:
1551: return ret;
1552: }
1553:
1.34 skrll 1554: /*
1555: * Open new pipe: called from usbd_setup_pipe_flags.
1556: * Fills methods of pipe.
1557: * If pipe is not for ep0, calls configure_endpoint.
1558: */
1.1 jakllsch 1559: static usbd_status
1.34 skrll 1560: xhci_open(struct usbd_pipe *pipe)
1.1 jakllsch 1561: {
1.34 skrll 1562: struct usbd_device * const dev = pipe->up_dev;
1563: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
1564: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1.1 jakllsch 1565: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1566:
1.27 skrll 1567: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1568: DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr,
1.53 skrll 1569: dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed);
1.75 pgoyette 1570: DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx",
1.53 skrll 1571: xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress,
1572: ed->bmAttributes);
1.75 pgoyette 1573: DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize),
1574: ed->bInterval, 0, 0);
1.1 jakllsch 1575:
1576: if (sc->sc_dying)
1577: return USBD_IOERROR;
1578:
1579: /* Root Hub */
1.34 skrll 1580: if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) {
1.1 jakllsch 1581: switch (ed->bEndpointAddress) {
1582: case USB_CONTROL_ENDPOINT:
1.34 skrll 1583: pipe->up_methods = &roothub_ctrl_methods;
1.1 jakllsch 1584: break;
1.34 skrll 1585: case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
1586: pipe->up_methods = &xhci_root_intr_methods;
1.1 jakllsch 1587: break;
1588: default:
1.34 skrll 1589: pipe->up_methods = NULL;
1.75 pgoyette 1590: DPRINTFN(0, "bad bEndpointAddress 0x%02jx",
1.27 skrll 1591: ed->bEndpointAddress, 0, 0, 0);
1.1 jakllsch 1592: return USBD_INVAL;
1593: }
1594: return USBD_NORMAL_COMPLETION;
1595: }
1596:
1597: switch (xfertype) {
1598: case UE_CONTROL:
1.34 skrll 1599: pipe->up_methods = &xhci_device_ctrl_methods;
1.1 jakllsch 1600: break;
1601: case UE_ISOCHRONOUS:
1.34 skrll 1602: pipe->up_methods = &xhci_device_isoc_methods;
1.1 jakllsch 1603: return USBD_INVAL;
1604: break;
1605: case UE_BULK:
1.34 skrll 1606: pipe->up_methods = &xhci_device_bulk_methods;
1.1 jakllsch 1607: break;
1608: case UE_INTERRUPT:
1.34 skrll 1609: pipe->up_methods = &xhci_device_intr_methods;
1.1 jakllsch 1610: break;
1611: default:
1612: return USBD_IOERROR;
1613: break;
1614: }
1615:
1616: if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT)
1.34 skrll 1617: return xhci_configure_endpoint(pipe);
1.1 jakllsch 1618:
1619: return USBD_NORMAL_COMPLETION;
1620: }
1621:
1.34 skrll 1622: /*
1623: * Closes pipe, called from usbd_kill_pipe via close methods.
1624: * If the endpoint to be closed is ep0, disable_slot.
1625: * Should be called with sc_lock held.
1626: */
1.1 jakllsch 1627: static void
1.34 skrll 1628: xhci_close_pipe(struct usbd_pipe *pipe)
1.1 jakllsch 1629: {
1.34 skrll 1630: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1631: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1632: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1633: const u_int dci = xhci_ep_get_dci(ed);
1634: struct xhci_trb trb;
1635: uint32_t *cp;
1.1 jakllsch 1636:
1.27 skrll 1637: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 1638:
1.34 skrll 1639: if (sc->sc_dying)
1.1 jakllsch 1640: return;
1641:
1.41 skrll 1642: /* xs is uninitialized before xhci_init_slot */
1.34 skrll 1643: if (xs == NULL || xs->xs_idx == 0)
1.1 jakllsch 1644: return;
1645:
1.75 pgoyette 1646: DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx,
1647: dci, 0);
1.1 jakllsch 1648:
1.34 skrll 1649: KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx");
1650: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1651:
1.34 skrll 1652: if (pipe->up_dev->ud_depth == 0)
1653: return;
1.1 jakllsch 1654:
1.34 skrll 1655: if (dci == XHCI_DCI_EP_CONTROL) {
1656: DPRINTFN(4, "closing ep0", 0, 0, 0, 0);
1657: xhci_disable_slot(sc, xs->xs_idx);
1658: return;
1659: }
1.1 jakllsch 1660:
1.66 skrll 1661: if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED)
1662: (void)xhci_stop_endpoint(pipe);
1.1 jakllsch 1663:
1.34 skrll 1664: /*
1665: * set appropriate bit to be dropped.
1666: * don't set DC bit to 1, otherwise all endpoints
1667: * would be deconfigured.
1668: */
1669: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
1670: cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci));
1671: cp[1] = htole32(0);
1.1 jakllsch 1672:
1.34 skrll 1673: /* XXX should be most significant one, not dci? */
1674: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1675: cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci));
1.1 jakllsch 1676:
1.55 skrll 1677: /* configure ep context performs an implicit dequeue */
1678: xhci_host_dequeue(&xs->xs_ep[dci].xe_tr);
1679:
1.34 skrll 1680: /* sync input contexts before they are read from memory */
1681: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 1682:
1.34 skrll 1683: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1684: trb.trb_2 = 0;
1685: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1686: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1.1 jakllsch 1687:
1.34 skrll 1688: (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1689: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1690: }
1.1 jakllsch 1691:
1.34 skrll 1692: /*
1693: * Abort transfer.
1.63 skrll 1694: * Should be called with sc_lock held.
1.34 skrll 1695: */
1696: static void
1697: xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
1698: {
1.86.2.6 pgoyette 1699: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 1700: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.63 skrll 1701: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
1702: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1703:
1.86.2.6 pgoyette 1704: KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT),
1705: "invalid status for abort: %d", (int)status);
1706:
1.75 pgoyette 1707: DPRINTFN(4, "xfer %#jx pipe %#jx status %jd",
1708: (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0);
1.1 jakllsch 1709:
1.34 skrll 1710: KASSERT(mutex_owned(&sc->sc_lock));
1.86.2.6 pgoyette 1711: ASSERT_SLEEPABLE();
1.1 jakllsch 1712:
1.86.2.6 pgoyette 1713: if (status == USBD_CANCELLED) {
1714: /*
1715: * We are synchronously aborting. Try to stop the
1716: * callout and task, but if we can't, wait for them to
1717: * complete.
1718: */
1719: callout_halt(&xfer->ux_callout, &sc->sc_lock);
1720: usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask,
1721: USB_TASKQ_HC, &sc->sc_lock);
1722: } else {
1723: /* Otherwise, we are timing out. */
1724: KASSERT(status == USBD_TIMEOUT);
1.1 jakllsch 1725: }
1.34 skrll 1726:
1.63 skrll 1727: /*
1.86.2.6 pgoyette 1728: * The xfer cannot have been cancelled already. It is the
1729: * responsibility of the caller of usbd_abort_pipe not to try
1730: * to abort a pipe multiple times, whether concurrently or
1731: * sequentially.
1.63 skrll 1732: */
1.86.2.6 pgoyette 1733: KASSERT(xfer->ux_status != USBD_CANCELLED);
1734:
1735: /* Only the timeout, which runs only once, can time it out. */
1736: KASSERT(xfer->ux_status != USBD_TIMEOUT);
1737:
1738: /* If anyone else beat us, we're done. */
1739: if (xfer->ux_status != USBD_IN_PROGRESS)
1.63 skrll 1740: return;
1.86.2.6 pgoyette 1741:
1742: /* We beat everyone else. Claim the status. */
1743: xfer->ux_status = status;
1.63 skrll 1744:
1745: /*
1.86.2.6 pgoyette 1746: * If we're dying, skip the hardware action and just notify the
1747: * software that we're done.
1.63 skrll 1748: */
1.86.2.6 pgoyette 1749: if (sc->sc_dying) {
1750: DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer,
1751: xfer->ux_status, 0, 0);
1752: goto dying;
1753: }
1.63 skrll 1754:
1755: /*
1.86.2.6 pgoyette 1756: * HC Step 1: Stop execution of TD on the ring.
1.63 skrll 1757: */
1758: switch (xhci_get_epstate(sc, xs, dci)) {
1759: case XHCI_EPSTATE_HALTED:
1760: (void)xhci_reset_endpoint_locked(xfer->ux_pipe);
1761: break;
1762: case XHCI_EPSTATE_STOPPED:
1763: break;
1764: default:
1765: (void)xhci_stop_endpoint(xfer->ux_pipe);
1766: break;
1767: }
1768: #ifdef DIAGNOSTIC
1769: uint32_t epst = xhci_get_epstate(sc, xs, dci);
1770: if (epst != XHCI_EPSTATE_STOPPED)
1.75 pgoyette 1771: DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0);
1.63 skrll 1772: #endif
1773:
1774: /*
1.86.2.6 pgoyette 1775: * HC Step 2: Remove any vestiges of the xfer from the ring.
1.63 skrll 1776: */
1777: xhci_set_dequeue_locked(xfer->ux_pipe);
1778:
1779: /*
1.86.2.6 pgoyette 1780: * Final Step: Notify completion to waiting xfers.
1.63 skrll 1781: */
1.86.2.6 pgoyette 1782: dying:
1.34 skrll 1783: usb_transfer_complete(xfer);
1784: DPRINTFN(14, "end", 0, 0, 0, 0);
1785:
1786: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1787: }
1788:
1.55 skrll 1789: static void
1790: xhci_host_dequeue(struct xhci_ring * const xr)
1791: {
1792: /* When dequeueing the controller, update our struct copy too */
1793: memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE);
1794: usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE,
1795: BUS_DMASYNC_PREWRITE);
1796: memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies));
1797:
1798: xr->xr_ep = 0;
1799: xr->xr_cs = 1;
1800: }
1801:
1.34 skrll 1802: /*
1803: * Recover STALLed endpoint.
1804: * xHCI 1.1 sect 4.10.2.1
1805: * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove
1806: * all transfers on transfer ring.
1807: * These are done in thread context asynchronously.
1808: */
1.1 jakllsch 1809: static void
1.34 skrll 1810: xhci_clear_endpoint_stall_async_task(void *cookie)
1.1 jakllsch 1811: {
1.34 skrll 1812: struct usbd_xfer * const xfer = cookie;
1813: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1814: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
1815: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1816: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.1 jakllsch 1817:
1.27 skrll 1818: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1819: DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx,
1820: dci, 0);
1.1 jakllsch 1821:
1.34 skrll 1822: xhci_reset_endpoint(xfer->ux_pipe);
1823: xhci_set_dequeue(xfer->ux_pipe);
1824:
1825: mutex_enter(&sc->sc_lock);
1826: tr->is_halted = false;
1827: usb_transfer_complete(xfer);
1828: mutex_exit(&sc->sc_lock);
1829: DPRINTFN(4, "ends", 0, 0, 0, 0);
1830: }
1831:
1832: static usbd_status
1833: xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer)
1834: {
1835: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1836: struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe;
1837:
1838: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1839: DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
1.34 skrll 1840:
1841: if (sc->sc_dying) {
1842: return USBD_IOERROR;
1843: }
1844:
1845: usb_init_task(&xp->xp_async_task,
1846: xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE);
1847: usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC);
1848: DPRINTFN(4, "ends", 0, 0, 0, 0);
1849:
1850: return USBD_NORMAL_COMPLETION;
1851: }
1852:
1853: /* Process roothub port status/change events and notify to uhub_intr. */
1854: static void
1.68 skrll 1855: xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport)
1.34 skrll 1856: {
1857: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 1858: DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev),
1.68 skrll 1859: ctlrport, 0, 0);
1.34 skrll 1860:
1.68 skrll 1861: if (ctlrport > sc->sc_maxports)
1.34 skrll 1862: return;
1863:
1.68 skrll 1864: const size_t bn = xhci_ctlrport2bus(sc, ctlrport);
1865: const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport);
1866: struct usbd_xfer * const xfer = sc->sc_intrxfer[bn];
1867:
1.75 pgoyette 1868: DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change",
1869: device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer);
1.68 skrll 1870:
1871: if (xfer == NULL)
1.34 skrll 1872: return;
1873:
1.68 skrll 1874: uint8_t *p = xfer->ux_buf;
1.34 skrll 1875: memset(p, 0, xfer->ux_length);
1.68 skrll 1876: p[rhp / NBBY] |= 1 << (rhp % NBBY);
1.34 skrll 1877: xfer->ux_actlen = xfer->ux_length;
1878: xfer->ux_status = USBD_NORMAL_COMPLETION;
1879: usb_transfer_complete(xfer);
1880: }
1881:
1882: /* Process Transfer Events */
1883: static void
1884: xhci_event_transfer(struct xhci_softc * const sc,
1885: const struct xhci_trb * const trb)
1886: {
1887: uint64_t trb_0;
1888: uint32_t trb_2, trb_3;
1889: uint8_t trbcode;
1890: u_int slot, dci;
1891: struct xhci_slot *xs;
1892: struct xhci_ring *xr;
1893: struct xhci_xfer *xx;
1894: struct usbd_xfer *xfer;
1895: usbd_status err;
1896:
1897: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1898:
1899: trb_0 = le64toh(trb->trb_0);
1900: trb_2 = le32toh(trb->trb_2);
1901: trb_3 = le32toh(trb->trb_3);
1902: trbcode = XHCI_TRB_2_ERROR_GET(trb_2);
1903: slot = XHCI_TRB_3_SLOT_GET(trb_3);
1904: dci = XHCI_TRB_3_EP_GET(trb_3);
1905: xs = &sc->sc_slots[slot];
1906: xr = &xs->xs_ep[dci].xe_tr;
1907:
1908: /* sanity check */
1909: KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots,
1910: "invalid xs_idx %u slot %u", xs->xs_idx, slot);
1911:
1.40 skrll 1912: int idx = 0;
1.34 skrll 1913: if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) {
1.40 skrll 1914: if (xhci_trb_get_idx(xr, trb_0, &idx)) {
1.75 pgoyette 1915: DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0);
1.34 skrll 1916: return;
1917: }
1918: xx = xr->xr_cookies[idx];
1919:
1.63 skrll 1920: /* clear cookie of consumed TRB */
1921: xr->xr_cookies[idx] = NULL;
1922:
1.34 skrll 1923: /*
1.63 skrll 1924: * xx is NULL if pipe is opened but xfer is not started.
1925: * It happens when stopping idle pipe.
1.34 skrll 1926: */
1927: if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) {
1.75 pgoyette 1928: DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju",
1929: idx, (uintptr_t)xx, trbcode, dci);
1930: DPRINTFN(1, " orig TRB %jx type %ju", trb_0,
1.53 skrll 1931: XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)),
1932: 0, 0);
1.63 skrll 1933: return;
1.34 skrll 1934: }
1935: } else {
1.54 skrll 1936: /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */
1.34 skrll 1937: xx = (void *)(uintptr_t)(trb_0 & ~0x3);
1938: }
1939: /* XXX this may not happen */
1940: if (xx == NULL) {
1941: DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0);
1942: return;
1943: }
1944: xfer = &xx->xx_xfer;
1945: /* XXX this may happen when detaching */
1946: if (xfer == NULL) {
1.75 pgoyette 1947: DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx",
1948: (uintptr_t)xx, trb_0, 0, 0);
1.34 skrll 1949: return;
1950: }
1.75 pgoyette 1951: DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
1.34 skrll 1952: /* XXX I dunno why this happens */
1953: KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer);
1954:
1955: if (!xfer->ux_pipe->up_repeat &&
1956: SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) {
1.75 pgoyette 1957: DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer,
1958: 0, 0, 0);
1.34 skrll 1959: return;
1960: }
1961:
1962: /* 4.11.5.2 Event Data TRB */
1963: if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) {
1.75 pgoyette 1964: DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx"
1965: " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0);
1.34 skrll 1966: if ((trb_0 & 0x3) == 0x3) {
1967: xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2);
1968: }
1969: }
1970:
1971: switch (trbcode) {
1972: case XHCI_TRB_ERROR_SHORT_PKT:
1973: case XHCI_TRB_ERROR_SUCCESS:
1.54 skrll 1974: /*
1.63 skrll 1975: * A ctrl transfer can generate two events if it has a Data
1976: * stage. A short data stage can be OK and should not
1977: * complete the transfer as the status stage needs to be
1978: * performed.
1.54 skrll 1979: *
1980: * Note: Data and Status stage events point at same xfer.
1981: * ux_actlen and ux_dmabuf will be passed to
1982: * usb_transfer_complete after the Status stage event.
1983: *
1984: * It can be distingished which stage generates the event:
1985: * + by checking least 3 bits of trb_0 if ED==1.
1986: * (see xhci_device_ctrl_start).
1987: * + by checking the type of original TRB if ED==0.
1988: *
1989: * In addition, intr, bulk, and isoc transfer currently
1990: * consists of single TD, so the "skip" is not needed.
1991: * ctrl xfer uses EVENT_DATA, and others do not.
1992: * Thus driver can switch the flow by checking ED bit.
1993: */
1.63 skrll 1994: if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) {
1995: if (xfer->ux_actlen == 0)
1996: xfer->ux_actlen = xfer->ux_length -
1997: XHCI_TRB_2_REM_GET(trb_2);
1998: if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3))
1999: == XHCI_TRB_TYPE_DATA_STAGE) {
2000: return;
2001: }
2002: } else if ((trb_0 & 0x3) == 0x3) {
2003: return;
2004: }
1.34 skrll 2005: err = USBD_NORMAL_COMPLETION;
2006: break;
1.63 skrll 2007: case XHCI_TRB_ERROR_STOPPED:
2008: case XHCI_TRB_ERROR_LENGTH:
2009: case XHCI_TRB_ERROR_STOPPED_SHORT:
2010: /*
2011: * don't complete the transfer being aborted
2012: * as abort_xfer does instead.
2013: */
1.86.2.6 pgoyette 2014: if (xfer->ux_status == USBD_CANCELLED ||
2015: xfer->ux_status == USBD_TIMEOUT) {
1.75 pgoyette 2016: DPRINTFN(14, "ignore aborting xfer %#jx",
2017: (uintptr_t)xfer, 0, 0, 0);
1.63 skrll 2018: return;
2019: }
2020: err = USBD_CANCELLED;
2021: break;
1.34 skrll 2022: case XHCI_TRB_ERROR_STALL:
2023: case XHCI_TRB_ERROR_BABBLE:
1.75 pgoyette 2024: DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
1.34 skrll 2025: xr->is_halted = true;
2026: /*
2027: * Stalled endpoints can be recoverd by issuing
2028: * command TRB TYPE_RESET_EP on xHCI instead of
2029: * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT
2030: * on the endpoint. However, this function may be
2031: * called from softint context (e.g. from umass),
2032: * in that case driver gets KASSERT in cv_timedwait
2033: * in xhci_do_command.
2034: * To avoid this, this runs reset_endpoint and
2035: * usb_transfer_complete in usb task thread
2036: * asynchronously (and then umass issues clear
2037: * UF_ENDPOINT_HALT).
2038: */
1.86.2.6 pgoyette 2039:
2040: /* Override the status. */
2041: xfer->ux_status = USBD_STALLED;
2042:
2043: /*
2044: * Cancel the timeout and the task, which have not yet
2045: * run. If they have already fired, at worst they are
2046: * waiting for the lock. They will see that the xfer
2047: * is no longer in progress and give up.
2048: */
1.57 skrll 2049: callout_stop(&xfer->ux_callout);
1.86.2.6 pgoyette 2050: usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask);
2051:
1.34 skrll 2052: xhci_clear_endpoint_stall_async(xfer);
2053: return;
2054: default:
1.75 pgoyette 2055: DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
1.34 skrll 2056: err = USBD_IOERROR;
2057: break;
2058: }
1.86.2.6 pgoyette 2059:
2060: /*
2061: * If software has completed it, either by cancellation
2062: * or timeout, drop it on the floor.
2063: */
2064: if (xfer->ux_status != USBD_IN_PROGRESS) {
2065: KASSERTMSG((xfer->ux_status == USBD_CANCELLED ||
2066: xfer->ux_status == USBD_TIMEOUT),
2067: "xfer %p status %x", xfer, xfer->ux_status);
2068: return;;
2069: }
2070:
2071: /* Otherwise, set the status. */
1.34 skrll 2072: xfer->ux_status = err;
2073:
1.86.2.6 pgoyette 2074: /*
2075: * Cancel the timeout and the task, which have not yet
2076: * run. If they have already fired, at worst they are
2077: * waiting for the lock. They will see that the xfer
2078: * is no longer in progress and give up.
2079: */
2080: callout_stop(&xfer->ux_callout);
2081: usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask);
2082:
2083: if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 ||
2084: (trb_0 & 0x3) == 0x0) {
1.34 skrll 2085: usb_transfer_complete(xfer);
2086: }
2087: }
2088:
2089: /* Process Command complete events */
2090: static void
1.50 skrll 2091: xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb)
1.34 skrll 2092: {
2093: uint64_t trb_0;
2094: uint32_t trb_2, trb_3;
2095:
2096: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2097:
1.68 skrll 2098: KASSERT(mutex_owned(&sc->sc_lock));
2099:
1.34 skrll 2100: trb_0 = le64toh(trb->trb_0);
2101: trb_2 = le32toh(trb->trb_2);
2102: trb_3 = le32toh(trb->trb_3);
2103:
2104: if (trb_0 == sc->sc_command_addr) {
1.68 skrll 2105: sc->sc_resultpending = false;
2106:
1.34 skrll 2107: sc->sc_result_trb.trb_0 = trb_0;
2108: sc->sc_result_trb.trb_2 = trb_2;
2109: sc->sc_result_trb.trb_3 = trb_3;
2110: if (XHCI_TRB_2_ERROR_GET(trb_2) !=
2111: XHCI_TRB_ERROR_SUCCESS) {
2112: DPRINTFN(1, "command completion "
1.75 pgoyette 2113: "failure: 0x%016jx 0x%08jx 0x%08jx",
2114: trb_0, trb_2, trb_3, 0);
1.34 skrll 2115: }
2116: cv_signal(&sc->sc_command_cv);
2117: } else {
1.75 pgoyette 2118: DPRINTFN(1, "spurious event: %#jx 0x%016jx "
2119: "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3);
1.34 skrll 2120: }
2121: }
2122:
2123: /*
2124: * Process events.
2125: * called from xhci_softintr
2126: */
2127: static void
2128: xhci_handle_event(struct xhci_softc * const sc,
2129: const struct xhci_trb * const trb)
2130: {
2131: uint64_t trb_0;
2132: uint32_t trb_2, trb_3;
2133:
2134: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2135:
2136: trb_0 = le64toh(trb->trb_0);
2137: trb_2 = le32toh(trb->trb_2);
2138: trb_3 = le32toh(trb->trb_3);
2139:
1.75 pgoyette 2140: DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx",
2141: (uintptr_t)trb, trb_0, trb_2, trb_3);
1.34 skrll 2142:
2143: /*
2144: * 4.11.3.1, 6.4.2.1
2145: * TRB Pointer is invalid for these completion codes.
2146: */
2147: switch (XHCI_TRB_2_ERROR_GET(trb_2)) {
2148: case XHCI_TRB_ERROR_RING_UNDERRUN:
2149: case XHCI_TRB_ERROR_RING_OVERRUN:
2150: case XHCI_TRB_ERROR_VF_RING_FULL:
2151: return;
2152: default:
2153: if (trb_0 == 0) {
2154: return;
2155: }
2156: break;
2157: }
2158:
2159: switch (XHCI_TRB_3_TYPE_GET(trb_3)) {
2160: case XHCI_TRB_EVENT_TRANSFER:
2161: xhci_event_transfer(sc, trb);
2162: break;
2163: case XHCI_TRB_EVENT_CMD_COMPLETE:
2164: xhci_event_cmd(sc, trb);
2165: break;
2166: case XHCI_TRB_EVENT_PORT_STS_CHANGE:
2167: xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff));
2168: break;
2169: default:
2170: break;
2171: }
2172: }
2173:
2174: static void
2175: xhci_softintr(void *v)
2176: {
2177: struct usbd_bus * const bus = v;
2178: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
2179: struct xhci_ring * const er = &sc->sc_er;
2180: struct xhci_trb *trb;
2181: int i, j, k;
2182:
2183: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2184:
1.73 skrll 2185: KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock));
1.34 skrll 2186:
2187: i = er->xr_ep;
2188: j = er->xr_cs;
1.1 jakllsch 2189:
1.75 pgoyette 2190: DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0);
1.27 skrll 2191:
1.1 jakllsch 2192: while (1) {
2193: usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE,
2194: BUS_DMASYNC_POSTREAD);
2195: trb = &er->xr_trb[i];
2196: k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
2197:
2198: if (j != k)
2199: break;
2200:
2201: xhci_handle_event(sc, trb);
2202:
2203: i++;
1.52 skrll 2204: if (i == er->xr_ntrb) {
1.1 jakllsch 2205: i = 0;
2206: j ^= 1;
2207: }
2208: }
2209:
2210: er->xr_ep = i;
2211: er->xr_cs = j;
2212:
2213: xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) |
2214: XHCI_ERDP_LO_BUSY);
2215:
1.27 skrll 2216: DPRINTFN(16, "ends", 0, 0, 0, 0);
1.1 jakllsch 2217:
2218: return;
2219: }
2220:
2221: static void
2222: xhci_poll(struct usbd_bus *bus)
2223: {
1.34 skrll 2224: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2225:
1.27 skrll 2226: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2227:
1.86.2.5 pgoyette 2228: mutex_enter(&sc->sc_intr_lock);
1.73 skrll 2229: int ret = xhci_intr1(sc);
2230: if (ret) {
2231: xhci_softintr(bus);
2232: }
1.86.2.5 pgoyette 2233: mutex_exit(&sc->sc_intr_lock);
1.1 jakllsch 2234:
2235: return;
2236: }
2237:
1.34 skrll 2238: static struct usbd_xfer *
2239: xhci_allocx(struct usbd_bus *bus, unsigned int nframes)
1.1 jakllsch 2240: {
1.34 skrll 2241: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
2242: struct usbd_xfer *xfer;
1.1 jakllsch 2243:
1.27 skrll 2244: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2245:
1.77 skrll 2246: xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
1.1 jakllsch 2247: if (xfer != NULL) {
1.6 skrll 2248: memset(xfer, 0, sizeof(struct xhci_xfer));
1.86.2.6 pgoyette 2249: usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, xfer,
2250: USB_TASKQ_MPSAFE);
1.1 jakllsch 2251: #ifdef DIAGNOSTIC
1.34 skrll 2252: xfer->ux_state = XFER_BUSY;
1.1 jakllsch 2253: #endif
2254: }
2255:
2256: return xfer;
2257: }
2258:
2259: static void
1.34 skrll 2260: xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1.1 jakllsch 2261: {
1.34 skrll 2262: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2263:
1.27 skrll 2264: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2265:
2266: #ifdef DIAGNOSTIC
1.34 skrll 2267: if (xfer->ux_state != XFER_BUSY) {
1.75 pgoyette 2268: DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx",
2269: (uintptr_t)xfer, xfer->ux_state, 0, 0);
1.1 jakllsch 2270: }
1.34 skrll 2271: xfer->ux_state = XFER_FREE;
1.1 jakllsch 2272: #endif
2273: pool_cache_put(sc->sc_xferpool, xfer);
2274: }
2275:
2276: static void
2277: xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
2278: {
1.34 skrll 2279: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2280:
2281: *lock = &sc->sc_lock;
2282: }
2283:
1.34 skrll 2284: extern uint32_t usb_cookie_no;
1.1 jakllsch 2285:
1.34 skrll 2286: /*
1.41 skrll 2287: * xHCI 4.3
2288: * Called when uhub_explore finds a new device (via usbd_new_device).
2289: * Port initialization and speed detection (4.3.1) are already done in uhub.c.
2290: * This function does:
2291: * Allocate and construct dev structure of default endpoint (ep0).
2292: * Allocate and open pipe of ep0.
2293: * Enable slot and initialize slot context.
2294: * Set Address.
2295: * Read initial device descriptor.
1.34 skrll 2296: * Determine initial MaxPacketSize (mps) by speed.
1.41 skrll 2297: * Read full device descriptor.
2298: * Register this device.
1.54 skrll 2299: * Finally state of device transitions ADDRESSED.
1.34 skrll 2300: */
1.1 jakllsch 2301: static usbd_status
1.34 skrll 2302: xhci_new_device(device_t parent, struct usbd_bus *bus, int depth,
1.1 jakllsch 2303: int speed, int port, struct usbd_port *up)
2304: {
1.34 skrll 2305: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
2306: struct usbd_device *dev;
1.1 jakllsch 2307: usbd_status err;
2308: usb_device_descriptor_t *dd;
2309: struct xhci_slot *xs;
2310: uint32_t *cp;
2311:
1.27 skrll 2312: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2313: DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx",
2314: port, depth, speed, (uintptr_t)up);
1.27 skrll 2315:
1.34 skrll 2316: dev = kmem_zalloc(sizeof(*dev), KM_SLEEP);
2317: dev->ud_bus = bus;
1.51 skrll 2318: dev->ud_quirks = &usbd_no_quirk;
2319: dev->ud_addr = 0;
2320: dev->ud_ddesc.bMaxPacketSize = 0;
2321: dev->ud_depth = depth;
2322: dev->ud_powersrc = up;
2323: dev->ud_myhub = up->up_parent;
2324: dev->ud_speed = speed;
2325: dev->ud_langid = USBD_NOLANG;
2326: dev->ud_cookie.cookie = ++usb_cookie_no;
1.1 jakllsch 2327:
2328: /* Set up default endpoint handle. */
1.34 skrll 2329: dev->ud_ep0.ue_edesc = &dev->ud_ep0desc;
1.51 skrll 2330: /* doesn't matter, just don't let it uninitialized */
2331: dev->ud_ep0.ue_toggle = 0;
1.1 jakllsch 2332:
2333: /* Set up default endpoint descriptor. */
1.34 skrll 2334: dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE;
2335: dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT;
2336: dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT;
2337: dev->ud_ep0desc.bmAttributes = UE_CONTROL;
1.51 skrll 2338: dev->ud_ep0desc.bInterval = 0;
1.50 skrll 2339:
1.34 skrll 2340: /* 4.3, 4.8.2.1 */
2341: switch (speed) {
2342: case USB_SPEED_SUPER:
2343: case USB_SPEED_SUPER_PLUS:
2344: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET);
2345: break;
2346: case USB_SPEED_FULL:
2347: /* XXX using 64 as initial mps of ep0 in FS */
2348: case USB_SPEED_HIGH:
2349: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET);
2350: break;
2351: case USB_SPEED_LOW:
2352: default:
2353: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET);
2354: break;
2355: }
1.1 jakllsch 2356:
1.51 skrll 2357: up->up_dev = dev;
2358:
2359: /* Establish the default pipe. */
2360: err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL,
2361: &dev->ud_pipe0);
2362: if (err) {
2363: goto bad;
2364: }
1.1 jakllsch 2365:
1.51 skrll 2366: dd = &dev->ud_ddesc;
1.1 jakllsch 2367:
1.68 skrll 2368: if (depth == 0 && port == 0) {
2369: KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL);
2370: bus->ub_devices[USB_ROOTHUB_INDEX] = dev;
1.51 skrll 2371: err = usbd_get_initial_ddesc(dev, dd);
1.61 skrll 2372: if (err) {
1.75 pgoyette 2373: DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0);
1.34 skrll 2374: goto bad;
1.61 skrll 2375: }
2376:
1.1 jakllsch 2377: err = usbd_reload_device_desc(dev);
1.61 skrll 2378: if (err) {
1.75 pgoyette 2379: DPRINTFN(1, "reload desc %ju", err, 0, 0, 0);
1.34 skrll 2380: goto bad;
1.61 skrll 2381: }
1.1 jakllsch 2382: } else {
1.49 skrll 2383: uint8_t slot = 0;
2384:
1.48 skrll 2385: /* 4.3.2 */
1.1 jakllsch 2386: err = xhci_enable_slot(sc, &slot);
1.63 skrll 2387: if (err) {
1.75 pgoyette 2388: DPRINTFN(1, "enable slot %ju", err, 0, 0, 0);
1.34 skrll 2389: goto bad;
1.63 skrll 2390: }
1.50 skrll 2391:
1.1 jakllsch 2392: xs = &sc->sc_slots[slot];
1.34 skrll 2393: dev->ud_hcpriv = xs;
1.50 skrll 2394:
1.48 skrll 2395: /* 4.3.3 initialize slot structure */
2396: err = xhci_init_slot(dev, slot);
1.34 skrll 2397: if (err) {
1.75 pgoyette 2398: DPRINTFN(1, "init slot %ju", err, 0, 0, 0);
1.34 skrll 2399: dev->ud_hcpriv = NULL;
2400: /*
2401: * We have to disable_slot here because
2402: * xs->xs_idx == 0 when xhci_init_slot fails,
2403: * in that case usbd_remove_dev won't work.
2404: */
2405: mutex_enter(&sc->sc_lock);
2406: xhci_disable_slot(sc, slot);
2407: mutex_exit(&sc->sc_lock);
2408: goto bad;
2409: }
2410:
1.48 skrll 2411: /* 4.3.4 Address Assignment */
1.51 skrll 2412: err = xhci_set_address(dev, slot, false);
1.61 skrll 2413: if (err) {
1.75 pgoyette 2414: DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0);
1.48 skrll 2415: goto bad;
1.61 skrll 2416: }
1.48 skrll 2417:
1.34 skrll 2418: /* Allow device time to set new address */
2419: usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE);
1.50 skrll 2420:
1.86.2.4 pgoyette 2421: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1.1 jakllsch 2422: cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT);
1.79 christos 2423: HEXDUMP("slot context", cp, sc->sc_ctxsz);
1.64 skrll 2424: uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3]));
1.75 pgoyette 2425: DPRINTFN(4, "device address %ju", addr, 0, 0, 0);
1.68 skrll 2426: /*
2427: * XXX ensure we know when the hardware does something
2428: * we can't yet cope with
2429: */
1.59 maya 2430: KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr);
1.34 skrll 2431: dev->ud_addr = addr;
1.68 skrll 2432:
2433: KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL,
2434: "addr %d already allocated", dev->ud_addr);
2435: /*
2436: * The root hub is given its own slot
2437: */
2438: bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev;
1.1 jakllsch 2439:
2440: err = usbd_get_initial_ddesc(dev, dd);
1.61 skrll 2441: if (err) {
1.75 pgoyette 2442: DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0);
1.34 skrll 2443: goto bad;
1.61 skrll 2444: }
1.50 skrll 2445:
1.24 skrll 2446: /* 4.8.2.1 */
1.34 skrll 2447: if (USB_IS_SS(speed)) {
2448: if (dd->bMaxPacketSize != 9) {
2449: printf("%s: invalid mps 2^%u for SS ep0,"
2450: " using 512\n",
2451: device_xname(sc->sc_dev),
2452: dd->bMaxPacketSize);
2453: dd->bMaxPacketSize = 9;
2454: }
2455: USETW(dev->ud_ep0desc.wMaxPacketSize,
1.24 skrll 2456: (1 << dd->bMaxPacketSize));
1.34 skrll 2457: } else
2458: USETW(dev->ud_ep0desc.wMaxPacketSize,
1.24 skrll 2459: dd->bMaxPacketSize);
1.75 pgoyette 2460: DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0);
1.62 skrll 2461: err = xhci_update_ep0_mps(sc, xs,
1.34 skrll 2462: UGETW(dev->ud_ep0desc.wMaxPacketSize));
1.62 skrll 2463: if (err) {
1.75 pgoyette 2464: DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0);
1.62 skrll 2465: goto bad;
2466: }
1.50 skrll 2467:
1.1 jakllsch 2468: err = usbd_reload_device_desc(dev);
1.61 skrll 2469: if (err) {
1.75 pgoyette 2470: DPRINTFN(1, "reload desc %ju", err, 0, 0, 0);
1.34 skrll 2471: goto bad;
1.61 skrll 2472: }
1.1 jakllsch 2473: }
2474:
1.75 pgoyette 2475: DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,",
1.34 skrll 2476: dev->ud_addr, UGETW(dd->bcdUSB), 0, 0);
1.75 pgoyette 2477: DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,",
1.27 skrll 2478: dd->bDeviceClass, dd->bDeviceSubClass,
2479: dd->bDeviceProtocol, 0);
1.75 pgoyette 2480: DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd",
1.27 skrll 2481: dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations,
1.34 skrll 2482: dev->ud_speed);
1.1 jakllsch 2483:
1.33 skrll 2484: usbd_get_device_strings(dev);
2485:
1.1 jakllsch 2486: usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev);
2487:
1.68 skrll 2488: if (depth == 0 && port == 0) {
1.1 jakllsch 2489: usbd_attach_roothub(parent, dev);
1.75 pgoyette 2490: DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0);
1.1 jakllsch 2491: return USBD_NORMAL_COMPLETION;
2492: }
2493:
1.34 skrll 2494: err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr);
2495: bad:
2496: if (err != USBD_NORMAL_COMPLETION) {
1.1 jakllsch 2497: usbd_remove_device(dev, up);
2498: }
2499:
1.34 skrll 2500: return err;
1.1 jakllsch 2501: }
2502:
2503: static usbd_status
2504: xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr,
2505: size_t ntrb, size_t align)
2506: {
2507: usbd_status err;
2508: size_t size = ntrb * XHCI_TRB_SIZE;
2509:
1.27 skrll 2510: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2511:
1.1 jakllsch 2512: err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma);
2513: if (err)
2514: return err;
2515: mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
2516: xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP);
2517: xr->xr_trb = xhci_ring_trbv(xr, 0);
2518: xr->xr_ntrb = ntrb;
2519: xr->is_halted = false;
1.55 skrll 2520: xhci_host_dequeue(xr);
1.1 jakllsch 2521:
2522: return USBD_NORMAL_COMPLETION;
2523: }
2524:
2525: static void
2526: xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr)
2527: {
2528: usb_freemem(&sc->sc_bus, &xr->xr_dma);
2529: mutex_destroy(&xr->xr_lock);
2530: kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb);
2531: }
2532:
2533: static void
2534: xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr,
2535: void *cookie, struct xhci_trb * const trbs, size_t ntrbs)
2536: {
2537: size_t i;
2538: u_int ri;
2539: u_int cs;
2540: uint64_t parameter;
2541: uint32_t status;
2542: uint32_t control;
2543:
1.27 skrll 2544: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2545:
1.59 maya 2546: KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs);
1.1 jakllsch 2547: for (i = 0; i < ntrbs; i++) {
1.75 pgoyette 2548: DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr,
2549: (uintptr_t)trbs, i, 0);
2550: DPRINTFN(12, " %016jx %08jx %08jx",
1.27 skrll 2551: trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0);
1.59 maya 2552: KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) !=
1.63 skrll 2553: XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3);
1.1 jakllsch 2554: }
2555:
1.75 pgoyette 2556: DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep,
2557: xr->xr_cs, 0);
1.1 jakllsch 2558:
2559: ri = xr->xr_ep;
2560: cs = xr->xr_cs;
2561:
1.11 dsl 2562: /*
2563: * Although the xhci hardware can do scatter/gather dma from
2564: * arbitrary sized buffers, there is a non-obvious restriction
2565: * that a LINK trb is only allowed at the end of a burst of
2566: * transfers - which might be 16kB.
2567: * Arbitrary aligned LINK trb definitely fail on Ivy bridge.
2568: * The simple solution is not to allow a LINK trb in the middle
2569: * of anything - as here.
1.13 dsl 2570: * XXX: (dsl) There are xhci controllers out there (eg some made by
2571: * ASMedia) that seem to lock up if they process a LINK trb but
2572: * cannot process the linked-to trb yet.
2573: * The code should write the 'cycle' bit on the link trb AFTER
2574: * adding the other trb.
1.11 dsl 2575: */
1.65 skrll 2576: u_int firstep = xr->xr_ep;
2577: u_int firstcs = xr->xr_cs;
1.1 jakllsch 2578:
1.65 skrll 2579: for (i = 0; i < ntrbs; ) {
2580: u_int oldri = ri;
2581: u_int oldcs = cs;
2582:
2583: if (ri >= (xr->xr_ntrb - 1)) {
2584: /* Put Link TD at the end of ring */
2585: parameter = xhci_ring_trbp(xr, 0);
2586: status = 0;
2587: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
2588: XHCI_TRB_3_TC_BIT;
2589: xr->xr_cookies[ri] = NULL;
2590: xr->xr_ep = 0;
2591: xr->xr_cs ^= 1;
2592: ri = xr->xr_ep;
2593: cs = xr->xr_cs;
1.1 jakllsch 2594: } else {
1.65 skrll 2595: parameter = trbs[i].trb_0;
2596: status = trbs[i].trb_2;
2597: control = trbs[i].trb_3;
2598:
2599: xr->xr_cookies[ri] = cookie;
2600: ri++;
2601: i++;
1.1 jakllsch 2602: }
1.65 skrll 2603: /*
2604: * If this is a first TRB, mark it invalid to prevent
2605: * xHC from running it immediately.
2606: */
2607: if (oldri == firstep) {
2608: if (oldcs) {
2609: control &= ~XHCI_TRB_3_CYCLE_BIT;
2610: } else {
2611: control |= XHCI_TRB_3_CYCLE_BIT;
2612: }
2613: } else {
2614: if (oldcs) {
2615: control |= XHCI_TRB_3_CYCLE_BIT;
2616: } else {
2617: control &= ~XHCI_TRB_3_CYCLE_BIT;
2618: }
2619: }
2620: xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control);
2621: usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri,
2622: XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 2623: }
2624:
1.65 skrll 2625: /* Now invert cycle bit of first TRB */
2626: if (firstcs) {
2627: xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
1.34 skrll 2628: } else {
1.65 skrll 2629: xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1.34 skrll 2630: }
1.65 skrll 2631: usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep,
2632: XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 2633:
2634: xr->xr_ep = ri;
2635: xr->xr_cs = cs;
2636:
1.75 pgoyette 2637: DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep,
2638: xr->xr_cs, 0);
1.1 jakllsch 2639: }
2640:
1.34 skrll 2641: /*
1.39 skrll 2642: * Stop execution commands, purge all commands on command ring, and
1.54 skrll 2643: * rewind dequeue pointer.
1.39 skrll 2644: */
2645: static void
2646: xhci_abort_command(struct xhci_softc *sc)
2647: {
2648: struct xhci_ring * const cr = &sc->sc_cr;
2649: uint64_t crcr;
2650: int i;
2651:
2652: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2653: DPRINTFN(14, "command %#jx timeout, aborting",
1.39 skrll 2654: sc->sc_command_addr, 0, 0, 0);
2655:
2656: mutex_enter(&cr->xr_lock);
2657:
2658: /* 4.6.1.2 Aborting a Command */
2659: crcr = xhci_op_read_8(sc, XHCI_CRCR);
2660: xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA);
2661:
2662: for (i = 0; i < 500; i++) {
2663: crcr = xhci_op_read_8(sc, XHCI_CRCR);
2664: if ((crcr & XHCI_CRCR_LO_CRR) == 0)
2665: break;
2666: usb_delay_ms(&sc->sc_bus, 1);
2667: }
2668: if ((crcr & XHCI_CRCR_LO_CRR) != 0) {
2669: DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0);
2670: /* reset HC here? */
2671: }
2672:
2673: /* reset command ring dequeue pointer */
2674: cr->xr_ep = 0;
2675: cr->xr_cs = 1;
2676: xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs);
2677:
2678: mutex_exit(&cr->xr_lock);
2679: }
2680:
2681: /*
1.34 skrll 2682: * Put a command on command ring, ring bell, set timer, and cv_timedwait.
1.54 skrll 2683: * Command completion is notified by cv_signal from xhci_event_cmd()
2684: * (called from xhci_softint), or timed-out.
2685: * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(),
2686: * then do_command examines it.
1.34 skrll 2687: */
1.1 jakllsch 2688: static usbd_status
1.50 skrll 2689: xhci_do_command_locked(struct xhci_softc * const sc,
2690: struct xhci_trb * const trb, int timeout)
1.1 jakllsch 2691: {
2692: struct xhci_ring * const cr = &sc->sc_cr;
2693: usbd_status err;
2694:
1.27 skrll 2695: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2696: DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx",
1.27 skrll 2697: trb->trb_0, trb->trb_2, trb->trb_3, 0);
1.1 jakllsch 2698:
1.34 skrll 2699: KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx");
2700: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 2701:
1.68 skrll 2702: while (sc->sc_command_addr != 0)
2703: cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock);
2704:
1.67 skrll 2705: /*
2706: * If enqueue pointer points at last of ring, it's Link TRB,
2707: * command TRB will be stored in 0th TRB.
2708: */
2709: if (cr->xr_ep == cr->xr_ntrb - 1)
2710: sc->sc_command_addr = xhci_ring_trbp(cr, 0);
2711: else
2712: sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep);
1.1 jakllsch 2713:
1.68 skrll 2714: sc->sc_resultpending = true;
2715:
1.1 jakllsch 2716: mutex_enter(&cr->xr_lock);
2717: xhci_ring_put(sc, cr, NULL, trb, 1);
2718: mutex_exit(&cr->xr_lock);
2719:
2720: xhci_db_write_4(sc, XHCI_DOORBELL(0), 0);
2721:
1.68 skrll 2722: while (sc->sc_resultpending) {
2723: if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock,
2724: MAX(1, mstohz(timeout))) == EWOULDBLOCK) {
2725: xhci_abort_command(sc);
2726: err = USBD_TIMEOUT;
2727: goto timedout;
2728: }
1.1 jakllsch 2729: }
2730:
2731: trb->trb_0 = sc->sc_result_trb.trb_0;
2732: trb->trb_2 = sc->sc_result_trb.trb_2;
2733: trb->trb_3 = sc->sc_result_trb.trb_3;
2734:
1.75 pgoyette 2735: DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx",
1.27 skrll 2736: trb->trb_0, trb->trb_2, trb->trb_3, 0);
1.1 jakllsch 2737:
2738: switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) {
2739: case XHCI_TRB_ERROR_SUCCESS:
2740: err = USBD_NORMAL_COMPLETION;
2741: break;
2742: default:
2743: case 192 ... 223:
2744: err = USBD_IOERROR;
2745: break;
2746: case 224 ... 255:
2747: err = USBD_NORMAL_COMPLETION;
2748: break;
2749: }
2750:
2751: timedout:
1.68 skrll 2752: sc->sc_resultpending = false;
1.1 jakllsch 2753: sc->sc_command_addr = 0;
1.68 skrll 2754: cv_broadcast(&sc->sc_cmdbusy_cv);
2755:
1.34 skrll 2756: return err;
2757: }
2758:
2759: static usbd_status
2760: xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb,
2761: int timeout)
2762: {
2763:
2764: mutex_enter(&sc->sc_lock);
1.38 skrll 2765: usbd_status ret = xhci_do_command_locked(sc, trb, timeout);
1.1 jakllsch 2766: mutex_exit(&sc->sc_lock);
1.34 skrll 2767:
2768: return ret;
1.1 jakllsch 2769: }
2770:
2771: static usbd_status
2772: xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp)
2773: {
2774: struct xhci_trb trb;
2775: usbd_status err;
2776:
1.27 skrll 2777: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2778:
1.1 jakllsch 2779: trb.trb_0 = 0;
2780: trb.trb_2 = 0;
2781: trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT);
2782:
2783: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
2784: if (err != USBD_NORMAL_COMPLETION) {
2785: return err;
2786: }
2787:
2788: *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3);
2789:
2790: return err;
2791: }
2792:
1.34 skrll 2793: /*
1.41 skrll 2794: * xHCI 4.6.4
2795: * Deallocate ring and device/input context DMA buffers, and disable_slot.
2796: * All endpoints in the slot should be stopped.
1.34 skrll 2797: * Should be called with sc_lock held.
2798: */
2799: static usbd_status
2800: xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot)
2801: {
2802: struct xhci_trb trb;
2803: struct xhci_slot *xs;
2804: usbd_status err;
2805:
2806: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2807:
2808: if (sc->sc_dying)
2809: return USBD_IOERROR;
2810:
2811: trb.trb_0 = 0;
2812: trb.trb_2 = 0;
2813: trb.trb_3 = htole32(
2814: XHCI_TRB_3_SLOT_SET(slot) |
2815: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT));
2816:
2817: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
2818:
2819: if (!err) {
2820: xs = &sc->sc_slots[slot];
2821: if (xs->xs_idx != 0) {
1.48 skrll 2822: xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32);
1.34 skrll 2823: xhci_set_dcba(sc, 0, slot);
2824: memset(xs, 0, sizeof(*xs));
2825: }
2826: }
2827:
2828: return err;
2829: }
2830:
2831: /*
1.41 skrll 2832: * Set address of device and transition slot state from ENABLED to ADDRESSED
2833: * if Block Setaddress Request (BSR) is false.
2834: * If BSR==true, transition slot state from ENABLED to DEFAULT.
1.34 skrll 2835: * see xHCI 1.1 4.5.3, 3.3.4
1.41 skrll 2836: * Should be called without sc_lock held.
1.34 skrll 2837: */
1.1 jakllsch 2838: static usbd_status
2839: xhci_address_device(struct xhci_softc * const sc,
2840: uint64_t icp, uint8_t slot_id, bool bsr)
2841: {
2842: struct xhci_trb trb;
2843: usbd_status err;
2844:
1.27 skrll 2845: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2846:
1.1 jakllsch 2847: trb.trb_0 = icp;
2848: trb.trb_2 = 0;
2849: trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) |
2850: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
2851: (bsr ? XHCI_TRB_3_BSR_BIT : 0);
2852:
2853: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.34 skrll 2854:
2855: if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS)
2856: err = USBD_NO_ADDR;
2857:
1.1 jakllsch 2858: return err;
2859: }
2860:
2861: static usbd_status
2862: xhci_update_ep0_mps(struct xhci_softc * const sc,
2863: struct xhci_slot * const xs, u_int mps)
2864: {
2865: struct xhci_trb trb;
2866: usbd_status err;
2867: uint32_t * cp;
2868:
1.27 skrll 2869: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2870: DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0);
1.1 jakllsch 2871:
2872: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
2873: cp[0] = htole32(0);
2874: cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL));
2875:
2876: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL));
2877: cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps));
2878:
2879: /* sync input contexts before they are read from memory */
2880: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1.79 christos 2881: HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0),
1.1 jakllsch 2882: sc->sc_ctxsz * 4);
2883:
2884: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
2885: trb.trb_2 = 0;
2886: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
2887: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX);
2888:
2889: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
2890: return err;
2891: }
2892:
2893: static void
2894: xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si)
2895: {
2896: uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0);
2897:
1.27 skrll 2898: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2899: DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd",
2900: (uintptr_t)&dcbaa[si], dcba, si, 0);
1.1 jakllsch 2901:
1.5 matt 2902: dcbaa[si] = htole64(dcba);
1.1 jakllsch 2903: usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t),
2904: BUS_DMASYNC_PREWRITE);
2905: }
2906:
1.34 skrll 2907: /*
1.48 skrll 2908: * Allocate device and input context DMA buffer, and
2909: * TRB DMA buffer for each endpoint.
1.34 skrll 2910: */
1.1 jakllsch 2911: static usbd_status
1.48 skrll 2912: xhci_init_slot(struct usbd_device *dev, uint32_t slot)
1.1 jakllsch 2913: {
1.34 skrll 2914: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
1.1 jakllsch 2915: struct xhci_slot *xs;
2916: usbd_status err;
2917: u_int dci;
2918:
1.27 skrll 2919: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2920: DPRINTFN(4, "slot %ju", slot, 0, 0, 0);
1.1 jakllsch 2921:
2922: xs = &sc->sc_slots[slot];
2923:
2924: /* allocate contexts */
2925: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz,
2926: &xs->xs_dc_dma);
2927: if (err)
2928: return err;
2929: memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz);
2930:
2931: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz,
2932: &xs->xs_ic_dma);
2933: if (err)
1.34 skrll 2934: goto bad1;
1.1 jakllsch 2935: memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz);
2936:
2937: for (dci = 0; dci < 32; dci++) {
2938: //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint));
2939: memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci]));
2940: if (dci == XHCI_DCI_SLOT)
2941: continue;
2942: err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr,
2943: XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN);
2944: if (err) {
1.27 skrll 2945: DPRINTFN(0, "ring init failure", 0, 0, 0, 0);
1.34 skrll 2946: goto bad2;
1.1 jakllsch 2947: }
2948: }
2949:
1.48 skrll 2950: bad2:
2951: if (err == USBD_NORMAL_COMPLETION) {
2952: xs->xs_idx = slot;
2953: } else {
2954: xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci);
2955: }
2956:
2957: return err;
2958:
2959: bad1:
2960: usb_freemem(&sc->sc_bus, &xs->xs_dc_dma);
2961: xs->xs_idx = 0;
2962: return err;
2963: }
2964:
2965: static void
2966: xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci,
2967: int end_dci)
2968: {
2969: u_int dci;
2970:
2971: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2972: DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci,
2973: end_dci, 0);
1.48 skrll 2974:
2975: for (dci = start_dci; dci < end_dci; dci++) {
2976: xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr);
2977: memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci]));
2978: }
2979: usb_freemem(&sc->sc_bus, &xs->xs_ic_dma);
2980: usb_freemem(&sc->sc_bus, &xs->xs_dc_dma);
2981: xs->xs_idx = 0;
2982: }
2983:
2984: /*
2985: * Setup slot context, set Device Context Base Address, and issue
2986: * Set Address Device command.
2987: */
2988: static usbd_status
1.51 skrll 2989: xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr)
1.48 skrll 2990: {
2991: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
2992: struct xhci_slot *xs;
2993: usbd_status err;
1.51 skrll 2994:
2995: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 2996: DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0);
1.51 skrll 2997:
2998: xs = &sc->sc_slots[slot];
2999:
3000: xhci_setup_ctx(dev->ud_pipe0);
3001:
1.79 christos 3002: HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0),
1.51 skrll 3003: sc->sc_ctxsz * 3);
3004:
3005: xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot);
3006:
3007: err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr);
3008:
3009: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1.79 christos 3010: HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0),
1.51 skrll 3011: sc->sc_ctxsz * 2);
3012:
3013: return err;
3014: }
3015:
3016: /*
3017: * 4.8.2, 6.2.3.2
3018: * construct slot/endpoint context parameters and do syncmem
3019: */
3020: static void
3021: xhci_setup_ctx(struct usbd_pipe *pipe)
3022: {
3023: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
3024: struct usbd_device *dev = pipe->up_dev;
3025: struct xhci_slot * const xs = dev->ud_hcpriv;
3026: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
3027: const u_int dci = xhci_ep_get_dci(ed);
3028: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1.48 skrll 3029: uint32_t *cp;
1.51 skrll 3030: uint16_t mps = UGETW(ed->wMaxPacketSize);
3031: uint8_t speed = dev->ud_speed;
3032: uint8_t ival = ed->bInterval;
1.48 skrll 3033:
1.51 skrll 3034: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 3035: DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju",
3036: (uintptr_t)pipe, xs->xs_idx, dci, speed);
1.48 skrll 3037:
1.1 jakllsch 3038: /* set up initial input control context */
3039: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
3040: cp[0] = htole32(0);
1.51 skrll 3041: cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci));
1.71 skrll 3042: cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT));
1.51 skrll 3043: cp[7] = htole32(0);
1.1 jakllsch 3044:
3045: /* set up input slot context */
3046: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1.51 skrll 3047: cp[0] =
3048: XHCI_SCTX_0_CTX_NUM_SET(dci) |
3049: XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed));
3050: cp[1] = 0;
3051: cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0);
3052: cp[3] = 0;
3053: xhci_setup_route(pipe, cp);
3054: xhci_setup_tthub(pipe, cp);
3055:
3056: cp[0] = htole32(cp[0]);
3057: cp[1] = htole32(cp[1]);
3058: cp[2] = htole32(cp[2]);
3059: cp[3] = htole32(cp[3]);
3060:
3061: /* set up input endpoint context */
3062: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci));
3063: cp[0] =
3064: XHCI_EPCTX_0_EPSTATE_SET(0) |
3065: XHCI_EPCTX_0_MULT_SET(0) |
3066: XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
3067: XHCI_EPCTX_0_LSA_SET(0) |
3068: XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0);
3069: cp[1] =
3070: XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) |
3071: XHCI_EPCTX_1_HID_SET(0) |
3072: XHCI_EPCTX_1_MAXB_SET(0);
3073:
3074: if (xfertype != UE_ISOCHRONOUS)
3075: cp[1] |= XHCI_EPCTX_1_CERR_SET(3);
3076:
3077: if (xfertype == UE_CONTROL)
3078: cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */
3079: else if (USB_IS_SS(speed))
3080: cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps);
3081: else
3082: cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps));
3083:
3084: xhci_setup_maxburst(pipe, cp);
3085:
3086: switch (xfertype) {
3087: case UE_CONTROL:
3088: break;
3089: case UE_BULK:
3090: /* XXX Set MaxPStreams, HID, and LSA if streams enabled */
3091: break;
3092: case UE_INTERRUPT:
3093: if (pipe->up_interval != USBD_DEFAULT_INTERVAL)
3094: ival = pipe->up_interval;
3095:
3096: ival = xhci_bival2ival(ival, speed);
3097: cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival);
3098: break;
3099: case UE_ISOCHRONOUS:
3100: if (pipe->up_interval != USBD_DEFAULT_INTERVAL)
3101: ival = pipe->up_interval;
3102:
3103: /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */
3104: if (speed == USB_SPEED_FULL)
3105: ival += 3; /* 1ms -> 125us */
3106: ival--;
3107: cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival);
3108: break;
3109: default:
3110: break;
3111: }
1.75 pgoyette 3112: DPRINTFN(4, "setting ival %ju MaxBurst %#jx",
1.53 skrll 3113: XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0);
1.1 jakllsch 3114:
1.55 skrll 3115: /* rewind TR dequeue pointer in xHC */
1.1 jakllsch 3116: /* can't use xhci_ep_get_dci() yet? */
3117: *(uint64_t *)(&cp[2]) = htole64(
1.51 skrll 3118: xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) |
1.1 jakllsch 3119: XHCI_EPCTX_2_DCS_SET(1));
1.51 skrll 3120:
3121: cp[0] = htole32(cp[0]);
3122: cp[1] = htole32(cp[1]);
3123: cp[4] = htole32(cp[4]);
1.1 jakllsch 3124:
1.55 skrll 3125: /* rewind TR dequeue pointer in driver */
3126: struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr;
3127: mutex_enter(&xr->xr_lock);
3128: xhci_host_dequeue(xr);
3129: mutex_exit(&xr->xr_lock);
3130:
1.1 jakllsch 3131: /* sync input contexts before they are read from memory */
3132: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1.51 skrll 3133: }
3134:
3135: /*
3136: * Setup route string and roothub port of given device for slot context
3137: */
3138: static void
3139: xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp)
3140: {
1.68 skrll 3141: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.51 skrll 3142: struct usbd_device *dev = pipe->up_dev;
3143: struct usbd_port *up = dev->ud_powersrc;
3144: struct usbd_device *hub;
3145: struct usbd_device *adev;
3146: uint8_t rhport = 0;
3147: uint32_t route = 0;
3148:
3149: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3150:
3151: /* Locate root hub port and Determine route string */
3152: /* 4.3.3 route string does not include roothub port */
3153: for (hub = dev; hub != NULL; hub = hub->ud_myhub) {
3154: uint32_t dep;
3155:
1.75 pgoyette 3156: DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd",
3157: (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc,
3158: hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno :
3159: -1);
1.51 skrll 3160:
3161: if (hub->ud_powersrc == NULL)
3162: break;
3163: dep = hub->ud_depth;
3164: if (dep == 0)
3165: break;
3166: rhport = hub->ud_powersrc->up_portno;
3167: if (dep > USB_HUB_MAX_DEPTH)
3168: continue;
3169:
3170: route |=
3171: (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport)
3172: << ((dep - 1) * 4);
3173: }
3174: route = route >> 4;
1.68 skrll 3175: size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1;
1.51 skrll 3176:
3177: /* Locate port on upstream high speed hub */
3178: for (adev = dev, hub = up->up_parent;
3179: hub != NULL && hub->ud_speed != USB_SPEED_HIGH;
3180: adev = hub, hub = hub->ud_myhub)
3181: ;
3182: if (hub) {
3183: int p;
3184: for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) {
3185: if (hub->ud_hub->uh_ports[p].up_dev == adev) {
3186: dev->ud_myhsport = &hub->ud_hub->uh_ports[p];
3187: goto found;
3188: }
3189: }
1.68 skrll 3190: panic("%s: cannot find HS port", __func__);
1.51 skrll 3191: found:
1.75 pgoyette 3192: DPRINTFN(4, "high speed port %jd", p, 0, 0, 0);
1.51 skrll 3193: } else {
3194: dev->ud_myhsport = NULL;
3195: }
3196:
1.68 skrll 3197: const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport);
3198:
1.75 pgoyette 3199: DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport,
3200: ctlrport, route, (uintptr_t)hub);
1.68 skrll 3201:
1.51 skrll 3202: cp[0] |= XHCI_SCTX_0_ROUTE_SET(route);
1.68 skrll 3203: cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport);
1.51 skrll 3204: }
3205:
3206: /*
3207: * Setup whether device is hub, whether device uses MTT, and
3208: * TT informations if it uses MTT.
3209: */
3210: static void
3211: xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp)
3212: {
3213: struct usbd_device *dev = pipe->up_dev;
1.78 christos 3214: struct usbd_port *myhsport = dev->ud_myhsport;
1.51 skrll 3215: usb_device_descriptor_t * const dd = &dev->ud_ddesc;
3216: uint32_t speed = dev->ud_speed;
1.83 skrll 3217: uint8_t rhaddr = dev->ud_bus->ub_rhaddr;
1.51 skrll 3218: uint8_t tthubslot, ttportnum;
3219: bool ishub;
3220: bool usemtt;
3221:
3222: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3223:
3224: /*
3225: * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2
3226: * tthubslot:
3227: * This is the slot ID of parent HS hub
3228: * if LS/FS device is connected && connected through HS hub.
3229: * This is 0 if device is not LS/FS device ||
3230: * parent hub is not HS hub ||
3231: * attached to root hub.
3232: * ttportnum:
3233: * This is the downstream facing port of parent HS hub
3234: * if LS/FS device is connected.
3235: * This is 0 if device is not LS/FS device ||
3236: * parent hub is not HS hub ||
3237: * attached to root hub.
3238: */
1.83 skrll 3239: if (myhsport &&
3240: myhsport->up_parent->ud_addr != rhaddr &&
1.51 skrll 3241: (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) {
1.78 christos 3242: ttportnum = myhsport->up_portno;
3243: tthubslot = myhsport->up_parent->ud_addr;
1.51 skrll 3244: } else {
3245: ttportnum = 0;
3246: tthubslot = 0;
3247: }
1.75 pgoyette 3248: DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd",
1.78 christos 3249: (uintptr_t)myhsport, ttportnum, tthubslot, 0);
1.51 skrll 3250:
3251: /* ishub is valid after reading UDESC_DEVICE */
3252: ishub = (dd->bDeviceClass == UDCLASS_HUB);
3253:
3254: /* dev->ud_hub is valid after reading UDESC_HUB */
3255: if (ishub && dev->ud_hub) {
3256: usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc;
3257: uint8_t ttt =
3258: __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK);
3259:
3260: cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts);
3261: cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt);
1.75 pgoyette 3262: DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0);
1.51 skrll 3263: }
3264:
1.83 skrll 3265: #define IS_MTTHUB(dd) \
3266: ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT)
1.51 skrll 3267:
3268: /*
3269: * MTT flag is set if
1.83 skrll 3270: * 1. this is HS hub && MTTs are supported and enabled; or
3271: * 2. this is LS or FS device && there is a parent HS hub where MTTs
3272: * are supported and enabled.
3273: *
3274: * XXX enabled is not tested yet
1.51 skrll 3275: */
1.83 skrll 3276: if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd))
1.51 skrll 3277: usemtt = true;
1.83 skrll 3278: else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) &&
3279: myhsport &&
3280: myhsport->up_parent->ud_addr != rhaddr &&
3281: IS_MTTHUB(&myhsport->up_parent->ud_ddesc))
1.51 skrll 3282: usemtt = true;
3283: else
3284: usemtt = false;
1.75 pgoyette 3285: DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd",
1.51 skrll 3286: dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt);
3287:
1.83 skrll 3288: #undef IS_MTTHUB
1.51 skrll 3289:
3290: cp[0] |=
3291: XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) |
3292: XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0);
3293: cp[2] |=
3294: XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) |
3295: XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum);
3296: }
3297:
3298: /* set up params for periodic endpoint */
3299: static void
3300: xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp)
3301: {
3302: struct usbd_device *dev = pipe->up_dev;
3303: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
3304: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
3305: usbd_desc_iter_t iter;
3306: const usb_cdc_descriptor_t *cdcd;
3307: uint32_t maxb = 0;
3308: uint16_t mps = UGETW(ed->wMaxPacketSize);
3309: uint8_t speed = dev->ud_speed;
3310: uint8_t ep;
3311:
3312: /* config desc is NULL when opening ep0 */
3313: if (dev == NULL || dev->ud_cdesc == NULL)
3314: goto no_cdcd;
3315: cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev,
3316: UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY);
3317: if (cdcd == NULL)
3318: goto no_cdcd;
3319: usb_desc_iter_init(dev, &iter);
3320: iter.cur = (const void *)cdcd;
3321:
3322: /* find endpoint_ss_comp desc for ep of this pipe */
3323: for (ep = 0;;) {
3324: cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter);
3325: if (cdcd == NULL)
3326: break;
3327: if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) {
3328: ep = ((const usb_endpoint_descriptor_t *)cdcd)->
3329: bEndpointAddress;
3330: if (UE_GET_ADDR(ep) ==
3331: UE_GET_ADDR(ed->bEndpointAddress)) {
3332: cdcd = (const usb_cdc_descriptor_t *)
3333: usb_desc_iter_next(&iter);
3334: break;
3335: }
3336: ep = 0;
3337: }
3338: }
3339: if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) {
3340: const usb_endpoint_ss_comp_descriptor_t * esscd =
3341: (const usb_endpoint_ss_comp_descriptor_t *)cdcd;
3342: maxb = esscd->bMaxBurst;
3343: }
3344:
3345: no_cdcd:
3346: /* 6.2.3.4, 4.8.2.4 */
3347: if (USB_IS_SS(speed)) {
1.60 skrll 3348: /* USB 3.1 9.6.6 */
1.51 skrll 3349: cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps);
1.60 skrll 3350: /* USB 3.1 9.6.7 */
1.51 skrll 3351: cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb);
3352: #ifdef notyet
3353: if (xfertype == UE_ISOCHRONOUS) {
3354: }
3355: if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) {
3356: /* use ESIT */
3357: cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x);
3358: cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x);
3359:
3360: /* XXX if LEC = 1, set ESIT instead */
3361: cp[0] |= XHCI_EPCTX_0_MULT_SET(0);
3362: } else {
3363: /* use ival */
3364: }
3365: #endif
3366: } else {
1.60 skrll 3367: /* USB 2.0 9.6.6 */
1.51 skrll 3368: cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps));
1.1 jakllsch 3369:
1.51 skrll 3370: /* 6.2.3.4 */
3371: if (speed == USB_SPEED_HIGH &&
3372: (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) {
3373: maxb = UE_GET_TRANS(mps);
3374: } else {
3375: /* LS/FS or HS CTRL or HS BULK */
3376: maxb = 0;
3377: }
3378: cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb);
3379: }
3380: }
1.1 jakllsch 3381:
1.51 skrll 3382: /*
3383: * Convert endpoint bInterval value to endpoint context interval value
3384: * for Interrupt pipe.
3385: * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6
3386: */
3387: static uint32_t
3388: xhci_bival2ival(uint32_t ival, uint32_t speed)
3389: {
3390: if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
3391: int i;
1.1 jakllsch 3392:
1.51 skrll 3393: /*
3394: * round ival down to "the nearest base 2 multiple of
3395: * bInterval * 8".
3396: * bInterval is at most 255 as its type is uByte.
3397: * 255(ms) = 2040(x 125us) < 2^11, so start with 10.
3398: */
3399: for (i = 10; i > 0; i--) {
3400: if ((ival * 8) >= (1 << i))
3401: break;
3402: }
3403: ival = i;
3404: } else {
3405: /* Interval = bInterval-1 for SS/HS */
3406: ival--;
3407: }
1.1 jakllsch 3408:
1.51 skrll 3409: return ival;
1.1 jakllsch 3410: }
3411:
3412: /* ----- */
3413:
3414: static void
1.34 skrll 3415: xhci_noop(struct usbd_pipe *pipe)
1.1 jakllsch 3416: {
1.27 skrll 3417: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3418: }
3419:
1.34 skrll 3420: /*
3421: * Process root hub request.
3422: */
3423: static int
3424: xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
3425: void *buf, int buflen)
1.1 jakllsch 3426: {
1.34 skrll 3427: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 3428: usb_port_status_t ps;
3429: int l, totlen = 0;
1.34 skrll 3430: uint16_t len, value, index;
1.1 jakllsch 3431: int port, i;
3432: uint32_t v;
3433:
1.27 skrll 3434: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3435:
3436: if (sc->sc_dying)
1.34 skrll 3437: return -1;
1.1 jakllsch 3438:
1.68 skrll 3439: size_t bn = bus == &sc->sc_bus ? 0 : 1;
3440:
1.34 skrll 3441: len = UGETW(req->wLength);
1.1 jakllsch 3442: value = UGETW(req->wValue);
3443: index = UGETW(req->wIndex);
3444:
1.75 pgoyette 3445: DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx",
1.27 skrll 3446: req->bmRequestType | (req->bRequest << 8), value, index, len);
1.1 jakllsch 3447:
3448: #define C(x,y) ((x) | ((y) << 8))
1.34 skrll 3449: switch (C(req->bRequest, req->bmRequestType)) {
1.1 jakllsch 3450: case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1.75 pgoyette 3451: DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0);
1.1 jakllsch 3452: if (len == 0)
3453: break;
1.34 skrll 3454: switch (value) {
3455: #define sd ((usb_string_descriptor_t *)buf)
3456: case C(2, UDESC_STRING):
3457: /* Product */
1.86.2.4 pgoyette 3458: totlen = usb_makestrdesc(sd, len, "xHCI root hub");
1.1 jakllsch 3459: break;
3460: #undef sd
3461: default:
1.34 skrll 3462: /* default from usbroothub */
3463: return buflen;
1.1 jakllsch 3464: }
3465: break;
1.34 skrll 3466:
1.1 jakllsch 3467: /* Hub requests */
3468: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3469: break;
1.34 skrll 3470: /* Clear Port Feature request */
1.68 skrll 3471: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): {
3472: const size_t cp = xhci_rhport2ctlrport(sc, bn, index);
3473:
1.75 pgoyette 3474: DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd",
1.68 skrll 3475: index, value, bn, cp);
3476: if (index < 1 || index > sc->sc_rhportcount[bn]) {
1.34 skrll 3477: return -1;
1.1 jakllsch 3478: }
1.68 skrll 3479: port = XHCI_PORTSC(cp);
1.1 jakllsch 3480: v = xhci_op_read_4(sc, port);
1.75 pgoyette 3481: DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0);
1.1 jakllsch 3482: v &= ~XHCI_PS_CLEAR;
3483: switch (value) {
3484: case UHF_PORT_ENABLE:
1.34 skrll 3485: xhci_op_write_4(sc, port, v & ~XHCI_PS_PED);
1.1 jakllsch 3486: break;
3487: case UHF_PORT_SUSPEND:
1.34 skrll 3488: return -1;
1.1 jakllsch 3489: case UHF_PORT_POWER:
3490: break;
3491: case UHF_PORT_TEST:
3492: case UHF_PORT_INDICATOR:
1.34 skrll 3493: return -1;
1.1 jakllsch 3494: case UHF_C_PORT_CONNECTION:
3495: xhci_op_write_4(sc, port, v | XHCI_PS_CSC);
3496: break;
3497: case UHF_C_PORT_ENABLE:
3498: case UHF_C_PORT_SUSPEND:
3499: case UHF_C_PORT_OVER_CURRENT:
1.34 skrll 3500: return -1;
3501: case UHF_C_BH_PORT_RESET:
3502: xhci_op_write_4(sc, port, v | XHCI_PS_WRC);
3503: break;
1.1 jakllsch 3504: case UHF_C_PORT_RESET:
3505: xhci_op_write_4(sc, port, v | XHCI_PS_PRC);
3506: break;
1.34 skrll 3507: case UHF_C_PORT_LINK_STATE:
3508: xhci_op_write_4(sc, port, v | XHCI_PS_PLC);
3509: break;
3510: case UHF_C_PORT_CONFIG_ERROR:
3511: xhci_op_write_4(sc, port, v | XHCI_PS_CEC);
3512: break;
1.1 jakllsch 3513: default:
1.34 skrll 3514: return -1;
1.1 jakllsch 3515: }
3516: break;
1.68 skrll 3517: }
1.1 jakllsch 3518: case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3519: if (len == 0)
3520: break;
3521: if ((value & 0xff) != 0) {
1.34 skrll 3522: return -1;
1.1 jakllsch 3523: }
1.34 skrll 3524: usb_hub_descriptor_t hubd;
3525:
1.86.2.6 pgoyette 3526: totlen = uimin(buflen, sizeof(hubd));
1.34 skrll 3527: memcpy(&hubd, buf, totlen);
1.68 skrll 3528: hubd.bNbrPorts = sc->sc_rhportcount[bn];
1.1 jakllsch 3529: USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH);
3530: hubd.bPwrOn2PwrGood = 200;
1.68 skrll 3531: for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) {
3532: /* XXX can't find out? */
3533: hubd.DeviceRemovable[i++] = 0;
3534: }
1.3 skrll 3535: hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1.86.2.6 pgoyette 3536: totlen = uimin(totlen, hubd.bDescLength);
1.34 skrll 3537: memcpy(buf, &hubd, totlen);
1.1 jakllsch 3538: break;
3539: case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3540: if (len != 4) {
1.34 skrll 3541: return -1;
1.1 jakllsch 3542: }
3543: memset(buf, 0, len); /* ? XXX */
3544: totlen = len;
3545: break;
1.34 skrll 3546: /* Get Port Status request */
1.68 skrll 3547: case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): {
3548: const size_t cp = xhci_rhport2ctlrport(sc, bn, index);
3549:
1.75 pgoyette 3550: DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju",
3551: bn, index, cp, 0);
1.68 skrll 3552: if (index < 1 || index > sc->sc_rhportcount[bn]) {
1.34 skrll 3553: return -1;
1.1 jakllsch 3554: }
3555: if (len != 4) {
1.34 skrll 3556: return -1;
1.1 jakllsch 3557: }
1.68 skrll 3558: v = xhci_op_read_4(sc, XHCI_PORTSC(cp));
1.75 pgoyette 3559: DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0);
1.34 skrll 3560: i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v));
1.1 jakllsch 3561: if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS;
3562: if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED;
3563: if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
3564: //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND;
3565: if (v & XHCI_PS_PR) i |= UPS_RESET;
1.34 skrll 3566: if (v & XHCI_PS_PP) {
3567: if (i & UPS_OTHER_SPEED)
3568: i |= UPS_PORT_POWER_SS;
3569: else
3570: i |= UPS_PORT_POWER;
3571: }
3572: if (i & UPS_OTHER_SPEED)
3573: i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v));
3574: if (sc->sc_vendor_port_status)
3575: i = sc->sc_vendor_port_status(sc, v, i);
1.1 jakllsch 3576: USETW(ps.wPortStatus, i);
3577: i = 0;
3578: if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
3579: if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
3580: if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
3581: if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET;
1.34 skrll 3582: if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET;
3583: if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE;
3584: if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR;
1.1 jakllsch 3585: USETW(ps.wPortChange, i);
1.86.2.6 pgoyette 3586: totlen = uimin(len, sizeof(ps));
1.34 skrll 3587: memcpy(buf, &ps, totlen);
1.1 jakllsch 3588: break;
1.68 skrll 3589: }
1.1 jakllsch 3590: case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1.34 skrll 3591: return -1;
3592: case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE):
3593: break;
1.1 jakllsch 3594: case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3595: break;
1.34 skrll 3596: /* Set Port Feature request */
3597: case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): {
3598: int optval = (index >> 8) & 0xff;
3599: index &= 0xff;
1.68 skrll 3600: if (index < 1 || index > sc->sc_rhportcount[bn]) {
1.34 skrll 3601: return -1;
1.1 jakllsch 3602: }
1.68 skrll 3603:
3604: const size_t cp = xhci_rhport2ctlrport(sc, bn, index);
3605:
3606: port = XHCI_PORTSC(cp);
1.1 jakllsch 3607: v = xhci_op_read_4(sc, port);
1.75 pgoyette 3608: DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0);
1.1 jakllsch 3609: v &= ~XHCI_PS_CLEAR;
3610: switch (value) {
3611: case UHF_PORT_ENABLE:
3612: xhci_op_write_4(sc, port, v | XHCI_PS_PED);
3613: break;
3614: case UHF_PORT_SUSPEND:
3615: /* XXX suspend */
3616: break;
3617: case UHF_PORT_RESET:
1.34 skrll 3618: v &= ~(XHCI_PS_PED | XHCI_PS_PR);
1.1 jakllsch 3619: xhci_op_write_4(sc, port, v | XHCI_PS_PR);
3620: /* Wait for reset to complete. */
3621: usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3622: if (sc->sc_dying) {
1.34 skrll 3623: return -1;
1.1 jakllsch 3624: }
3625: v = xhci_op_read_4(sc, port);
3626: if (v & XHCI_PS_PR) {
3627: xhci_op_write_4(sc, port, v & ~XHCI_PS_PR);
3628: usb_delay_ms(&sc->sc_bus, 10);
3629: /* XXX */
3630: }
3631: break;
3632: case UHF_PORT_POWER:
3633: /* XXX power control */
3634: break;
3635: /* XXX more */
3636: case UHF_C_PORT_RESET:
3637: xhci_op_write_4(sc, port, v | XHCI_PS_PRC);
3638: break;
1.34 skrll 3639: case UHF_PORT_U1_TIMEOUT:
3640: if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) {
3641: return -1;
3642: }
1.68 skrll 3643: port = XHCI_PORTPMSC(cp);
1.34 skrll 3644: v = xhci_op_read_4(sc, port);
1.75 pgoyette 3645: DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx",
3646: index, cp, v, 0);
1.34 skrll 3647: v &= ~XHCI_PM3_U1TO_SET(0xff);
3648: v |= XHCI_PM3_U1TO_SET(optval);
3649: xhci_op_write_4(sc, port, v);
3650: break;
3651: case UHF_PORT_U2_TIMEOUT:
3652: if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) {
3653: return -1;
3654: }
1.68 skrll 3655: port = XHCI_PORTPMSC(cp);
1.34 skrll 3656: v = xhci_op_read_4(sc, port);
1.75 pgoyette 3657: DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx",
3658: index, cp, v, 0);
1.34 skrll 3659: v &= ~XHCI_PM3_U2TO_SET(0xff);
3660: v |= XHCI_PM3_U2TO_SET(optval);
3661: xhci_op_write_4(sc, port, v);
3662: break;
1.1 jakllsch 3663: default:
1.34 skrll 3664: return -1;
1.1 jakllsch 3665: }
1.34 skrll 3666: }
1.1 jakllsch 3667: break;
3668: case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3669: case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3670: case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3671: case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3672: break;
3673: default:
1.34 skrll 3674: /* default from usbroothub */
3675: return buflen;
1.1 jakllsch 3676: }
1.27 skrll 3677:
1.34 skrll 3678: return totlen;
1.1 jakllsch 3679: }
3680:
1.28 skrll 3681: /* root hub interrupt */
1.1 jakllsch 3682:
3683: static usbd_status
1.34 skrll 3684: xhci_root_intr_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3685: {
1.34 skrll 3686: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3687: usbd_status err;
3688:
1.27 skrll 3689: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3690:
1.1 jakllsch 3691: /* Insert last in queue. */
3692: mutex_enter(&sc->sc_lock);
3693: err = usb_insert_transfer(xfer);
3694: mutex_exit(&sc->sc_lock);
3695: if (err)
3696: return err;
3697:
3698: /* Pipe isn't running, start first */
1.34 skrll 3699: return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3700: }
3701:
1.34 skrll 3702: /* Wait for roothub port status/change */
1.1 jakllsch 3703: static usbd_status
1.34 skrll 3704: xhci_root_intr_start(struct usbd_xfer *xfer)
1.1 jakllsch 3705: {
1.34 skrll 3706: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.68 skrll 3707: const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1;
1.86.2.7! pgoyette 3708: const bool polling = sc->sc_bus.ub_usepolling;
1.1 jakllsch 3709:
1.27 skrll 3710: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3711:
1.1 jakllsch 3712: if (sc->sc_dying)
3713: return USBD_IOERROR;
3714:
1.86.2.7! pgoyette 3715: if (!polling)
! 3716: mutex_enter(&sc->sc_lock);
1.68 skrll 3717: sc->sc_intrxfer[bn] = xfer;
1.86.2.7! pgoyette 3718: if (!polling)
! 3719: mutex_exit(&sc->sc_lock);
1.1 jakllsch 3720:
3721: return USBD_IN_PROGRESS;
3722: }
3723:
3724: static void
1.34 skrll 3725: xhci_root_intr_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3726: {
1.86 prlw1 3727: struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer);
1.1 jakllsch 3728:
1.27 skrll 3729: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3730:
1.1 jakllsch 3731: KASSERT(mutex_owned(&sc->sc_lock));
1.34 skrll 3732: KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
1.21 skrll 3733:
1.34 skrll 3734: xfer->ux_status = USBD_CANCELLED;
1.1 jakllsch 3735: usb_transfer_complete(xfer);
3736: }
3737:
3738: static void
1.34 skrll 3739: xhci_root_intr_close(struct usbd_pipe *pipe)
1.1 jakllsch 3740: {
1.34 skrll 3741: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.68 skrll 3742: const struct usbd_xfer *xfer = pipe->up_intrxfer;
3743: const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1;
1.1 jakllsch 3744:
1.27 skrll 3745: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3746:
1.1 jakllsch 3747: KASSERT(mutex_owned(&sc->sc_lock));
3748:
1.68 skrll 3749: sc->sc_intrxfer[bn] = NULL;
1.1 jakllsch 3750: }
3751:
3752: static void
1.34 skrll 3753: xhci_root_intr_done(struct usbd_xfer *xfer)
1.1 jakllsch 3754: {
1.27 skrll 3755: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3756:
1.1 jakllsch 3757: }
3758:
3759: /* -------------- */
3760: /* device control */
3761:
3762: static usbd_status
1.34 skrll 3763: xhci_device_ctrl_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3764: {
1.34 skrll 3765: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3766: usbd_status err;
3767:
1.27 skrll 3768: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3769:
1.1 jakllsch 3770: /* Insert last in queue. */
3771: mutex_enter(&sc->sc_lock);
3772: err = usb_insert_transfer(xfer);
3773: mutex_exit(&sc->sc_lock);
3774: if (err)
1.34 skrll 3775: return err;
1.1 jakllsch 3776:
3777: /* Pipe isn't running, start first */
1.34 skrll 3778: return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3779: }
3780:
3781: static usbd_status
1.34 skrll 3782: xhci_device_ctrl_start(struct usbd_xfer *xfer)
1.1 jakllsch 3783: {
1.34 skrll 3784: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
3785: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3786: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3787: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.35 skrll 3788: struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer);
1.34 skrll 3789: usb_device_request_t * const req = &xfer->ux_request;
3790: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 3791: const uint32_t len = UGETW(req->wLength);
1.34 skrll 3792: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3793: uint64_t parameter;
3794: uint32_t status;
3795: uint32_t control;
3796: u_int i;
1.86.2.7! pgoyette 3797: const bool polling = sc->sc_bus.ub_usepolling;
1.1 jakllsch 3798:
1.27 skrll 3799: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 3800: DPRINTFN(12, "req: %04jx %04jx %04jx %04jx",
1.27 skrll 3801: req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue),
3802: UGETW(req->wIndex), UGETW(req->wLength));
1.1 jakllsch 3803:
3804: /* we rely on the bottom bits for extra info */
1.59 maya 3805: KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx",
3806: (uintptr_t) xfer);
1.1 jakllsch 3807:
1.34 skrll 3808: KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0);
1.1 jakllsch 3809:
3810: i = 0;
3811:
3812: /* setup phase */
1.63 skrll 3813: memcpy(¶meter, req, sizeof(parameter));
1.1 jakllsch 3814: status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req));
3815: control = ((len == 0) ? XHCI_TRB_3_TRT_NONE :
3816: (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) |
3817: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
3818: XHCI_TRB_3_IDT_BIT;
3819: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3820:
1.34 skrll 3821: if (len != 0) {
3822: /* data phase */
3823: parameter = DMAADDR(dma, 0);
1.59 maya 3824: KASSERTMSG(len <= 0x10000, "len %d", len);
1.34 skrll 3825: status = XHCI_TRB_2_IRQ_SET(0) |
3826: XHCI_TRB_2_TDSZ_SET(1) |
3827: XHCI_TRB_2_BYTES_SET(len);
3828: control = (isread ? XHCI_TRB_3_DIR_IN : 0) |
3829: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1.63 skrll 3830: (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) |
1.34 skrll 3831: XHCI_TRB_3_IOC_BIT;
3832: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3833: }
1.1 jakllsch 3834:
3835: parameter = 0;
1.28 skrll 3836: status = XHCI_TRB_2_IRQ_SET(0);
1.1 jakllsch 3837: /* the status stage has inverted direction */
1.28 skrll 3838: control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) |
1.1 jakllsch 3839: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
3840: XHCI_TRB_3_IOC_BIT;
3841: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
1.86.2.6 pgoyette 3842: xfer->ux_status = USBD_IN_PROGRESS;
1.1 jakllsch 3843:
1.86.2.7! pgoyette 3844: if (!polling)
! 3845: mutex_enter(&tr->xr_lock);
1.1 jakllsch 3846: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
1.86.2.7! pgoyette 3847: if (!polling)
! 3848: mutex_exit(&tr->xr_lock);
1.1 jakllsch 3849:
3850: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
3851:
1.73 skrll 3852: if (xfer->ux_timeout && !xhci_polling_p(sc)) {
1.34 skrll 3853: callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1.1 jakllsch 3854: xhci_timeout, xfer);
3855: }
3856:
3857: return USBD_IN_PROGRESS;
3858: }
3859:
3860: static void
1.34 skrll 3861: xhci_device_ctrl_done(struct usbd_xfer *xfer)
1.1 jakllsch 3862: {
1.27 skrll 3863: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3864: usb_device_request_t *req = &xfer->ux_request;
3865: int len = UGETW(req->wLength);
3866: int rd = req->bmRequestType & UT_READ;
1.1 jakllsch 3867:
1.34 skrll 3868: if (len)
3869: usb_syncmem(&xfer->ux_dmabuf, 0, len,
3870: rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.1 jakllsch 3871: }
3872:
3873: static void
1.34 skrll 3874: xhci_device_ctrl_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3875: {
1.27 skrll 3876: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3877:
3878: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 3879: }
3880:
3881: static void
1.34 skrll 3882: xhci_device_ctrl_close(struct usbd_pipe *pipe)
1.1 jakllsch 3883: {
1.27 skrll 3884: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3885:
3886: xhci_close_pipe(pipe);
1.1 jakllsch 3887: }
3888:
1.34 skrll 3889: /* ------------------ */
3890: /* device isochronous */
1.1 jakllsch 3891:
3892: /* ----------- */
3893: /* device bulk */
3894:
3895: static usbd_status
1.34 skrll 3896: xhci_device_bulk_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3897: {
1.34 skrll 3898: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3899: usbd_status err;
3900:
1.27 skrll 3901: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3902:
1.1 jakllsch 3903: /* Insert last in queue. */
3904: mutex_enter(&sc->sc_lock);
3905: err = usb_insert_transfer(xfer);
3906: mutex_exit(&sc->sc_lock);
3907: if (err)
3908: return err;
3909:
3910: /*
3911: * Pipe isn't running (otherwise err would be USBD_INPROG),
3912: * so start it first.
3913: */
1.34 skrll 3914: return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3915: }
3916:
3917: static usbd_status
1.34 skrll 3918: xhci_device_bulk_start(struct usbd_xfer *xfer)
1.1 jakllsch 3919: {
1.34 skrll 3920: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
3921: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3922: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3923: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.35 skrll 3924: struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer);
1.34 skrll 3925: const uint32_t len = xfer->ux_length;
3926: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3927: uint64_t parameter;
3928: uint32_t status;
3929: uint32_t control;
3930: u_int i = 0;
1.86.2.7! pgoyette 3931: const bool polling = sc->sc_bus.ub_usepolling;
1.1 jakllsch 3932:
1.27 skrll 3933: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3934:
1.75 pgoyette 3935: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
3936: 0);
1.1 jakllsch 3937:
3938: if (sc->sc_dying)
3939: return USBD_IOERROR;
3940:
1.34 skrll 3941: KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0);
1.1 jakllsch 3942:
3943: parameter = DMAADDR(dma, 0);
1.11 dsl 3944: /*
1.13 dsl 3945: * XXX: (dsl) The physical buffer must not cross a 64k boundary.
1.11 dsl 3946: * If the user supplied buffer crosses such a boundary then 2
3947: * (or more) TRB should be used.
3948: * If multiple TRB are used the td_size field must be set correctly.
3949: * For v1.0 devices (like ivy bridge) this is the number of usb data
3950: * blocks needed to complete the transfer.
3951: * Setting it to 1 in the last TRB causes an extra zero-length
3952: * data block be sent.
3953: * The earlier documentation differs, I don't know how it behaves.
3954: */
1.59 maya 3955: KASSERTMSG(len <= 0x10000, "len %d", len);
1.1 jakllsch 3956: status = XHCI_TRB_2_IRQ_SET(0) |
3957: XHCI_TRB_2_TDSZ_SET(1) |
3958: XHCI_TRB_2_BYTES_SET(len);
3959: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1.63 skrll 3960: (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) |
3961: XHCI_TRB_3_IOC_BIT;
1.1 jakllsch 3962: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
1.86.2.6 pgoyette 3963: xfer->ux_status = USBD_IN_PROGRESS;
1.1 jakllsch 3964:
1.86.2.7! pgoyette 3965: if (!polling)
! 3966: mutex_enter(&tr->xr_lock);
1.1 jakllsch 3967: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
1.86.2.7! pgoyette 3968: if (!polling)
! 3969: mutex_exit(&tr->xr_lock);
1.1 jakllsch 3970:
3971: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
3972:
1.73 skrll 3973: if (xfer->ux_timeout && !xhci_polling_p(sc)) {
1.34 skrll 3974: callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
3975: xhci_timeout, xfer);
3976: }
3977:
1.1 jakllsch 3978: return USBD_IN_PROGRESS;
3979: }
3980:
3981: static void
1.34 skrll 3982: xhci_device_bulk_done(struct usbd_xfer *xfer)
1.1 jakllsch 3983: {
1.27 skrll 3984: #ifdef USB_DEBUG
1.34 skrll 3985: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3986: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.27 skrll 3987: #endif
1.34 skrll 3988: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 3989:
1.27 skrll 3990: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3991:
1.75 pgoyette 3992: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
3993: 0);
1.1 jakllsch 3994:
1.34 skrll 3995: usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1.1 jakllsch 3996: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3997: }
3998:
3999: static void
1.34 skrll 4000: xhci_device_bulk_abort(struct usbd_xfer *xfer)
1.1 jakllsch 4001: {
1.27 skrll 4002: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 4003:
4004: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 4005: }
4006:
4007: static void
1.34 skrll 4008: xhci_device_bulk_close(struct usbd_pipe *pipe)
1.1 jakllsch 4009: {
1.27 skrll 4010: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 4011:
4012: xhci_close_pipe(pipe);
1.1 jakllsch 4013: }
4014:
1.34 skrll 4015: /* ---------------- */
4016: /* device interrupt */
1.1 jakllsch 4017:
4018: static usbd_status
1.34 skrll 4019: xhci_device_intr_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 4020: {
1.34 skrll 4021: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 4022: usbd_status err;
4023:
1.27 skrll 4024: XHCIHIST_FUNC(); XHCIHIST_CALLED();
4025:
1.1 jakllsch 4026: /* Insert last in queue. */
4027: mutex_enter(&sc->sc_lock);
4028: err = usb_insert_transfer(xfer);
4029: mutex_exit(&sc->sc_lock);
4030: if (err)
4031: return err;
4032:
4033: /*
4034: * Pipe isn't running (otherwise err would be USBD_INPROG),
4035: * so start it first.
4036: */
1.34 skrll 4037: return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 4038: }
4039:
4040: static usbd_status
1.34 skrll 4041: xhci_device_intr_start(struct usbd_xfer *xfer)
1.1 jakllsch 4042: {
1.34 skrll 4043: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
4044: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
4045: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 4046: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.35 skrll 4047: struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer);
1.34 skrll 4048: const uint32_t len = xfer->ux_length;
1.86.2.5 pgoyette 4049: const bool polling = xhci_polling_p(sc);
1.34 skrll 4050: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 4051: uint64_t parameter;
4052: uint32_t status;
4053: uint32_t control;
4054: u_int i = 0;
4055:
1.27 skrll 4056: XHCIHIST_FUNC(); XHCIHIST_CALLED();
4057:
1.75 pgoyette 4058: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
4059: 0);
1.1 jakllsch 4060:
4061: if (sc->sc_dying)
4062: return USBD_IOERROR;
4063:
1.34 skrll 4064: KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0);
1.1 jakllsch 4065:
4066: parameter = DMAADDR(dma, 0);
1.59 maya 4067: KASSERTMSG(len <= 0x10000, "len %d", len);
1.1 jakllsch 4068: status = XHCI_TRB_2_IRQ_SET(0) |
4069: XHCI_TRB_2_TDSZ_SET(1) |
4070: XHCI_TRB_2_BYTES_SET(len);
4071: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1.63 skrll 4072: (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) |
4073: XHCI_TRB_3_IOC_BIT;
1.1 jakllsch 4074: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
1.86.2.6 pgoyette 4075: xfer->ux_status = USBD_IN_PROGRESS;
1.1 jakllsch 4076:
1.86.2.5 pgoyette 4077: if (!polling)
4078: mutex_enter(&tr->xr_lock);
1.1 jakllsch 4079: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
1.86.2.5 pgoyette 4080: if (!polling)
4081: mutex_exit(&tr->xr_lock);
1.1 jakllsch 4082:
4083: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4084:
1.86.2.5 pgoyette 4085: if (xfer->ux_timeout && !polling) {
1.34 skrll 4086: callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
4087: xhci_timeout, xfer);
4088: }
4089:
1.1 jakllsch 4090: return USBD_IN_PROGRESS;
4091: }
4092:
4093: static void
1.34 skrll 4094: xhci_device_intr_done(struct usbd_xfer *xfer)
1.1 jakllsch 4095: {
1.34 skrll 4096: struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer);
1.27 skrll 4097: #ifdef USB_DEBUG
1.34 skrll 4098: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
4099: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.19 ozaki-r 4100: #endif
1.34 skrll 4101: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 4102:
1.27 skrll 4103: XHCIHIST_FUNC(); XHCIHIST_CALLED();
4104:
1.75 pgoyette 4105: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
4106: 0);
1.1 jakllsch 4107:
1.73 skrll 4108: KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock));
1.1 jakllsch 4109:
1.34 skrll 4110: usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1.1 jakllsch 4111: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
4112: }
4113:
4114: static void
1.34 skrll 4115: xhci_device_intr_abort(struct usbd_xfer *xfer)
1.1 jakllsch 4116: {
1.34 skrll 4117: struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer);
1.27 skrll 4118:
4119: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.10 skrll 4120:
4121: KASSERT(mutex_owned(&sc->sc_lock));
1.75 pgoyette 4122: DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0);
1.34 skrll 4123: KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
4124: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 4125: }
4126:
4127: static void
1.34 skrll 4128: xhci_device_intr_close(struct usbd_pipe *pipe)
1.1 jakllsch 4129: {
1.34 skrll 4130: //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.27 skrll 4131:
4132: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.75 pgoyette 4133: DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0);
1.27 skrll 4134:
1.34 skrll 4135: xhci_close_pipe(pipe);
1.1 jakllsch 4136: }
4137:
4138: /* ------------ */
4139:
4140: static void
4141: xhci_timeout(void *addr)
4142: {
1.86.2.6 pgoyette 4143: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 4144: struct xhci_xfer * const xx = addr;
1.34 skrll 4145: struct usbd_xfer * const xfer = &xx->xx_xfer;
4146: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.86.2.6 pgoyette 4147: struct usbd_device *dev = xfer->ux_pipe->up_dev;
1.1 jakllsch 4148:
1.86.2.6 pgoyette 4149: mutex_enter(&sc->sc_lock);
4150: if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS)
4151: usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC);
4152: mutex_exit(&sc->sc_lock);
1.1 jakllsch 4153: }
4154:
4155: static void
4156: xhci_timeout_task(void *addr)
4157: {
1.86.2.6 pgoyette 4158: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 4159: struct usbd_xfer * const xfer = addr;
4160: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 4161:
4162: mutex_enter(&sc->sc_lock);
4163: xhci_abort_xfer(xfer, USBD_TIMEOUT);
4164: mutex_exit(&sc->sc_lock);
4165: }
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