Annotation of src/sys/dev/usb/xhci.c, Revision 1.72.2.5
1.72.2.5! snj 1: /* $NetBSD: xhci.c,v 1.72.2.4 2017/11/23 13:29:32 martin Exp $ */
1.1 jakllsch 2:
3: /*
4: * Copyright (c) 2013 Jonathan A. Kollasch
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17: * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20: * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23: * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27: */
28:
1.34 skrll 29: /*
1.41 skrll 30: * USB rev 2.0 and rev 3.1 specification
31: * http://www.usb.org/developers/docs/
1.34 skrll 32: * xHCI rev 1.1 specification
1.41 skrll 33: * http://www.intel.com/technology/usb/spec.htm
1.34 skrll 34: */
35:
1.1 jakllsch 36: #include <sys/cdefs.h>
1.72.2.5! snj 37: __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.72.2.4 2017/11/23 13:29:32 martin Exp $");
1.27 skrll 38:
1.46 pooka 39: #ifdef _KERNEL_OPT
1.27 skrll 40: #include "opt_usb.h"
1.46 pooka 41: #endif
1.1 jakllsch 42:
43: #include <sys/param.h>
44: #include <sys/systm.h>
45: #include <sys/kernel.h>
46: #include <sys/kmem.h>
47: #include <sys/device.h>
48: #include <sys/select.h>
49: #include <sys/proc.h>
50: #include <sys/queue.h>
51: #include <sys/mutex.h>
52: #include <sys/condvar.h>
53: #include <sys/bus.h>
54: #include <sys/cpu.h>
1.27 skrll 55: #include <sys/sysctl.h>
1.1 jakllsch 56:
57: #include <machine/endian.h>
58:
59: #include <dev/usb/usb.h>
60: #include <dev/usb/usbdi.h>
61: #include <dev/usb/usbdivar.h>
1.34 skrll 62: #include <dev/usb/usbdi_util.h>
1.27 skrll 63: #include <dev/usb/usbhist.h>
1.1 jakllsch 64: #include <dev/usb/usb_mem.h>
65: #include <dev/usb/usb_quirks.h>
66:
67: #include <dev/usb/xhcireg.h>
68: #include <dev/usb/xhcivar.h>
1.34 skrll 69: #include <dev/usb/usbroothub.h>
1.1 jakllsch 70:
1.27 skrll 71:
72: #ifdef USB_DEBUG
73: #ifndef XHCI_DEBUG
74: #define xhcidebug 0
1.34 skrll 75: #else /* !XHCI_DEBUG */
1.27 skrll 76: static int xhcidebug = 0;
77:
78: SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup")
79: {
80: int err;
81: const struct sysctlnode *rnode;
82: const struct sysctlnode *cnode;
83:
84: err = sysctl_createv(clog, 0, NULL, &rnode,
85: CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci",
86: SYSCTL_DESCR("xhci global controls"),
87: NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
88:
89: if (err)
90: goto fail;
91:
92: /* control debugging printfs */
93: err = sysctl_createv(clog, 0, &rnode, &cnode,
94: CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
95: "debug", SYSCTL_DESCR("Enable debugging output"),
96: NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL);
97: if (err)
98: goto fail;
99:
100: return;
101: fail:
102: aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
103: }
104:
1.34 skrll 105: #endif /* !XHCI_DEBUG */
1.27 skrll 106: #endif /* USB_DEBUG */
107:
108: #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D)
109: #define XHCIHIST_FUNC() USBHIST_FUNC()
110: #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug)
1.1 jakllsch 111:
112: #define XHCI_DCI_SLOT 0
113: #define XHCI_DCI_EP_CONTROL 1
114:
115: #define XHCI_ICI_INPUT_CONTROL 0
116:
117: struct xhci_pipe {
118: struct usbd_pipe xp_pipe;
1.34 skrll 119: struct usb_task xp_async_task;
1.1 jakllsch 120: };
121:
122: #define XHCI_COMMAND_RING_TRBS 256
123: #define XHCI_EVENT_RING_TRBS 256
124: #define XHCI_EVENT_RING_SEGMENTS 1
125: #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT
126:
1.34 skrll 127: static usbd_status xhci_open(struct usbd_pipe *);
128: static void xhci_close_pipe(struct usbd_pipe *);
1.1 jakllsch 129: static int xhci_intr1(struct xhci_softc * const);
130: static void xhci_softintr(void *);
131: static void xhci_poll(struct usbd_bus *);
1.34 skrll 132: static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int);
133: static void xhci_freex(struct usbd_bus *, struct usbd_xfer *);
1.1 jakllsch 134: static void xhci_get_lock(struct usbd_bus *, kmutex_t **);
1.34 skrll 135: static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int,
1.1 jakllsch 136: struct usbd_port *);
1.34 skrll 137: static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
138: void *, int);
1.1 jakllsch 139:
1.34 skrll 140: static usbd_status xhci_configure_endpoint(struct usbd_pipe *);
141: //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *);
142: static usbd_status xhci_reset_endpoint(struct usbd_pipe *);
143: static usbd_status xhci_stop_endpoint(struct usbd_pipe *);
1.1 jakllsch 144:
1.55 skrll 145: static void xhci_host_dequeue(struct xhci_ring * const);
1.34 skrll 146: static usbd_status xhci_set_dequeue(struct usbd_pipe *);
1.1 jakllsch 147:
148: static usbd_status xhci_do_command(struct xhci_softc * const,
149: struct xhci_trb * const, int);
1.34 skrll 150: static usbd_status xhci_do_command_locked(struct xhci_softc * const,
151: struct xhci_trb * const, int);
1.48 skrll 152: static usbd_status xhci_init_slot(struct usbd_device *, uint32_t);
153: static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int);
1.51 skrll 154: static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool);
1.1 jakllsch 155: static usbd_status xhci_enable_slot(struct xhci_softc * const,
156: uint8_t * const);
1.34 skrll 157: static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t);
1.1 jakllsch 158: static usbd_status xhci_address_device(struct xhci_softc * const,
159: uint64_t, uint8_t, bool);
1.34 skrll 160: static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int);
1.1 jakllsch 161: static usbd_status xhci_update_ep0_mps(struct xhci_softc * const,
162: struct xhci_slot * const, u_int);
163: static usbd_status xhci_ring_init(struct xhci_softc * const,
164: struct xhci_ring * const, size_t, size_t);
165: static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const);
166:
1.51 skrll 167: static void xhci_setup_ctx(struct usbd_pipe *);
168: static void xhci_setup_route(struct usbd_pipe *, uint32_t *);
169: static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *);
170: static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *);
171: static uint32_t xhci_bival2ival(uint32_t, uint32_t);
172:
1.34 skrll 173: static void xhci_noop(struct usbd_pipe *);
1.1 jakllsch 174:
1.34 skrll 175: static usbd_status xhci_root_intr_transfer(struct usbd_xfer *);
176: static usbd_status xhci_root_intr_start(struct usbd_xfer *);
177: static void xhci_root_intr_abort(struct usbd_xfer *);
178: static void xhci_root_intr_close(struct usbd_pipe *);
179: static void xhci_root_intr_done(struct usbd_xfer *);
180:
181: static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *);
182: static usbd_status xhci_device_ctrl_start(struct usbd_xfer *);
183: static void xhci_device_ctrl_abort(struct usbd_xfer *);
184: static void xhci_device_ctrl_close(struct usbd_pipe *);
185: static void xhci_device_ctrl_done(struct usbd_xfer *);
186:
187: static usbd_status xhci_device_intr_transfer(struct usbd_xfer *);
188: static usbd_status xhci_device_intr_start(struct usbd_xfer *);
189: static void xhci_device_intr_abort(struct usbd_xfer *);
190: static void xhci_device_intr_close(struct usbd_pipe *);
191: static void xhci_device_intr_done(struct usbd_xfer *);
192:
193: static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *);
194: static usbd_status xhci_device_bulk_start(struct usbd_xfer *);
195: static void xhci_device_bulk_abort(struct usbd_xfer *);
196: static void xhci_device_bulk_close(struct usbd_pipe *);
197: static void xhci_device_bulk_done(struct usbd_xfer *);
1.1 jakllsch 198:
199: static void xhci_timeout(void *);
200: static void xhci_timeout_task(void *);
201:
202: static const struct usbd_bus_methods xhci_bus_methods = {
1.34 skrll 203: .ubm_open = xhci_open,
204: .ubm_softint = xhci_softintr,
205: .ubm_dopoll = xhci_poll,
206: .ubm_allocx = xhci_allocx,
207: .ubm_freex = xhci_freex,
208: .ubm_getlock = xhci_get_lock,
209: .ubm_newdev = xhci_new_device,
210: .ubm_rhctrl = xhci_roothub_ctrl,
1.1 jakllsch 211: };
212:
213: static const struct usbd_pipe_methods xhci_root_intr_methods = {
1.34 skrll 214: .upm_transfer = xhci_root_intr_transfer,
215: .upm_start = xhci_root_intr_start,
216: .upm_abort = xhci_root_intr_abort,
217: .upm_close = xhci_root_intr_close,
218: .upm_cleartoggle = xhci_noop,
219: .upm_done = xhci_root_intr_done,
1.1 jakllsch 220: };
221:
222:
223: static const struct usbd_pipe_methods xhci_device_ctrl_methods = {
1.34 skrll 224: .upm_transfer = xhci_device_ctrl_transfer,
225: .upm_start = xhci_device_ctrl_start,
226: .upm_abort = xhci_device_ctrl_abort,
227: .upm_close = xhci_device_ctrl_close,
228: .upm_cleartoggle = xhci_noop,
229: .upm_done = xhci_device_ctrl_done,
1.1 jakllsch 230: };
231:
232: static const struct usbd_pipe_methods xhci_device_isoc_methods = {
1.34 skrll 233: .upm_cleartoggle = xhci_noop,
1.1 jakllsch 234: };
235:
236: static const struct usbd_pipe_methods xhci_device_bulk_methods = {
1.34 skrll 237: .upm_transfer = xhci_device_bulk_transfer,
238: .upm_start = xhci_device_bulk_start,
239: .upm_abort = xhci_device_bulk_abort,
240: .upm_close = xhci_device_bulk_close,
241: .upm_cleartoggle = xhci_noop,
242: .upm_done = xhci_device_bulk_done,
1.1 jakllsch 243: };
244:
245: static const struct usbd_pipe_methods xhci_device_intr_methods = {
1.34 skrll 246: .upm_transfer = xhci_device_intr_transfer,
247: .upm_start = xhci_device_intr_start,
248: .upm_abort = xhci_device_intr_abort,
249: .upm_close = xhci_device_intr_close,
250: .upm_cleartoggle = xhci_noop,
251: .upm_done = xhci_device_intr_done,
1.1 jakllsch 252: };
253:
254: static inline uint32_t
1.34 skrll 255: xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset)
256: {
257: return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
258: }
259:
260: static inline uint32_t
1.1 jakllsch 261: xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset)
262: {
263: return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset);
264: }
265:
1.34 skrll 266: static inline void
267: xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset,
268: uint32_t value)
269: {
270: bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value);
271: }
272:
1.4 apb 273: #if 0 /* unused */
1.1 jakllsch 274: static inline void
275: xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset,
276: uint32_t value)
277: {
278: bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value);
279: }
1.4 apb 280: #endif /* unused */
1.1 jakllsch 281:
282: static inline uint32_t
283: xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset)
284: {
285: return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset);
286: }
287:
288: static inline uint32_t
289: xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset)
290: {
291: return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
292: }
293:
294: static inline void
295: xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset,
296: uint32_t value)
297: {
298: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
299: }
300:
301: static inline uint64_t
302: xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset)
303: {
304: uint64_t value;
305:
306: if (sc->sc_ac64) {
307: #ifdef XHCI_USE_BUS_SPACE_8
308: value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset);
309: #else
310: value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
311: value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh,
312: offset + 4) << 32;
313: #endif
314: } else {
315: value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
316: }
317:
318: return value;
319: }
320:
321: static inline void
322: xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset,
323: uint64_t value)
324: {
325: if (sc->sc_ac64) {
326: #ifdef XHCI_USE_BUS_SPACE_8
327: bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value);
328: #else
329: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0,
330: (value >> 0) & 0xffffffff);
331: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4,
332: (value >> 32) & 0xffffffff);
333: #endif
334: } else {
335: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
336: }
337: }
338:
339: static inline uint32_t
340: xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset)
341: {
342: return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
343: }
344:
345: static inline void
346: xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset,
347: uint32_t value)
348: {
349: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
350: }
351:
1.4 apb 352: #if 0 /* unused */
1.1 jakllsch 353: static inline uint64_t
354: xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset)
355: {
356: uint64_t value;
357:
358: if (sc->sc_ac64) {
359: #ifdef XHCI_USE_BUS_SPACE_8
360: value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset);
361: #else
362: value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
363: value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh,
364: offset + 4) << 32;
365: #endif
366: } else {
367: value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
368: }
369:
370: return value;
371: }
1.4 apb 372: #endif /* unused */
1.1 jakllsch 373:
374: static inline void
375: xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset,
376: uint64_t value)
377: {
378: if (sc->sc_ac64) {
379: #ifdef XHCI_USE_BUS_SPACE_8
380: bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value);
381: #else
382: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0,
383: (value >> 0) & 0xffffffff);
384: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4,
385: (value >> 32) & 0xffffffff);
386: #endif
387: } else {
388: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
389: }
390: }
391:
1.4 apb 392: #if 0 /* unused */
1.1 jakllsch 393: static inline uint32_t
394: xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset)
395: {
396: return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset);
397: }
1.4 apb 398: #endif /* unused */
1.1 jakllsch 399:
400: static inline void
401: xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset,
402: uint32_t value)
403: {
404: bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value);
405: }
406:
407: /* --- */
408:
409: static inline uint8_t
410: xhci_ep_get_type(usb_endpoint_descriptor_t * const ed)
411: {
1.34 skrll 412: u_int eptype = 0;
1.1 jakllsch 413:
414: switch (UE_GET_XFERTYPE(ed->bmAttributes)) {
415: case UE_CONTROL:
416: eptype = 0x0;
417: break;
418: case UE_ISOCHRONOUS:
419: eptype = 0x1;
420: break;
421: case UE_BULK:
422: eptype = 0x2;
423: break;
424: case UE_INTERRUPT:
425: eptype = 0x3;
426: break;
427: }
428:
429: if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
430: (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
431: return eptype | 0x4;
432: else
433: return eptype;
434: }
435:
436: static u_int
437: xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed)
438: {
439: /* xHCI 1.0 section 4.5.1 */
440: u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress);
441: u_int in = 0;
442:
443: if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
444: (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
445: in = 1;
446:
447: return epaddr * 2 + in;
448: }
449:
450: static inline u_int
451: xhci_dci_to_ici(const u_int i)
452: {
453: return i + 1;
454: }
455:
456: static inline void *
457: xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs,
458: const u_int dci)
459: {
460: return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
461: }
462:
1.4 apb 463: #if 0 /* unused */
1.1 jakllsch 464: static inline bus_addr_t
465: xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs,
466: const u_int dci)
467: {
468: return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
469: }
1.4 apb 470: #endif /* unused */
1.1 jakllsch 471:
472: static inline void *
473: xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs,
474: const u_int ici)
475: {
476: return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
477: }
478:
479: static inline bus_addr_t
480: xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs,
481: const u_int ici)
482: {
483: return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
484: }
485:
486: static inline struct xhci_trb *
487: xhci_ring_trbv(struct xhci_ring * const xr, u_int idx)
488: {
489: return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
490: }
491:
492: static inline bus_addr_t
493: xhci_ring_trbp(struct xhci_ring * const xr, u_int idx)
494: {
495: return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
496: }
497:
498: static inline void
499: xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
500: uint32_t control)
501: {
1.34 skrll 502: trb->trb_0 = htole64(parameter);
503: trb->trb_2 = htole32(status);
504: trb->trb_3 = htole32(control);
1.1 jakllsch 505: }
506:
1.40 skrll 507: static int
508: xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx)
509: {
510: /* base address of TRBs */
511: bus_addr_t trbp = xhci_ring_trbp(xr, 0);
512:
513: /* trb_0 range sanity check */
514: if (trb_0 == 0 || trb_0 < trbp ||
515: (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 ||
516: (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) {
517: return 1;
518: }
519: *idx = (trb_0 - trbp) / sizeof(struct xhci_trb);
520: return 0;
521: }
522:
1.63 skrll 523: static unsigned int
524: xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs,
525: u_int dci)
526: {
527: uint32_t *cp;
528:
529: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
530: cp = xhci_slot_get_dcv(sc, xs, dci);
531: return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0]));
532: }
533:
1.68 skrll 534: static inline unsigned int
535: xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport)
536: {
537: const unsigned int port = ctlrport - 1;
538: const uint8_t bit = __BIT(port % NBBY);
539:
540: return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit);
541: }
542:
543: /*
544: * Return the roothub port for a controller port. Both are 1..n.
545: */
546: static inline unsigned int
547: xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport)
548: {
549:
550: return sc->sc_ctlrportmap[ctrlport - 1];
551: }
552:
553: /*
554: * Return the controller port for a bus roothub port. Both are 1..n.
555: */
556: static inline unsigned int
557: xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn,
558: unsigned int rhport)
559: {
560:
561: return sc->sc_rhportmap[bn][rhport - 1];
562: }
563:
1.1 jakllsch 564: /* --- */
565:
566: void
567: xhci_childdet(device_t self, device_t child)
568: {
569: struct xhci_softc * const sc = device_private(self);
570:
571: KASSERT(sc->sc_child == child);
572: if (child == sc->sc_child)
573: sc->sc_child = NULL;
574: }
575:
576: int
577: xhci_detach(struct xhci_softc *sc, int flags)
578: {
579: int rv = 0;
580:
1.68 skrll 581: if (sc->sc_child2 != NULL) {
582: rv = config_detach(sc->sc_child2, flags);
583: if (rv != 0)
584: return rv;
585: }
586:
587: if (sc->sc_child != NULL) {
1.1 jakllsch 588: rv = config_detach(sc->sc_child, flags);
1.68 skrll 589: if (rv != 0)
590: return rv;
591: }
1.1 jakllsch 592:
593: /* XXX unconfigure/free slots */
594:
595: /* verify: */
596: xhci_rt_write_4(sc, XHCI_IMAN(0), 0);
597: xhci_op_write_4(sc, XHCI_USBCMD, 0);
598: /* do we need to wait for stop? */
599:
600: xhci_op_write_8(sc, XHCI_CRCR, 0);
601: xhci_ring_free(sc, &sc->sc_cr);
602: cv_destroy(&sc->sc_command_cv);
1.68 skrll 603: cv_destroy(&sc->sc_cmdbusy_cv);
1.1 jakllsch 604:
605: xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0);
606: xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0);
607: xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY);
608: xhci_ring_free(sc, &sc->sc_er);
609:
610: usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
611:
612: xhci_op_write_8(sc, XHCI_DCBAAP, 0);
613: usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
614:
615: kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots);
616:
1.70 skrll 617: kmem_free(sc->sc_ctlrportbus,
618: howmany(sc->sc_maxports * sizeof(uint8_t), NBBY));
1.68 skrll 619: kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int));
620:
621: for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
622: kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int));
623: }
624:
1.1 jakllsch 625: mutex_destroy(&sc->sc_lock);
626: mutex_destroy(&sc->sc_intr_lock);
627:
628: pool_cache_destroy(sc->sc_xferpool);
629:
630: return rv;
631: }
632:
633: int
634: xhci_activate(device_t self, enum devact act)
635: {
636: struct xhci_softc * const sc = device_private(self);
637:
638: switch (act) {
639: case DVACT_DEACTIVATE:
640: sc->sc_dying = true;
641: return 0;
642: default:
643: return EOPNOTSUPP;
644: }
645: }
646:
647: bool
648: xhci_suspend(device_t dv, const pmf_qual_t *qual)
649: {
650: return false;
651: }
652:
653: bool
654: xhci_resume(device_t dv, const pmf_qual_t *qual)
655: {
656: return false;
657: }
658:
659: bool
660: xhci_shutdown(device_t self, int flags)
661: {
662: return false;
663: }
664:
1.40 skrll 665: static int
666: xhci_hc_reset(struct xhci_softc * const sc)
667: {
668: uint32_t usbcmd, usbsts;
669: int i;
670:
671: /* Check controller not ready */
1.42 skrll 672: for (i = 0; i < XHCI_WAIT_CNR; i++) {
1.40 skrll 673: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
674: if ((usbsts & XHCI_STS_CNR) == 0)
675: break;
676: usb_delay_ms(&sc->sc_bus, 1);
677: }
1.42 skrll 678: if (i >= XHCI_WAIT_CNR) {
1.40 skrll 679: aprint_error_dev(sc->sc_dev, "controller not ready timeout\n");
680: return EIO;
681: }
682:
683: /* Halt controller */
684: usbcmd = 0;
685: xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
686: usb_delay_ms(&sc->sc_bus, 1);
687:
688: /* Reset controller */
689: usbcmd = XHCI_CMD_HCRST;
690: xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
1.42 skrll 691: for (i = 0; i < XHCI_WAIT_HCRST; i++) {
1.72.2.3 snj 692: /*
693: * Wait 1ms first. Existing Intel xHCI requies 1ms delay to
694: * prevent system hang (Errata).
695: */
696: usb_delay_ms(&sc->sc_bus, 1);
1.40 skrll 697: usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
698: if ((usbcmd & XHCI_CMD_HCRST) == 0)
699: break;
700: }
1.42 skrll 701: if (i >= XHCI_WAIT_HCRST) {
1.40 skrll 702: aprint_error_dev(sc->sc_dev, "host controller reset timeout\n");
703: return EIO;
704: }
705:
706: /* Check controller not ready */
1.42 skrll 707: for (i = 0; i < XHCI_WAIT_CNR; i++) {
1.40 skrll 708: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
709: if ((usbsts & XHCI_STS_CNR) == 0)
710: break;
711: usb_delay_ms(&sc->sc_bus, 1);
712: }
1.42 skrll 713: if (i >= XHCI_WAIT_CNR) {
1.40 skrll 714: aprint_error_dev(sc->sc_dev,
715: "controller not ready timeout after reset\n");
716: return EIO;
717: }
718:
719: return 0;
720: }
721:
1.1 jakllsch 722:
723: static void
724: hexdump(const char *msg, const void *base, size_t len)
725: {
726: #if 0
727: size_t cnt;
728: const uint32_t *p;
729: extern paddr_t vtophys(vaddr_t);
730:
731: p = base;
732: cnt = 0;
733:
734: printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base,
735: (void *)vtophys((vaddr_t)base));
736:
737: while (cnt < len) {
738: if (cnt % 16 == 0)
739: printf("%p: ", p);
740: else if (cnt % 8 == 0)
741: printf(" |");
742: printf(" %08x", *p++);
743: cnt += 4;
744: if (cnt % 16 == 0)
745: printf("\n");
746: }
1.44 skrll 747: if (cnt % 16 != 0)
748: printf("\n");
1.1 jakllsch 749: #endif
750: }
751:
1.68 skrll 752: /* 7.2 xHCI Support Protocol Capability */
753: static void
754: xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp)
755: {
756: /* XXX Cache this lot */
757:
758: const uint32_t w0 = xhci_read_4(sc, ecp);
759: const uint32_t w4 = xhci_read_4(sc, ecp + 4);
760: const uint32_t w8 = xhci_read_4(sc, ecp + 8);
761: const uint32_t wc = xhci_read_4(sc, ecp + 0xc);
762:
763: aprint_debug_dev(sc->sc_dev,
764: " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc);
765:
766: if (w4 != XHCI_XECP_USBID)
767: return;
768:
769: const int major = XHCI_XECP_SP_W0_MAJOR(w0);
770: const int minor = XHCI_XECP_SP_W0_MINOR(w0);
771: const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8);
772: const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8);
773:
774: const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16));
775: switch (mm) {
776: case 0x0200:
777: case 0x0300:
778: case 0x0301:
779: aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n",
780: major == 3 ? "ss" : "hs", cpo, cpo + cpc -1);
781: break;
782: default:
783: aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n",
784: major, minor);
785: return;
786: }
787:
788: const size_t bus = (major == 3) ? 0 : 1;
789:
790: /* Index arrays with 0..n-1 where ports are numbered 1..n */
791: for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) {
792: if (sc->sc_ctlrportmap[cp] != 0) {
793: aprint_error_dev(sc->sc_dev, "contoller port %zu "
794: "already assigned", cp);
795: continue;
796: }
797:
798: sc->sc_ctlrportbus[cp / NBBY] |=
799: bus == 0 ? 0 : __BIT(cp % NBBY);
800:
801: const size_t rhp = sc->sc_rhportcount[bus]++;
802:
803: KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0,
804: "bus %zu rhp %zu is %d", bus, rhp,
805: sc->sc_rhportmap[bus][rhp]);
806:
807: sc->sc_rhportmap[bus][rhp] = cp + 1;
808: sc->sc_ctlrportmap[cp] = rhp + 1;
809: }
810: }
811:
1.40 skrll 812: /* Process extended capabilities */
813: static void
814: xhci_ecp(struct xhci_softc *sc, uint32_t hcc)
815: {
816: XHCIHIST_FUNC(); XHCIHIST_CALLED();
817:
1.68 skrll 818: bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4;
1.40 skrll 819: while (ecp != 0) {
1.68 skrll 820: uint32_t ecr = xhci_read_4(sc, ecp);
1.69 skrll 821: aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr);
1.40 skrll 822: switch (XHCI_XECP_ID(ecr)) {
823: case XHCI_ID_PROTOCOLS: {
1.68 skrll 824: xhci_id_protocols(sc, ecp);
1.40 skrll 825: break;
826: }
827: case XHCI_ID_USB_LEGACY: {
828: uint8_t bios_sem;
829:
830: /* Take host controller ownership from BIOS */
831: bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM);
832: if (bios_sem) {
833: /* sets xHCI to be owned by OS */
834: xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1);
835: aprint_debug_dev(sc->sc_dev,
836: "waiting for BIOS to give up control\n");
837: for (int i = 0; i < 5000; i++) {
838: bios_sem = xhci_read_1(sc, ecp +
839: XHCI_XECP_BIOS_SEM);
840: if (bios_sem == 0)
841: break;
842: DELAY(1000);
843: }
844: if (bios_sem) {
845: aprint_error_dev(sc->sc_dev,
846: "timed out waiting for BIOS\n");
847: }
848: }
849: break;
850: }
851: default:
852: break;
853: }
854: ecr = xhci_read_4(sc, ecp);
855: if (XHCI_XECP_NEXT(ecr) == 0) {
856: ecp = 0;
857: } else {
858: ecp += XHCI_XECP_NEXT(ecr) * 4;
859: }
860: }
861: }
862:
1.34 skrll 863: #define XHCI_HCCPREV1_BITS \
864: "\177\020" /* New bitmask */ \
865: "f\020\020XECP\0" \
866: "f\014\4MAXPSA\0" \
867: "b\013CFC\0" \
868: "b\012SEC\0" \
869: "b\011SBD\0" \
870: "b\010FSE\0" \
871: "b\7NSS\0" \
872: "b\6LTC\0" \
873: "b\5LHRC\0" \
874: "b\4PIND\0" \
875: "b\3PPC\0" \
876: "b\2CZC\0" \
877: "b\1BNC\0" \
878: "b\0AC64\0" \
879: "\0"
880: #define XHCI_HCCV1_x_BITS \
881: "\177\020" /* New bitmask */ \
882: "f\020\020XECP\0" \
883: "f\014\4MAXPSA\0" \
884: "b\013CFC\0" \
885: "b\012SEC\0" \
886: "b\011SPC\0" \
887: "b\010PAE\0" \
888: "b\7NSS\0" \
889: "b\6LTC\0" \
890: "b\5LHRC\0" \
891: "b\4PIND\0" \
892: "b\3PPC\0" \
893: "b\2CSZ\0" \
894: "b\1BNC\0" \
895: "b\0AC64\0" \
896: "\0"
1.1 jakllsch 897:
1.15 skrll 898: int
1.1 jakllsch 899: xhci_init(struct xhci_softc *sc)
900: {
901: bus_size_t bsz;
1.34 skrll 902: uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff;
1.40 skrll 903: uint32_t pagesize, config;
904: int i = 0;
1.1 jakllsch 905: uint16_t hciversion;
906: uint8_t caplength;
907:
1.27 skrll 908: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 909:
1.68 skrll 910: /* Set up the bus struct for the usb 3 and usb 2 buses */
911: sc->sc_bus.ub_methods = &xhci_bus_methods;
912: sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe);
1.34 skrll 913: sc->sc_bus.ub_revision = USBREV_3_0;
914: sc->sc_bus.ub_usedma = true;
1.68 skrll 915: sc->sc_bus.ub_hcpriv = sc;
916:
917: sc->sc_bus2.ub_methods = &xhci_bus_methods;
918: sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe);
919: sc->sc_bus2.ub_revision = USBREV_2_0;
920: sc->sc_bus2.ub_usedma = true;
921: sc->sc_bus2.ub_hcpriv = sc;
922: sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag;
1.1 jakllsch 923:
924: cap = xhci_read_4(sc, XHCI_CAPLENGTH);
925: caplength = XHCI_CAP_CAPLENGTH(cap);
926: hciversion = XHCI_CAP_HCIVERSION(cap);
927:
1.34 skrll 928: if (hciversion < XHCI_HCIVERSION_0_96 ||
929: hciversion > XHCI_HCIVERSION_1_0) {
1.1 jakllsch 930: aprint_normal_dev(sc->sc_dev,
931: "xHCI version %x.%x not known to be supported\n",
932: (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
933: } else {
934: aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n",
935: (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
936: }
937:
938: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength,
939: &sc->sc_cbh) != 0) {
940: aprint_error_dev(sc->sc_dev, "capability subregion failure\n");
1.15 skrll 941: return ENOMEM;
1.1 jakllsch 942: }
943:
944: hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1);
945: sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1);
946: sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1);
947: sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1);
948: hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2);
1.34 skrll 949: hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3);
950: aprint_debug_dev(sc->sc_dev,
951: "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3);
952:
1.1 jakllsch 953: hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS);
954: sc->sc_ac64 = XHCI_HCC_AC64(hcc);
955: sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32;
956:
1.34 skrll 957: char sbuf[128];
958: if (hciversion < XHCI_HCIVERSION_1_0)
959: snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc);
960: else
961: snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc);
962: aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf);
1.12 jakllsch 963: aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4);
1.34 skrll 964:
1.68 skrll 965: /* default all ports to bus 0, i.e. usb 3 */
1.70 skrll 966: sc->sc_ctlrportbus = kmem_zalloc(
967: howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP);
1.68 skrll 968: sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
969:
970: /* controller port to bus roothub port map */
971: for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) {
972: sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP);
973: }
974:
975: /*
976: * Process all Extended Capabilities
977: */
1.40 skrll 978: xhci_ecp(sc, hcc);
1.1 jakllsch 979:
1.68 skrll 980: bsz = XHCI_PORTSC(sc->sc_maxports);
1.1 jakllsch 981: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz,
982: &sc->sc_obh) != 0) {
983: aprint_error_dev(sc->sc_dev, "operational subregion failure\n");
1.15 skrll 984: return ENOMEM;
1.1 jakllsch 985: }
986:
987: dboff = xhci_cap_read_4(sc, XHCI_DBOFF);
988: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff,
989: sc->sc_maxslots * 4, &sc->sc_dbh) != 0) {
990: aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n");
1.15 skrll 991: return ENOMEM;
1.1 jakllsch 992: }
993:
994: rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF);
995: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff,
996: sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) {
997: aprint_error_dev(sc->sc_dev, "runtime subregion failure\n");
1.15 skrll 998: return ENOMEM;
1.1 jakllsch 999: }
1000:
1.40 skrll 1001: int rv;
1002: rv = xhci_hc_reset(sc);
1003: if (rv != 0) {
1004: return rv;
1.37 skrll 1005: }
1.1 jakllsch 1006:
1.34 skrll 1007: if (sc->sc_vendor_init)
1008: sc->sc_vendor_init(sc);
1009:
1.1 jakllsch 1010: pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE);
1.12 jakllsch 1011: aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize);
1.1 jakllsch 1012: pagesize = ffs(pagesize);
1.37 skrll 1013: if (pagesize == 0) {
1014: aprint_error_dev(sc->sc_dev, "pagesize is 0\n");
1.15 skrll 1015: return EIO;
1.37 skrll 1016: }
1.1 jakllsch 1017: sc->sc_pgsz = 1 << (12 + (pagesize - 1));
1.12 jakllsch 1018: aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz);
1019: aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n",
1.1 jakllsch 1020: (uint32_t)sc->sc_maxslots);
1.34 skrll 1021: aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports);
1.1 jakllsch 1022:
1.5 matt 1023: usbd_status err;
1024:
1025: sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2);
1.12 jakllsch 1026: aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf);
1.5 matt 1027: if (sc->sc_maxspbuf != 0) {
1028: err = usb_allocmem(&sc->sc_bus,
1029: sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t),
1030: &sc->sc_spbufarray_dma);
1.37 skrll 1031: if (err) {
1032: aprint_error_dev(sc->sc_dev,
1033: "spbufarray init fail, err %d\n", err);
1034: return ENOMEM;
1035: }
1.30 skrll 1036:
1.36 skrll 1037: sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) *
1038: sc->sc_maxspbuf, KM_SLEEP);
1.5 matt 1039: uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0);
1040: for (i = 0; i < sc->sc_maxspbuf; i++) {
1041: usb_dma_t * const dma = &sc->sc_spbuf_dma[i];
1042: /* allocate contexts */
1043: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz,
1044: sc->sc_pgsz, dma);
1.37 skrll 1045: if (err) {
1046: aprint_error_dev(sc->sc_dev,
1047: "spbufarray_dma init fail, err %d\n", err);
1048: rv = ENOMEM;
1049: goto bad1;
1050: }
1.5 matt 1051: spbufarray[i] = htole64(DMAADDR(dma, 0));
1052: usb_syncmem(dma, 0, sc->sc_pgsz,
1053: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1054: }
1055:
1.30 skrll 1056: usb_syncmem(&sc->sc_spbufarray_dma, 0,
1.5 matt 1057: sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE);
1058: }
1059:
1.1 jakllsch 1060: config = xhci_op_read_4(sc, XHCI_CONFIG);
1061: config &= ~0xFF;
1062: config |= sc->sc_maxslots & 0xFF;
1063: xhci_op_write_4(sc, XHCI_CONFIG, config);
1064:
1065: err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS,
1066: XHCI_COMMAND_RING_SEGMENTS_ALIGN);
1067: if (err) {
1.37 skrll 1068: aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n",
1069: err);
1070: rv = ENOMEM;
1071: goto bad1;
1.1 jakllsch 1072: }
1073:
1074: err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS,
1075: XHCI_EVENT_RING_SEGMENTS_ALIGN);
1076: if (err) {
1.37 skrll 1077: aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n",
1078: err);
1079: rv = ENOMEM;
1080: goto bad2;
1.1 jakllsch 1081: }
1082:
1.16 skrll 1083: usb_dma_t *dma;
1084: size_t size;
1085: size_t align;
1086:
1087: dma = &sc->sc_eventst_dma;
1088: size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE,
1089: XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN);
1.37 skrll 1090: KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size);
1.16 skrll 1091: align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN;
1092: err = usb_allocmem(&sc->sc_bus, size, align, dma);
1.37 skrll 1093: if (err) {
1094: aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n",
1095: err);
1096: rv = ENOMEM;
1097: goto bad3;
1098: }
1.16 skrll 1099:
1100: memset(KERNADDR(dma, 0), 0, size);
1101: usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
1.37 skrll 1102: aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n",
1.16 skrll 1103: (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0),
1104: KERNADDR(&sc->sc_eventst_dma, 0),
1.34 skrll 1105: sc->sc_eventst_dma.udma_block->size);
1.16 skrll 1106:
1107: dma = &sc->sc_dcbaa_dma;
1108: size = (1 + sc->sc_maxslots) * sizeof(uint64_t);
1.37 skrll 1109: KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size);
1.16 skrll 1110: align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN;
1111: err = usb_allocmem(&sc->sc_bus, size, align, dma);
1.37 skrll 1112: if (err) {
1113: aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err);
1114: rv = ENOMEM;
1115: goto bad4;
1116: }
1117: aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n",
1118: (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0),
1119: KERNADDR(&sc->sc_dcbaa_dma, 0),
1120: sc->sc_dcbaa_dma.udma_block->size);
1.16 skrll 1121:
1122: memset(KERNADDR(dma, 0), 0, size);
1123: if (sc->sc_maxspbuf != 0) {
1124: /*
1125: * DCBA entry 0 hold the scratchbuf array pointer.
1126: */
1127: *(uint64_t *)KERNADDR(dma, 0) =
1128: htole64(DMAADDR(&sc->sc_spbufarray_dma, 0));
1.1 jakllsch 1129: }
1.16 skrll 1130: usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 1131:
1132: sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots,
1133: KM_SLEEP);
1.37 skrll 1134: if (sc->sc_slots == NULL) {
1135: aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err);
1136: rv = ENOMEM;
1137: goto bad;
1138: }
1139:
1140: sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0,
1141: "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
1142: if (sc->sc_xferpool == NULL) {
1143: aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n",
1144: err);
1145: rv = ENOMEM;
1146: goto bad;
1147: }
1.1 jakllsch 1148:
1149: cv_init(&sc->sc_command_cv, "xhcicmd");
1.68 skrll 1150: cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq");
1.34 skrll 1151: mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1152: mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
1153:
1.1 jakllsch 1154: struct xhci_erste *erst;
1155: erst = KERNADDR(&sc->sc_eventst_dma, 0);
1156: erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0));
1.52 skrll 1157: erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb);
1.1 jakllsch 1158: erst[0].erste_3 = htole32(0);
1159: usb_syncmem(&sc->sc_eventst_dma, 0,
1160: XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE);
1161:
1162: xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS);
1163: xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0));
1164: xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) |
1165: XHCI_ERDP_LO_BUSY);
1166: xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0));
1167: xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) |
1168: sc->sc_cr.xr_cs);
1169:
1170: #if 0
1171: hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0),
1172: XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS);
1173: #endif
1174:
1175: xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA);
1.34 skrll 1176: if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0)
1177: /* Intel xhci needs interrupt rate moderated. */
1178: xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP);
1179: else
1180: xhci_rt_write_4(sc, XHCI_IMOD(0), 0);
1.53 skrll 1181: aprint_debug_dev(sc->sc_dev, "current IMOD %u\n",
1.34 skrll 1182: xhci_rt_read_4(sc, XHCI_IMOD(0)));
1.1 jakllsch 1183:
1184: xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */
1.12 jakllsch 1185: aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n",
1.1 jakllsch 1186: xhci_op_read_4(sc, XHCI_USBCMD));
1187:
1.37 skrll 1188: return 0;
1189:
1190: bad:
1191: if (sc->sc_xferpool) {
1192: pool_cache_destroy(sc->sc_xferpool);
1193: sc->sc_xferpool = NULL;
1194: }
1195:
1196: if (sc->sc_slots) {
1197: kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) *
1198: sc->sc_maxslots);
1199: sc->sc_slots = NULL;
1200: }
1201:
1202: usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
1203: bad4:
1204: usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
1205: bad3:
1206: xhci_ring_free(sc, &sc->sc_er);
1207: bad2:
1208: xhci_ring_free(sc, &sc->sc_cr);
1209: i = sc->sc_maxspbuf;
1210: bad1:
1211: for (int j = 0; j < i; j++)
1212: usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]);
1213: usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma);
1214:
1215: return rv;
1.1 jakllsch 1216: }
1217:
1.72.2.1 snj 1218: static inline bool
1219: xhci_polling_p(struct xhci_softc * const sc)
1220: {
1221: return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling;
1222: }
1223:
1.1 jakllsch 1224: int
1225: xhci_intr(void *v)
1226: {
1227: struct xhci_softc * const sc = v;
1.25 skrll 1228: int ret = 0;
1.1 jakllsch 1229:
1.27 skrll 1230: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1231:
1.25 skrll 1232: if (sc == NULL)
1.1 jakllsch 1233: return 0;
1234:
1.25 skrll 1235: mutex_spin_enter(&sc->sc_intr_lock);
1236:
1237: if (sc->sc_dying || !device_has_power(sc->sc_dev))
1238: goto done;
1239:
1.1 jakllsch 1240: /* If we get an interrupt while polling, then just ignore it. */
1.72.2.1 snj 1241: if (xhci_polling_p(sc)) {
1.1 jakllsch 1242: #ifdef DIAGNOSTIC
1.27 skrll 1243: DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1.1 jakllsch 1244: #endif
1.25 skrll 1245: goto done;
1.1 jakllsch 1246: }
1247:
1.25 skrll 1248: ret = xhci_intr1(sc);
1.72.2.1 snj 1249: if (ret) {
1250: usb_schedsoftintr(&sc->sc_bus);
1251: }
1.25 skrll 1252: done:
1253: mutex_spin_exit(&sc->sc_intr_lock);
1254: return ret;
1.1 jakllsch 1255: }
1256:
1257: int
1258: xhci_intr1(struct xhci_softc * const sc)
1259: {
1260: uint32_t usbsts;
1261: uint32_t iman;
1262:
1.27 skrll 1263: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1264:
1.1 jakllsch 1265: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.72.2.2 snj 1266: DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0);
1.1 jakllsch 1267: #if 0
1268: if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) {
1269: return 0;
1270: }
1271: #endif
1272: xhci_op_write_4(sc, XHCI_USBSTS,
1273: usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */
1274: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.72.2.2 snj 1275: DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0);
1.1 jakllsch 1276:
1277: iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1.72.2.2 snj 1278: DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0);
1.34 skrll 1279: iman |= XHCI_IMAN_INTR_PEND;
1.1 jakllsch 1280: xhci_rt_write_4(sc, XHCI_IMAN(0), iman);
1281: iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1.72.2.2 snj 1282: DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0);
1.1 jakllsch 1283: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.72.2.2 snj 1284: DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0);
1.1 jakllsch 1285:
1286: return 1;
1287: }
1288:
1.34 skrll 1289: /*
1290: * 3 port speed types used in USB stack
1291: *
1292: * usbdi speed
1293: * definition: USB_SPEED_* in usb.h
1294: * They are used in struct usbd_device in USB stack.
1295: * ioctl interface uses these values too.
1296: * port_status speed
1297: * definition: UPS_*_SPEED in usb.h
1298: * They are used in usb_port_status_t and valid only for USB 2.0.
1299: * Speed value is always 0 for Super Speed or more, and dwExtPortStatus
1300: * of usb_port_status_ext_t indicates port speed.
1301: * Note that some 3.0 values overlap with 2.0 values.
1302: * (e.g. 0x200 means UPS_POER_POWER_SS in SS and
1303: * means UPS_LOW_SPEED in HS.)
1304: * port status returned from hub also uses these values.
1305: * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed
1306: * or more.
1307: * xspeed:
1308: * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1)
1309: * They are used in only slot context and PORTSC reg of xhci.
1310: * The difference between usbdi speed and xspeed is
1311: * that FS and LS values are swapped.
1312: */
1313:
1314: /* convert usbdi speed to xspeed */
1315: static int
1316: xhci_speed2xspeed(int speed)
1317: {
1318: switch (speed) {
1319: case USB_SPEED_LOW: return 2;
1320: case USB_SPEED_FULL: return 1;
1321: default: return speed;
1322: }
1323: }
1324:
1325: #if 0
1326: /* convert xspeed to usbdi speed */
1327: static int
1328: xhci_xspeed2speed(int xspeed)
1329: {
1330: switch (xspeed) {
1331: case 1: return USB_SPEED_FULL;
1332: case 2: return USB_SPEED_LOW;
1333: default: return xspeed;
1334: }
1335: }
1336: #endif
1337:
1338: /* convert xspeed to port status speed */
1339: static int
1340: xhci_xspeed2psspeed(int xspeed)
1341: {
1342: switch (xspeed) {
1343: case 0: return 0;
1344: case 1: return UPS_FULL_SPEED;
1345: case 2: return UPS_LOW_SPEED;
1346: case 3: return UPS_HIGH_SPEED;
1347: default: return UPS_OTHER_SPEED;
1348: }
1349: }
1350:
1351: /*
1.54 skrll 1352: * Construct input contexts and issue TRB to open pipe.
1.34 skrll 1353: */
1.1 jakllsch 1354: static usbd_status
1.34 skrll 1355: xhci_configure_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1356: {
1.34 skrll 1357: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1358: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1359: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1360: struct xhci_trb trb;
1361: usbd_status err;
1362:
1.27 skrll 1363: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1364: DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx",
1.34 skrll 1365: xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress,
1366: pipe->up_endpoint->ue_edesc->bmAttributes);
1.1 jakllsch 1367:
1368: /* XXX ensure input context is available? */
1369:
1370: memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz);
1371:
1.51 skrll 1372: /* set up context */
1373: xhci_setup_ctx(pipe);
1.1 jakllsch 1374:
1375: hexdump("input control context", xhci_slot_get_icv(sc, xs, 0),
1376: sc->sc_ctxsz * 1);
1377: hexdump("input endpoint context", xhci_slot_get_icv(sc, xs,
1378: xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1);
1379:
1380: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1381: trb.trb_2 = 0;
1382: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1383: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1384:
1385: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1386:
1387: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1388: hexdump("output context", xhci_slot_get_dcv(sc, xs, dci),
1389: sc->sc_ctxsz * 1);
1390:
1391: return err;
1392: }
1393:
1.34 skrll 1394: #if 0
1.1 jakllsch 1395: static usbd_status
1.34 skrll 1396: xhci_unconfigure_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1397: {
1.27 skrll 1398: #ifdef USB_DEBUG
1.34 skrll 1399: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1.27 skrll 1400: #endif
1401:
1402: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1403: DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0);
1.27 skrll 1404:
1.1 jakllsch 1405: return USBD_NORMAL_COMPLETION;
1406: }
1.34 skrll 1407: #endif
1.1 jakllsch 1408:
1.34 skrll 1409: /* 4.6.8, 6.4.3.7 */
1.1 jakllsch 1410: static usbd_status
1.63 skrll 1411: xhci_reset_endpoint_locked(struct usbd_pipe *pipe)
1.1 jakllsch 1412: {
1.34 skrll 1413: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1414: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1415: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1416: struct xhci_trb trb;
1417: usbd_status err;
1418:
1.27 skrll 1419: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1420: DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1.34 skrll 1421:
1.63 skrll 1422: KASSERT(mutex_owned(&sc->sc_lock));
1423:
1.1 jakllsch 1424: trb.trb_0 = 0;
1425: trb.trb_2 = 0;
1426: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1427: XHCI_TRB_3_EP_SET(dci) |
1428: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP);
1429:
1.63 skrll 1430: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.1 jakllsch 1431:
1432: return err;
1433: }
1434:
1.63 skrll 1435: static usbd_status
1436: xhci_reset_endpoint(struct usbd_pipe *pipe)
1437: {
1438: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1439:
1440: mutex_enter(&sc->sc_lock);
1441: usbd_status ret = xhci_reset_endpoint_locked(pipe);
1442: mutex_exit(&sc->sc_lock);
1443:
1444: return ret;
1445: }
1446:
1.34 skrll 1447: /*
1448: * 4.6.9, 6.4.3.8
1449: * Stop execution of TDs on xfer ring.
1450: * Should be called with sc_lock held.
1451: */
1.1 jakllsch 1452: static usbd_status
1.34 skrll 1453: xhci_stop_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1454: {
1.34 skrll 1455: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1456: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1.1 jakllsch 1457: struct xhci_trb trb;
1458: usbd_status err;
1.34 skrll 1459: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1460:
1.27 skrll 1461: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1462: DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1.34 skrll 1463:
1464: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1465:
1466: trb.trb_0 = 0;
1467: trb.trb_2 = 0;
1468: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1469: XHCI_TRB_3_EP_SET(dci) |
1470: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP);
1471:
1.34 skrll 1472: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.1 jakllsch 1473:
1474: return err;
1475: }
1476:
1.34 skrll 1477: /*
1478: * Set TR Dequeue Pointer.
1.54 skrll 1479: * xHCI 1.1 4.6.10 6.4.3.9
1480: * Purge all of the TRBs on ring and reinitialize ring.
1481: * Set TR dequeue Pointr to 0 and Cycle State to 1.
1482: * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE
1483: * error will be generated.
1.34 skrll 1484: */
1.1 jakllsch 1485: static usbd_status
1.63 skrll 1486: xhci_set_dequeue_locked(struct usbd_pipe *pipe)
1.1 jakllsch 1487: {
1.34 skrll 1488: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1489: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1490: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1491: struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr;
1492: struct xhci_trb trb;
1493: usbd_status err;
1494:
1.27 skrll 1495: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1496: DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1.1 jakllsch 1497:
1.63 skrll 1498: KASSERT(mutex_owned(&sc->sc_lock));
1499:
1.56 skrll 1500: xhci_host_dequeue(xr);
1.1 jakllsch 1501:
1.34 skrll 1502: /* set DCS */
1.1 jakllsch 1503: trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */
1504: trb.trb_2 = 0;
1505: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1506: XHCI_TRB_3_EP_SET(dci) |
1507: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE);
1508:
1.63 skrll 1509: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.1 jakllsch 1510:
1511: return err;
1512: }
1513:
1.63 skrll 1514: static usbd_status
1515: xhci_set_dequeue(struct usbd_pipe *pipe)
1516: {
1517: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1518:
1519: mutex_enter(&sc->sc_lock);
1520: usbd_status ret = xhci_set_dequeue_locked(pipe);
1521: mutex_exit(&sc->sc_lock);
1522:
1523: return ret;
1524: }
1525:
1.34 skrll 1526: /*
1527: * Open new pipe: called from usbd_setup_pipe_flags.
1528: * Fills methods of pipe.
1529: * If pipe is not for ep0, calls configure_endpoint.
1530: */
1.1 jakllsch 1531: static usbd_status
1.34 skrll 1532: xhci_open(struct usbd_pipe *pipe)
1.1 jakllsch 1533: {
1.34 skrll 1534: struct usbd_device * const dev = pipe->up_dev;
1535: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
1536: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1.1 jakllsch 1537: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1538:
1.27 skrll 1539: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1540: DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr,
1.53 skrll 1541: dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed);
1.72.2.2 snj 1542: DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx",
1.53 skrll 1543: xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress,
1544: ed->bmAttributes);
1.72.2.2 snj 1545: DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize),
1546: ed->bInterval, 0, 0);
1.1 jakllsch 1547:
1548: if (sc->sc_dying)
1549: return USBD_IOERROR;
1550:
1551: /* Root Hub */
1.34 skrll 1552: if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) {
1.1 jakllsch 1553: switch (ed->bEndpointAddress) {
1554: case USB_CONTROL_ENDPOINT:
1.34 skrll 1555: pipe->up_methods = &roothub_ctrl_methods;
1.1 jakllsch 1556: break;
1.34 skrll 1557: case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
1558: pipe->up_methods = &xhci_root_intr_methods;
1.1 jakllsch 1559: break;
1560: default:
1.34 skrll 1561: pipe->up_methods = NULL;
1.72.2.2 snj 1562: DPRINTFN(0, "bad bEndpointAddress 0x%02jx",
1.27 skrll 1563: ed->bEndpointAddress, 0, 0, 0);
1.1 jakllsch 1564: return USBD_INVAL;
1565: }
1566: return USBD_NORMAL_COMPLETION;
1567: }
1568:
1569: switch (xfertype) {
1570: case UE_CONTROL:
1.34 skrll 1571: pipe->up_methods = &xhci_device_ctrl_methods;
1.1 jakllsch 1572: break;
1573: case UE_ISOCHRONOUS:
1.34 skrll 1574: pipe->up_methods = &xhci_device_isoc_methods;
1.1 jakllsch 1575: return USBD_INVAL;
1576: break;
1577: case UE_BULK:
1.34 skrll 1578: pipe->up_methods = &xhci_device_bulk_methods;
1.1 jakllsch 1579: break;
1580: case UE_INTERRUPT:
1.34 skrll 1581: pipe->up_methods = &xhci_device_intr_methods;
1.1 jakllsch 1582: break;
1583: default:
1584: return USBD_IOERROR;
1585: break;
1586: }
1587:
1588: if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT)
1.34 skrll 1589: return xhci_configure_endpoint(pipe);
1.1 jakllsch 1590:
1591: return USBD_NORMAL_COMPLETION;
1592: }
1593:
1.34 skrll 1594: /*
1595: * Closes pipe, called from usbd_kill_pipe via close methods.
1596: * If the endpoint to be closed is ep0, disable_slot.
1597: * Should be called with sc_lock held.
1598: */
1.1 jakllsch 1599: static void
1.34 skrll 1600: xhci_close_pipe(struct usbd_pipe *pipe)
1.1 jakllsch 1601: {
1.34 skrll 1602: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1603: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1604: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1605: const u_int dci = xhci_ep_get_dci(ed);
1606: struct xhci_trb trb;
1607: uint32_t *cp;
1.1 jakllsch 1608:
1.27 skrll 1609: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 1610:
1.34 skrll 1611: if (sc->sc_dying)
1.1 jakllsch 1612: return;
1613:
1.41 skrll 1614: /* xs is uninitialized before xhci_init_slot */
1.34 skrll 1615: if (xs == NULL || xs->xs_idx == 0)
1.1 jakllsch 1616: return;
1617:
1.72.2.2 snj 1618: DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx,
1619: dci, 0);
1.1 jakllsch 1620:
1.34 skrll 1621: KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx");
1622: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1623:
1.34 skrll 1624: if (pipe->up_dev->ud_depth == 0)
1625: return;
1.1 jakllsch 1626:
1.34 skrll 1627: if (dci == XHCI_DCI_EP_CONTROL) {
1628: DPRINTFN(4, "closing ep0", 0, 0, 0, 0);
1629: xhci_disable_slot(sc, xs->xs_idx);
1630: return;
1631: }
1.1 jakllsch 1632:
1.66 skrll 1633: if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED)
1634: (void)xhci_stop_endpoint(pipe);
1.1 jakllsch 1635:
1.34 skrll 1636: /*
1637: * set appropriate bit to be dropped.
1638: * don't set DC bit to 1, otherwise all endpoints
1639: * would be deconfigured.
1640: */
1641: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
1642: cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci));
1643: cp[1] = htole32(0);
1.1 jakllsch 1644:
1.34 skrll 1645: /* XXX should be most significant one, not dci? */
1646: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1647: cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci));
1.1 jakllsch 1648:
1.55 skrll 1649: /* configure ep context performs an implicit dequeue */
1650: xhci_host_dequeue(&xs->xs_ep[dci].xe_tr);
1651:
1.34 skrll 1652: /* sync input contexts before they are read from memory */
1653: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 1654:
1.34 skrll 1655: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1656: trb.trb_2 = 0;
1657: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1658: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1.1 jakllsch 1659:
1.34 skrll 1660: (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1661: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1662: }
1.1 jakllsch 1663:
1.34 skrll 1664: /*
1665: * Abort transfer.
1.63 skrll 1666: * Should be called with sc_lock held.
1.34 skrll 1667: */
1668: static void
1669: xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
1670: {
1671: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.63 skrll 1672: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
1673: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1674:
1.34 skrll 1675: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1676: DPRINTFN(4, "xfer %#jx pipe %#jx status %jd",
1677: (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0);
1.1 jakllsch 1678:
1.34 skrll 1679: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1680:
1.34 skrll 1681: if (sc->sc_dying) {
1682: /* If we're dying, just do the software part. */
1.72.2.2 snj 1683: DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer,
1684: xfer->ux_status, 0, 0);
1.54 skrll 1685: xfer->ux_status = status;
1.34 skrll 1686: callout_stop(&xfer->ux_callout);
1687: usb_transfer_complete(xfer);
1688: return;
1.1 jakllsch 1689: }
1.34 skrll 1690:
1.63 skrll 1691: /*
1692: * If an abort is already in progress then just wait for it to
1693: * complete and return.
1694: */
1695: if (xfer->ux_hcflags & UXFER_ABORTING) {
1696: DPRINTFN(4, "already aborting", 0, 0, 0, 0);
1697: #ifdef DIAGNOSTIC
1698: if (status == USBD_TIMEOUT)
1699: DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0);
1700: #endif
1701: /* Override the status which might be USBD_TIMEOUT. */
1702: xfer->ux_status = status;
1.72.2.2 snj 1703: DPRINTFN(4, "xfer %#jx waiting for abort to finish",
1704: (uintptr_t)xfer, 0, 0, 0);
1.63 skrll 1705: xfer->ux_hcflags |= UXFER_ABORTWAIT;
1706: while (xfer->ux_hcflags & UXFER_ABORTING)
1707: cv_wait(&xfer->ux_hccv, &sc->sc_lock);
1708: return;
1709: }
1710: xfer->ux_hcflags |= UXFER_ABORTING;
1711:
1712: /*
1713: * Step 1: Stop xfer timeout timer.
1714: */
1.34 skrll 1715: xfer->ux_status = status;
1716: callout_stop(&xfer->ux_callout);
1.63 skrll 1717:
1718: /*
1719: * Step 2: Stop execution of TD on the ring.
1720: */
1721: switch (xhci_get_epstate(sc, xs, dci)) {
1722: case XHCI_EPSTATE_HALTED:
1723: (void)xhci_reset_endpoint_locked(xfer->ux_pipe);
1724: break;
1725: case XHCI_EPSTATE_STOPPED:
1726: break;
1727: default:
1728: (void)xhci_stop_endpoint(xfer->ux_pipe);
1729: break;
1730: }
1731: #ifdef DIAGNOSTIC
1732: uint32_t epst = xhci_get_epstate(sc, xs, dci);
1733: if (epst != XHCI_EPSTATE_STOPPED)
1.72.2.2 snj 1734: DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0);
1.63 skrll 1735: #endif
1736:
1737: /*
1738: * Step 3: Remove any vestiges of the xfer from the ring.
1739: */
1740: xhci_set_dequeue_locked(xfer->ux_pipe);
1741:
1742: /*
1743: * Step 4: Notify completion to waiting xfers.
1744: */
1745: int wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
1746: xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
1.34 skrll 1747: usb_transfer_complete(xfer);
1.63 skrll 1748: if (wake) {
1749: cv_broadcast(&xfer->ux_hccv);
1750: }
1.34 skrll 1751: DPRINTFN(14, "end", 0, 0, 0, 0);
1752:
1753: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1754: }
1755:
1.55 skrll 1756: static void
1757: xhci_host_dequeue(struct xhci_ring * const xr)
1758: {
1759: /* When dequeueing the controller, update our struct copy too */
1760: memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE);
1761: usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE,
1762: BUS_DMASYNC_PREWRITE);
1763: memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies));
1764:
1765: xr->xr_ep = 0;
1766: xr->xr_cs = 1;
1767: }
1768:
1.34 skrll 1769: /*
1770: * Recover STALLed endpoint.
1771: * xHCI 1.1 sect 4.10.2.1
1772: * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove
1773: * all transfers on transfer ring.
1774: * These are done in thread context asynchronously.
1775: */
1.1 jakllsch 1776: static void
1.34 skrll 1777: xhci_clear_endpoint_stall_async_task(void *cookie)
1.1 jakllsch 1778: {
1.34 skrll 1779: struct usbd_xfer * const xfer = cookie;
1780: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1781: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
1782: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1783: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.1 jakllsch 1784:
1.27 skrll 1785: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1786: DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx,
1787: dci, 0);
1.1 jakllsch 1788:
1.34 skrll 1789: xhci_reset_endpoint(xfer->ux_pipe);
1790: xhci_set_dequeue(xfer->ux_pipe);
1791:
1792: mutex_enter(&sc->sc_lock);
1793: tr->is_halted = false;
1794: usb_transfer_complete(xfer);
1795: mutex_exit(&sc->sc_lock);
1796: DPRINTFN(4, "ends", 0, 0, 0, 0);
1797: }
1798:
1799: static usbd_status
1800: xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer)
1801: {
1802: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1803: struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe;
1804:
1805: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1806: DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
1.34 skrll 1807:
1808: if (sc->sc_dying) {
1809: return USBD_IOERROR;
1810: }
1811:
1812: usb_init_task(&xp->xp_async_task,
1813: xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE);
1814: usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC);
1815: DPRINTFN(4, "ends", 0, 0, 0, 0);
1816:
1817: return USBD_NORMAL_COMPLETION;
1818: }
1819:
1820: /* Process roothub port status/change events and notify to uhub_intr. */
1821: static void
1.68 skrll 1822: xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport)
1.34 skrll 1823: {
1824: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 1825: DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev),
1.68 skrll 1826: ctlrport, 0, 0);
1.34 skrll 1827:
1.68 skrll 1828: if (ctlrport > sc->sc_maxports)
1.34 skrll 1829: return;
1830:
1.68 skrll 1831: const size_t bn = xhci_ctlrport2bus(sc, ctlrport);
1832: const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport);
1833: struct usbd_xfer * const xfer = sc->sc_intrxfer[bn];
1834:
1.72.2.2 snj 1835: DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change",
1836: device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer);
1.68 skrll 1837:
1838: if (xfer == NULL)
1.34 skrll 1839: return;
1840:
1.68 skrll 1841: uint8_t *p = xfer->ux_buf;
1.34 skrll 1842: memset(p, 0, xfer->ux_length);
1.68 skrll 1843: p[rhp / NBBY] |= 1 << (rhp % NBBY);
1.34 skrll 1844: xfer->ux_actlen = xfer->ux_length;
1845: xfer->ux_status = USBD_NORMAL_COMPLETION;
1846: usb_transfer_complete(xfer);
1847: }
1848:
1849: /* Process Transfer Events */
1850: static void
1851: xhci_event_transfer(struct xhci_softc * const sc,
1852: const struct xhci_trb * const trb)
1853: {
1854: uint64_t trb_0;
1855: uint32_t trb_2, trb_3;
1856: uint8_t trbcode;
1857: u_int slot, dci;
1858: struct xhci_slot *xs;
1859: struct xhci_ring *xr;
1860: struct xhci_xfer *xx;
1861: struct usbd_xfer *xfer;
1862: usbd_status err;
1863:
1864: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1865:
1866: trb_0 = le64toh(trb->trb_0);
1867: trb_2 = le32toh(trb->trb_2);
1868: trb_3 = le32toh(trb->trb_3);
1869: trbcode = XHCI_TRB_2_ERROR_GET(trb_2);
1870: slot = XHCI_TRB_3_SLOT_GET(trb_3);
1871: dci = XHCI_TRB_3_EP_GET(trb_3);
1872: xs = &sc->sc_slots[slot];
1873: xr = &xs->xs_ep[dci].xe_tr;
1874:
1875: /* sanity check */
1876: KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots,
1877: "invalid xs_idx %u slot %u", xs->xs_idx, slot);
1878:
1.40 skrll 1879: int idx = 0;
1.34 skrll 1880: if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) {
1.40 skrll 1881: if (xhci_trb_get_idx(xr, trb_0, &idx)) {
1.72.2.2 snj 1882: DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0);
1.34 skrll 1883: return;
1884: }
1885: xx = xr->xr_cookies[idx];
1886:
1.63 skrll 1887: /* clear cookie of consumed TRB */
1888: xr->xr_cookies[idx] = NULL;
1889:
1.34 skrll 1890: /*
1.63 skrll 1891: * xx is NULL if pipe is opened but xfer is not started.
1892: * It happens when stopping idle pipe.
1.34 skrll 1893: */
1894: if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) {
1.72.2.2 snj 1895: DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju",
1896: idx, (uintptr_t)xx, trbcode, dci);
1897: DPRINTFN(1, " orig TRB %jx type %ju", trb_0,
1.53 skrll 1898: XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)),
1899: 0, 0);
1.63 skrll 1900: return;
1.34 skrll 1901: }
1902: } else {
1.54 skrll 1903: /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */
1.34 skrll 1904: xx = (void *)(uintptr_t)(trb_0 & ~0x3);
1905: }
1906: /* XXX this may not happen */
1907: if (xx == NULL) {
1908: DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0);
1909: return;
1910: }
1911: xfer = &xx->xx_xfer;
1912: /* XXX this may happen when detaching */
1913: if (xfer == NULL) {
1.72.2.2 snj 1914: DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx",
1915: (uintptr_t)xx, trb_0, 0, 0);
1.34 skrll 1916: return;
1917: }
1.72.2.2 snj 1918: DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
1.34 skrll 1919: /* XXX I dunno why this happens */
1920: KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer);
1921:
1922: if (!xfer->ux_pipe->up_repeat &&
1923: SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) {
1.72.2.2 snj 1924: DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer,
1925: 0, 0, 0);
1.34 skrll 1926: return;
1927: }
1928:
1929: /* 4.11.5.2 Event Data TRB */
1930: if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) {
1.72.2.2 snj 1931: DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx"
1932: " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0);
1.34 skrll 1933: if ((trb_0 & 0x3) == 0x3) {
1934: xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2);
1935: }
1936: }
1937:
1938: switch (trbcode) {
1939: case XHCI_TRB_ERROR_SHORT_PKT:
1940: case XHCI_TRB_ERROR_SUCCESS:
1.54 skrll 1941: /*
1.63 skrll 1942: * A ctrl transfer can generate two events if it has a Data
1943: * stage. A short data stage can be OK and should not
1944: * complete the transfer as the status stage needs to be
1945: * performed.
1.54 skrll 1946: *
1947: * Note: Data and Status stage events point at same xfer.
1948: * ux_actlen and ux_dmabuf will be passed to
1949: * usb_transfer_complete after the Status stage event.
1950: *
1951: * It can be distingished which stage generates the event:
1952: * + by checking least 3 bits of trb_0 if ED==1.
1953: * (see xhci_device_ctrl_start).
1954: * + by checking the type of original TRB if ED==0.
1955: *
1956: * In addition, intr, bulk, and isoc transfer currently
1957: * consists of single TD, so the "skip" is not needed.
1958: * ctrl xfer uses EVENT_DATA, and others do not.
1959: * Thus driver can switch the flow by checking ED bit.
1960: */
1.63 skrll 1961: if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) {
1962: if (xfer->ux_actlen == 0)
1963: xfer->ux_actlen = xfer->ux_length -
1964: XHCI_TRB_2_REM_GET(trb_2);
1965: if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3))
1966: == XHCI_TRB_TYPE_DATA_STAGE) {
1967: return;
1968: }
1969: } else if ((trb_0 & 0x3) == 0x3) {
1970: return;
1971: }
1.34 skrll 1972: err = USBD_NORMAL_COMPLETION;
1973: break;
1.63 skrll 1974: case XHCI_TRB_ERROR_STOPPED:
1975: case XHCI_TRB_ERROR_LENGTH:
1976: case XHCI_TRB_ERROR_STOPPED_SHORT:
1977: /*
1978: * don't complete the transfer being aborted
1979: * as abort_xfer does instead.
1980: */
1981: if (xfer->ux_hcflags & UXFER_ABORTING) {
1.72.2.2 snj 1982: DPRINTFN(14, "ignore aborting xfer %#jx",
1983: (uintptr_t)xfer, 0, 0, 0);
1.63 skrll 1984: return;
1985: }
1986: err = USBD_CANCELLED;
1987: break;
1.34 skrll 1988: case XHCI_TRB_ERROR_STALL:
1989: case XHCI_TRB_ERROR_BABBLE:
1.72.2.2 snj 1990: DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
1.34 skrll 1991: xr->is_halted = true;
1992: err = USBD_STALLED;
1993: /*
1994: * Stalled endpoints can be recoverd by issuing
1995: * command TRB TYPE_RESET_EP on xHCI instead of
1996: * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT
1997: * on the endpoint. However, this function may be
1998: * called from softint context (e.g. from umass),
1999: * in that case driver gets KASSERT in cv_timedwait
2000: * in xhci_do_command.
2001: * To avoid this, this runs reset_endpoint and
2002: * usb_transfer_complete in usb task thread
2003: * asynchronously (and then umass issues clear
2004: * UF_ENDPOINT_HALT).
2005: */
2006: xfer->ux_status = err;
1.57 skrll 2007: callout_stop(&xfer->ux_callout);
1.34 skrll 2008: xhci_clear_endpoint_stall_async(xfer);
2009: return;
2010: default:
1.72.2.2 snj 2011: DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
1.34 skrll 2012: err = USBD_IOERROR;
2013: break;
2014: }
2015: xfer->ux_status = err;
2016:
2017: if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) {
2018: if ((trb_0 & 0x3) == 0x0) {
2019: callout_stop(&xfer->ux_callout);
2020: usb_transfer_complete(xfer);
2021: }
2022: } else {
2023: callout_stop(&xfer->ux_callout);
2024: usb_transfer_complete(xfer);
2025: }
2026: }
2027:
2028: /* Process Command complete events */
2029: static void
1.50 skrll 2030: xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb)
1.34 skrll 2031: {
2032: uint64_t trb_0;
2033: uint32_t trb_2, trb_3;
2034:
2035: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2036:
1.68 skrll 2037: KASSERT(mutex_owned(&sc->sc_lock));
2038:
1.34 skrll 2039: trb_0 = le64toh(trb->trb_0);
2040: trb_2 = le32toh(trb->trb_2);
2041: trb_3 = le32toh(trb->trb_3);
2042:
2043: if (trb_0 == sc->sc_command_addr) {
1.68 skrll 2044: sc->sc_resultpending = false;
2045:
1.34 skrll 2046: sc->sc_result_trb.trb_0 = trb_0;
2047: sc->sc_result_trb.trb_2 = trb_2;
2048: sc->sc_result_trb.trb_3 = trb_3;
2049: if (XHCI_TRB_2_ERROR_GET(trb_2) !=
2050: XHCI_TRB_ERROR_SUCCESS) {
2051: DPRINTFN(1, "command completion "
1.72.2.2 snj 2052: "failure: 0x%016jx 0x%08jx 0x%08jx",
2053: trb_0, trb_2, trb_3, 0);
1.34 skrll 2054: }
2055: cv_signal(&sc->sc_command_cv);
2056: } else {
1.72.2.2 snj 2057: DPRINTFN(1, "spurious event: %#jx 0x%016jx "
2058: "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3);
1.34 skrll 2059: }
2060: }
2061:
2062: /*
2063: * Process events.
2064: * called from xhci_softintr
2065: */
2066: static void
2067: xhci_handle_event(struct xhci_softc * const sc,
2068: const struct xhci_trb * const trb)
2069: {
2070: uint64_t trb_0;
2071: uint32_t trb_2, trb_3;
2072:
2073: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2074:
2075: trb_0 = le64toh(trb->trb_0);
2076: trb_2 = le32toh(trb->trb_2);
2077: trb_3 = le32toh(trb->trb_3);
2078:
1.72.2.2 snj 2079: DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx",
2080: (uintptr_t)trb, trb_0, trb_2, trb_3);
1.34 skrll 2081:
2082: /*
2083: * 4.11.3.1, 6.4.2.1
2084: * TRB Pointer is invalid for these completion codes.
2085: */
2086: switch (XHCI_TRB_2_ERROR_GET(trb_2)) {
2087: case XHCI_TRB_ERROR_RING_UNDERRUN:
2088: case XHCI_TRB_ERROR_RING_OVERRUN:
2089: case XHCI_TRB_ERROR_VF_RING_FULL:
2090: return;
2091: default:
2092: if (trb_0 == 0) {
2093: return;
2094: }
2095: break;
2096: }
2097:
2098: switch (XHCI_TRB_3_TYPE_GET(trb_3)) {
2099: case XHCI_TRB_EVENT_TRANSFER:
2100: xhci_event_transfer(sc, trb);
2101: break;
2102: case XHCI_TRB_EVENT_CMD_COMPLETE:
2103: xhci_event_cmd(sc, trb);
2104: break;
2105: case XHCI_TRB_EVENT_PORT_STS_CHANGE:
2106: xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff));
2107: break;
2108: default:
2109: break;
2110: }
2111: }
2112:
2113: static void
2114: xhci_softintr(void *v)
2115: {
2116: struct usbd_bus * const bus = v;
2117: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
2118: struct xhci_ring * const er = &sc->sc_er;
2119: struct xhci_trb *trb;
2120: int i, j, k;
2121:
2122: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2123:
1.72.2.1 snj 2124: KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock));
1.34 skrll 2125:
2126: i = er->xr_ep;
2127: j = er->xr_cs;
1.1 jakllsch 2128:
1.72.2.2 snj 2129: DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0);
1.27 skrll 2130:
1.1 jakllsch 2131: while (1) {
2132: usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE,
2133: BUS_DMASYNC_POSTREAD);
2134: trb = &er->xr_trb[i];
2135: k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
2136:
2137: if (j != k)
2138: break;
2139:
2140: xhci_handle_event(sc, trb);
2141:
2142: i++;
1.52 skrll 2143: if (i == er->xr_ntrb) {
1.1 jakllsch 2144: i = 0;
2145: j ^= 1;
2146: }
2147: }
2148:
2149: er->xr_ep = i;
2150: er->xr_cs = j;
2151:
2152: xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) |
2153: XHCI_ERDP_LO_BUSY);
2154:
1.27 skrll 2155: DPRINTFN(16, "ends", 0, 0, 0, 0);
1.1 jakllsch 2156:
2157: return;
2158: }
2159:
2160: static void
2161: xhci_poll(struct usbd_bus *bus)
2162: {
1.34 skrll 2163: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2164:
1.27 skrll 2165: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2166:
1.25 skrll 2167: mutex_spin_enter(&sc->sc_intr_lock);
1.72.2.1 snj 2168: int ret = xhci_intr1(sc);
2169: if (ret) {
2170: xhci_softintr(bus);
2171: }
1.25 skrll 2172: mutex_spin_exit(&sc->sc_intr_lock);
1.1 jakllsch 2173:
2174: return;
2175: }
2176:
1.34 skrll 2177: static struct usbd_xfer *
2178: xhci_allocx(struct usbd_bus *bus, unsigned int nframes)
1.1 jakllsch 2179: {
1.34 skrll 2180: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
2181: struct usbd_xfer *xfer;
1.1 jakllsch 2182:
1.27 skrll 2183: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2184:
1.72.2.4 martin 2185: xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
1.1 jakllsch 2186: if (xfer != NULL) {
1.6 skrll 2187: memset(xfer, 0, sizeof(struct xhci_xfer));
1.1 jakllsch 2188: #ifdef DIAGNOSTIC
1.34 skrll 2189: xfer->ux_state = XFER_BUSY;
1.1 jakllsch 2190: #endif
2191: }
2192:
2193: return xfer;
2194: }
2195:
2196: static void
1.34 skrll 2197: xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1.1 jakllsch 2198: {
1.34 skrll 2199: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2200:
1.27 skrll 2201: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2202:
2203: #ifdef DIAGNOSTIC
1.34 skrll 2204: if (xfer->ux_state != XFER_BUSY) {
1.72.2.2 snj 2205: DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx",
2206: (uintptr_t)xfer, xfer->ux_state, 0, 0);
1.1 jakllsch 2207: }
1.34 skrll 2208: xfer->ux_state = XFER_FREE;
1.1 jakllsch 2209: #endif
2210: pool_cache_put(sc->sc_xferpool, xfer);
2211: }
2212:
2213: static void
2214: xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
2215: {
1.34 skrll 2216: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2217:
2218: *lock = &sc->sc_lock;
2219: }
2220:
1.34 skrll 2221: extern uint32_t usb_cookie_no;
1.1 jakllsch 2222:
1.34 skrll 2223: /*
1.41 skrll 2224: * xHCI 4.3
2225: * Called when uhub_explore finds a new device (via usbd_new_device).
2226: * Port initialization and speed detection (4.3.1) are already done in uhub.c.
2227: * This function does:
2228: * Allocate and construct dev structure of default endpoint (ep0).
2229: * Allocate and open pipe of ep0.
2230: * Enable slot and initialize slot context.
2231: * Set Address.
2232: * Read initial device descriptor.
1.34 skrll 2233: * Determine initial MaxPacketSize (mps) by speed.
1.41 skrll 2234: * Read full device descriptor.
2235: * Register this device.
1.54 skrll 2236: * Finally state of device transitions ADDRESSED.
1.34 skrll 2237: */
1.1 jakllsch 2238: static usbd_status
1.34 skrll 2239: xhci_new_device(device_t parent, struct usbd_bus *bus, int depth,
1.1 jakllsch 2240: int speed, int port, struct usbd_port *up)
2241: {
1.34 skrll 2242: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
2243: struct usbd_device *dev;
1.1 jakllsch 2244: usbd_status err;
2245: usb_device_descriptor_t *dd;
2246: struct xhci_slot *xs;
2247: uint32_t *cp;
2248:
1.27 skrll 2249: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2250: DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx",
2251: port, depth, speed, (uintptr_t)up);
1.27 skrll 2252:
1.34 skrll 2253: dev = kmem_zalloc(sizeof(*dev), KM_SLEEP);
2254: dev->ud_bus = bus;
1.51 skrll 2255: dev->ud_quirks = &usbd_no_quirk;
2256: dev->ud_addr = 0;
2257: dev->ud_ddesc.bMaxPacketSize = 0;
2258: dev->ud_depth = depth;
2259: dev->ud_powersrc = up;
2260: dev->ud_myhub = up->up_parent;
2261: dev->ud_speed = speed;
2262: dev->ud_langid = USBD_NOLANG;
2263: dev->ud_cookie.cookie = ++usb_cookie_no;
1.1 jakllsch 2264:
2265: /* Set up default endpoint handle. */
1.34 skrll 2266: dev->ud_ep0.ue_edesc = &dev->ud_ep0desc;
1.51 skrll 2267: /* doesn't matter, just don't let it uninitialized */
2268: dev->ud_ep0.ue_toggle = 0;
1.1 jakllsch 2269:
2270: /* Set up default endpoint descriptor. */
1.34 skrll 2271: dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE;
2272: dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT;
2273: dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT;
2274: dev->ud_ep0desc.bmAttributes = UE_CONTROL;
1.51 skrll 2275: dev->ud_ep0desc.bInterval = 0;
1.50 skrll 2276:
1.34 skrll 2277: /* 4.3, 4.8.2.1 */
2278: switch (speed) {
2279: case USB_SPEED_SUPER:
2280: case USB_SPEED_SUPER_PLUS:
2281: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET);
2282: break;
2283: case USB_SPEED_FULL:
2284: /* XXX using 64 as initial mps of ep0 in FS */
2285: case USB_SPEED_HIGH:
2286: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET);
2287: break;
2288: case USB_SPEED_LOW:
2289: default:
2290: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET);
2291: break;
2292: }
1.1 jakllsch 2293:
1.51 skrll 2294: up->up_dev = dev;
2295:
2296: /* Establish the default pipe. */
2297: err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL,
2298: &dev->ud_pipe0);
2299: if (err) {
2300: goto bad;
2301: }
1.1 jakllsch 2302:
1.51 skrll 2303: dd = &dev->ud_ddesc;
1.1 jakllsch 2304:
1.68 skrll 2305: if (depth == 0 && port == 0) {
2306: KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL);
2307: bus->ub_devices[USB_ROOTHUB_INDEX] = dev;
1.51 skrll 2308: err = usbd_get_initial_ddesc(dev, dd);
1.61 skrll 2309: if (err) {
1.72.2.2 snj 2310: DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0);
1.34 skrll 2311: goto bad;
1.61 skrll 2312: }
2313:
1.1 jakllsch 2314: err = usbd_reload_device_desc(dev);
1.61 skrll 2315: if (err) {
1.72.2.2 snj 2316: DPRINTFN(1, "reload desc %ju", err, 0, 0, 0);
1.34 skrll 2317: goto bad;
1.61 skrll 2318: }
1.1 jakllsch 2319: } else {
1.49 skrll 2320: uint8_t slot = 0;
2321:
1.48 skrll 2322: /* 4.3.2 */
1.1 jakllsch 2323: err = xhci_enable_slot(sc, &slot);
1.63 skrll 2324: if (err) {
1.72.2.2 snj 2325: DPRINTFN(1, "enable slot %ju", err, 0, 0, 0);
1.34 skrll 2326: goto bad;
1.63 skrll 2327: }
1.50 skrll 2328:
1.1 jakllsch 2329: xs = &sc->sc_slots[slot];
1.34 skrll 2330: dev->ud_hcpriv = xs;
1.50 skrll 2331:
1.48 skrll 2332: /* 4.3.3 initialize slot structure */
2333: err = xhci_init_slot(dev, slot);
1.34 skrll 2334: if (err) {
1.72.2.2 snj 2335: DPRINTFN(1, "init slot %ju", err, 0, 0, 0);
1.34 skrll 2336: dev->ud_hcpriv = NULL;
2337: /*
2338: * We have to disable_slot here because
2339: * xs->xs_idx == 0 when xhci_init_slot fails,
2340: * in that case usbd_remove_dev won't work.
2341: */
2342: mutex_enter(&sc->sc_lock);
2343: xhci_disable_slot(sc, slot);
2344: mutex_exit(&sc->sc_lock);
2345: goto bad;
2346: }
2347:
1.48 skrll 2348: /* 4.3.4 Address Assignment */
1.51 skrll 2349: err = xhci_set_address(dev, slot, false);
1.61 skrll 2350: if (err) {
1.72.2.2 snj 2351: DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0);
1.48 skrll 2352: goto bad;
1.61 skrll 2353: }
1.48 skrll 2354:
1.34 skrll 2355: /* Allow device time to set new address */
2356: usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE);
1.50 skrll 2357:
1.1 jakllsch 2358: cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT);
2359: //hexdump("slot context", cp, sc->sc_ctxsz);
1.64 skrll 2360: uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3]));
1.72.2.2 snj 2361: DPRINTFN(4, "device address %ju", addr, 0, 0, 0);
1.68 skrll 2362: /*
2363: * XXX ensure we know when the hardware does something
2364: * we can't yet cope with
2365: */
1.59 maya 2366: KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr);
1.34 skrll 2367: dev->ud_addr = addr;
1.68 skrll 2368:
2369: KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL,
2370: "addr %d already allocated", dev->ud_addr);
2371: /*
2372: * The root hub is given its own slot
2373: */
2374: bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev;
1.1 jakllsch 2375:
2376: err = usbd_get_initial_ddesc(dev, dd);
1.61 skrll 2377: if (err) {
1.72.2.2 snj 2378: DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0);
1.34 skrll 2379: goto bad;
1.61 skrll 2380: }
1.50 skrll 2381:
1.24 skrll 2382: /* 4.8.2.1 */
1.34 skrll 2383: if (USB_IS_SS(speed)) {
2384: if (dd->bMaxPacketSize != 9) {
2385: printf("%s: invalid mps 2^%u for SS ep0,"
2386: " using 512\n",
2387: device_xname(sc->sc_dev),
2388: dd->bMaxPacketSize);
2389: dd->bMaxPacketSize = 9;
2390: }
2391: USETW(dev->ud_ep0desc.wMaxPacketSize,
1.24 skrll 2392: (1 << dd->bMaxPacketSize));
1.34 skrll 2393: } else
2394: USETW(dev->ud_ep0desc.wMaxPacketSize,
1.24 skrll 2395: dd->bMaxPacketSize);
1.72.2.2 snj 2396: DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0);
1.62 skrll 2397: err = xhci_update_ep0_mps(sc, xs,
1.34 skrll 2398: UGETW(dev->ud_ep0desc.wMaxPacketSize));
1.62 skrll 2399: if (err) {
1.72.2.2 snj 2400: DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0);
1.62 skrll 2401: goto bad;
2402: }
1.50 skrll 2403:
1.1 jakllsch 2404: err = usbd_reload_device_desc(dev);
1.61 skrll 2405: if (err) {
1.72.2.2 snj 2406: DPRINTFN(1, "reload desc %ju", err, 0, 0, 0);
1.34 skrll 2407: goto bad;
1.61 skrll 2408: }
1.1 jakllsch 2409: }
2410:
1.72.2.2 snj 2411: DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,",
1.34 skrll 2412: dev->ud_addr, UGETW(dd->bcdUSB), 0, 0);
1.72.2.2 snj 2413: DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,",
1.27 skrll 2414: dd->bDeviceClass, dd->bDeviceSubClass,
2415: dd->bDeviceProtocol, 0);
1.72.2.2 snj 2416: DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd",
1.27 skrll 2417: dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations,
1.34 skrll 2418: dev->ud_speed);
1.1 jakllsch 2419:
1.33 skrll 2420: usbd_get_device_strings(dev);
2421:
1.1 jakllsch 2422: usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev);
2423:
1.68 skrll 2424: if (depth == 0 && port == 0) {
1.1 jakllsch 2425: usbd_attach_roothub(parent, dev);
1.72.2.2 snj 2426: DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0);
1.1 jakllsch 2427: return USBD_NORMAL_COMPLETION;
2428: }
2429:
1.34 skrll 2430: err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr);
2431: bad:
2432: if (err != USBD_NORMAL_COMPLETION) {
1.1 jakllsch 2433: usbd_remove_device(dev, up);
2434: }
2435:
1.34 skrll 2436: return err;
1.1 jakllsch 2437: }
2438:
2439: static usbd_status
2440: xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr,
2441: size_t ntrb, size_t align)
2442: {
2443: usbd_status err;
2444: size_t size = ntrb * XHCI_TRB_SIZE;
2445:
1.27 skrll 2446: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2447:
1.1 jakllsch 2448: err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma);
2449: if (err)
2450: return err;
2451: mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
2452: xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP);
2453: xr->xr_trb = xhci_ring_trbv(xr, 0);
2454: xr->xr_ntrb = ntrb;
2455: xr->is_halted = false;
1.55 skrll 2456: xhci_host_dequeue(xr);
1.1 jakllsch 2457:
2458: return USBD_NORMAL_COMPLETION;
2459: }
2460:
2461: static void
2462: xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr)
2463: {
2464: usb_freemem(&sc->sc_bus, &xr->xr_dma);
2465: mutex_destroy(&xr->xr_lock);
2466: kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb);
2467: }
2468:
2469: static void
2470: xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr,
2471: void *cookie, struct xhci_trb * const trbs, size_t ntrbs)
2472: {
2473: size_t i;
2474: u_int ri;
2475: u_int cs;
2476: uint64_t parameter;
2477: uint32_t status;
2478: uint32_t control;
2479:
1.27 skrll 2480: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2481:
1.59 maya 2482: KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs);
1.1 jakllsch 2483: for (i = 0; i < ntrbs; i++) {
1.72.2.2 snj 2484: DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr,
2485: (uintptr_t)trbs, i, 0);
2486: DPRINTFN(12, " %016jx %08jx %08jx",
1.27 skrll 2487: trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0);
1.59 maya 2488: KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) !=
1.63 skrll 2489: XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3);
1.1 jakllsch 2490: }
2491:
1.72.2.2 snj 2492: DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep,
2493: xr->xr_cs, 0);
1.1 jakllsch 2494:
2495: ri = xr->xr_ep;
2496: cs = xr->xr_cs;
2497:
1.11 dsl 2498: /*
2499: * Although the xhci hardware can do scatter/gather dma from
2500: * arbitrary sized buffers, there is a non-obvious restriction
2501: * that a LINK trb is only allowed at the end of a burst of
2502: * transfers - which might be 16kB.
2503: * Arbitrary aligned LINK trb definitely fail on Ivy bridge.
2504: * The simple solution is not to allow a LINK trb in the middle
2505: * of anything - as here.
1.13 dsl 2506: * XXX: (dsl) There are xhci controllers out there (eg some made by
2507: * ASMedia) that seem to lock up if they process a LINK trb but
2508: * cannot process the linked-to trb yet.
2509: * The code should write the 'cycle' bit on the link trb AFTER
2510: * adding the other trb.
1.11 dsl 2511: */
1.65 skrll 2512: u_int firstep = xr->xr_ep;
2513: u_int firstcs = xr->xr_cs;
1.1 jakllsch 2514:
1.65 skrll 2515: for (i = 0; i < ntrbs; ) {
2516: u_int oldri = ri;
2517: u_int oldcs = cs;
2518:
2519: if (ri >= (xr->xr_ntrb - 1)) {
2520: /* Put Link TD at the end of ring */
2521: parameter = xhci_ring_trbp(xr, 0);
2522: status = 0;
2523: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
2524: XHCI_TRB_3_TC_BIT;
2525: xr->xr_cookies[ri] = NULL;
2526: xr->xr_ep = 0;
2527: xr->xr_cs ^= 1;
2528: ri = xr->xr_ep;
2529: cs = xr->xr_cs;
1.1 jakllsch 2530: } else {
1.65 skrll 2531: parameter = trbs[i].trb_0;
2532: status = trbs[i].trb_2;
2533: control = trbs[i].trb_3;
2534:
2535: xr->xr_cookies[ri] = cookie;
2536: ri++;
2537: i++;
1.1 jakllsch 2538: }
1.65 skrll 2539: /*
2540: * If this is a first TRB, mark it invalid to prevent
2541: * xHC from running it immediately.
2542: */
2543: if (oldri == firstep) {
2544: if (oldcs) {
2545: control &= ~XHCI_TRB_3_CYCLE_BIT;
2546: } else {
2547: control |= XHCI_TRB_3_CYCLE_BIT;
2548: }
2549: } else {
2550: if (oldcs) {
2551: control |= XHCI_TRB_3_CYCLE_BIT;
2552: } else {
2553: control &= ~XHCI_TRB_3_CYCLE_BIT;
2554: }
2555: }
2556: xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control);
2557: usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri,
2558: XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 2559: }
2560:
1.65 skrll 2561: /* Now invert cycle bit of first TRB */
2562: if (firstcs) {
2563: xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
1.34 skrll 2564: } else {
1.65 skrll 2565: xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1.34 skrll 2566: }
1.65 skrll 2567: usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep,
2568: XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE);
1.1 jakllsch 2569:
2570: xr->xr_ep = ri;
2571: xr->xr_cs = cs;
2572:
1.72.2.2 snj 2573: DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep,
2574: xr->xr_cs, 0);
1.1 jakllsch 2575: }
2576:
1.34 skrll 2577: /*
1.39 skrll 2578: * Stop execution commands, purge all commands on command ring, and
1.54 skrll 2579: * rewind dequeue pointer.
1.39 skrll 2580: */
2581: static void
2582: xhci_abort_command(struct xhci_softc *sc)
2583: {
2584: struct xhci_ring * const cr = &sc->sc_cr;
2585: uint64_t crcr;
2586: int i;
2587:
2588: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2589: DPRINTFN(14, "command %#jx timeout, aborting",
1.39 skrll 2590: sc->sc_command_addr, 0, 0, 0);
2591:
2592: mutex_enter(&cr->xr_lock);
2593:
2594: /* 4.6.1.2 Aborting a Command */
2595: crcr = xhci_op_read_8(sc, XHCI_CRCR);
2596: xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA);
2597:
2598: for (i = 0; i < 500; i++) {
2599: crcr = xhci_op_read_8(sc, XHCI_CRCR);
2600: if ((crcr & XHCI_CRCR_LO_CRR) == 0)
2601: break;
2602: usb_delay_ms(&sc->sc_bus, 1);
2603: }
2604: if ((crcr & XHCI_CRCR_LO_CRR) != 0) {
2605: DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0);
2606: /* reset HC here? */
2607: }
2608:
2609: /* reset command ring dequeue pointer */
2610: cr->xr_ep = 0;
2611: cr->xr_cs = 1;
2612: xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs);
2613:
2614: mutex_exit(&cr->xr_lock);
2615: }
2616:
2617: /*
1.34 skrll 2618: * Put a command on command ring, ring bell, set timer, and cv_timedwait.
1.54 skrll 2619: * Command completion is notified by cv_signal from xhci_event_cmd()
2620: * (called from xhci_softint), or timed-out.
2621: * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(),
2622: * then do_command examines it.
1.34 skrll 2623: */
1.1 jakllsch 2624: static usbd_status
1.50 skrll 2625: xhci_do_command_locked(struct xhci_softc * const sc,
2626: struct xhci_trb * const trb, int timeout)
1.1 jakllsch 2627: {
2628: struct xhci_ring * const cr = &sc->sc_cr;
2629: usbd_status err;
2630:
1.27 skrll 2631: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2632: DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx",
1.27 skrll 2633: trb->trb_0, trb->trb_2, trb->trb_3, 0);
1.1 jakllsch 2634:
1.34 skrll 2635: KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx");
2636: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 2637:
1.68 skrll 2638: while (sc->sc_command_addr != 0)
2639: cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock);
2640:
1.67 skrll 2641: /*
2642: * If enqueue pointer points at last of ring, it's Link TRB,
2643: * command TRB will be stored in 0th TRB.
2644: */
2645: if (cr->xr_ep == cr->xr_ntrb - 1)
2646: sc->sc_command_addr = xhci_ring_trbp(cr, 0);
2647: else
2648: sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep);
1.1 jakllsch 2649:
1.68 skrll 2650: sc->sc_resultpending = true;
2651:
1.1 jakllsch 2652: mutex_enter(&cr->xr_lock);
2653: xhci_ring_put(sc, cr, NULL, trb, 1);
2654: mutex_exit(&cr->xr_lock);
2655:
2656: xhci_db_write_4(sc, XHCI_DOORBELL(0), 0);
2657:
1.68 skrll 2658: while (sc->sc_resultpending) {
2659: if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock,
2660: MAX(1, mstohz(timeout))) == EWOULDBLOCK) {
2661: xhci_abort_command(sc);
2662: err = USBD_TIMEOUT;
2663: goto timedout;
2664: }
1.1 jakllsch 2665: }
2666:
2667: trb->trb_0 = sc->sc_result_trb.trb_0;
2668: trb->trb_2 = sc->sc_result_trb.trb_2;
2669: trb->trb_3 = sc->sc_result_trb.trb_3;
2670:
1.72.2.2 snj 2671: DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx",
1.27 skrll 2672: trb->trb_0, trb->trb_2, trb->trb_3, 0);
1.1 jakllsch 2673:
2674: switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) {
2675: case XHCI_TRB_ERROR_SUCCESS:
2676: err = USBD_NORMAL_COMPLETION;
2677: break;
2678: default:
2679: case 192 ... 223:
2680: err = USBD_IOERROR;
2681: break;
2682: case 224 ... 255:
2683: err = USBD_NORMAL_COMPLETION;
2684: break;
2685: }
2686:
2687: timedout:
1.68 skrll 2688: sc->sc_resultpending = false;
1.1 jakllsch 2689: sc->sc_command_addr = 0;
1.68 skrll 2690: cv_broadcast(&sc->sc_cmdbusy_cv);
2691:
1.34 skrll 2692: return err;
2693: }
2694:
2695: static usbd_status
2696: xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb,
2697: int timeout)
2698: {
2699:
2700: mutex_enter(&sc->sc_lock);
1.38 skrll 2701: usbd_status ret = xhci_do_command_locked(sc, trb, timeout);
1.1 jakllsch 2702: mutex_exit(&sc->sc_lock);
1.34 skrll 2703:
2704: return ret;
1.1 jakllsch 2705: }
2706:
2707: static usbd_status
2708: xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp)
2709: {
2710: struct xhci_trb trb;
2711: usbd_status err;
2712:
1.27 skrll 2713: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2714:
1.1 jakllsch 2715: trb.trb_0 = 0;
2716: trb.trb_2 = 0;
2717: trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT);
2718:
2719: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
2720: if (err != USBD_NORMAL_COMPLETION) {
2721: return err;
2722: }
2723:
2724: *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3);
2725:
2726: return err;
2727: }
2728:
1.34 skrll 2729: /*
1.41 skrll 2730: * xHCI 4.6.4
2731: * Deallocate ring and device/input context DMA buffers, and disable_slot.
2732: * All endpoints in the slot should be stopped.
1.34 skrll 2733: * Should be called with sc_lock held.
2734: */
2735: static usbd_status
2736: xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot)
2737: {
2738: struct xhci_trb trb;
2739: struct xhci_slot *xs;
2740: usbd_status err;
2741:
2742: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2743:
2744: if (sc->sc_dying)
2745: return USBD_IOERROR;
2746:
2747: trb.trb_0 = 0;
2748: trb.trb_2 = 0;
2749: trb.trb_3 = htole32(
2750: XHCI_TRB_3_SLOT_SET(slot) |
2751: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT));
2752:
2753: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
2754:
2755: if (!err) {
2756: xs = &sc->sc_slots[slot];
2757: if (xs->xs_idx != 0) {
1.48 skrll 2758: xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32);
1.34 skrll 2759: xhci_set_dcba(sc, 0, slot);
2760: memset(xs, 0, sizeof(*xs));
2761: }
2762: }
2763:
2764: return err;
2765: }
2766:
2767: /*
1.41 skrll 2768: * Set address of device and transition slot state from ENABLED to ADDRESSED
2769: * if Block Setaddress Request (BSR) is false.
2770: * If BSR==true, transition slot state from ENABLED to DEFAULT.
1.34 skrll 2771: * see xHCI 1.1 4.5.3, 3.3.4
1.41 skrll 2772: * Should be called without sc_lock held.
1.34 skrll 2773: */
1.1 jakllsch 2774: static usbd_status
2775: xhci_address_device(struct xhci_softc * const sc,
2776: uint64_t icp, uint8_t slot_id, bool bsr)
2777: {
2778: struct xhci_trb trb;
2779: usbd_status err;
2780:
1.27 skrll 2781: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2782:
1.1 jakllsch 2783: trb.trb_0 = icp;
2784: trb.trb_2 = 0;
2785: trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) |
2786: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
2787: (bsr ? XHCI_TRB_3_BSR_BIT : 0);
2788:
2789: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.34 skrll 2790:
2791: if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS)
2792: err = USBD_NO_ADDR;
2793:
1.1 jakllsch 2794: return err;
2795: }
2796:
2797: static usbd_status
2798: xhci_update_ep0_mps(struct xhci_softc * const sc,
2799: struct xhci_slot * const xs, u_int mps)
2800: {
2801: struct xhci_trb trb;
2802: usbd_status err;
2803: uint32_t * cp;
2804:
1.27 skrll 2805: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2806: DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0);
1.1 jakllsch 2807:
2808: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
2809: cp[0] = htole32(0);
2810: cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL));
2811:
2812: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL));
2813: cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps));
2814:
2815: /* sync input contexts before they are read from memory */
2816: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
2817: hexdump("input context", xhci_slot_get_icv(sc, xs, 0),
2818: sc->sc_ctxsz * 4);
2819:
2820: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
2821: trb.trb_2 = 0;
2822: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
2823: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX);
2824:
2825: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
2826: return err;
2827: }
2828:
2829: static void
2830: xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si)
2831: {
2832: uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0);
2833:
1.27 skrll 2834: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2835: DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd",
2836: (uintptr_t)&dcbaa[si], dcba, si, 0);
1.1 jakllsch 2837:
1.5 matt 2838: dcbaa[si] = htole64(dcba);
1.1 jakllsch 2839: usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t),
2840: BUS_DMASYNC_PREWRITE);
2841: }
2842:
1.34 skrll 2843: /*
1.48 skrll 2844: * Allocate device and input context DMA buffer, and
2845: * TRB DMA buffer for each endpoint.
1.34 skrll 2846: */
1.1 jakllsch 2847: static usbd_status
1.48 skrll 2848: xhci_init_slot(struct usbd_device *dev, uint32_t slot)
1.1 jakllsch 2849: {
1.34 skrll 2850: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
1.1 jakllsch 2851: struct xhci_slot *xs;
2852: usbd_status err;
2853: u_int dci;
2854:
1.27 skrll 2855: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2856: DPRINTFN(4, "slot %ju", slot, 0, 0, 0);
1.1 jakllsch 2857:
2858: xs = &sc->sc_slots[slot];
2859:
2860: /* allocate contexts */
2861: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz,
2862: &xs->xs_dc_dma);
2863: if (err)
2864: return err;
2865: memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz);
2866:
2867: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz,
2868: &xs->xs_ic_dma);
2869: if (err)
1.34 skrll 2870: goto bad1;
1.1 jakllsch 2871: memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz);
2872:
2873: for (dci = 0; dci < 32; dci++) {
2874: //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint));
2875: memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci]));
2876: if (dci == XHCI_DCI_SLOT)
2877: continue;
2878: err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr,
2879: XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN);
2880: if (err) {
1.27 skrll 2881: DPRINTFN(0, "ring init failure", 0, 0, 0, 0);
1.34 skrll 2882: goto bad2;
1.1 jakllsch 2883: }
2884: }
2885:
1.48 skrll 2886: bad2:
2887: if (err == USBD_NORMAL_COMPLETION) {
2888: xs->xs_idx = slot;
2889: } else {
2890: xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci);
2891: }
2892:
2893: return err;
2894:
2895: bad1:
2896: usb_freemem(&sc->sc_bus, &xs->xs_dc_dma);
2897: xs->xs_idx = 0;
2898: return err;
2899: }
2900:
2901: static void
2902: xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci,
2903: int end_dci)
2904: {
2905: u_int dci;
2906:
2907: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2908: DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci,
2909: end_dci, 0);
1.48 skrll 2910:
2911: for (dci = start_dci; dci < end_dci; dci++) {
2912: xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr);
2913: memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci]));
2914: }
2915: usb_freemem(&sc->sc_bus, &xs->xs_ic_dma);
2916: usb_freemem(&sc->sc_bus, &xs->xs_dc_dma);
2917: xs->xs_idx = 0;
2918: }
2919:
2920: /*
2921: * Setup slot context, set Device Context Base Address, and issue
2922: * Set Address Device command.
2923: */
2924: static usbd_status
1.51 skrll 2925: xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr)
1.48 skrll 2926: {
2927: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
2928: struct xhci_slot *xs;
2929: usbd_status err;
1.51 skrll 2930:
2931: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2932: DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0);
1.51 skrll 2933:
2934: xs = &sc->sc_slots[slot];
2935:
2936: xhci_setup_ctx(dev->ud_pipe0);
2937:
2938: hexdump("input context", xhci_slot_get_icv(sc, xs, 0),
2939: sc->sc_ctxsz * 3);
2940:
2941: xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot);
2942:
2943: err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr);
2944:
2945: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
2946: hexdump("output context", xhci_slot_get_dcv(sc, xs, 0),
2947: sc->sc_ctxsz * 2);
2948:
2949: return err;
2950: }
2951:
2952: /*
2953: * 4.8.2, 6.2.3.2
2954: * construct slot/endpoint context parameters and do syncmem
2955: */
2956: static void
2957: xhci_setup_ctx(struct usbd_pipe *pipe)
2958: {
2959: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
2960: struct usbd_device *dev = pipe->up_dev;
2961: struct xhci_slot * const xs = dev->ud_hcpriv;
2962: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
2963: const u_int dci = xhci_ep_get_dci(ed);
2964: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1.48 skrll 2965: uint32_t *cp;
1.51 skrll 2966: uint16_t mps = UGETW(ed->wMaxPacketSize);
2967: uint8_t speed = dev->ud_speed;
2968: uint8_t ival = ed->bInterval;
1.48 skrll 2969:
1.51 skrll 2970: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 2971: DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju",
2972: (uintptr_t)pipe, xs->xs_idx, dci, speed);
1.48 skrll 2973:
1.1 jakllsch 2974: /* set up initial input control context */
2975: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
2976: cp[0] = htole32(0);
1.51 skrll 2977: cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci));
1.71 skrll 2978: cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT));
1.51 skrll 2979: cp[7] = htole32(0);
1.1 jakllsch 2980:
2981: /* set up input slot context */
2982: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1.51 skrll 2983: cp[0] =
2984: XHCI_SCTX_0_CTX_NUM_SET(dci) |
2985: XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed));
2986: cp[1] = 0;
2987: cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2988: cp[3] = 0;
2989: xhci_setup_route(pipe, cp);
2990: xhci_setup_tthub(pipe, cp);
2991:
2992: cp[0] = htole32(cp[0]);
2993: cp[1] = htole32(cp[1]);
2994: cp[2] = htole32(cp[2]);
2995: cp[3] = htole32(cp[3]);
2996:
2997: /* set up input endpoint context */
2998: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci));
2999: cp[0] =
3000: XHCI_EPCTX_0_EPSTATE_SET(0) |
3001: XHCI_EPCTX_0_MULT_SET(0) |
3002: XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
3003: XHCI_EPCTX_0_LSA_SET(0) |
3004: XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0);
3005: cp[1] =
3006: XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) |
3007: XHCI_EPCTX_1_HID_SET(0) |
3008: XHCI_EPCTX_1_MAXB_SET(0);
3009:
3010: if (xfertype != UE_ISOCHRONOUS)
3011: cp[1] |= XHCI_EPCTX_1_CERR_SET(3);
3012:
3013: if (xfertype == UE_CONTROL)
3014: cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */
3015: else if (USB_IS_SS(speed))
3016: cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps);
3017: else
3018: cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps));
3019:
3020: xhci_setup_maxburst(pipe, cp);
3021:
3022: switch (xfertype) {
3023: case UE_CONTROL:
3024: break;
3025: case UE_BULK:
3026: /* XXX Set MaxPStreams, HID, and LSA if streams enabled */
3027: break;
3028: case UE_INTERRUPT:
3029: if (pipe->up_interval != USBD_DEFAULT_INTERVAL)
3030: ival = pipe->up_interval;
3031:
3032: ival = xhci_bival2ival(ival, speed);
3033: cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival);
3034: break;
3035: case UE_ISOCHRONOUS:
3036: if (pipe->up_interval != USBD_DEFAULT_INTERVAL)
3037: ival = pipe->up_interval;
3038:
3039: /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */
3040: if (speed == USB_SPEED_FULL)
3041: ival += 3; /* 1ms -> 125us */
3042: ival--;
3043: cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival);
3044: break;
3045: default:
3046: break;
3047: }
1.72.2.2 snj 3048: DPRINTFN(4, "setting ival %ju MaxBurst %#jx",
1.53 skrll 3049: XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0);
1.1 jakllsch 3050:
1.55 skrll 3051: /* rewind TR dequeue pointer in xHC */
1.1 jakllsch 3052: /* can't use xhci_ep_get_dci() yet? */
3053: *(uint64_t *)(&cp[2]) = htole64(
1.51 skrll 3054: xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) |
1.1 jakllsch 3055: XHCI_EPCTX_2_DCS_SET(1));
1.51 skrll 3056:
3057: cp[0] = htole32(cp[0]);
3058: cp[1] = htole32(cp[1]);
3059: cp[4] = htole32(cp[4]);
1.1 jakllsch 3060:
1.55 skrll 3061: /* rewind TR dequeue pointer in driver */
3062: struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr;
3063: mutex_enter(&xr->xr_lock);
3064: xhci_host_dequeue(xr);
3065: mutex_exit(&xr->xr_lock);
3066:
1.1 jakllsch 3067: /* sync input contexts before they are read from memory */
3068: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1.51 skrll 3069: }
3070:
3071: /*
3072: * Setup route string and roothub port of given device for slot context
3073: */
3074: static void
3075: xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp)
3076: {
1.68 skrll 3077: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.51 skrll 3078: struct usbd_device *dev = pipe->up_dev;
3079: struct usbd_port *up = dev->ud_powersrc;
3080: struct usbd_device *hub;
3081: struct usbd_device *adev;
3082: uint8_t rhport = 0;
3083: uint32_t route = 0;
3084:
3085: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3086:
3087: /* Locate root hub port and Determine route string */
3088: /* 4.3.3 route string does not include roothub port */
3089: for (hub = dev; hub != NULL; hub = hub->ud_myhub) {
3090: uint32_t dep;
3091:
1.72.2.2 snj 3092: DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd",
3093: (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc,
3094: hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno :
3095: -1);
1.51 skrll 3096:
3097: if (hub->ud_powersrc == NULL)
3098: break;
3099: dep = hub->ud_depth;
3100: if (dep == 0)
3101: break;
3102: rhport = hub->ud_powersrc->up_portno;
3103: if (dep > USB_HUB_MAX_DEPTH)
3104: continue;
3105:
3106: route |=
3107: (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport)
3108: << ((dep - 1) * 4);
3109: }
3110: route = route >> 4;
1.68 skrll 3111: size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1;
1.51 skrll 3112:
3113: /* Locate port on upstream high speed hub */
3114: for (adev = dev, hub = up->up_parent;
3115: hub != NULL && hub->ud_speed != USB_SPEED_HIGH;
3116: adev = hub, hub = hub->ud_myhub)
3117: ;
3118: if (hub) {
3119: int p;
3120: for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) {
3121: if (hub->ud_hub->uh_ports[p].up_dev == adev) {
3122: dev->ud_myhsport = &hub->ud_hub->uh_ports[p];
3123: goto found;
3124: }
3125: }
1.68 skrll 3126: panic("%s: cannot find HS port", __func__);
1.51 skrll 3127: found:
1.72.2.2 snj 3128: DPRINTFN(4, "high speed port %jd", p, 0, 0, 0);
1.51 skrll 3129: } else {
3130: dev->ud_myhsport = NULL;
3131: }
3132:
1.68 skrll 3133: const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport);
3134:
1.72.2.2 snj 3135: DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport,
3136: ctlrport, route, (uintptr_t)hub);
1.68 skrll 3137:
1.51 skrll 3138: cp[0] |= XHCI_SCTX_0_ROUTE_SET(route);
1.68 skrll 3139: cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport);
1.51 skrll 3140: }
3141:
3142: /*
3143: * Setup whether device is hub, whether device uses MTT, and
3144: * TT informations if it uses MTT.
3145: */
3146: static void
3147: xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp)
3148: {
3149: struct usbd_device *dev = pipe->up_dev;
1.72.2.5! snj 3150: struct usbd_port *myhsport = dev->ud_myhsport;
1.51 skrll 3151: usb_device_descriptor_t * const dd = &dev->ud_ddesc;
3152: uint32_t speed = dev->ud_speed;
1.72.2.5! snj 3153: uint8_t rhaddr = dev->ud_bus->ub_rhaddr;
1.51 skrll 3154: uint8_t tthubslot, ttportnum;
3155: bool ishub;
3156: bool usemtt;
3157:
3158: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3159:
3160: /*
3161: * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2
3162: * tthubslot:
3163: * This is the slot ID of parent HS hub
3164: * if LS/FS device is connected && connected through HS hub.
3165: * This is 0 if device is not LS/FS device ||
3166: * parent hub is not HS hub ||
3167: * attached to root hub.
3168: * ttportnum:
3169: * This is the downstream facing port of parent HS hub
3170: * if LS/FS device is connected.
3171: * This is 0 if device is not LS/FS device ||
3172: * parent hub is not HS hub ||
3173: * attached to root hub.
3174: */
1.72.2.5! snj 3175: if (myhsport &&
! 3176: myhsport->up_parent->ud_addr != rhaddr &&
1.51 skrll 3177: (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) {
1.72.2.5! snj 3178: ttportnum = myhsport->up_portno;
! 3179: tthubslot = myhsport->up_parent->ud_addr;
1.51 skrll 3180: } else {
3181: ttportnum = 0;
3182: tthubslot = 0;
3183: }
1.72.2.2 snj 3184: DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd",
1.72.2.5! snj 3185: (uintptr_t)myhsport, ttportnum, tthubslot, 0);
1.51 skrll 3186:
3187: /* ishub is valid after reading UDESC_DEVICE */
3188: ishub = (dd->bDeviceClass == UDCLASS_HUB);
3189:
3190: /* dev->ud_hub is valid after reading UDESC_HUB */
3191: if (ishub && dev->ud_hub) {
3192: usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc;
3193: uint8_t ttt =
3194: __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK);
3195:
3196: cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts);
3197: cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt);
1.72.2.2 snj 3198: DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0);
1.51 skrll 3199: }
3200:
1.72.2.5! snj 3201: #define IS_MTTHUB(dd) \
! 3202: ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT)
1.51 skrll 3203:
3204: /*
3205: * MTT flag is set if
1.72.2.5! snj 3206: * 1. this is HS hub && MTTs are supported and enabled; or
! 3207: * 2. this is LS or FS device && there is a parent HS hub where MTTs
! 3208: * are supported and enabled.
! 3209: *
! 3210: * XXX enabled is not tested yet
1.51 skrll 3211: */
1.72.2.5! snj 3212: if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd))
1.51 skrll 3213: usemtt = true;
1.72.2.5! snj 3214: else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) &&
! 3215: myhsport &&
! 3216: myhsport->up_parent->ud_addr != rhaddr &&
! 3217: IS_MTTHUB(&myhsport->up_parent->ud_ddesc))
1.51 skrll 3218: usemtt = true;
3219: else
3220: usemtt = false;
1.72.2.2 snj 3221: DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd",
1.51 skrll 3222: dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt);
3223:
1.72.2.5! snj 3224: #undef IS_MTTHUB
1.51 skrll 3225:
3226: cp[0] |=
3227: XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) |
3228: XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0);
3229: cp[2] |=
3230: XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) |
3231: XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum);
3232: }
3233:
3234: /* set up params for periodic endpoint */
3235: static void
3236: xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp)
3237: {
3238: struct usbd_device *dev = pipe->up_dev;
3239: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
3240: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
3241: usbd_desc_iter_t iter;
3242: const usb_cdc_descriptor_t *cdcd;
3243: uint32_t maxb = 0;
3244: uint16_t mps = UGETW(ed->wMaxPacketSize);
3245: uint8_t speed = dev->ud_speed;
3246: uint8_t ep;
3247:
3248: /* config desc is NULL when opening ep0 */
3249: if (dev == NULL || dev->ud_cdesc == NULL)
3250: goto no_cdcd;
3251: cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev,
3252: UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY);
3253: if (cdcd == NULL)
3254: goto no_cdcd;
3255: usb_desc_iter_init(dev, &iter);
3256: iter.cur = (const void *)cdcd;
3257:
3258: /* find endpoint_ss_comp desc for ep of this pipe */
3259: for (ep = 0;;) {
3260: cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter);
3261: if (cdcd == NULL)
3262: break;
3263: if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) {
3264: ep = ((const usb_endpoint_descriptor_t *)cdcd)->
3265: bEndpointAddress;
3266: if (UE_GET_ADDR(ep) ==
3267: UE_GET_ADDR(ed->bEndpointAddress)) {
3268: cdcd = (const usb_cdc_descriptor_t *)
3269: usb_desc_iter_next(&iter);
3270: break;
3271: }
3272: ep = 0;
3273: }
3274: }
3275: if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) {
3276: const usb_endpoint_ss_comp_descriptor_t * esscd =
3277: (const usb_endpoint_ss_comp_descriptor_t *)cdcd;
3278: maxb = esscd->bMaxBurst;
3279: }
3280:
3281: no_cdcd:
3282: /* 6.2.3.4, 4.8.2.4 */
3283: if (USB_IS_SS(speed)) {
1.60 skrll 3284: /* USB 3.1 9.6.6 */
1.51 skrll 3285: cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps);
1.60 skrll 3286: /* USB 3.1 9.6.7 */
1.51 skrll 3287: cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb);
3288: #ifdef notyet
3289: if (xfertype == UE_ISOCHRONOUS) {
3290: }
3291: if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) {
3292: /* use ESIT */
3293: cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x);
3294: cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x);
3295:
3296: /* XXX if LEC = 1, set ESIT instead */
3297: cp[0] |= XHCI_EPCTX_0_MULT_SET(0);
3298: } else {
3299: /* use ival */
3300: }
3301: #endif
3302: } else {
1.60 skrll 3303: /* USB 2.0 9.6.6 */
1.51 skrll 3304: cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps));
1.1 jakllsch 3305:
1.51 skrll 3306: /* 6.2.3.4 */
3307: if (speed == USB_SPEED_HIGH &&
3308: (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) {
3309: maxb = UE_GET_TRANS(mps);
3310: } else {
3311: /* LS/FS or HS CTRL or HS BULK */
3312: maxb = 0;
3313: }
3314: cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb);
3315: }
3316: }
1.1 jakllsch 3317:
1.51 skrll 3318: /*
3319: * Convert endpoint bInterval value to endpoint context interval value
3320: * for Interrupt pipe.
3321: * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6
3322: */
3323: static uint32_t
3324: xhci_bival2ival(uint32_t ival, uint32_t speed)
3325: {
3326: if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
3327: int i;
1.1 jakllsch 3328:
1.51 skrll 3329: /*
3330: * round ival down to "the nearest base 2 multiple of
3331: * bInterval * 8".
3332: * bInterval is at most 255 as its type is uByte.
3333: * 255(ms) = 2040(x 125us) < 2^11, so start with 10.
3334: */
3335: for (i = 10; i > 0; i--) {
3336: if ((ival * 8) >= (1 << i))
3337: break;
3338: }
3339: ival = i;
3340: } else {
3341: /* Interval = bInterval-1 for SS/HS */
3342: ival--;
3343: }
1.1 jakllsch 3344:
1.51 skrll 3345: return ival;
1.1 jakllsch 3346: }
3347:
3348: /* ----- */
3349:
3350: static void
1.34 skrll 3351: xhci_noop(struct usbd_pipe *pipe)
1.1 jakllsch 3352: {
1.27 skrll 3353: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3354: }
3355:
1.34 skrll 3356: /*
3357: * Process root hub request.
3358: */
3359: static int
3360: xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
3361: void *buf, int buflen)
1.1 jakllsch 3362: {
1.34 skrll 3363: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 3364: usb_port_status_t ps;
3365: int l, totlen = 0;
1.34 skrll 3366: uint16_t len, value, index;
1.1 jakllsch 3367: int port, i;
3368: uint32_t v;
3369:
1.27 skrll 3370: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3371:
3372: if (sc->sc_dying)
1.34 skrll 3373: return -1;
1.1 jakllsch 3374:
1.68 skrll 3375: size_t bn = bus == &sc->sc_bus ? 0 : 1;
3376:
1.34 skrll 3377: len = UGETW(req->wLength);
1.1 jakllsch 3378: value = UGETW(req->wValue);
3379: index = UGETW(req->wIndex);
3380:
1.72.2.2 snj 3381: DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx",
1.27 skrll 3382: req->bmRequestType | (req->bRequest << 8), value, index, len);
1.1 jakllsch 3383:
3384: #define C(x,y) ((x) | ((y) << 8))
1.34 skrll 3385: switch (C(req->bRequest, req->bmRequestType)) {
1.1 jakllsch 3386: case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1.72.2.2 snj 3387: DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0);
1.1 jakllsch 3388: if (len == 0)
3389: break;
1.34 skrll 3390: switch (value) {
3391: case C(0, UDESC_DEVICE): {
3392: usb_device_descriptor_t devd;
3393: totlen = min(buflen, sizeof(devd));
3394: memcpy(&devd, buf, totlen);
3395: USETW(devd.idVendor, sc->sc_id_vendor);
3396: memcpy(buf, &devd, totlen);
1.1 jakllsch 3397: break;
1.34 skrll 3398: }
3399: #define sd ((usb_string_descriptor_t *)buf)
3400: case C(1, UDESC_STRING):
3401: /* Vendor */
3402: totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
3403: break;
3404: case C(2, UDESC_STRING):
3405: /* Product */
3406: totlen = usb_makestrdesc(sd, len, "xHCI Root Hub");
1.1 jakllsch 3407: break;
3408: #undef sd
3409: default:
1.34 skrll 3410: /* default from usbroothub */
3411: return buflen;
1.1 jakllsch 3412: }
3413: break;
1.34 skrll 3414:
1.1 jakllsch 3415: /* Hub requests */
3416: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3417: break;
1.34 skrll 3418: /* Clear Port Feature request */
1.68 skrll 3419: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): {
3420: const size_t cp = xhci_rhport2ctlrport(sc, bn, index);
3421:
1.72.2.2 snj 3422: DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd",
1.68 skrll 3423: index, value, bn, cp);
3424: if (index < 1 || index > sc->sc_rhportcount[bn]) {
1.34 skrll 3425: return -1;
1.1 jakllsch 3426: }
1.68 skrll 3427: port = XHCI_PORTSC(cp);
1.1 jakllsch 3428: v = xhci_op_read_4(sc, port);
1.72.2.2 snj 3429: DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0);
1.1 jakllsch 3430: v &= ~XHCI_PS_CLEAR;
3431: switch (value) {
3432: case UHF_PORT_ENABLE:
1.34 skrll 3433: xhci_op_write_4(sc, port, v & ~XHCI_PS_PED);
1.1 jakllsch 3434: break;
3435: case UHF_PORT_SUSPEND:
1.34 skrll 3436: return -1;
1.1 jakllsch 3437: case UHF_PORT_POWER:
3438: break;
3439: case UHF_PORT_TEST:
3440: case UHF_PORT_INDICATOR:
1.34 skrll 3441: return -1;
1.1 jakllsch 3442: case UHF_C_PORT_CONNECTION:
3443: xhci_op_write_4(sc, port, v | XHCI_PS_CSC);
3444: break;
3445: case UHF_C_PORT_ENABLE:
3446: case UHF_C_PORT_SUSPEND:
3447: case UHF_C_PORT_OVER_CURRENT:
1.34 skrll 3448: return -1;
3449: case UHF_C_BH_PORT_RESET:
3450: xhci_op_write_4(sc, port, v | XHCI_PS_WRC);
3451: break;
1.1 jakllsch 3452: case UHF_C_PORT_RESET:
3453: xhci_op_write_4(sc, port, v | XHCI_PS_PRC);
3454: break;
1.34 skrll 3455: case UHF_C_PORT_LINK_STATE:
3456: xhci_op_write_4(sc, port, v | XHCI_PS_PLC);
3457: break;
3458: case UHF_C_PORT_CONFIG_ERROR:
3459: xhci_op_write_4(sc, port, v | XHCI_PS_CEC);
3460: break;
1.1 jakllsch 3461: default:
1.34 skrll 3462: return -1;
1.1 jakllsch 3463: }
3464: break;
1.68 skrll 3465: }
1.1 jakllsch 3466: case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3467: if (len == 0)
3468: break;
3469: if ((value & 0xff) != 0) {
1.34 skrll 3470: return -1;
1.1 jakllsch 3471: }
1.34 skrll 3472: usb_hub_descriptor_t hubd;
3473:
3474: totlen = min(buflen, sizeof(hubd));
3475: memcpy(&hubd, buf, totlen);
1.68 skrll 3476: hubd.bNbrPorts = sc->sc_rhportcount[bn];
1.1 jakllsch 3477: USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH);
3478: hubd.bPwrOn2PwrGood = 200;
1.68 skrll 3479: for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) {
3480: /* XXX can't find out? */
3481: hubd.DeviceRemovable[i++] = 0;
3482: }
1.3 skrll 3483: hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1.34 skrll 3484: totlen = min(totlen, hubd.bDescLength);
3485: memcpy(buf, &hubd, totlen);
1.1 jakllsch 3486: break;
3487: case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3488: if (len != 4) {
1.34 skrll 3489: return -1;
1.1 jakllsch 3490: }
3491: memset(buf, 0, len); /* ? XXX */
3492: totlen = len;
3493: break;
1.34 skrll 3494: /* Get Port Status request */
1.68 skrll 3495: case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): {
3496: const size_t cp = xhci_rhport2ctlrport(sc, bn, index);
3497:
1.72.2.2 snj 3498: DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju",
3499: bn, index, cp, 0);
1.68 skrll 3500: if (index < 1 || index > sc->sc_rhportcount[bn]) {
1.34 skrll 3501: return -1;
1.1 jakllsch 3502: }
3503: if (len != 4) {
1.34 skrll 3504: return -1;
1.1 jakllsch 3505: }
1.68 skrll 3506: v = xhci_op_read_4(sc, XHCI_PORTSC(cp));
1.72.2.2 snj 3507: DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0);
1.34 skrll 3508: i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v));
1.1 jakllsch 3509: if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS;
3510: if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED;
3511: if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
3512: //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND;
3513: if (v & XHCI_PS_PR) i |= UPS_RESET;
1.34 skrll 3514: if (v & XHCI_PS_PP) {
3515: if (i & UPS_OTHER_SPEED)
3516: i |= UPS_PORT_POWER_SS;
3517: else
3518: i |= UPS_PORT_POWER;
3519: }
3520: if (i & UPS_OTHER_SPEED)
3521: i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v));
3522: if (sc->sc_vendor_port_status)
3523: i = sc->sc_vendor_port_status(sc, v, i);
1.1 jakllsch 3524: USETW(ps.wPortStatus, i);
3525: i = 0;
3526: if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
3527: if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
3528: if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
3529: if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET;
1.34 skrll 3530: if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET;
3531: if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE;
3532: if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR;
1.1 jakllsch 3533: USETW(ps.wPortChange, i);
1.34 skrll 3534: totlen = min(len, sizeof(ps));
3535: memcpy(buf, &ps, totlen);
1.1 jakllsch 3536: break;
1.68 skrll 3537: }
1.1 jakllsch 3538: case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1.34 skrll 3539: return -1;
3540: case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE):
3541: break;
1.1 jakllsch 3542: case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3543: break;
1.34 skrll 3544: /* Set Port Feature request */
3545: case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): {
3546: int optval = (index >> 8) & 0xff;
3547: index &= 0xff;
1.68 skrll 3548: if (index < 1 || index > sc->sc_rhportcount[bn]) {
1.34 skrll 3549: return -1;
1.1 jakllsch 3550: }
1.68 skrll 3551:
3552: const size_t cp = xhci_rhport2ctlrport(sc, bn, index);
3553:
3554: port = XHCI_PORTSC(cp);
1.1 jakllsch 3555: v = xhci_op_read_4(sc, port);
1.72.2.2 snj 3556: DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0);
1.1 jakllsch 3557: v &= ~XHCI_PS_CLEAR;
3558: switch (value) {
3559: case UHF_PORT_ENABLE:
3560: xhci_op_write_4(sc, port, v | XHCI_PS_PED);
3561: break;
3562: case UHF_PORT_SUSPEND:
3563: /* XXX suspend */
3564: break;
3565: case UHF_PORT_RESET:
1.34 skrll 3566: v &= ~(XHCI_PS_PED | XHCI_PS_PR);
1.1 jakllsch 3567: xhci_op_write_4(sc, port, v | XHCI_PS_PR);
3568: /* Wait for reset to complete. */
3569: usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3570: if (sc->sc_dying) {
1.34 skrll 3571: return -1;
1.1 jakllsch 3572: }
3573: v = xhci_op_read_4(sc, port);
3574: if (v & XHCI_PS_PR) {
3575: xhci_op_write_4(sc, port, v & ~XHCI_PS_PR);
3576: usb_delay_ms(&sc->sc_bus, 10);
3577: /* XXX */
3578: }
3579: break;
3580: case UHF_PORT_POWER:
3581: /* XXX power control */
3582: break;
3583: /* XXX more */
3584: case UHF_C_PORT_RESET:
3585: xhci_op_write_4(sc, port, v | XHCI_PS_PRC);
3586: break;
1.34 skrll 3587: case UHF_PORT_U1_TIMEOUT:
3588: if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) {
3589: return -1;
3590: }
1.68 skrll 3591: port = XHCI_PORTPMSC(cp);
1.34 skrll 3592: v = xhci_op_read_4(sc, port);
1.72.2.2 snj 3593: DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx",
3594: index, cp, v, 0);
1.34 skrll 3595: v &= ~XHCI_PM3_U1TO_SET(0xff);
3596: v |= XHCI_PM3_U1TO_SET(optval);
3597: xhci_op_write_4(sc, port, v);
3598: break;
3599: case UHF_PORT_U2_TIMEOUT:
3600: if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) {
3601: return -1;
3602: }
1.68 skrll 3603: port = XHCI_PORTPMSC(cp);
1.34 skrll 3604: v = xhci_op_read_4(sc, port);
1.72.2.2 snj 3605: DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx",
3606: index, cp, v, 0);
1.34 skrll 3607: v &= ~XHCI_PM3_U2TO_SET(0xff);
3608: v |= XHCI_PM3_U2TO_SET(optval);
3609: xhci_op_write_4(sc, port, v);
3610: break;
1.1 jakllsch 3611: default:
1.34 skrll 3612: return -1;
1.1 jakllsch 3613: }
1.34 skrll 3614: }
1.1 jakllsch 3615: break;
3616: case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3617: case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3618: case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3619: case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3620: break;
3621: default:
1.34 skrll 3622: /* default from usbroothub */
3623: return buflen;
1.1 jakllsch 3624: }
1.27 skrll 3625:
1.34 skrll 3626: return totlen;
1.1 jakllsch 3627: }
3628:
1.28 skrll 3629: /* root hub interrupt */
1.1 jakllsch 3630:
3631: static usbd_status
1.34 skrll 3632: xhci_root_intr_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3633: {
1.34 skrll 3634: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3635: usbd_status err;
3636:
1.27 skrll 3637: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3638:
1.1 jakllsch 3639: /* Insert last in queue. */
3640: mutex_enter(&sc->sc_lock);
3641: err = usb_insert_transfer(xfer);
3642: mutex_exit(&sc->sc_lock);
3643: if (err)
3644: return err;
3645:
3646: /* Pipe isn't running, start first */
1.34 skrll 3647: return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3648: }
3649:
1.34 skrll 3650: /* Wait for roothub port status/change */
1.1 jakllsch 3651: static usbd_status
1.34 skrll 3652: xhci_root_intr_start(struct usbd_xfer *xfer)
1.1 jakllsch 3653: {
1.34 skrll 3654: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.68 skrll 3655: const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1;
1.1 jakllsch 3656:
1.27 skrll 3657: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3658:
1.1 jakllsch 3659: if (sc->sc_dying)
3660: return USBD_IOERROR;
3661:
3662: mutex_enter(&sc->sc_lock);
1.68 skrll 3663: sc->sc_intrxfer[bn] = xfer;
1.1 jakllsch 3664: mutex_exit(&sc->sc_lock);
3665:
3666: return USBD_IN_PROGRESS;
3667: }
3668:
3669: static void
1.34 skrll 3670: xhci_root_intr_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3671: {
1.34 skrll 3672: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.68 skrll 3673: const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1;
1.1 jakllsch 3674:
1.27 skrll 3675: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3676:
1.1 jakllsch 3677: KASSERT(mutex_owned(&sc->sc_lock));
1.34 skrll 3678: KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
1.21 skrll 3679:
1.68 skrll 3680: sc->sc_intrxfer[bn] = NULL;
1.22 skrll 3681:
1.34 skrll 3682: xfer->ux_status = USBD_CANCELLED;
1.1 jakllsch 3683: usb_transfer_complete(xfer);
3684: }
3685:
3686: static void
1.34 skrll 3687: xhci_root_intr_close(struct usbd_pipe *pipe)
1.1 jakllsch 3688: {
1.34 skrll 3689: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.68 skrll 3690: const struct usbd_xfer *xfer = pipe->up_intrxfer;
3691: const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1;
1.1 jakllsch 3692:
1.27 skrll 3693: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3694:
1.1 jakllsch 3695: KASSERT(mutex_owned(&sc->sc_lock));
3696:
1.68 skrll 3697: sc->sc_intrxfer[bn] = NULL;
1.1 jakllsch 3698: }
3699:
3700: static void
1.34 skrll 3701: xhci_root_intr_done(struct usbd_xfer *xfer)
1.1 jakllsch 3702: {
1.27 skrll 3703: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3704:
1.1 jakllsch 3705: }
3706:
3707: /* -------------- */
3708: /* device control */
3709:
3710: static usbd_status
1.34 skrll 3711: xhci_device_ctrl_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3712: {
1.34 skrll 3713: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3714: usbd_status err;
3715:
1.27 skrll 3716: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3717:
1.1 jakllsch 3718: /* Insert last in queue. */
3719: mutex_enter(&sc->sc_lock);
3720: err = usb_insert_transfer(xfer);
3721: mutex_exit(&sc->sc_lock);
3722: if (err)
1.34 skrll 3723: return err;
1.1 jakllsch 3724:
3725: /* Pipe isn't running, start first */
1.34 skrll 3726: return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3727: }
3728:
3729: static usbd_status
1.34 skrll 3730: xhci_device_ctrl_start(struct usbd_xfer *xfer)
1.1 jakllsch 3731: {
1.34 skrll 3732: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
3733: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3734: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3735: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.35 skrll 3736: struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer);
1.34 skrll 3737: usb_device_request_t * const req = &xfer->ux_request;
3738: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 3739: const uint32_t len = UGETW(req->wLength);
1.34 skrll 3740: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3741: uint64_t parameter;
3742: uint32_t status;
3743: uint32_t control;
3744: u_int i;
3745:
1.27 skrll 3746: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 3747: DPRINTFN(12, "req: %04jx %04jx %04jx %04jx",
1.27 skrll 3748: req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue),
3749: UGETW(req->wIndex), UGETW(req->wLength));
1.1 jakllsch 3750:
3751: /* we rely on the bottom bits for extra info */
1.59 maya 3752: KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx",
3753: (uintptr_t) xfer);
1.1 jakllsch 3754:
1.34 skrll 3755: KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0);
1.1 jakllsch 3756:
3757: i = 0;
3758:
3759: /* setup phase */
1.63 skrll 3760: memcpy(¶meter, req, sizeof(parameter));
1.1 jakllsch 3761: status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req));
3762: control = ((len == 0) ? XHCI_TRB_3_TRT_NONE :
3763: (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) |
3764: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
3765: XHCI_TRB_3_IDT_BIT;
3766: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3767:
1.34 skrll 3768: if (len != 0) {
3769: /* data phase */
3770: parameter = DMAADDR(dma, 0);
1.59 maya 3771: KASSERTMSG(len <= 0x10000, "len %d", len);
1.34 skrll 3772: status = XHCI_TRB_2_IRQ_SET(0) |
3773: XHCI_TRB_2_TDSZ_SET(1) |
3774: XHCI_TRB_2_BYTES_SET(len);
3775: control = (isread ? XHCI_TRB_3_DIR_IN : 0) |
3776: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1.63 skrll 3777: (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) |
1.34 skrll 3778: XHCI_TRB_3_IOC_BIT;
3779: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3780: }
1.1 jakllsch 3781:
3782: parameter = 0;
1.28 skrll 3783: status = XHCI_TRB_2_IRQ_SET(0);
1.1 jakllsch 3784: /* the status stage has inverted direction */
1.28 skrll 3785: control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) |
1.1 jakllsch 3786: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
3787: XHCI_TRB_3_IOC_BIT;
3788: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3789:
3790: mutex_enter(&tr->xr_lock);
3791: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
3792: mutex_exit(&tr->xr_lock);
3793:
3794: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
3795:
1.72.2.1 snj 3796: if (xfer->ux_timeout && !xhci_polling_p(sc)) {
1.34 skrll 3797: callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1.1 jakllsch 3798: xhci_timeout, xfer);
3799: }
3800:
3801: return USBD_IN_PROGRESS;
3802: }
3803:
3804: static void
1.34 skrll 3805: xhci_device_ctrl_done(struct usbd_xfer *xfer)
1.1 jakllsch 3806: {
1.27 skrll 3807: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3808: usb_device_request_t *req = &xfer->ux_request;
3809: int len = UGETW(req->wLength);
3810: int rd = req->bmRequestType & UT_READ;
1.1 jakllsch 3811:
1.34 skrll 3812: if (len)
3813: usb_syncmem(&xfer->ux_dmabuf, 0, len,
3814: rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.1 jakllsch 3815: }
3816:
3817: static void
1.34 skrll 3818: xhci_device_ctrl_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3819: {
1.27 skrll 3820: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3821:
3822: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 3823: }
3824:
3825: static void
1.34 skrll 3826: xhci_device_ctrl_close(struct usbd_pipe *pipe)
1.1 jakllsch 3827: {
1.27 skrll 3828: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3829:
3830: xhci_close_pipe(pipe);
1.1 jakllsch 3831: }
3832:
1.34 skrll 3833: /* ------------------ */
3834: /* device isochronous */
1.1 jakllsch 3835:
3836: /* ----------- */
3837: /* device bulk */
3838:
3839: static usbd_status
1.34 skrll 3840: xhci_device_bulk_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3841: {
1.34 skrll 3842: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3843: usbd_status err;
3844:
1.27 skrll 3845: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3846:
1.1 jakllsch 3847: /* Insert last in queue. */
3848: mutex_enter(&sc->sc_lock);
3849: err = usb_insert_transfer(xfer);
3850: mutex_exit(&sc->sc_lock);
3851: if (err)
3852: return err;
3853:
3854: /*
3855: * Pipe isn't running (otherwise err would be USBD_INPROG),
3856: * so start it first.
3857: */
1.34 skrll 3858: return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3859: }
3860:
3861: static usbd_status
1.34 skrll 3862: xhci_device_bulk_start(struct usbd_xfer *xfer)
1.1 jakllsch 3863: {
1.34 skrll 3864: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
3865: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3866: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3867: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.35 skrll 3868: struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer);
1.34 skrll 3869: const uint32_t len = xfer->ux_length;
3870: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3871: uint64_t parameter;
3872: uint32_t status;
3873: uint32_t control;
3874: u_int i = 0;
3875:
1.27 skrll 3876: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3877:
1.72.2.2 snj 3878: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
3879: 0);
1.1 jakllsch 3880:
3881: if (sc->sc_dying)
3882: return USBD_IOERROR;
3883:
1.34 skrll 3884: KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0);
1.1 jakllsch 3885:
3886: parameter = DMAADDR(dma, 0);
1.11 dsl 3887: /*
1.13 dsl 3888: * XXX: (dsl) The physical buffer must not cross a 64k boundary.
1.11 dsl 3889: * If the user supplied buffer crosses such a boundary then 2
3890: * (or more) TRB should be used.
3891: * If multiple TRB are used the td_size field must be set correctly.
3892: * For v1.0 devices (like ivy bridge) this is the number of usb data
3893: * blocks needed to complete the transfer.
3894: * Setting it to 1 in the last TRB causes an extra zero-length
3895: * data block be sent.
3896: * The earlier documentation differs, I don't know how it behaves.
3897: */
1.59 maya 3898: KASSERTMSG(len <= 0x10000, "len %d", len);
1.1 jakllsch 3899: status = XHCI_TRB_2_IRQ_SET(0) |
3900: XHCI_TRB_2_TDSZ_SET(1) |
3901: XHCI_TRB_2_BYTES_SET(len);
3902: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1.63 skrll 3903: (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) |
3904: XHCI_TRB_3_IOC_BIT;
1.1 jakllsch 3905: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3906:
3907: mutex_enter(&tr->xr_lock);
3908: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
3909: mutex_exit(&tr->xr_lock);
3910:
3911: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
3912:
1.72.2.1 snj 3913: if (xfer->ux_timeout && !xhci_polling_p(sc)) {
1.34 skrll 3914: callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
3915: xhci_timeout, xfer);
3916: }
3917:
1.1 jakllsch 3918: return USBD_IN_PROGRESS;
3919: }
3920:
3921: static void
1.34 skrll 3922: xhci_device_bulk_done(struct usbd_xfer *xfer)
1.1 jakllsch 3923: {
1.27 skrll 3924: #ifdef USB_DEBUG
1.34 skrll 3925: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3926: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.27 skrll 3927: #endif
1.34 skrll 3928: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 3929:
1.27 skrll 3930: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3931:
1.72.2.2 snj 3932: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
3933: 0);
1.1 jakllsch 3934:
1.34 skrll 3935: usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1.1 jakllsch 3936: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3937: }
3938:
3939: static void
1.34 skrll 3940: xhci_device_bulk_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3941: {
1.27 skrll 3942: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3943:
3944: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 3945: }
3946:
3947: static void
1.34 skrll 3948: xhci_device_bulk_close(struct usbd_pipe *pipe)
1.1 jakllsch 3949: {
1.27 skrll 3950: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.34 skrll 3951:
3952: xhci_close_pipe(pipe);
1.1 jakllsch 3953: }
3954:
1.34 skrll 3955: /* ---------------- */
3956: /* device interrupt */
1.1 jakllsch 3957:
3958: static usbd_status
1.34 skrll 3959: xhci_device_intr_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3960: {
1.34 skrll 3961: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3962: usbd_status err;
3963:
1.27 skrll 3964: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3965:
1.1 jakllsch 3966: /* Insert last in queue. */
3967: mutex_enter(&sc->sc_lock);
3968: err = usb_insert_transfer(xfer);
3969: mutex_exit(&sc->sc_lock);
3970: if (err)
3971: return err;
3972:
3973: /*
3974: * Pipe isn't running (otherwise err would be USBD_INPROG),
3975: * so start it first.
3976: */
1.34 skrll 3977: return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3978: }
3979:
3980: static usbd_status
1.34 skrll 3981: xhci_device_intr_start(struct usbd_xfer *xfer)
1.1 jakllsch 3982: {
1.34 skrll 3983: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
3984: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3985: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3986: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1.35 skrll 3987: struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer);
1.34 skrll 3988: const uint32_t len = xfer->ux_length;
3989: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3990: uint64_t parameter;
3991: uint32_t status;
3992: uint32_t control;
3993: u_int i = 0;
3994:
1.27 skrll 3995: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3996:
1.72.2.2 snj 3997: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
3998: 0);
1.1 jakllsch 3999:
4000: if (sc->sc_dying)
4001: return USBD_IOERROR;
4002:
1.34 skrll 4003: KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0);
1.1 jakllsch 4004:
4005: parameter = DMAADDR(dma, 0);
1.59 maya 4006: KASSERTMSG(len <= 0x10000, "len %d", len);
1.1 jakllsch 4007: status = XHCI_TRB_2_IRQ_SET(0) |
4008: XHCI_TRB_2_TDSZ_SET(1) |
4009: XHCI_TRB_2_BYTES_SET(len);
4010: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1.63 skrll 4011: (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) |
4012: XHCI_TRB_3_IOC_BIT;
1.1 jakllsch 4013: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
4014:
4015: mutex_enter(&tr->xr_lock);
4016: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
4017: mutex_exit(&tr->xr_lock);
4018:
4019: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4020:
1.72.2.1 snj 4021: if (xfer->ux_timeout && !xhci_polling_p(sc)) {
1.34 skrll 4022: callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
4023: xhci_timeout, xfer);
4024: }
4025:
1.1 jakllsch 4026: return USBD_IN_PROGRESS;
4027: }
4028:
4029: static void
1.34 skrll 4030: xhci_device_intr_done(struct usbd_xfer *xfer)
1.1 jakllsch 4031: {
1.34 skrll 4032: struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer);
1.27 skrll 4033: #ifdef USB_DEBUG
1.34 skrll 4034: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
4035: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.19 ozaki-r 4036: #endif
1.34 skrll 4037: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 4038:
1.27 skrll 4039: XHCIHIST_FUNC(); XHCIHIST_CALLED();
4040:
1.72.2.2 snj 4041: DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci,
4042: 0);
1.1 jakllsch 4043:
1.72.2.1 snj 4044: KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock));
1.1 jakllsch 4045:
1.34 skrll 4046: usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1.1 jakllsch 4047: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
4048: }
4049:
4050: static void
1.34 skrll 4051: xhci_device_intr_abort(struct usbd_xfer *xfer)
1.1 jakllsch 4052: {
1.34 skrll 4053: struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer);
1.27 skrll 4054:
4055: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.10 skrll 4056:
4057: KASSERT(mutex_owned(&sc->sc_lock));
1.72.2.2 snj 4058: DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0);
1.34 skrll 4059: KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
4060: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 4061: }
4062:
4063: static void
1.34 skrll 4064: xhci_device_intr_close(struct usbd_pipe *pipe)
1.1 jakllsch 4065: {
1.34 skrll 4066: //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.27 skrll 4067:
4068: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.72.2.2 snj 4069: DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0);
1.27 skrll 4070:
1.34 skrll 4071: xhci_close_pipe(pipe);
1.1 jakllsch 4072: }
4073:
4074: /* ------------ */
4075:
4076: static void
4077: xhci_timeout(void *addr)
4078: {
4079: struct xhci_xfer * const xx = addr;
1.34 skrll 4080: struct usbd_xfer * const xfer = &xx->xx_xfer;
4081: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 4082:
1.27 skrll 4083: XHCIHIST_FUNC(); XHCIHIST_CALLED();
4084:
1.1 jakllsch 4085: if (sc->sc_dying) {
4086: return;
4087: }
4088:
4089: usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr,
4090: USB_TASKQ_MPSAFE);
1.34 skrll 4091: usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task,
1.1 jakllsch 4092: USB_TASKQ_HC);
4093: }
4094:
4095: static void
4096: xhci_timeout_task(void *addr)
4097: {
1.34 skrll 4098: struct usbd_xfer * const xfer = addr;
4099: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 4100:
1.27 skrll 4101: XHCIHIST_FUNC(); XHCIHIST_CALLED();
4102:
1.1 jakllsch 4103: mutex_enter(&sc->sc_lock);
4104: xhci_abort_xfer(xfer, USBD_TIMEOUT);
4105: mutex_exit(&sc->sc_lock);
4106: }
CVSweb <webmaster@jp.NetBSD.org>
![[BACK]](/icons/back.gif){kind=icon}
Return to xhci.c CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [cvs.NetBSD.org] / src / sys / dev / usb