Annotation of src/sys/dev/usb/xhci.c, Revision 1.28.2.51
1.28.2.51! skrll 1: /* $NetBSD: xhci.c,v 1.28.2.50 2016/02/06 08:50:52 skrll Exp $ */
1.1 jakllsch 2:
3: /*
4: * Copyright (c) 2013 Jonathan A. Kollasch
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17: * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20: * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21: * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23: * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27: */
28:
1.28.2.21 skrll 29: /*
30: * USB rev 3.1 specification
31: * http://www.usb.org/developers/docs/usb_31_040315.zip
32: * USB rev 2.0 specification
33: * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip
34: * xHCI rev 1.1 specification
35: * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
36: */
37:
1.1 jakllsch 38: #include <sys/cdefs.h>
1.28.2.51! skrll 39: __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.50 2016/02/06 08:50:52 skrll Exp $");
1.27 skrll 40:
41: #include "opt_usb.h"
1.1 jakllsch 42:
43: #include <sys/param.h>
44: #include <sys/systm.h>
45: #include <sys/kernel.h>
46: #include <sys/kmem.h>
47: #include <sys/device.h>
48: #include <sys/select.h>
49: #include <sys/proc.h>
50: #include <sys/queue.h>
51: #include <sys/mutex.h>
52: #include <sys/condvar.h>
53: #include <sys/bus.h>
54: #include <sys/cpu.h>
1.27 skrll 55: #include <sys/sysctl.h>
1.1 jakllsch 56:
57: #include <machine/endian.h>
58:
59: #include <dev/usb/usb.h>
60: #include <dev/usb/usbdi.h>
61: #include <dev/usb/usbdivar.h>
1.28.2.19 skrll 62: #include <dev/usb/usbdi_util.h>
1.27 skrll 63: #include <dev/usb/usbhist.h>
1.1 jakllsch 64: #include <dev/usb/usb_mem.h>
65: #include <dev/usb/usb_quirks.h>
66:
67: #include <dev/usb/xhcireg.h>
68: #include <dev/usb/xhcivar.h>
1.28.2.11 skrll 69: #include <dev/usb/usbroothub.h>
1.1 jakllsch 70:
1.27 skrll 71:
72: #ifdef USB_DEBUG
73: #ifndef XHCI_DEBUG
74: #define xhcidebug 0
1.28.2.18 skrll 75: #else /* !XHCI_DEBUG */
1.27 skrll 76: static int xhcidebug = 0;
77:
78: SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup")
79: {
80: int err;
81: const struct sysctlnode *rnode;
82: const struct sysctlnode *cnode;
83:
84: err = sysctl_createv(clog, 0, NULL, &rnode,
85: CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci",
86: SYSCTL_DESCR("xhci global controls"),
87: NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
88:
89: if (err)
90: goto fail;
91:
92: /* control debugging printfs */
93: err = sysctl_createv(clog, 0, &rnode, &cnode,
94: CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
95: "debug", SYSCTL_DESCR("Enable debugging output"),
96: NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL);
97: if (err)
98: goto fail;
99:
100: return;
101: fail:
102: aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
103: }
104:
1.28.2.18 skrll 105: #endif /* !XHCI_DEBUG */
1.27 skrll 106: #endif /* USB_DEBUG */
107:
108: #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D)
109: #define XHCIHIST_FUNC() USBHIST_FUNC()
110: #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug)
1.1 jakllsch 111:
112: #define XHCI_DCI_SLOT 0
113: #define XHCI_DCI_EP_CONTROL 1
114:
115: #define XHCI_ICI_INPUT_CONTROL 0
116:
117: struct xhci_pipe {
118: struct usbd_pipe xp_pipe;
1.28.2.22 skrll 119: struct usb_task xp_async_task;
1.1 jakllsch 120: };
121:
122: #define XHCI_COMMAND_RING_TRBS 256
123: #define XHCI_EVENT_RING_TRBS 256
124: #define XHCI_EVENT_RING_SEGMENTS 1
125: #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT
126:
1.28.2.14 skrll 127: static usbd_status xhci_open(struct usbd_pipe *);
1.28.2.33 skrll 128: static void xhci_close_pipe(struct usbd_pipe *);
1.1 jakllsch 129: static int xhci_intr1(struct xhci_softc * const);
130: static void xhci_softintr(void *);
131: static void xhci_poll(struct usbd_bus *);
1.28.2.41 skrll 132: static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int);
1.28.2.14 skrll 133: static void xhci_freex(struct usbd_bus *, struct usbd_xfer *);
1.1 jakllsch 134: static void xhci_get_lock(struct usbd_bus *, kmutex_t **);
1.28.2.14 skrll 135: static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int,
1.1 jakllsch 136: struct usbd_port *);
1.28.2.12 skrll 137: static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
138: void *, int);
1.1 jakllsch 139:
1.28.2.14 skrll 140: static usbd_status xhci_configure_endpoint(struct usbd_pipe *);
1.28.2.19 skrll 141: //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *);
1.28.2.14 skrll 142: static usbd_status xhci_reset_endpoint(struct usbd_pipe *);
1.28.2.19 skrll 143: static usbd_status xhci_stop_endpoint(struct usbd_pipe *);
1.1 jakllsch 144:
1.28.2.14 skrll 145: static usbd_status xhci_set_dequeue(struct usbd_pipe *);
1.1 jakllsch 146:
147: static usbd_status xhci_do_command(struct xhci_softc * const,
148: struct xhci_trb * const, int);
1.28.2.19 skrll 149: static usbd_status xhci_do_command1(struct xhci_softc * const,
150: struct xhci_trb * const, int, int);
151: static usbd_status xhci_do_command_locked(struct xhci_softc * const,
152: struct xhci_trb * const, int);
153: static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int);
1.1 jakllsch 154: static usbd_status xhci_enable_slot(struct xhci_softc * const,
155: uint8_t * const);
1.28.2.19 skrll 156: static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t);
1.1 jakllsch 157: static usbd_status xhci_address_device(struct xhci_softc * const,
158: uint64_t, uint8_t, bool);
159: static usbd_status xhci_update_ep0_mps(struct xhci_softc * const,
160: struct xhci_slot * const, u_int);
161: static usbd_status xhci_ring_init(struct xhci_softc * const,
162: struct xhci_ring * const, size_t, size_t);
163: static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const);
164:
1.28.2.14 skrll 165: static void xhci_noop(struct usbd_pipe *);
1.1 jakllsch 166:
1.28.2.14 skrll 167: static usbd_status xhci_root_intr_transfer(struct usbd_xfer *);
168: static usbd_status xhci_root_intr_start(struct usbd_xfer *);
169: static void xhci_root_intr_abort(struct usbd_xfer *);
170: static void xhci_root_intr_close(struct usbd_pipe *);
171: static void xhci_root_intr_done(struct usbd_xfer *);
172:
173: static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *);
174: static usbd_status xhci_device_ctrl_start(struct usbd_xfer *);
175: static void xhci_device_ctrl_abort(struct usbd_xfer *);
176: static void xhci_device_ctrl_close(struct usbd_pipe *);
177: static void xhci_device_ctrl_done(struct usbd_xfer *);
178:
179: static usbd_status xhci_device_intr_transfer(struct usbd_xfer *);
180: static usbd_status xhci_device_intr_start(struct usbd_xfer *);
181: static void xhci_device_intr_abort(struct usbd_xfer *);
182: static void xhci_device_intr_close(struct usbd_pipe *);
183: static void xhci_device_intr_done(struct usbd_xfer *);
184:
185: static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *);
186: static usbd_status xhci_device_bulk_start(struct usbd_xfer *);
187: static void xhci_device_bulk_abort(struct usbd_xfer *);
188: static void xhci_device_bulk_close(struct usbd_pipe *);
189: static void xhci_device_bulk_done(struct usbd_xfer *);
1.1 jakllsch 190:
191: static void xhci_timeout(void *);
192: static void xhci_timeout_task(void *);
193:
194: static const struct usbd_bus_methods xhci_bus_methods = {
1.28.2.3 skrll 195: .ubm_open = xhci_open,
196: .ubm_softint = xhci_softintr,
197: .ubm_dopoll = xhci_poll,
198: .ubm_allocx = xhci_allocx,
199: .ubm_freex = xhci_freex,
200: .ubm_getlock = xhci_get_lock,
201: .ubm_newdev = xhci_new_device,
1.28.2.12 skrll 202: .ubm_rhctrl = xhci_roothub_ctrl,
1.1 jakllsch 203: };
204:
205: static const struct usbd_pipe_methods xhci_root_intr_methods = {
1.28.2.3 skrll 206: .upm_transfer = xhci_root_intr_transfer,
207: .upm_start = xhci_root_intr_start,
208: .upm_abort = xhci_root_intr_abort,
209: .upm_close = xhci_root_intr_close,
210: .upm_cleartoggle = xhci_noop,
211: .upm_done = xhci_root_intr_done,
1.1 jakllsch 212: };
213:
214:
215: static const struct usbd_pipe_methods xhci_device_ctrl_methods = {
1.28.2.3 skrll 216: .upm_transfer = xhci_device_ctrl_transfer,
217: .upm_start = xhci_device_ctrl_start,
218: .upm_abort = xhci_device_ctrl_abort,
219: .upm_close = xhci_device_ctrl_close,
220: .upm_cleartoggle = xhci_noop,
221: .upm_done = xhci_device_ctrl_done,
1.1 jakllsch 222: };
223:
224: static const struct usbd_pipe_methods xhci_device_isoc_methods = {
1.28.2.3 skrll 225: .upm_cleartoggle = xhci_noop,
1.1 jakllsch 226: };
227:
228: static const struct usbd_pipe_methods xhci_device_bulk_methods = {
1.28.2.3 skrll 229: .upm_transfer = xhci_device_bulk_transfer,
230: .upm_start = xhci_device_bulk_start,
231: .upm_abort = xhci_device_bulk_abort,
232: .upm_close = xhci_device_bulk_close,
233: .upm_cleartoggle = xhci_noop,
234: .upm_done = xhci_device_bulk_done,
1.1 jakllsch 235: };
236:
237: static const struct usbd_pipe_methods xhci_device_intr_methods = {
1.28.2.3 skrll 238: .upm_transfer = xhci_device_intr_transfer,
239: .upm_start = xhci_device_intr_start,
240: .upm_abort = xhci_device_intr_abort,
241: .upm_close = xhci_device_intr_close,
242: .upm_cleartoggle = xhci_noop,
243: .upm_done = xhci_device_intr_done,
1.1 jakllsch 244: };
245:
246: static inline uint32_t
1.28.2.19 skrll 247: xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset)
248: {
249: return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
250: }
251:
252: static inline uint32_t
1.1 jakllsch 253: xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset)
254: {
255: return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset);
256: }
257:
1.28.2.19 skrll 258: static inline void
259: xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset,
260: uint32_t value)
261: {
262: bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value);
263: }
264:
1.4 apb 265: #if 0 /* unused */
1.1 jakllsch 266: static inline void
267: xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset,
268: uint32_t value)
269: {
270: bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value);
271: }
1.4 apb 272: #endif /* unused */
1.1 jakllsch 273:
274: static inline uint32_t
275: xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset)
276: {
277: return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset);
278: }
279:
280: static inline uint32_t
281: xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset)
282: {
283: return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
284: }
285:
286: static inline void
287: xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset,
288: uint32_t value)
289: {
290: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
291: }
292:
1.4 apb 293: #if 0 /* unused */
1.1 jakllsch 294: static inline uint64_t
295: xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset)
296: {
297: uint64_t value;
298:
299: if (sc->sc_ac64) {
300: #ifdef XHCI_USE_BUS_SPACE_8
301: value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset);
302: #else
303: value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
304: value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh,
305: offset + 4) << 32;
306: #endif
307: } else {
308: value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
309: }
310:
311: return value;
312: }
1.4 apb 313: #endif /* unused */
1.1 jakllsch 314:
315: static inline void
316: xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset,
317: uint64_t value)
318: {
319: if (sc->sc_ac64) {
320: #ifdef XHCI_USE_BUS_SPACE_8
321: bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value);
322: #else
323: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0,
324: (value >> 0) & 0xffffffff);
325: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4,
326: (value >> 32) & 0xffffffff);
327: #endif
328: } else {
329: bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
330: }
331: }
332:
333: static inline uint32_t
334: xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset)
335: {
336: return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
337: }
338:
339: static inline void
340: xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset,
341: uint32_t value)
342: {
343: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
344: }
345:
1.4 apb 346: #if 0 /* unused */
1.1 jakllsch 347: static inline uint64_t
348: xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset)
349: {
350: uint64_t value;
351:
352: if (sc->sc_ac64) {
353: #ifdef XHCI_USE_BUS_SPACE_8
354: value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset);
355: #else
356: value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
357: value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh,
358: offset + 4) << 32;
359: #endif
360: } else {
361: value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
362: }
363:
364: return value;
365: }
1.4 apb 366: #endif /* unused */
1.1 jakllsch 367:
368: static inline void
369: xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset,
370: uint64_t value)
371: {
372: if (sc->sc_ac64) {
373: #ifdef XHCI_USE_BUS_SPACE_8
374: bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value);
375: #else
376: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0,
377: (value >> 0) & 0xffffffff);
378: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4,
379: (value >> 32) & 0xffffffff);
380: #endif
381: } else {
382: bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
383: }
384: }
385:
1.4 apb 386: #if 0 /* unused */
1.1 jakllsch 387: static inline uint32_t
388: xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset)
389: {
390: return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset);
391: }
1.4 apb 392: #endif /* unused */
1.1 jakllsch 393:
394: static inline void
395: xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset,
396: uint32_t value)
397: {
398: bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value);
399: }
400:
401: /* --- */
402:
403: static inline uint8_t
404: xhci_ep_get_type(usb_endpoint_descriptor_t * const ed)
405: {
1.28.2.19 skrll 406: u_int eptype = 0;
1.1 jakllsch 407:
408: switch (UE_GET_XFERTYPE(ed->bmAttributes)) {
409: case UE_CONTROL:
410: eptype = 0x0;
411: break;
412: case UE_ISOCHRONOUS:
413: eptype = 0x1;
414: break;
415: case UE_BULK:
416: eptype = 0x2;
417: break;
418: case UE_INTERRUPT:
419: eptype = 0x3;
420: break;
421: }
422:
423: if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
424: (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
425: return eptype | 0x4;
426: else
427: return eptype;
428: }
429:
430: static u_int
431: xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed)
432: {
433: /* xHCI 1.0 section 4.5.1 */
434: u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress);
435: u_int in = 0;
436:
437: if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) ||
438: (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN))
439: in = 1;
440:
441: return epaddr * 2 + in;
442: }
443:
444: static inline u_int
445: xhci_dci_to_ici(const u_int i)
446: {
447: return i + 1;
448: }
449:
450: static inline void *
451: xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs,
452: const u_int dci)
453: {
454: return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
455: }
456:
1.4 apb 457: #if 0 /* unused */
1.1 jakllsch 458: static inline bus_addr_t
459: xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs,
460: const u_int dci)
461: {
462: return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
463: }
1.4 apb 464: #endif /* unused */
1.1 jakllsch 465:
466: static inline void *
467: xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs,
468: const u_int ici)
469: {
470: return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
471: }
472:
473: static inline bus_addr_t
474: xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs,
475: const u_int ici)
476: {
477: return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici);
478: }
479:
480: static inline struct xhci_trb *
481: xhci_ring_trbv(struct xhci_ring * const xr, u_int idx)
482: {
483: return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
484: }
485:
486: static inline bus_addr_t
487: xhci_ring_trbp(struct xhci_ring * const xr, u_int idx)
488: {
489: return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx);
490: }
491:
492: static inline void
493: xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
494: uint32_t control)
495: {
1.28.2.34 skrll 496: trb->trb_0 = htole64(parameter);
497: trb->trb_2 = htole32(status);
498: trb->trb_3 = htole32(control);
1.1 jakllsch 499: }
500:
501: /* --- */
502:
503: void
504: xhci_childdet(device_t self, device_t child)
505: {
506: struct xhci_softc * const sc = device_private(self);
507:
508: KASSERT(sc->sc_child == child);
509: if (child == sc->sc_child)
510: sc->sc_child = NULL;
511: }
512:
513: int
514: xhci_detach(struct xhci_softc *sc, int flags)
515: {
516: int rv = 0;
517:
518: if (sc->sc_child != NULL)
519: rv = config_detach(sc->sc_child, flags);
520:
521: if (rv != 0)
1.28.2.13 skrll 522: return rv;
1.1 jakllsch 523:
524: /* XXX unconfigure/free slots */
525:
526: /* verify: */
527: xhci_rt_write_4(sc, XHCI_IMAN(0), 0);
528: xhci_op_write_4(sc, XHCI_USBCMD, 0);
529: /* do we need to wait for stop? */
530:
531: xhci_op_write_8(sc, XHCI_CRCR, 0);
532: xhci_ring_free(sc, &sc->sc_cr);
533: cv_destroy(&sc->sc_command_cv);
534:
535: xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0);
536: xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0);
537: xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY);
538: xhci_ring_free(sc, &sc->sc_er);
539:
540: usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma);
541:
542: xhci_op_write_8(sc, XHCI_DCBAAP, 0);
543: usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma);
544:
545: kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots);
546:
547: mutex_destroy(&sc->sc_lock);
548: mutex_destroy(&sc->sc_intr_lock);
1.28.2.19 skrll 549: cv_destroy(&sc->sc_softwake_cv);
1.1 jakllsch 550:
551: pool_cache_destroy(sc->sc_xferpool);
552:
553: return rv;
554: }
555:
556: int
557: xhci_activate(device_t self, enum devact act)
558: {
559: struct xhci_softc * const sc = device_private(self);
560:
561: switch (act) {
562: case DVACT_DEACTIVATE:
563: sc->sc_dying = true;
564: return 0;
565: default:
566: return EOPNOTSUPP;
567: }
568: }
569:
570: bool
571: xhci_suspend(device_t dv, const pmf_qual_t *qual)
572: {
573: return false;
574: }
575:
576: bool
577: xhci_resume(device_t dv, const pmf_qual_t *qual)
578: {
579: return false;
580: }
581:
582: bool
583: xhci_shutdown(device_t self, int flags)
584: {
585: return false;
586: }
587:
588:
589: static void
590: hexdump(const char *msg, const void *base, size_t len)
591: {
592: #if 0
593: size_t cnt;
594: const uint32_t *p;
595: extern paddr_t vtophys(vaddr_t);
596:
597: p = base;
598: cnt = 0;
599:
600: printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base,
601: (void *)vtophys((vaddr_t)base));
602:
603: while (cnt < len) {
604: if (cnt % 16 == 0)
605: printf("%p: ", p);
606: else if (cnt % 8 == 0)
607: printf(" |");
608: printf(" %08x", *p++);
609: cnt += 4;
610: if (cnt % 16 == 0)
611: printf("\n");
612: }
613: #endif
614: }
615:
1.28.2.37 skrll 616: #define XHCI_HCCPREV1_BITS \
617: "\177\020" /* New bitmask */ \
618: "f\020\020XECP\0" \
619: "f\014\4MAXPSA\0" \
620: "b\013CFC\0" \
621: "b\012SEC\0" \
622: "b\011SBD\0" \
623: "b\010FSE\0" \
624: "b\7NSS\0" \
625: "b\6LTC\0" \
626: "b\5LHRC\0" \
627: "b\4PIND\0" \
628: "b\3PPC\0" \
629: "b\2CZC\0" \
630: "b\1BNC\0" \
631: "b\0AC64\0" \
632: "\0"
633: #define XHCI_HCCV1_x_BITS \
634: "\177\020" /* New bitmask */ \
635: "f\020\020XECP\0" \
636: "f\014\4MAXPSA\0" \
637: "b\013CFC\0" \
638: "b\012SEC\0" \
639: "b\011SPC\0" \
640: "b\010PAE\0" \
641: "b\7NSS\0" \
642: "b\6LTC\0" \
643: "b\5LHRC\0" \
644: "b\4PIND\0" \
645: "b\3PPC\0" \
646: "b\2CSZ\0" \
647: "b\1BNC\0" \
648: "b\0AC64\0" \
649: "\0"
1.1 jakllsch 650:
1.15 skrll 651: int
1.1 jakllsch 652: xhci_init(struct xhci_softc *sc)
653: {
654: bus_size_t bsz;
1.28.2.37 skrll 655: uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff;
1.1 jakllsch 656: uint32_t ecp, ecr;
657: uint32_t usbcmd, usbsts, pagesize, config;
658: int i;
659: uint16_t hciversion;
660: uint8_t caplength;
661:
1.27 skrll 662: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 663:
1.28.2.40 skrll 664: sc->sc_bus.ub_revision = USBREV_3_0;
1.28.2.5 skrll 665: sc->sc_bus.ub_usedma = true;
1.1 jakllsch 666:
667: cap = xhci_read_4(sc, XHCI_CAPLENGTH);
668: caplength = XHCI_CAP_CAPLENGTH(cap);
669: hciversion = XHCI_CAP_HCIVERSION(cap);
670:
1.28.2.37 skrll 671: if (hciversion < XHCI_HCIVERSION_0_96 ||
672: hciversion > XHCI_HCIVERSION_1_0) {
1.1 jakllsch 673: aprint_normal_dev(sc->sc_dev,
674: "xHCI version %x.%x not known to be supported\n",
675: (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
676: } else {
677: aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n",
678: (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff);
679: }
680:
681: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength,
682: &sc->sc_cbh) != 0) {
683: aprint_error_dev(sc->sc_dev, "capability subregion failure\n");
1.15 skrll 684: return ENOMEM;
1.1 jakllsch 685: }
686:
687: hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1);
688: sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1);
689: sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1);
690: sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1);
691: hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2);
1.28.2.37 skrll 692: hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3);
693: aprint_debug_dev(sc->sc_dev,
694: "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3);
1.1 jakllsch 695:
1.28.2.37 skrll 696: hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS);
1.1 jakllsch 697: sc->sc_ac64 = XHCI_HCC_AC64(hcc);
698: sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32;
699:
1.28.2.37 skrll 700: char sbuf[128];
701: if (hciversion < XHCI_HCIVERSION_1_0)
702: snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc);
703: else
1.28.2.39 skrll 704: snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc);
1.28.2.37 skrll 705: aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf);
1.12 jakllsch 706: aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4);
1.28.2.37 skrll 707:
1.1 jakllsch 708: ecp = XHCI_HCC_XECP(hcc) * 4;
709: while (ecp != 0) {
710: ecr = xhci_read_4(sc, ecp);
1.12 jakllsch 711: aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr);
1.1 jakllsch 712: switch (XHCI_XECP_ID(ecr)) {
713: case XHCI_ID_PROTOCOLS: {
714: uint32_t w0, w4, w8;
715: uint16_t w2;
716: w0 = xhci_read_4(sc, ecp + 0);
717: w2 = (w0 >> 16) & 0xffff;
718: w4 = xhci_read_4(sc, ecp + 4);
719: w8 = xhci_read_4(sc, ecp + 8);
1.12 jakllsch 720: aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n",
1.1 jakllsch 721: w0, w4, w8);
722: if (w4 == 0x20425355 && w2 == 0x0300) {
723: sc->sc_ss_port_start = (w8 >> 0) & 0xff;;
724: sc->sc_ss_port_count = (w8 >> 8) & 0xff;;
725: }
726: if (w4 == 0x20425355 && w2 == 0x0200) {
727: sc->sc_hs_port_start = (w8 >> 0) & 0xff;
728: sc->sc_hs_port_count = (w8 >> 8) & 0xff;
729: }
730: break;
731: }
1.28.2.19 skrll 732: case XHCI_ID_USB_LEGACY: {
733: uint8_t bios_sem;
734:
735: /* Take host controller from BIOS */
736: bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM);
737: if (bios_sem) {
738: /* sets xHCI to be owned by OS */
739: xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1);
740: aprint_debug(
741: "waiting for BIOS to give up control\n");
742: for (i = 0; i < 5000; i++) {
743: bios_sem = xhci_read_1(sc, ecp +
744: XHCI_XECP_BIOS_SEM);
745: if (bios_sem == 0)
746: break;
747: DELAY(1000);
748: }
749: if (bios_sem)
750: printf("timed out waiting for BIOS\n");
751: }
752: break;
753: }
1.1 jakllsch 754: default:
755: break;
756: }
757: ecr = xhci_read_4(sc, ecp);
758: if (XHCI_XECP_NEXT(ecr) == 0) {
759: ecp = 0;
760: } else {
761: ecp += XHCI_XECP_NEXT(ecr) * 4;
762: }
763: }
764:
765: bsz = XHCI_PORTSC(sc->sc_maxports + 1);
766: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz,
767: &sc->sc_obh) != 0) {
768: aprint_error_dev(sc->sc_dev, "operational subregion failure\n");
1.15 skrll 769: return ENOMEM;
1.1 jakllsch 770: }
771:
772: dboff = xhci_cap_read_4(sc, XHCI_DBOFF);
773: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff,
774: sc->sc_maxslots * 4, &sc->sc_dbh) != 0) {
775: aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n");
1.15 skrll 776: return ENOMEM;
1.1 jakllsch 777: }
778:
779: rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF);
780: if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff,
781: sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) {
782: aprint_error_dev(sc->sc_dev, "runtime subregion failure\n");
1.15 skrll 783: return ENOMEM;
1.1 jakllsch 784: }
785:
786: for (i = 0; i < 100; i++) {
787: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
788: if ((usbsts & XHCI_STS_CNR) == 0)
789: break;
790: usb_delay_ms(&sc->sc_bus, 1);
791: }
792: if (i >= 100)
1.15 skrll 793: return EIO;
1.1 jakllsch 794:
795: usbcmd = 0;
796: xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
797: usb_delay_ms(&sc->sc_bus, 1);
798:
799: usbcmd = XHCI_CMD_HCRST;
800: xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
801: for (i = 0; i < 100; i++) {
802: usbcmd = xhci_op_read_4(sc, XHCI_USBCMD);
803: if ((usbcmd & XHCI_CMD_HCRST) == 0)
804: break;
805: usb_delay_ms(&sc->sc_bus, 1);
806: }
807: if (i >= 100)
1.15 skrll 808: return EIO;
1.1 jakllsch 809:
810: for (i = 0; i < 100; i++) {
811: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
812: if ((usbsts & XHCI_STS_CNR) == 0)
813: break;
814: usb_delay_ms(&sc->sc_bus, 1);
815: }
816: if (i >= 100)
1.15 skrll 817: return EIO;
1.1 jakllsch 818:
1.28.2.34 skrll 819: if (sc->sc_vendor_init)
820: sc->sc_vendor_init(sc);
821:
1.1 jakllsch 822: pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE);
1.12 jakllsch 823: aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize);
1.1 jakllsch 824: pagesize = ffs(pagesize);
825: if (pagesize == 0)
1.15 skrll 826: return EIO;
1.1 jakllsch 827: sc->sc_pgsz = 1 << (12 + (pagesize - 1));
1.12 jakllsch 828: aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz);
829: aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n",
1.1 jakllsch 830: (uint32_t)sc->sc_maxslots);
1.28.2.19 skrll 831: aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports);
1.1 jakllsch 832:
1.5 matt 833: usbd_status err;
834:
835: sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2);
1.12 jakllsch 836: aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf);
1.5 matt 837: if (sc->sc_maxspbuf != 0) {
838: err = usb_allocmem(&sc->sc_bus,
839: sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t),
840: &sc->sc_spbufarray_dma);
841: if (err)
842: return err;
1.28.2.1 skrll 843:
1.5 matt 844: sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP);
845: uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0);
846: for (i = 0; i < sc->sc_maxspbuf; i++) {
847: usb_dma_t * const dma = &sc->sc_spbuf_dma[i];
848: /* allocate contexts */
849: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz,
850: sc->sc_pgsz, dma);
851: if (err)
852: return err;
853: spbufarray[i] = htole64(DMAADDR(dma, 0));
854: usb_syncmem(dma, 0, sc->sc_pgsz,
855: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
856: }
857:
1.28.2.1 skrll 858: usb_syncmem(&sc->sc_spbufarray_dma, 0,
1.5 matt 859: sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE);
860: }
861:
1.1 jakllsch 862: config = xhci_op_read_4(sc, XHCI_CONFIG);
863: config &= ~0xFF;
864: config |= sc->sc_maxslots & 0xFF;
865: xhci_op_write_4(sc, XHCI_CONFIG, config);
866:
867: err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS,
868: XHCI_COMMAND_RING_SEGMENTS_ALIGN);
869: if (err) {
870: aprint_error_dev(sc->sc_dev, "command ring init fail\n");
871: return err;
872: }
873:
874: err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS,
875: XHCI_EVENT_RING_SEGMENTS_ALIGN);
876: if (err) {
877: aprint_error_dev(sc->sc_dev, "event ring init fail\n");
878: return err;
879: }
880:
1.16 skrll 881: usb_dma_t *dma;
882: size_t size;
883: size_t align;
884:
885: dma = &sc->sc_eventst_dma;
886: size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE,
887: XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN);
888: KASSERT(size <= (512 * 1024));
889: align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN;
890: err = usb_allocmem(&sc->sc_bus, size, align, dma);
891:
892: memset(KERNADDR(dma, 0), 0, size);
893: usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
894: aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n",
895: usbd_errstr(err),
896: (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0),
897: KERNADDR(&sc->sc_eventst_dma, 0),
1.28.2.5 skrll 898: sc->sc_eventst_dma.udma_block->size);
1.16 skrll 899:
900: dma = &sc->sc_dcbaa_dma;
901: size = (1 + sc->sc_maxslots) * sizeof(uint64_t);
902: KASSERT(size <= 2048);
903: align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN;
904: err = usb_allocmem(&sc->sc_bus, size, align, dma);
905:
906: memset(KERNADDR(dma, 0), 0, size);
907: if (sc->sc_maxspbuf != 0) {
908: /*
909: * DCBA entry 0 hold the scratchbuf array pointer.
910: */
911: *(uint64_t *)KERNADDR(dma, 0) =
912: htole64(DMAADDR(&sc->sc_spbufarray_dma, 0));
1.1 jakllsch 913: }
1.16 skrll 914: usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE);
915: aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n",
916: usbd_errstr(err),
917: (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0),
918: KERNADDR(&sc->sc_dcbaa_dma, 0),
1.28.2.5 skrll 919: sc->sc_dcbaa_dma.udma_block->size);
1.1 jakllsch 920:
921: sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots,
922: KM_SLEEP);
923:
924: cv_init(&sc->sc_command_cv, "xhcicmd");
1.28.2.19 skrll 925: mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
1.28.2.34 skrll 926: mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
1.28.2.19 skrll 927: cv_init(&sc->sc_softwake_cv, "xhciab");
928:
929: sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0,
1.28.2.48 skrll 930: "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
1.28.2.19 skrll 931:
932: /* Set up the bus struct. */
933: sc->sc_bus.ub_methods = &xhci_bus_methods;
934: sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe);
1.1 jakllsch 935:
936: struct xhci_erste *erst;
937: erst = KERNADDR(&sc->sc_eventst_dma, 0);
938: erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0));
939: erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS);
940: erst[0].erste_3 = htole32(0);
941: usb_syncmem(&sc->sc_eventst_dma, 0,
942: XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE);
943:
944: xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS);
945: xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0));
946: xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) |
947: XHCI_ERDP_LO_BUSY);
948: xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0));
949: xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) |
950: sc->sc_cr.xr_cs);
951:
952: #if 0
953: hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0),
954: XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS);
955: #endif
956:
957: xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA);
1.28.2.19 skrll 958: if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0)
959: /* Intel xhci needs interrupt rate moderated. */
960: xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP);
961: else
962: xhci_rt_write_4(sc, XHCI_IMOD(0), 0);
1.28.2.26 skrll 963: aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n",
964: xhci_rt_read_4(sc, XHCI_IMOD(0)));
1.1 jakllsch 965:
966: xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */
1.12 jakllsch 967: aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n",
1.1 jakllsch 968: xhci_op_read_4(sc, XHCI_USBCMD));
969:
970: return USBD_NORMAL_COMPLETION;
971: }
972:
973: int
974: xhci_intr(void *v)
975: {
976: struct xhci_softc * const sc = v;
1.25 skrll 977: int ret = 0;
1.1 jakllsch 978:
1.27 skrll 979: XHCIHIST_FUNC(); XHCIHIST_CALLED();
980:
1.25 skrll 981: if (sc == NULL)
1.1 jakllsch 982: return 0;
983:
1.25 skrll 984: mutex_spin_enter(&sc->sc_intr_lock);
985:
986: if (sc->sc_dying || !device_has_power(sc->sc_dev))
987: goto done;
988:
1.1 jakllsch 989: /* If we get an interrupt while polling, then just ignore it. */
1.28.2.5 skrll 990: if (sc->sc_bus.ub_usepolling) {
1.1 jakllsch 991: #ifdef DIAGNOSTIC
1.27 skrll 992: DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1.1 jakllsch 993: #endif
1.25 skrll 994: goto done;
1.1 jakllsch 995: }
996:
1.25 skrll 997: ret = xhci_intr1(sc);
998: done:
999: mutex_spin_exit(&sc->sc_intr_lock);
1000: return ret;
1.1 jakllsch 1001: }
1002:
1003: int
1004: xhci_intr1(struct xhci_softc * const sc)
1005: {
1006: uint32_t usbsts;
1007: uint32_t iman;
1008:
1.27 skrll 1009: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1010:
1.1 jakllsch 1011: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.27 skrll 1012: DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0);
1.1 jakllsch 1013: #if 0
1014: if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) {
1015: return 0;
1016: }
1017: #endif
1018: xhci_op_write_4(sc, XHCI_USBSTS,
1019: usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */
1020: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.27 skrll 1021: DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0);
1.1 jakllsch 1022:
1023: iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1.27 skrll 1024: DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0);
1.28.2.19 skrll 1025:
1.28.2.34 skrll 1026: /* XXX 4.17.5 IP may be 0 if MSI/MSI-X is used */
1.28.2.19 skrll 1027: if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) {
1028: if ((iman & XHCI_IMAN_INTR_PEND) == 0) {
1029: return 0;
1030: }
1031: }
1032:
1.1 jakllsch 1033: xhci_rt_write_4(sc, XHCI_IMAN(0), iman);
1034: iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
1.27 skrll 1035: DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0);
1.1 jakllsch 1036: usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
1.27 skrll 1037: DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0);
1.1 jakllsch 1038:
1039: usb_schedsoftintr(&sc->sc_bus);
1040:
1041: return 1;
1042: }
1043:
1.28.2.19 skrll 1044: /*
1045: * 3 port speed types used in USB stack
1046: *
1047: * usbdi speed
1048: * definition: USB_SPEED_* in usb.h
1049: * They are used in struct usbd_device in USB stack.
1050: * ioctl interface uses these values too.
1051: * port_status speed
1052: * definition: UPS_*_SPEED in usb.h
1.28.2.27 skrll 1053: * They are used in usb_port_status_t and valid only for USB 2.0.
1.28.2.28 skrll 1054: * Speed value is always 0 for Super Speed or more, and dwExtPortStatus
1055: * of usb_port_status_ext_t indicates port speed.
1.28.2.27 skrll 1056: * Note that some 3.0 values overlap with 2.0 values.
1.28.2.19 skrll 1057: * (e.g. 0x200 means UPS_POER_POWER_SS in SS and
1058: * means UPS_LOW_SPEED in HS.)
1.28.2.28 skrll 1059: * port status returned from hub also uses these values.
1060: * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed
1061: * or more.
1.28.2.19 skrll 1062: * xspeed:
1063: * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1)
1064: * They are used in only slot context and PORTSC reg of xhci.
1.28.2.27 skrll 1065: * The difference between usbdi speed and xspeed is
1066: * that FS and LS values are swapped.
1.28.2.19 skrll 1067: */
1068:
1.28.2.27 skrll 1069: /* convert usbdi speed to xspeed */
1.28.2.19 skrll 1070: static int
1071: xhci_speed2xspeed(int speed)
1072: {
1073: switch (speed) {
1074: case USB_SPEED_LOW: return 2;
1075: case USB_SPEED_FULL: return 1;
1.28.2.27 skrll 1076: default: return speed;
1077: }
1078: }
1079:
1.28.2.46 skrll 1080: #if 0
1.28.2.27 skrll 1081: /* convert xspeed to usbdi speed */
1082: static int
1083: xhci_xspeed2speed(int xspeed)
1084: {
1085: switch (xspeed) {
1086: case 1: return USB_SPEED_FULL;
1087: case 2: return USB_SPEED_LOW;
1088: default: return xspeed;
1089: }
1090: }
1.28.2.46 skrll 1091: #endif
1.28.2.27 skrll 1092:
1093: /* convert xspeed to port status speed */
1094: static int
1095: xhci_xspeed2psspeed(int xspeed)
1096: {
1097: switch (xspeed) {
1098: case 0: return 0;
1099: case 1: return UPS_FULL_SPEED;
1100: case 2: return UPS_LOW_SPEED;
1101: case 3: return UPS_HIGH_SPEED;
1102: default: return UPS_OTHER_SPEED;
1.28.2.19 skrll 1103: }
1104: }
1105:
1106: /* construct slot context */
1107: static void
1108: xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp)
1109: {
1110: usb_device_descriptor_t * const dd = &dev->ud_ddesc;
1111: int speed = dev->ud_speed;
1112: int tthubslot, ttportnum;
1113: bool ishub;
1114: bool usemtt;
1115:
1116: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1117:
1118: /*
1.28.2.37 skrll 1119: * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2
1.28.2.19 skrll 1120: * tthubslot:
1121: * This is the slot ID of parent HS hub
1122: * if LS/FS device is connected && connected through HS hub.
1123: * This is 0 if device is not LS/FS device ||
1124: * parent hub is not HS hub ||
1125: * attached to root hub.
1126: * ttportnum:
1127: * This is the downstream facing port of parent HS hub
1128: * if LS/FS device is connected.
1129: * This is 0 if device is not LS/FS device ||
1130: * parent hub is not HS hub ||
1131: * attached to root hub.
1132: */
1133: if (dev->ud_myhsport != NULL &&
1134: dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 &&
1135: (dev->ud_myhub != NULL &&
1136: dev->ud_myhub->ud_speed == USB_SPEED_HIGH) &&
1137: (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) {
1138: ttportnum = dev->ud_myhsport->up_portno;
1139: tthubslot = dev->ud_myhsport->up_parent->ud_addr;
1140: } else {
1141: ttportnum = 0;
1142: tthubslot = 0;
1143: }
1144: DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d",
1145: dev->ud_myhsport, ttportnum, tthubslot, 0);
1146:
1147: /* ishub is valid after reading UDESC_DEVICE */
1148: ishub = (dd->bDeviceClass == UDCLASS_HUB);
1149:
1150: /* dev->ud_hub is valid after reading UDESC_HUB */
1151: if (ishub && dev->ud_hub) {
1152: usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc;
1153:
1154: cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts));
1155: cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET(
1156: __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK)));
1157: DPRINTFN(4, "nports=%d ttt=%d",
1158: hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0);
1159: }
1160:
1161: #define IS_TTHUB(dd) \
1162: ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \
1163: (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT)
1164:
1165: /*
1166: * MTT flag is set if
1167: * 1. this is HS hub && MTT is enabled
1168: * or
1169: * 2. this is not hub && this is LS or FS device &&
1170: * MTT of parent HS hub (and its parent, too) is enabled
1171: */
1172: if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd))
1173: usemtt = true;
1174: else if (!ishub &&
1175: (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) &&
1176: dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 &&
1177: (dev->ud_myhub != NULL &&
1178: dev->ud_myhub->ud_speed == USB_SPEED_HIGH) &&
1179: dev->ud_myhsport != NULL &&
1180: IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc))
1181: usemtt = true;
1182: else
1183: usemtt = false;
1184: DPRINTFN(4, "class %u proto %u ishub %d usemtt %d",
1185: dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt);
1186:
1187: cp[0] |= htole32(
1188: XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) |
1189: XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) |
1190: XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0)
1191: );
1192: cp[1] |= htole32(0);
1193: cp[2] |= htole32(
1194: XHCI_SCTX_2_IRQ_TARGET_SET(0) |
1195: XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) |
1196: XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum)
1197: );
1198: cp[3] |= htole32(0);
1199: }
1200:
1.28.2.37 skrll 1201: static uint32_t
1202: xhci_get_maxburst(struct usbd_pipe *pipe)
1203: {
1204: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1205: usbd_desc_iter_t iter;
1206: const usb_cdc_descriptor_t *cdcd;
1207: const usb_endpoint_ss_comp_descriptor_t * esscd = NULL;
1208: uint32_t maxb = 0;
1209: uint8_t ep;
1210:
1211: cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(
1212: pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY);
1213: usb_desc_iter_init(pipe->up_dev, &iter);
1214: iter.cur = (const void *)cdcd;
1215:
1216: /* find endpoint_ss_comp desc for ep of this pipe */
1217: for (ep = 0;;) {
1218: cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter);
1219: if (cdcd == NULL)
1220: break;
1221: if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) {
1222: ep = ((const usb_endpoint_descriptor_t *)cdcd)->
1223: bEndpointAddress;
1224: if (UE_GET_ADDR(ep) ==
1225: UE_GET_ADDR(ed->bEndpointAddress)) {
1226: cdcd = (const usb_cdc_descriptor_t *)
1227: usb_desc_iter_next(&iter);
1228: break;
1229: }
1230: ep = 0;
1231: }
1232: }
1233: if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) {
1234: esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd;
1235: maxb = esscd->bMaxBurst;
1236: }
1237:
1238: return maxb;
1239: }
1240:
1.28.2.20 skrll 1241: /*
1.28.2.37 skrll 1242: * Convert endpoint bInterval value to endpoint context interval value
1243: * for Interrupt pipe.
1244: * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6
1.28.2.20 skrll 1245: */
1.28.2.37 skrll 1246: static uint32_t
1247: xhci_bival2ival(uint32_t ival, int speed)
1248: {
1249: if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
1250: int i;
1251:
1252: /*
1253: * round ival down to "the nearest base 2 multiple of
1254: * bInterval * 8".
1255: * bInterval is at most 255 as its type is uByte.
1256: * 255(ms) = 2040(x 125us) < 2^11, so start with 10.
1257: */
1258: for (i = 10; i > 0; i--) {
1259: if ((ival * 8) >= (1 << i))
1260: break;
1261: }
1262: ival = i;
1263: } else {
1264: /* Interval = bInterval-1 for SS/HS */
1265: ival--;
1266: }
1267:
1268: return ival;
1269: }
1270:
1271: /*
1272: * 4.8.2, 6.2.3.2
1273: * construct common endpoint parameters
1274: */
1275: static void
1276: xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp)
1.1 jakllsch 1277: {
1.28.2.5 skrll 1278: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1279: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1.28.2.37 skrll 1280: const u_int dci = xhci_ep_get_dci(ed);
1.1 jakllsch 1281: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1.28.2.19 skrll 1282: uint32_t mps = UGETW(ed->wMaxPacketSize);
1283: uint32_t maxb = 0;
1284: int speed = pipe->up_dev->ud_speed;
1285: uint32_t ival = ed->bInterval;
1.1 jakllsch 1286:
1.28.2.19 skrll 1287: cp[0] = htole32(
1288: XHCI_EPCTX_0_EPSTATE_SET(0) |
1.28.2.37 skrll 1289: XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */
1.28.2.19 skrll 1290: XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
1.28.2.37 skrll 1291: XHCI_EPCTX_0_LSA_SET(0) |
1292: XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0)
1.28.2.19 skrll 1293: );
1294: cp[1] = htole32(
1295: XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) |
1.28.2.37 skrll 1296: XHCI_EPCTX_1_HID_SET(0) |
1.28.2.19 skrll 1297: XHCI_EPCTX_1_MAXB_SET(0)
1298: );
1299: if (xfertype != UE_ISOCHRONOUS)
1300: cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3));
1301:
1.28.2.37 skrll 1302: /* 6.2.3.4, 4.8.2.4 */
1.28.2.27 skrll 1303: if (USB_IS_SS(speed)) {
1.28.2.37 skrll 1304: /* UBS 3.1 9.6.6 */
1305: cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps));
1306: /* UBS 3.1 9.6.7 */
1307: maxb = xhci_get_maxburst(pipe);
1308: cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb));
1309: } else {
1310: /* UBS 2.0 9.6.6 */
1311: cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)));
1312:
1313: /* 6.2.3.4 */
1314: if (speed == USB_SPEED_HIGH &&
1315: (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) {
1316: maxb = UE_GET_TRANS(mps);
1317: } else {
1318: /* LS/FS or HS CTRL or HS BULK */
1319: maxb = 0;
1.28.2.19 skrll 1320: }
1321: cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb));
1322: }
1323:
1.28.2.37 skrll 1324: if (xfertype == UE_CONTROL)
1325: cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */
1326: else if (USB_IS_SS(speed))
1327: cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps));
1328: else
1329: cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)));
1330:
1.28.2.19 skrll 1331: switch (xfertype) {
1.28.2.37 skrll 1332: case UE_CONTROL:
1333: break;
1334: case UE_BULK:
1335: /* XXX Set MaxPStreams, HID, and LSA if streams enabled */
1336: break;
1.28.2.19 skrll 1337: case UE_INTERRUPT:
1.28.2.30 skrll 1338: if (pipe->up_interval != USBD_DEFAULT_INTERVAL)
1339: ival = pipe->up_interval;
1340:
1.28.2.37 skrll 1341: ival = xhci_bival2ival(ival, speed);
1.28.2.19 skrll 1342: cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival));
1343: break;
1344: case UE_ISOCHRONOUS:
1.28.2.37 skrll 1345: if (pipe->up_interval != USBD_DEFAULT_INTERVAL)
1346: ival = pipe->up_interval;
1347:
1348: /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */
1.28.2.30 skrll 1349: if (speed == USB_SPEED_FULL)
1350: ival += 3; /* 1ms -> 125us */
1351: ival--;
1.28.2.37 skrll 1352: cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival));
1.28.2.30 skrll 1353:
1.28.2.27 skrll 1354: if (USB_IS_SS(speed)) {
1.28.2.37 skrll 1355: /* XXX if LEC = 1, set ESIT instead */
1356: cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0));
1.28.2.19 skrll 1357: }
1358: break;
1359: default:
1360: break;
1.1 jakllsch 1361: }
1362: *(uint64_t *)(&cp[2]) = htole64(
1363: xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) |
1364: XHCI_EPCTX_2_DCS_SET(1));
1.28.2.37 skrll 1365: }
1366:
1367: /*
1368: * Construct input contexts and issue TRB
1369: */
1370: static usbd_status
1371: xhci_configure_endpoint(struct usbd_pipe *pipe)
1372: {
1.28.2.42 skrll 1373: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.28.2.37 skrll 1374: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1375: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1376: struct xhci_trb trb;
1377: usbd_status err;
1378: uint32_t *cp;
1379:
1380: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1381: DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x",
1382: xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress,
1383: pipe->up_endpoint->ue_edesc->bmAttributes);
1384:
1385: /* XXX ensure input context is available? */
1386:
1387: memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz);
1388:
1389: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
1390: cp[0] = htole32(0);
1391: cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci));
1392:
1393: /* set up input slot context */
1394: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1395: xhci_setup_sctx(pipe->up_dev, cp);
1396: cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci));
1397:
1398: /* set up input endpoint context */
1399: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci));
1400: xhci_setup_endp_ctx(pipe, cp);
1.1 jakllsch 1401:
1402: /* sync input contexts before they are read from memory */
1403: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1404: hexdump("input control context", xhci_slot_get_icv(sc, xs, 0),
1405: sc->sc_ctxsz * 1);
1406: hexdump("input endpoint context", xhci_slot_get_icv(sc, xs,
1407: xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1);
1408:
1409: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1410: trb.trb_2 = 0;
1411: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1412: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1413:
1414: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1415:
1416: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1417: hexdump("output context", xhci_slot_get_dcv(sc, xs, dci),
1418: sc->sc_ctxsz * 1);
1419:
1420: return err;
1421: }
1422:
1.28.2.19 skrll 1423: #if 0
1.1 jakllsch 1424: static usbd_status
1.28.2.14 skrll 1425: xhci_unconfigure_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1426: {
1.27 skrll 1427: #ifdef USB_DEBUG
1.28.2.5 skrll 1428: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1.27 skrll 1429: #endif
1430:
1431: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1432: DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0);
1433:
1.1 jakllsch 1434: return USBD_NORMAL_COMPLETION;
1435: }
1.28.2.19 skrll 1436: #endif
1.1 jakllsch 1437:
1.28.2.20 skrll 1438: /* 4.6.8, 6.4.3.7 */
1.1 jakllsch 1439: static usbd_status
1.28.2.14 skrll 1440: xhci_reset_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1441: {
1.28.2.42 skrll 1442: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.28.2.5 skrll 1443: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1444: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1445: struct xhci_trb trb;
1446: usbd_status err;
1447:
1.27 skrll 1448: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.19 skrll 1449: DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0);
1450:
1451: KASSERT(!mutex_owned(&sc->sc_lock));
1.1 jakllsch 1452:
1453: trb.trb_0 = 0;
1454: trb.trb_2 = 0;
1455: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1456: XHCI_TRB_3_EP_SET(dci) |
1457: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP);
1458:
1459: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1460:
1461: return err;
1462: }
1463:
1.28.2.20 skrll 1464: /*
1465: * 4.6.9, 6.4.3.8
1466: * Stop execution of TDs on xfer ring.
1467: * Should be called with sc_lock held.
1468: */
1.1 jakllsch 1469: static usbd_status
1.28.2.14 skrll 1470: xhci_stop_endpoint(struct usbd_pipe *pipe)
1.1 jakllsch 1471: {
1.28.2.42 skrll 1472: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.28.2.5 skrll 1473: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1.1 jakllsch 1474: struct xhci_trb trb;
1475: usbd_status err;
1.28.2.5 skrll 1476: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1477:
1.27 skrll 1478: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.19 skrll 1479: DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0);
1480:
1481: KASSERT(mutex_owned(&sc->sc_lock));
1.1 jakllsch 1482:
1483: trb.trb_0 = 0;
1484: trb.trb_2 = 0;
1485: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1486: XHCI_TRB_3_EP_SET(dci) |
1487: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP);
1488:
1.28.2.19 skrll 1489: err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.1 jakllsch 1490:
1491: return err;
1492: }
1493:
1.28.2.20 skrll 1494: /*
1495: * Set TR Dequeue Pointer.
1496: * xCHI 1.1 4.6.10 6.4.3.9
1.28.2.21 skrll 1497: * Purge all of the transfer requests on ring.
1.28.2.31 skrll 1498: * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error.
1.28.2.20 skrll 1499: */
1.1 jakllsch 1500: static usbd_status
1.28.2.14 skrll 1501: xhci_set_dequeue(struct usbd_pipe *pipe)
1.1 jakllsch 1502: {
1.28.2.42 skrll 1503: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.28.2.5 skrll 1504: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1505: const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1.1 jakllsch 1506: struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr;
1507: struct xhci_trb trb;
1508: usbd_status err;
1509:
1.27 skrll 1510: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1511: DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0);
1.1 jakllsch 1512:
1513: memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE);
1514: usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE,
1515: BUS_DMASYNC_PREWRITE);
1.28.2.37 skrll 1516: memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies));
1.1 jakllsch 1517:
1518: xr->xr_ep = 0;
1519: xr->xr_cs = 1;
1520:
1.28.2.20 skrll 1521: /* set DCS */
1.1 jakllsch 1522: trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */
1523: trb.trb_2 = 0;
1524: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1525: XHCI_TRB_3_EP_SET(dci) |
1526: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE);
1527:
1528: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1529:
1530: return err;
1531: }
1532:
1.28.2.20 skrll 1533: /*
1534: * Open new pipe: called from usbd_setup_pipe_flags.
1535: * Fills methods of pipe.
1536: * If pipe is not for ep0, calls configure_endpoint.
1537: */
1.1 jakllsch 1538: static usbd_status
1.28.2.14 skrll 1539: xhci_open(struct usbd_pipe *pipe)
1.1 jakllsch 1540: {
1.28.2.18 skrll 1541: struct usbd_device * const dev = pipe->up_dev;
1.28.2.42 skrll 1542: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
1.28.2.5 skrll 1543: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1.1 jakllsch 1544: const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1545:
1.27 skrll 1546: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1547: DPRINTFN(1, "addr %d depth %d port %d speed %d",
1.28.2.19 skrll 1548: dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno,
1549: dev->ud_speed);
1.1 jakllsch 1550:
1551: if (sc->sc_dying)
1552: return USBD_IOERROR;
1553:
1554: /* Root Hub */
1.28.2.19 skrll 1555: if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) {
1.1 jakllsch 1556: switch (ed->bEndpointAddress) {
1557: case USB_CONTROL_ENDPOINT:
1.28.2.12 skrll 1558: pipe->up_methods = &roothub_ctrl_methods;
1.1 jakllsch 1559: break;
1.28.2.12 skrll 1560: case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
1.28.2.5 skrll 1561: pipe->up_methods = &xhci_root_intr_methods;
1.1 jakllsch 1562: break;
1563: default:
1.28.2.5 skrll 1564: pipe->up_methods = NULL;
1.27 skrll 1565: DPRINTFN(0, "bad bEndpointAddress 0x%02x",
1566: ed->bEndpointAddress, 0, 0, 0);
1.1 jakllsch 1567: return USBD_INVAL;
1568: }
1569: return USBD_NORMAL_COMPLETION;
1570: }
1571:
1572: switch (xfertype) {
1573: case UE_CONTROL:
1.28.2.5 skrll 1574: pipe->up_methods = &xhci_device_ctrl_methods;
1.1 jakllsch 1575: break;
1576: case UE_ISOCHRONOUS:
1.28.2.5 skrll 1577: pipe->up_methods = &xhci_device_isoc_methods;
1.1 jakllsch 1578: return USBD_INVAL;
1579: break;
1580: case UE_BULK:
1.28.2.5 skrll 1581: pipe->up_methods = &xhci_device_bulk_methods;
1.1 jakllsch 1582: break;
1583: case UE_INTERRUPT:
1.28.2.5 skrll 1584: pipe->up_methods = &xhci_device_intr_methods;
1.1 jakllsch 1585: break;
1586: default:
1587: return USBD_IOERROR;
1588: break;
1589: }
1590:
1591: if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT)
1.28.2.19 skrll 1592: return xhci_configure_endpoint(pipe);
1.1 jakllsch 1593:
1594: return USBD_NORMAL_COMPLETION;
1595: }
1596:
1.28.2.20 skrll 1597: /*
1598: * Closes pipe, called from usbd_kill_pipe via close methods.
1599: * If the endpoint to be closed is ep0, disable_slot.
1600: * Should be called with sc_lock held.
1601: */
1.28.2.33 skrll 1602: static void
1.28.2.19 skrll 1603: xhci_close_pipe(struct usbd_pipe *pipe)
1604: {
1.28.2.42 skrll 1605: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.28.2.19 skrll 1606: struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv;
1607: usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc;
1608: const u_int dci = xhci_ep_get_dci(ed);
1609: struct xhci_trb trb;
1610: uint32_t *cp;
1611:
1612: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1613:
1614: if (sc->sc_dying)
1.28.2.33 skrll 1615: return;
1.28.2.19 skrll 1616:
1617: if (xs == NULL || xs->xs_idx == 0)
1618: /* xs is uninitialized before xhci_init_slot */
1.28.2.33 skrll 1619: return;
1.28.2.19 skrll 1620:
1.28.2.37 skrll 1621: DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0);
1.28.2.19 skrll 1622:
1623: KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx");
1624: KASSERT(mutex_owned(&sc->sc_lock));
1625:
1626: if (pipe->up_dev->ud_depth == 0)
1.28.2.33 skrll 1627: return;
1.28.2.19 skrll 1628:
1629: if (dci == XHCI_DCI_EP_CONTROL) {
1630: DPRINTFN(4, "closing ep0", 0, 0, 0, 0);
1.28.2.33 skrll 1631: xhci_disable_slot(sc, xs->xs_idx);
1632: return;
1.28.2.19 skrll 1633: }
1634:
1.28.2.20 skrll 1635: /*
1636: * This may fail in the case that xhci_close_pipe is called after
1637: * xhci_abort_xfer e.g. usbd_kill_pipe.
1638: */
1.28.2.19 skrll 1639: (void)xhci_stop_endpoint(pipe);
1640:
1641: /*
1642: * set appropriate bit to be dropped.
1643: * don't set DC bit to 1, otherwise all endpoints
1644: * would be deconfigured.
1645: */
1646: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
1647: cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci));
1648: cp[1] = htole32(0);
1649:
1650: /* XXX should be most significant one, not dci? */
1651: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1652: cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci));
1653:
1654: /* sync input contexts before they are read from memory */
1655: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
1656:
1657: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1658: trb.trb_2 = 0;
1659: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1660: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP);
1661:
1.28.2.35 skrll 1662: (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.28.2.19 skrll 1663: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
1664: }
1665:
1.28.2.20 skrll 1666: /*
1667: * Abort transfer.
1668: * Called with sc_lock held.
1669: * May be called from softintr context.
1670: */
1.28.2.19 skrll 1671: static void
1672: xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
1673: {
1.28.2.42 skrll 1674: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.28.2.19 skrll 1675:
1676: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1677: DPRINTFN(4, "xfer %p pipe %p status %d",
1678: xfer, xfer->ux_pipe, status, 0);
1679:
1680: KASSERT(mutex_owned(&sc->sc_lock));
1681:
1682: if (sc->sc_dying) {
1683: /* If we're dying, just do the software part. */
1684: DPRINTFN(4, "dying", 0, 0, 0, 0);
1685: xfer->ux_status = status; /* make software ignore it */
1686: callout_stop(&xfer->ux_callout);
1687: usb_transfer_complete(xfer);
1688: return;
1689: }
1690:
1691: /* XXX need more stuff */
1692: xfer->ux_status = status;
1693: callout_stop(&xfer->ux_callout);
1694: usb_transfer_complete(xfer);
1.28.2.37 skrll 1695: DPRINTFN(14, "end", 0, 0, 0, 0);
1.28.2.19 skrll 1696:
1697: KASSERT(mutex_owned(&sc->sc_lock));
1698: }
1699:
1.28.2.21 skrll 1700: /*
1701: * Recover STALLed endpoint.
1702: * xHCI 1.1 sect 4.10.2.1
1703: * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove
1704: * all transfers on transfer ring.
1705: * These are done in thread context asynchronously.
1706: */
1.28.2.19 skrll 1707: static void
1708: xhci_clear_endpoint_stall_async_task(void *cookie)
1709: {
1710: struct usbd_xfer * const xfer = cookie;
1.28.2.42 skrll 1711: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.28.2.19 skrll 1712: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
1713: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1714: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
1715:
1716: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1717: DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0);
1718:
1719: xhci_reset_endpoint(xfer->ux_pipe);
1720: xhci_set_dequeue(xfer->ux_pipe);
1721:
1722: mutex_enter(&sc->sc_lock);
1723: tr->is_halted = false;
1724: usb_transfer_complete(xfer);
1725: mutex_exit(&sc->sc_lock);
1726: DPRINTFN(4, "ends", 0, 0, 0, 0);
1727: }
1728:
1729: static usbd_status
1730: xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer)
1731: {
1.28.2.42 skrll 1732: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.28.2.22 skrll 1733: struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe;
1.28.2.19 skrll 1734:
1735: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1736: DPRINTFN(4, "xfer %p", xfer, 0, 0, 0);
1737:
1738: if (sc->sc_dying) {
1739: return USBD_IOERROR;
1740: }
1741:
1.28.2.22 skrll 1742: usb_init_task(&xp->xp_async_task,
1.28.2.19 skrll 1743: xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE);
1.28.2.22 skrll 1744: usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC);
1.28.2.19 skrll 1745: DPRINTFN(4, "ends", 0, 0, 0, 0);
1746:
1747: return USBD_NORMAL_COMPLETION;
1748: }
1749:
1.28.2.36 skrll 1750: /* Process roothub port status/change events and notify to uhub_intr. */
1.1 jakllsch 1751: static void
1752: xhci_rhpsc(struct xhci_softc * const sc, u_int port)
1753: {
1.28.2.18 skrll 1754: struct usbd_xfer * const xfer = sc->sc_intrxfer;
1.1 jakllsch 1755: uint8_t *p;
1756:
1.27 skrll 1757: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.32 skrll 1758: DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev),
1759: port, 0, 0);
1.1 jakllsch 1760:
1761: if (xfer == NULL)
1762: return;
1763:
1.28.2.32 skrll 1764: if (port > sc->sc_maxports)
1765: return;
1766:
1.28.2.5 skrll 1767: p = xfer->ux_buf;
1768: memset(p, 0, xfer->ux_length);
1.1 jakllsch 1769: p[port/NBBY] |= 1 << (port%NBBY);
1.28.2.5 skrll 1770: xfer->ux_actlen = xfer->ux_length;
1771: xfer->ux_status = USBD_NORMAL_COMPLETION;
1.1 jakllsch 1772: usb_transfer_complete(xfer);
1773: }
1774:
1.28.2.36 skrll 1775: /* Process Transfer Events */
1.1 jakllsch 1776: static void
1.28.2.36 skrll 1777: xhci_event_transfer(struct xhci_softc * const sc,
1.27 skrll 1778: const struct xhci_trb * const trb)
1.1 jakllsch 1779: {
1780: uint64_t trb_0;
1781: uint32_t trb_2, trb_3;
1.28.2.36 skrll 1782: uint8_t trbcode;
1783: u_int slot, dci;
1784: struct xhci_slot *xs;
1785: struct xhci_ring *xr;
1786: struct xhci_xfer *xx;
1787: struct usbd_xfer *xfer;
1788: usbd_status err;
1.1 jakllsch 1789:
1.27 skrll 1790: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 1791:
1792: trb_0 = le64toh(trb->trb_0);
1793: trb_2 = le32toh(trb->trb_2);
1794: trb_3 = le32toh(trb->trb_3);
1.28.2.36 skrll 1795: trbcode = XHCI_TRB_2_ERROR_GET(trb_2);
1796: slot = XHCI_TRB_3_SLOT_GET(trb_3);
1797: dci = XHCI_TRB_3_EP_GET(trb_3);
1798: xs = &sc->sc_slots[slot];
1799: xr = &xs->xs_ep[dci].xe_tr;
1.1 jakllsch 1800:
1.28.2.36 skrll 1801: /* sanity check */
1.28.2.37 skrll 1802: KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx < sc->sc_maxslots,
1803: "invalid xs_idx %u slot %u", xs->xs_idx, slot);
1.1 jakllsch 1804:
1.28.2.36 skrll 1805: if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) {
1.28.2.37 skrll 1806: /*
1807: * When ED == 0, trb_0 is physical address of the TRB
1808: * that caused this event. (6.4.2.1)
1809: */
1.28.2.36 skrll 1810: bus_addr_t trbp = xhci_ring_trbp(xr, 0);
1.28.2.32 skrll 1811:
1.28.2.36 skrll 1812: /* trb_0 range sanity check */
1813: if (trb_0 < trbp ||
1814: (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 ||
1815: (trb_0 - trbp) / sizeof(struct xhci_trb) >=
1816: xr->xr_ntrb) {
1817: DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64,
1818: trb_0, trbp, 0, 0);
1819: return;
1.28.2.24 skrll 1820: }
1.28.2.36 skrll 1821: int idx = (trb_0 - trbp) / sizeof(struct xhci_trb);
1822: xx = xr->xr_cookies[idx];
1.28.2.37 skrll 1823:
1824: /*
1825: * If endpoint is stopped between TDs, TRB pointer points at
1826: * next TRB, however, it is not put yet or is a garbage TRB.
1827: * That's why xr_cookies may be NULL or look like broken.
1828: * Note: this ev happens only when hciversion >= 1.0 or
1829: * hciversion == 0.96 and FSE of hcc1 is set.
1830: */
1831: if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) {
1832: DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %"
1833: PRIx64, idx, xx, trbcode, trb_0);
1834: }
1.28.2.36 skrll 1835: } else {
1.28.2.37 skrll 1836: /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */
1.28.2.36 skrll 1837: xx = (void *)(uintptr_t)(trb_0 & ~0x3);
1838: }
1839: /* XXX this may not happen */
1840: if (xx == NULL) {
1841: DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0);
1842: return;
1843: }
1844: xfer = &xx->xx_xfer;
1845: /* XXX this may happen when detaching */
1846: if (xfer == NULL) {
1.28.2.37 skrll 1847: DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64,
1848: xx, trb_0, 0, 0);
1.28.2.36 skrll 1849: return;
1850: }
1851: DPRINTFN(14, "xfer %p", xfer, 0, 0, 0);
1852: /* XXX I dunno why this happens */
1.28.2.37 skrll 1853: KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer);
1.28.2.36 skrll 1854:
1855: if (!xfer->ux_pipe->up_repeat &&
1856: SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) {
1.28.2.37 skrll 1857: DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0);
1.28.2.36 skrll 1858: return;
1859: }
1.1 jakllsch 1860:
1.28.2.37 skrll 1861: /* 4.11.5.2 Event Data TRB */
1.28.2.36 skrll 1862: if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) {
1.28.2.37 skrll 1863: DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32
1864: " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0);
1.28.2.36 skrll 1865: if ((trb_0 & 0x3) == 0x3) {
1866: xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2);
1.1 jakllsch 1867: }
1.28.2.36 skrll 1868: }
1.1 jakllsch 1869:
1.28.2.36 skrll 1870: switch (trbcode) {
1871: case XHCI_TRB_ERROR_SHORT_PKT:
1872: case XHCI_TRB_ERROR_SUCCESS:
1873: xfer->ux_actlen =
1874: xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2);
1875: err = USBD_NORMAL_COMPLETION;
1876: break;
1877: case XHCI_TRB_ERROR_STALL:
1878: case XHCI_TRB_ERROR_BABBLE:
1.28.2.37 skrll 1879: DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0);
1.28.2.36 skrll 1880: xr->is_halted = true;
1881: err = USBD_STALLED;
1882: /*
1883: * Stalled endpoints can be recoverd by issuing
1884: * command TRB TYPE_RESET_EP on xHCI instead of
1.28.2.37 skrll 1885: * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT
1.28.2.36 skrll 1886: * on the endpoint. However, this function may be
1887: * called from softint context (e.g. from umass),
1888: * in that case driver gets KASSERT in cv_timedwait
1889: * in xhci_do_command.
1890: * To avoid this, this runs reset_endpoint and
1891: * usb_transfer_complete in usb task thread
1892: * asynchronously (and then umass issues clear
1893: * UF_ENDPOINT_HALT).
1894: */
1895: xfer->ux_status = err;
1896: xhci_clear_endpoint_stall_async(xfer);
1897: return;
1898: default:
1.28.2.37 skrll 1899: DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0);
1.28.2.36 skrll 1900: err = USBD_IOERROR;
1901: break;
1902: }
1903: xfer->ux_status = err;
1.1 jakllsch 1904:
1.28.2.36 skrll 1905: if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) {
1906: if ((trb_0 & 0x3) == 0x0) {
1.1 jakllsch 1907: usb_transfer_complete(xfer);
1908: }
1.28.2.36 skrll 1909: } else {
1910: usb_transfer_complete(xfer);
1911: }
1912: }
1913:
1914: /* Process Command complete events */
1915: static void
1916: xhci_event_cmd(struct xhci_softc * const sc,
1917: const struct xhci_trb * const trb)
1918: {
1919: uint64_t trb_0;
1920: uint32_t trb_2, trb_3;
1921:
1922: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1923:
1924: trb_0 = le64toh(trb->trb_0);
1925: trb_2 = le32toh(trb->trb_2);
1926: trb_3 = le32toh(trb->trb_3);
1.1 jakllsch 1927:
1.28.2.36 skrll 1928: if (trb_0 == sc->sc_command_addr) {
1929: sc->sc_result_trb.trb_0 = trb_0;
1930: sc->sc_result_trb.trb_2 = trb_2;
1931: sc->sc_result_trb.trb_3 = trb_3;
1932: if (XHCI_TRB_2_ERROR_GET(trb_2) !=
1933: XHCI_TRB_ERROR_SUCCESS) {
1934: DPRINTFN(1, "command completion "
1935: "failure: 0x%016"PRIx64" 0x%08"PRIx32" "
1936: "0x%08"PRIx32, trb_0, trb_2, trb_3, 0);
1937: }
1938: cv_signal(&sc->sc_command_cv);
1939: } else {
1940: DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" "
1941: "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0,
1942: trb_2, trb_3);
1943: }
1944: }
1945:
1946: /*
1947: * Process events.
1948: * called from xhci_softintr
1949: */
1950: static void
1951: xhci_handle_event(struct xhci_softc * const sc,
1952: const struct xhci_trb * const trb)
1953: {
1954: uint64_t trb_0;
1955: uint32_t trb_2, trb_3;
1956:
1957: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1958:
1959: KASSERT(mutex_owned(&sc->sc_lock));
1960:
1961: trb_0 = le64toh(trb->trb_0);
1962: trb_2 = le32toh(trb->trb_2);
1963: trb_3 = le32toh(trb->trb_3);
1964:
1965: DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32,
1966: trb, trb_0, trb_2, trb_3);
1967:
1968: /*
1969: * 4.11.3.1, 6.4.2.1
1970: * TRB Pointer is invalid for these completion codes.
1971: */
1972: switch (XHCI_TRB_2_ERROR_GET(trb_2)) {
1973: case XHCI_TRB_ERROR_RING_UNDERRUN:
1974: case XHCI_TRB_ERROR_RING_OVERRUN:
1975: case XHCI_TRB_ERROR_VF_RING_FULL:
1976: return;
1977: default:
1978: if (trb_0 == 0) {
1979: return;
1.1 jakllsch 1980: }
1981: break;
1.28.2.36 skrll 1982: }
1983:
1984: switch (XHCI_TRB_3_TYPE_GET(trb_3)) {
1985: case XHCI_TRB_EVENT_TRANSFER:
1986: xhci_event_transfer(sc, trb);
1987: break;
1.1 jakllsch 1988: case XHCI_TRB_EVENT_CMD_COMPLETE:
1.28.2.36 skrll 1989: xhci_event_cmd(sc, trb);
1.1 jakllsch 1990: break;
1991: case XHCI_TRB_EVENT_PORT_STS_CHANGE:
1992: xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff));
1993: break;
1994: default:
1995: break;
1996: }
1997: }
1998:
1999: static void
2000: xhci_softintr(void *v)
2001: {
1.28.2.18 skrll 2002: struct usbd_bus * const bus = v;
1.28.2.42 skrll 2003: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2004: struct xhci_ring * const er = &sc->sc_er;
2005: struct xhci_trb *trb;
2006: int i, j, k;
2007:
1.27 skrll 2008: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2009:
2010: i = er->xr_ep;
2011: j = er->xr_cs;
2012:
1.27 skrll 2013: DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0);
2014:
1.1 jakllsch 2015: while (1) {
2016: usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE,
2017: BUS_DMASYNC_POSTREAD);
2018: trb = &er->xr_trb[i];
2019: k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
2020:
2021: if (j != k)
2022: break;
2023:
2024: xhci_handle_event(sc, trb);
2025:
2026: i++;
2027: if (i == XHCI_EVENT_RING_TRBS) {
2028: i = 0;
2029: j ^= 1;
2030: }
2031: }
2032:
2033: er->xr_ep = i;
2034: er->xr_cs = j;
2035:
2036: xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) |
2037: XHCI_ERDP_LO_BUSY);
2038:
1.27 skrll 2039: DPRINTFN(16, "ends", 0, 0, 0, 0);
1.1 jakllsch 2040:
2041: return;
2042: }
2043:
2044: static void
2045: xhci_poll(struct usbd_bus *bus)
2046: {
1.28.2.42 skrll 2047: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2048:
1.27 skrll 2049: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2050:
1.25 skrll 2051: mutex_spin_enter(&sc->sc_intr_lock);
1.1 jakllsch 2052: xhci_intr1(sc);
1.25 skrll 2053: mutex_spin_exit(&sc->sc_intr_lock);
1.1 jakllsch 2054:
2055: return;
2056: }
2057:
1.28.2.14 skrll 2058: static struct usbd_xfer *
1.28.2.41 skrll 2059: xhci_allocx(struct usbd_bus *bus, unsigned int nframes)
1.1 jakllsch 2060: {
1.28.2.42 skrll 2061: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.28.2.14 skrll 2062: struct usbd_xfer *xfer;
1.1 jakllsch 2063:
1.27 skrll 2064: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2065:
2066: xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
2067: if (xfer != NULL) {
1.6 skrll 2068: memset(xfer, 0, sizeof(struct xhci_xfer));
1.1 jakllsch 2069: #ifdef DIAGNOSTIC
1.28.2.5 skrll 2070: xfer->ux_state = XFER_BUSY;
1.1 jakllsch 2071: #endif
2072: }
2073:
2074: return xfer;
2075: }
2076:
2077: static void
1.28.2.14 skrll 2078: xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1.1 jakllsch 2079: {
1.28.2.42 skrll 2080: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2081:
1.27 skrll 2082: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2083:
2084: #ifdef DIAGNOSTIC
1.28.2.5 skrll 2085: if (xfer->ux_state != XFER_BUSY) {
1.27 skrll 2086: DPRINTFN(0, "xfer=%p not busy, 0x%08x",
1.28.2.5 skrll 2087: xfer, xfer->ux_state, 0, 0);
1.1 jakllsch 2088: }
1.28.2.5 skrll 2089: xfer->ux_state = XFER_FREE;
1.1 jakllsch 2090: #endif
2091: pool_cache_put(sc->sc_xferpool, xfer);
2092: }
2093:
2094: static void
2095: xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
2096: {
1.28.2.42 skrll 2097: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2098:
2099: *lock = &sc->sc_lock;
2100: }
2101:
1.28.2.1 skrll 2102: extern uint32_t usb_cookie_no;
1.1 jakllsch 2103:
1.28.2.20 skrll 2104: /*
1.28.2.38 skrll 2105: * Called if uhub_explore finds a new device (via usbd_new_device).
1.28.2.20 skrll 2106: * Allocate and construct dev structure of default endpoint (ep0).
2107: * Determine initial MaxPacketSize (mps) by speed.
2108: * Determine route string and roothub port for slot of dev.
2109: * Allocate pipe of ep0.
2110: * Enable and initialize slot and Set Address.
2111: * Read device descriptor.
2112: * Register this device.
2113: */
1.1 jakllsch 2114: static usbd_status
1.28.2.14 skrll 2115: xhci_new_device(device_t parent, struct usbd_bus *bus, int depth,
1.1 jakllsch 2116: int speed, int port, struct usbd_port *up)
2117: {
1.28.2.42 skrll 2118: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.28.2.14 skrll 2119: struct usbd_device *dev;
1.1 jakllsch 2120: usbd_status err;
2121: usb_device_descriptor_t *dd;
2122: struct usbd_device *hub;
2123: struct usbd_device *adev;
2124: int rhport = 0;
2125: struct xhci_slot *xs;
2126: uint32_t *cp;
1.28.2.19 skrll 2127: uint32_t route = 0;
2128: uint8_t slot = 0;
1.1 jakllsch 2129: uint8_t addr;
2130:
1.27 skrll 2131: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2132: DPRINTFN(4, "port=%d depth=%d speed=%d upport %d",
1.28.2.5 skrll 2133: port, depth, speed, up->up_portno);
1.27 skrll 2134:
1.28.2.8 skrll 2135: dev = kmem_zalloc(sizeof(*dev), KM_SLEEP);
1.1 jakllsch 2136: if (dev == NULL)
2137: return USBD_NOMEM;
2138:
1.28.2.5 skrll 2139: dev->ud_bus = bus;
1.1 jakllsch 2140:
2141: /* Set up default endpoint handle. */
1.28.2.5 skrll 2142: dev->ud_ep0.ue_edesc = &dev->ud_ep0desc;
1.1 jakllsch 2143:
2144: /* Set up default endpoint descriptor. */
1.28.2.5 skrll 2145: dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE;
2146: dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT;
2147: dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT;
2148: dev->ud_ep0desc.bmAttributes = UE_CONTROL;
1.28.2.19 skrll 2149: /* 4.3, 4.8.2.1 */
1.28.2.27 skrll 2150: if (USB_IS_SS(speed)) {
1.28.2.19 skrll 2151: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET);
1.28.2.27 skrll 2152: } else
2153: switch (speed) {
1.28.2.19 skrll 2154: case USB_SPEED_FULL:
2155: /* XXX using 64 as initial mps of ep0 in FS */
2156: case USB_SPEED_HIGH:
2157: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET);
2158: break;
2159: case USB_SPEED_LOW:
2160: default:
1.28.2.5 skrll 2161: USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET);
1.28.2.19 skrll 2162: break;
2163: }
1.28.2.5 skrll 2164: dev->ud_ep0desc.bInterval = 0;
1.1 jakllsch 2165:
2166: /* doesn't matter, just don't let it uninitialized */
1.28.2.5 skrll 2167: dev->ud_ep0.ue_toggle = 0;
1.1 jakllsch 2168:
1.28.2.5 skrll 2169: DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0);
1.1 jakllsch 2170:
1.28.2.5 skrll 2171: dev->ud_quirks = &usbd_no_quirk;
2172: dev->ud_addr = 0;
2173: dev->ud_ddesc.bMaxPacketSize = 0;
2174: dev->ud_depth = depth;
2175: dev->ud_powersrc = up;
2176: dev->ud_myhub = up->up_parent;
1.1 jakllsch 2177:
1.28.2.5 skrll 2178: up->up_dev = dev;
1.1 jakllsch 2179:
2180: /* Locate root hub port */
1.28.2.19 skrll 2181: for (hub = dev; hub != NULL; hub = hub->ud_myhub) {
2182: uint32_t dep;
2183:
2184: DPRINTFN(4, "hub %p depth %d upport %p upportno %d",
2185: hub, hub->ud_depth, hub->ud_powersrc,
2186: hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1);
2187:
2188: if (hub->ud_powersrc == NULL)
2189: break;
2190: dep = hub->ud_depth;
2191: if (dep == 0)
2192: break;
2193: rhport = hub->ud_powersrc->up_portno;
2194: if (dep > USB_HUB_MAX_DEPTH)
2195: continue;
1.1 jakllsch 2196:
1.28.2.19 skrll 2197: route |=
2198: (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport)
2199: << ((dep - 1) * 4);
2200: }
2201: route = route >> 4;
2202: DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0);
2203:
2204: /* Locate port on upstream high speed hub */
2205: for (adev = dev, hub = up->up_parent;
2206: hub != NULL && hub->ud_speed != USB_SPEED_HIGH;
2207: adev = hub, hub = hub->ud_myhub)
2208: ;
2209: if (hub) {
2210: int p;
2211: for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) {
1.28.2.5 skrll 2212: if (hub->ud_hub->uh_ports[p].up_dev == adev) {
1.28.2.19 skrll 2213: dev->ud_myhsport = &hub->ud_hub->uh_ports[p];
2214: goto found;
1.1 jakllsch 2215: }
2216: }
1.28.2.19 skrll 2217: panic("xhci_new_device: cannot find HS port");
2218: found:
2219: DPRINTFN(4, "high speed port %d", p, 0, 0, 0);
1.1 jakllsch 2220: } else {
1.28.2.19 skrll 2221: dev->ud_myhsport = NULL;
1.1 jakllsch 2222: }
2223:
1.28.2.5 skrll 2224: dev->ud_speed = speed;
2225: dev->ud_langid = USBD_NOLANG;
2226: dev->ud_cookie.cookie = ++usb_cookie_no;
1.1 jakllsch 2227:
2228: /* Establish the default pipe. */
1.28.2.5 skrll 2229: err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL,
2230: &dev->ud_pipe0);
1.1 jakllsch 2231: if (err) {
1.28.2.19 skrll 2232: goto bad;
1.1 jakllsch 2233: }
2234:
1.28.2.5 skrll 2235: dd = &dev->ud_ddesc;
1.1 jakllsch 2236:
2237: if ((depth == 0) && (port == 0)) {
1.28.2.5 skrll 2238: KASSERT(bus->ub_devices[dev->ud_addr] == NULL);
2239: bus->ub_devices[dev->ud_addr] = dev;
1.1 jakllsch 2240: err = usbd_get_initial_ddesc(dev, dd);
2241: if (err)
1.28.2.19 skrll 2242: goto bad;
1.1 jakllsch 2243: err = usbd_reload_device_desc(dev);
2244: if (err)
1.28.2.19 skrll 2245: goto bad;
1.1 jakllsch 2246: } else {
2247: err = xhci_enable_slot(sc, &slot);
2248: if (err)
1.28.2.19 skrll 2249: goto bad;
1.1 jakllsch 2250: xs = &sc->sc_slots[slot];
1.28.2.5 skrll 2251: dev->ud_hcpriv = xs;
1.28.2.19 skrll 2252: err = xhci_init_slot(dev, slot, route, rhport);
2253: if (err) {
2254: dev->ud_hcpriv = NULL;
1.28.2.23 skrll 2255: /*
2256: * We have to disable_slot here because
2257: * xs->xs_idx == 0 when xhci_init_slot fails,
2258: * in that case usbd_remove_dev won't work.
2259: */
2260: mutex_enter(&sc->sc_lock);
2261: xhci_disable_slot(sc, slot);
2262: mutex_exit(&sc->sc_lock);
1.28.2.19 skrll 2263: goto bad;
2264: }
2265:
2266: /* Allow device time to set new address */
2267: usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE);
1.1 jakllsch 2268: cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT);
2269: //hexdump("slot context", cp, sc->sc_ctxsz);
2270: addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]);
1.27 skrll 2271: DPRINTFN(4, "device address %u", addr, 0, 0, 0);
1.1 jakllsch 2272: /* XXX ensure we know when the hardware does something
2273: we can't yet cope with */
2274: KASSERT(addr >= 1 && addr <= 127);
1.28.2.5 skrll 2275: dev->ud_addr = addr;
2276: /* XXX dev->ud_addr not necessarily unique on bus */
2277: KASSERT(bus->ub_devices[dev->ud_addr] == NULL);
2278: bus->ub_devices[dev->ud_addr] = dev;
1.1 jakllsch 2279:
2280: err = usbd_get_initial_ddesc(dev, dd);
2281: if (err)
1.28.2.19 skrll 2282: goto bad;
1.24 skrll 2283: /* 4.8.2.1 */
1.28.2.27 skrll 2284: if (USB_IS_SS(speed)) {
1.28.2.19 skrll 2285: if (dd->bMaxPacketSize != 9) {
2286: printf("%s: invalid mps 2^%u for SS ep0,"
2287: " using 512\n",
2288: device_xname(sc->sc_dev),
2289: dd->bMaxPacketSize);
2290: dd->bMaxPacketSize = 9;
2291: }
1.28.2.5 skrll 2292: USETW(dev->ud_ep0desc.wMaxPacketSize,
1.24 skrll 2293: (1 << dd->bMaxPacketSize));
1.28.2.19 skrll 2294: } else
1.28.2.5 skrll 2295: USETW(dev->ud_ep0desc.wMaxPacketSize,
1.24 skrll 2296: dd->bMaxPacketSize);
1.27 skrll 2297: DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0);
1.24 skrll 2298: xhci_update_ep0_mps(sc, xs,
1.28.2.5 skrll 2299: UGETW(dev->ud_ep0desc.wMaxPacketSize));
1.1 jakllsch 2300: err = usbd_reload_device_desc(dev);
2301: if (err)
1.28.2.19 skrll 2302: goto bad;
1.1 jakllsch 2303:
1.28.2.19 skrll 2304: #if 0
2305: /* Re-establish the default pipe with the new MPS. */
2306: /* In xhci this is done by xhci_update_ep0_mps. */
1.28.2.5 skrll 2307: usbd_kill_pipe(dev->ud_pipe0);
2308: err = usbd_setup_pipe(dev, 0, &dev->ud_ep0,
2309: USBD_DEFAULT_INTERVAL, &dev->ud_pipe0);
1.28.2.19 skrll 2310: #endif
1.1 jakllsch 2311: }
2312:
1.27 skrll 2313: DPRINTFN(1, "adding unit addr=%d, rev=%02x,",
1.28.2.5 skrll 2314: dev->ud_addr, UGETW(dd->bcdUSB), 0, 0);
1.27 skrll 2315: DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,",
2316: dd->bDeviceClass, dd->bDeviceSubClass,
2317: dd->bDeviceProtocol, 0);
2318: DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d",
2319: dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations,
1.28.2.5 skrll 2320: dev->ud_speed);
1.1 jakllsch 2321:
1.28.2.49 skrll 2322: usbd_get_device_strings(dev);
2323:
1.1 jakllsch 2324: usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev);
2325:
2326: if ((depth == 0) && (port == 0)) {
2327: usbd_attach_roothub(parent, dev);
1.28.2.5 skrll 2328: DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0);
1.1 jakllsch 2329: return USBD_NORMAL_COMPLETION;
2330: }
2331:
2332:
1.28.2.5 skrll 2333: err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr);
1.28.2.19 skrll 2334: bad:
2335: if (err != USBD_NORMAL_COMPLETION) {
1.1 jakllsch 2336: usbd_remove_device(dev, up);
2337: }
2338:
1.28.2.19 skrll 2339: return err;
1.1 jakllsch 2340: }
2341:
2342: static usbd_status
2343: xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr,
2344: size_t ntrb, size_t align)
2345: {
2346: usbd_status err;
2347: size_t size = ntrb * XHCI_TRB_SIZE;
2348:
1.27 skrll 2349: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2350:
1.1 jakllsch 2351: err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma);
2352: if (err)
2353: return err;
2354: mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
2355: xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP);
2356: xr->xr_trb = xhci_ring_trbv(xr, 0);
2357: xr->xr_ntrb = ntrb;
2358: xr->xr_ep = 0;
2359: xr->xr_cs = 1;
2360: memset(xr->xr_trb, 0, size);
2361: usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE);
2362: xr->is_halted = false;
2363:
2364: return USBD_NORMAL_COMPLETION;
2365: }
2366:
2367: static void
2368: xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr)
2369: {
2370: usb_freemem(&sc->sc_bus, &xr->xr_dma);
2371: mutex_destroy(&xr->xr_lock);
2372: kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb);
2373: }
2374:
2375: static void
2376: xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr,
2377: void *cookie, struct xhci_trb * const trbs, size_t ntrbs)
2378: {
2379: size_t i;
2380: u_int ri;
2381: u_int cs;
2382: uint64_t parameter;
2383: uint32_t status;
2384: uint32_t control;
2385:
1.27 skrll 2386: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2387:
1.28.2.37 skrll 2388: KASSERT(ntrbs <= XHCI_XFER_NTRB);
1.1 jakllsch 2389: for (i = 0; i < ntrbs; i++) {
1.27 skrll 2390: DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0);
2391: DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32,
2392: trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0);
1.1 jakllsch 2393: KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) !=
2394: XHCI_TRB_TYPE_LINK);
2395: }
2396:
1.27 skrll 2397: DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0);
1.1 jakllsch 2398:
2399: ri = xr->xr_ep;
2400: cs = xr->xr_cs;
2401:
1.11 dsl 2402: /*
2403: * Although the xhci hardware can do scatter/gather dma from
2404: * arbitrary sized buffers, there is a non-obvious restriction
2405: * that a LINK trb is only allowed at the end of a burst of
2406: * transfers - which might be 16kB.
2407: * Arbitrary aligned LINK trb definitely fail on Ivy bridge.
2408: * The simple solution is not to allow a LINK trb in the middle
2409: * of anything - as here.
1.13 dsl 2410: * XXX: (dsl) There are xhci controllers out there (eg some made by
2411: * ASMedia) that seem to lock up if they process a LINK trb but
2412: * cannot process the linked-to trb yet.
2413: * The code should write the 'cycle' bit on the link trb AFTER
2414: * adding the other trb.
1.11 dsl 2415: */
1.1 jakllsch 2416: if (ri + ntrbs >= (xr->xr_ntrb - 1)) {
2417: parameter = xhci_ring_trbp(xr, 0);
2418: status = 0;
2419: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
2420: XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0);
1.28.2.34 skrll 2421: xhci_trb_put(&xr->xr_trb[ri], parameter, status, control);
1.1 jakllsch 2422: usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1,
2423: BUS_DMASYNC_PREWRITE);
2424: xr->xr_cookies[ri] = NULL;
2425: xr->xr_ep = 0;
2426: xr->xr_cs ^= 1;
2427: ri = xr->xr_ep;
2428: cs = xr->xr_cs;
2429: }
2430:
2431: ri++;
2432:
1.11 dsl 2433: /* Write any subsequent TRB first */
1.1 jakllsch 2434: for (i = 1; i < ntrbs; i++) {
2435: parameter = trbs[i].trb_0;
2436: status = trbs[i].trb_2;
2437: control = trbs[i].trb_3;
2438:
2439: if (cs) {
2440: control |= XHCI_TRB_3_CYCLE_BIT;
2441: } else {
2442: control &= ~XHCI_TRB_3_CYCLE_BIT;
2443: }
2444:
1.28.2.34 skrll 2445: xhci_trb_put(&xr->xr_trb[ri], parameter, status, control);
1.1 jakllsch 2446: usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1,
2447: BUS_DMASYNC_PREWRITE);
2448: xr->xr_cookies[ri] = cookie;
2449: ri++;
2450: }
2451:
1.11 dsl 2452: /* Write the first TRB last */
1.1 jakllsch 2453: i = 0;
1.28.2.16 skrll 2454: parameter = trbs[i].trb_0;
2455: status = trbs[i].trb_2;
2456: control = trbs[i].trb_3;
1.1 jakllsch 2457:
1.28.2.16 skrll 2458: if (xr->xr_cs) {
2459: control |= XHCI_TRB_3_CYCLE_BIT;
2460: } else {
2461: control &= ~XHCI_TRB_3_CYCLE_BIT;
1.1 jakllsch 2462: }
2463:
1.28.2.34 skrll 2464: xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control);
1.28.2.16 skrll 2465: usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1,
2466: BUS_DMASYNC_PREWRITE);
2467: xr->xr_cookies[xr->xr_ep] = cookie;
2468:
1.1 jakllsch 2469: xr->xr_ep = ri;
2470: xr->xr_cs = cs;
2471:
1.27 skrll 2472: DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0);
1.1 jakllsch 2473: }
2474:
1.28.2.20 skrll 2475: /*
2476: * Put a command on command ring, ring bell, set timer, and cv_timedwait.
2477: * Command completion is notified by cv_signal from xhci_handle_event
2478: * (called from interrupt from xHCI), or timed-out.
2479: * Command validation is performed in xhci_handle_event by checking if
2480: * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical.
2481: */
1.1 jakllsch 2482: static usbd_status
1.28.2.19 skrll 2483: xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb,
2484: int timeout, int locked)
1.1 jakllsch 2485: {
2486: struct xhci_ring * const cr = &sc->sc_cr;
2487: usbd_status err;
2488:
1.27 skrll 2489: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2490: DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32,
2491: trb->trb_0, trb->trb_2, trb->trb_3, 0);
1.1 jakllsch 2492:
1.28.2.19 skrll 2493: KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx");
2494:
2495: if (!locked)
2496: mutex_enter(&sc->sc_lock);
1.1 jakllsch 2497:
1.28.2.31 skrll 2498: /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */
1.1 jakllsch 2499: KASSERT(sc->sc_command_addr == 0);
2500: sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep);
2501:
2502: mutex_enter(&cr->xr_lock);
2503: xhci_ring_put(sc, cr, NULL, trb, 1);
2504: mutex_exit(&cr->xr_lock);
2505:
2506: xhci_db_write_4(sc, XHCI_DOORBELL(0), 0);
2507:
2508: if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock,
2509: MAX(1, mstohz(timeout))) == EWOULDBLOCK) {
2510: err = USBD_TIMEOUT;
2511: goto timedout;
2512: }
2513:
2514: trb->trb_0 = sc->sc_result_trb.trb_0;
2515: trb->trb_2 = sc->sc_result_trb.trb_2;
2516: trb->trb_3 = sc->sc_result_trb.trb_3;
2517:
1.27 skrll 2518: DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"",
2519: trb->trb_0, trb->trb_2, trb->trb_3, 0);
1.1 jakllsch 2520:
2521: switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) {
2522: case XHCI_TRB_ERROR_SUCCESS:
2523: err = USBD_NORMAL_COMPLETION;
2524: break;
2525: default:
2526: case 192 ... 223:
2527: err = USBD_IOERROR;
2528: break;
2529: case 224 ... 255:
2530: err = USBD_NORMAL_COMPLETION;
2531: break;
2532: }
2533:
2534: timedout:
2535: sc->sc_command_addr = 0;
1.28.2.19 skrll 2536: if (!locked)
2537: mutex_exit(&sc->sc_lock);
1.1 jakllsch 2538: return err;
2539: }
2540:
2541: static usbd_status
1.28.2.19 skrll 2542: xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb,
2543: int timeout)
2544: {
2545: return xhci_do_command1(sc, trb, timeout, 0);
2546: }
2547:
1.28.2.20 skrll 2548: /*
2549: * This allows xhci_do_command with already sc_lock held.
2550: * This is needed as USB stack calls close methods with sc_lock_held.
2551: * (see usbdivar.h)
2552: */
1.28.2.19 skrll 2553: static usbd_status
2554: xhci_do_command_locked(struct xhci_softc * const sc,
2555: struct xhci_trb * const trb, int timeout)
2556: {
2557: return xhci_do_command1(sc, trb, timeout, 1);
2558: }
2559:
2560: static usbd_status
1.1 jakllsch 2561: xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp)
2562: {
2563: struct xhci_trb trb;
2564: usbd_status err;
2565:
1.27 skrll 2566: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2567:
1.1 jakllsch 2568: trb.trb_0 = 0;
2569: trb.trb_2 = 0;
2570: trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT);
2571:
2572: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
2573: if (err != USBD_NORMAL_COMPLETION) {
2574: return err;
2575: }
2576:
2577: *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3);
2578:
2579: return err;
2580: }
2581:
1.28.2.20 skrll 2582: /*
2583: * Deallocate DMA buffer and ring buffer, and disable_slot.
2584: * Should be called with sc_lock held.
2585: */
1.1 jakllsch 2586: static usbd_status
1.28.2.19 skrll 2587: xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot)
2588: {
2589: struct xhci_trb trb;
2590: struct xhci_slot *xs;
2591:
2592: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2593:
2594: if (sc->sc_dying)
2595: return USBD_IOERROR;
2596:
2597: xs = &sc->sc_slots[slot];
2598: if (xs->xs_idx != 0) {
2599: for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) {
2600: xhci_ring_free(sc, &xs->xs_ep[i].xe_tr);
2601: memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i]));
2602: }
2603: usb_freemem(&sc->sc_bus, &xs->xs_ic_dma);
2604: usb_freemem(&sc->sc_bus, &xs->xs_dc_dma);
2605: }
2606:
2607: trb.trb_0 = 0;
2608: trb.trb_2 = 0;
2609: trb.trb_3 = htole32(
2610: XHCI_TRB_3_SLOT_SET(slot) |
2611: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT));
2612:
2613: return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
2614: }
2615:
1.28.2.20 skrll 2616: /*
2617: * Change slot state.
2618: * bsr=0: ENABLED -> ADDRESSED
2619: * bsr=1: ENABLED -> DEFAULT
2620: * see xHCI 1.1 4.5.3, 3.3.4
2621: */
1.28.2.19 skrll 2622: static usbd_status
1.1 jakllsch 2623: xhci_address_device(struct xhci_softc * const sc,
2624: uint64_t icp, uint8_t slot_id, bool bsr)
2625: {
2626: struct xhci_trb trb;
2627: usbd_status err;
2628:
1.27 skrll 2629: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2630:
1.1 jakllsch 2631: trb.trb_0 = icp;
2632: trb.trb_2 = 0;
2633: trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) |
2634: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
2635: (bsr ? XHCI_TRB_3_BSR_BIT : 0);
2636:
2637: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1.28.2.37 skrll 2638:
2639: if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS)
2640: err = USBD_NO_ADDR;
2641:
1.1 jakllsch 2642: return err;
2643: }
2644:
2645: static usbd_status
2646: xhci_update_ep0_mps(struct xhci_softc * const sc,
2647: struct xhci_slot * const xs, u_int mps)
2648: {
2649: struct xhci_trb trb;
2650: usbd_status err;
2651: uint32_t * cp;
2652:
1.27 skrll 2653: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2654: DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0);
1.1 jakllsch 2655:
2656: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
2657: cp[0] = htole32(0);
2658: cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL));
2659:
2660: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL));
2661: cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps));
2662:
2663: /* sync input contexts before they are read from memory */
2664: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
2665: hexdump("input context", xhci_slot_get_icv(sc, xs, 0),
2666: sc->sc_ctxsz * 4);
2667:
2668: trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
2669: trb.trb_2 = 0;
2670: trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
2671: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX);
2672:
2673: err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
2674: KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */
2675: return err;
2676: }
2677:
2678: static void
2679: xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si)
2680: {
2681: uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0);
2682:
1.27 skrll 2683: XHCIHIST_FUNC(); XHCIHIST_CALLED();
2684: DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d",
2685: &dcbaa[si], dcba, si, 0);
1.1 jakllsch 2686:
1.5 matt 2687: dcbaa[si] = htole64(dcba);
1.1 jakllsch 2688: usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t),
2689: BUS_DMASYNC_PREWRITE);
2690: }
2691:
1.28.2.20 skrll 2692: /*
2693: * Allocate DMA buffer and ring buffer for specified slot
2694: * and set Device Context Base Address
2695: * and issue Set Address device command.
2696: */
1.1 jakllsch 2697: static usbd_status
1.28.2.19 skrll 2698: xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport)
1.1 jakllsch 2699: {
1.28.2.42 skrll 2700: struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus);
1.1 jakllsch 2701: struct xhci_slot *xs;
2702: usbd_status err;
2703: u_int dci;
2704: uint32_t *cp;
1.28.2.19 skrll 2705: uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize);
1.1 jakllsch 2706:
1.27 skrll 2707: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.19 skrll 2708: DPRINTFN(4, "slot %u speed %d rhport %d route %05x",
2709: slot, dev->ud_speed, route, rhport);
1.1 jakllsch 2710:
2711: xs = &sc->sc_slots[slot];
2712:
2713: /* allocate contexts */
2714: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz,
2715: &xs->xs_dc_dma);
2716: if (err)
2717: return err;
2718: memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz);
2719:
2720: err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz,
2721: &xs->xs_ic_dma);
2722: if (err)
1.28.2.19 skrll 2723: goto bad1;
1.1 jakllsch 2724: memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz);
2725:
2726: for (dci = 0; dci < 32; dci++) {
2727: //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint));
2728: memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci]));
2729: if (dci == XHCI_DCI_SLOT)
2730: continue;
2731: err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr,
2732: XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN);
2733: if (err) {
1.27 skrll 2734: DPRINTFN(0, "ring init failure", 0, 0, 0, 0);
1.28.2.19 skrll 2735: goto bad2;
1.1 jakllsch 2736: }
2737: }
2738:
2739: /* set up initial input control context */
2740: cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL);
2741: cp[0] = htole32(0);
2742: cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)|
2743: XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT));
2744:
2745: /* set up input slot context */
2746: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT));
1.28.2.19 skrll 2747: xhci_setup_sctx(dev, cp);
2748: cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1));
2749: cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route));
2750: cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport));
1.1 jakllsch 2751:
2752: /* set up input EP0 context */
2753: cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL));
2754: cp[0] = htole32(0);
2755: cp[1] = htole32(
2756: XHCI_EPCTX_1_MAXP_SIZE_SET(mps) |
2757: XHCI_EPCTX_1_EPTYPE_SET(4) |
2758: XHCI_EPCTX_1_CERR_SET(3)
2759: );
2760: /* can't use xhci_ep_get_dci() yet? */
2761: *(uint64_t *)(&cp[2]) = htole64(
2762: xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) |
2763: XHCI_EPCTX_2_DCS_SET(1));
2764: cp[4] = htole32(
2765: XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)
2766: );
2767:
2768: /* sync input contexts before they are read from memory */
2769: usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE);
2770: hexdump("input context", xhci_slot_get_icv(sc, xs, 0),
2771: sc->sc_ctxsz * 3);
2772:
2773: xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot);
2774:
2775: err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot,
2776: false);
2777:
2778: usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD);
2779: hexdump("output context", xhci_slot_get_dcv(sc, xs, 0),
2780: sc->sc_ctxsz * 2);
2781:
1.28.2.19 skrll 2782: bad2:
2783: if (err == USBD_NORMAL_COMPLETION) {
2784: xs->xs_idx = slot;
2785: } else {
2786: for (int i = 1; i < dci; i++) {
2787: xhci_ring_free(sc, &xs->xs_ep[i].xe_tr);
2788: memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i]));
2789: }
2790: usb_freemem(&sc->sc_bus, &xs->xs_ic_dma);
2791: bad1:
2792: usb_freemem(&sc->sc_bus, &xs->xs_dc_dma);
2793: xs->xs_idx = 0;
2794: }
2795:
1.1 jakllsch 2796: return err;
2797: }
2798:
2799: /* ----- */
2800:
2801: static void
1.28.2.14 skrll 2802: xhci_noop(struct usbd_pipe *pipe)
1.1 jakllsch 2803: {
1.27 skrll 2804: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2805: }
2806:
1.28.2.20 skrll 2807: /*
2808: * Process root hub request.
2809: */
1.28.2.18 skrll 2810: static int
2811: xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
1.28.2.12 skrll 2812: void *buf, int buflen)
1.1 jakllsch 2813: {
1.28.2.42 skrll 2814: struct xhci_softc * const sc = XHCI_BUS2SC(bus);
1.1 jakllsch 2815: usb_port_status_t ps;
2816: int l, totlen = 0;
1.28.2.12 skrll 2817: uint16_t len, value, index;
1.1 jakllsch 2818: int port, i;
2819: uint32_t v;
2820:
1.27 skrll 2821: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 2822:
2823: if (sc->sc_dying)
1.28.2.12 skrll 2824: return -1;
1.1 jakllsch 2825:
1.28.2.12 skrll 2826: len = UGETW(req->wLength);
1.1 jakllsch 2827: value = UGETW(req->wValue);
2828: index = UGETW(req->wIndex);
2829:
1.27 skrll 2830: DPRINTFN(12, "rhreq: %04x %04x %04x %04x",
2831: req->bmRequestType | (req->bRequest << 8), value, index, len);
1.1 jakllsch 2832:
2833: #define C(x,y) ((x) | ((y) << 8))
1.28.2.12 skrll 2834: switch (C(req->bRequest, req->bmRequestType)) {
1.1 jakllsch 2835: case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1.27 skrll 2836: DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0);
1.1 jakllsch 2837: if (len == 0)
2838: break;
1.28.2.12 skrll 2839: switch (value) {
1.28.2.34 skrll 2840: case C(0, UDESC_DEVICE): {
2841: usb_device_descriptor_t devd;
2842: totlen = min(buflen, sizeof(devd));
2843: memcpy(&devd, buf, totlen);
2844: USETW(devd.idVendor, sc->sc_id_vendor);
2845: memcpy(buf, &devd, totlen);
2846: break;
2847: }
1.1 jakllsch 2848: #define sd ((usb_string_descriptor_t *)buf)
1.28.2.34 skrll 2849: case C(1, UDESC_STRING):
2850: /* Vendor */
2851: totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
2852: break;
1.28.2.12 skrll 2853: case C(2, UDESC_STRING):
2854: /* Product */
2855: totlen = usb_makestrdesc(sd, len, "xHCI Root Hub");
1.1 jakllsch 2856: break;
1.28.2.12 skrll 2857: #undef sd
1.1 jakllsch 2858: default:
1.28.2.12 skrll 2859: /* default from usbroothub */
2860: return buflen;
1.1 jakllsch 2861: }
2862: break;
1.28.2.12 skrll 2863:
1.1 jakllsch 2864: /* Hub requests */
2865: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2866: break;
1.28.2.44 skrll 2867: /* Clear Port Feature request */
1.1 jakllsch 2868: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1.27 skrll 2869: DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d",
2870: index, value, 0, 0);
1.28.2.19 skrll 2871: if (index < 1 || index > sc->sc_maxports) {
1.28.2.12 skrll 2872: return -1;
1.1 jakllsch 2873: }
1.28.2.19 skrll 2874: port = XHCI_PORTSC(index);
1.1 jakllsch 2875: v = xhci_op_read_4(sc, port);
1.27 skrll 2876: DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0);
1.1 jakllsch 2877: v &= ~XHCI_PS_CLEAR;
2878: switch (value) {
2879: case UHF_PORT_ENABLE:
1.28.2.43 skrll 2880: xhci_op_write_4(sc, port, v & ~XHCI_PS_PED);
1.1 jakllsch 2881: break;
2882: case UHF_PORT_SUSPEND:
1.28.2.12 skrll 2883: return -1;
1.1 jakllsch 2884: case UHF_PORT_POWER:
2885: break;
2886: case UHF_PORT_TEST:
2887: case UHF_PORT_INDICATOR:
1.28.2.12 skrll 2888: return -1;
1.1 jakllsch 2889: case UHF_C_PORT_CONNECTION:
2890: xhci_op_write_4(sc, port, v | XHCI_PS_CSC);
2891: break;
2892: case UHF_C_PORT_ENABLE:
2893: case UHF_C_PORT_SUSPEND:
2894: case UHF_C_PORT_OVER_CURRENT:
1.28.2.12 skrll 2895: return -1;
1.28.2.19 skrll 2896: case UHF_C_BH_PORT_RESET:
2897: xhci_op_write_4(sc, port, v | XHCI_PS_WRC);
2898: break;
1.1 jakllsch 2899: case UHF_C_PORT_RESET:
2900: xhci_op_write_4(sc, port, v | XHCI_PS_PRC);
2901: break;
1.28.2.19 skrll 2902: case UHF_C_PORT_LINK_STATE:
2903: xhci_op_write_4(sc, port, v | XHCI_PS_PLC);
2904: break;
2905: case UHF_C_PORT_CONFIG_ERROR:
2906: xhci_op_write_4(sc, port, v | XHCI_PS_CEC);
2907: break;
1.1 jakllsch 2908: default:
1.28.2.12 skrll 2909: return -1;
1.1 jakllsch 2910: }
2911: break;
2912: case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2913: if (len == 0)
2914: break;
2915: if ((value & 0xff) != 0) {
1.28.2.12 skrll 2916: return -1;
1.1 jakllsch 2917: }
1.28.2.12 skrll 2918: usb_hub_descriptor_t hubd;
2919:
2920: totlen = min(buflen, sizeof(hubd));
2921: memcpy(&hubd, buf, totlen);
1.28.2.19 skrll 2922: hubd.bNbrPorts = sc->sc_maxports;
1.1 jakllsch 2923: USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH);
2924: hubd.bPwrOn2PwrGood = 200;
1.2 apb 2925: for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8)
1.3 skrll 2926: hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
2927: hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1.28.2.12 skrll 2928: totlen = min(totlen, hubd.bDescLength);
2929: memcpy(buf, &hubd, totlen);
1.1 jakllsch 2930: break;
2931: case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2932: if (len != 4) {
1.28.2.12 skrll 2933: return -1;
1.1 jakllsch 2934: }
2935: memset(buf, 0, len); /* ? XXX */
2936: totlen = len;
2937: break;
1.28.2.44 skrll 2938: /* Get Port Status request */
1.1 jakllsch 2939: case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1.27 skrll 2940: DPRINTFN(8, "get port status i=%d", index, 0, 0, 0);
1.1 jakllsch 2941: if (index < 1 || index > sc->sc_maxports) {
1.28.2.12 skrll 2942: return -1;
1.1 jakllsch 2943: }
2944: if (len != 4) {
1.28.2.12 skrll 2945: return -1;
1.1 jakllsch 2946: }
1.28.2.19 skrll 2947: v = xhci_op_read_4(sc, XHCI_PORTSC(index));
2948: DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0);
1.28.2.27 skrll 2949: i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v));
1.1 jakllsch 2950: if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS;
2951: if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED;
2952: if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
2953: //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND;
2954: if (v & XHCI_PS_PR) i |= UPS_RESET;
1.28.2.19 skrll 2955: if (v & XHCI_PS_PP) {
1.28.2.27 skrll 2956: if (i & UPS_OTHER_SPEED)
1.28.2.19 skrll 2957: i |= UPS_PORT_POWER_SS;
2958: else
2959: i |= UPS_PORT_POWER;
2960: }
1.28.2.27 skrll 2961: if (i & UPS_OTHER_SPEED)
2962: i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v));
1.28.2.34 skrll 2963: if (sc->sc_vendor_port_status)
2964: i = sc->sc_vendor_port_status(sc, v, i);
1.1 jakllsch 2965: USETW(ps.wPortStatus, i);
2966: i = 0;
2967: if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
2968: if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
2969: if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
2970: if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET;
1.28.2.19 skrll 2971: if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET;
2972: if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE;
2973: if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR;
1.1 jakllsch 2974: USETW(ps.wPortChange, i);
1.28.2.12 skrll 2975: totlen = min(len, sizeof(ps));
2976: memcpy(buf, &ps, totlen);
1.1 jakllsch 2977: break;
2978: case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1.28.2.12 skrll 2979: return -1;
1.28.2.19 skrll 2980: case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE):
2981: break;
1.1 jakllsch 2982: case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2983: break;
1.28.2.44 skrll 2984: /* Set Port Feature request */
1.28.2.21 skrll 2985: case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): {
1.28.2.19 skrll 2986: int optval = (index >> 8) & 0xff;
2987: index &= 0xff;
2988: if (index < 1 || index > sc->sc_maxports) {
1.28.2.12 skrll 2989: return -1;
1.1 jakllsch 2990: }
1.28.2.19 skrll 2991: port = XHCI_PORTSC(index);
1.1 jakllsch 2992: v = xhci_op_read_4(sc, port);
1.27 skrll 2993: DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0);
1.28.2.45 skrll 2994: uint32_t v0 = v;
1.1 jakllsch 2995: v &= ~XHCI_PS_CLEAR;
2996: switch (value) {
2997: case UHF_PORT_ENABLE:
2998: xhci_op_write_4(sc, port, v | XHCI_PS_PED);
2999: break;
3000: case UHF_PORT_SUSPEND:
3001: /* XXX suspend */
3002: break;
3003: case UHF_PORT_RESET:
1.28.2.43 skrll 3004: v &= ~(XHCI_PS_PED | XHCI_PS_PR);
1.1 jakllsch 3005: xhci_op_write_4(sc, port, v | XHCI_PS_PR);
3006: /* Wait for reset to complete. */
3007: usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3008: if (sc->sc_dying) {
1.28.2.12 skrll 3009: return -1;
1.1 jakllsch 3010: }
3011: v = xhci_op_read_4(sc, port);
3012: if (v & XHCI_PS_PR) {
3013: xhci_op_write_4(sc, port, v & ~XHCI_PS_PR);
3014: usb_delay_ms(&sc->sc_bus, 10);
3015: /* XXX */
3016: }
3017: break;
3018: case UHF_PORT_POWER:
3019: /* XXX power control */
3020: break;
3021: /* XXX more */
3022: case UHF_C_PORT_RESET:
3023: xhci_op_write_4(sc, port, v | XHCI_PS_PRC);
3024: break;
1.28.2.19 skrll 3025: case UHF_PORT_U1_TIMEOUT:
1.28.2.45 skrll 3026: if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) {
1.28.2.19 skrll 3027: return -1;
3028: }
3029: port = XHCI_PORTPMSC(index);
3030: v = xhci_op_read_4(sc, port);
3031: v &= ~XHCI_PM3_U1TO_SET(0xff);
3032: v |= XHCI_PM3_U1TO_SET(optval);
3033: xhci_op_write_4(sc, port, v);
3034: break;
3035: case UHF_PORT_U2_TIMEOUT:
1.28.2.45 skrll 3036: if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) {
1.28.2.19 skrll 3037: return -1;
3038: }
3039: port = XHCI_PORTPMSC(index);
3040: v = xhci_op_read_4(sc, port);
3041: v &= ~XHCI_PM3_U2TO_SET(0xff);
3042: v |= XHCI_PM3_U2TO_SET(optval);
3043: xhci_op_write_4(sc, port, v);
3044: break;
1.1 jakllsch 3045: default:
1.28.2.12 skrll 3046: return -1;
1.1 jakllsch 3047: }
1.28.2.19 skrll 3048: }
1.1 jakllsch 3049: break;
3050: case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3051: case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3052: case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3053: case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3054: break;
3055: default:
1.28.2.12 skrll 3056: /* default from usbroothub */
3057: return buflen;
1.1 jakllsch 3058: }
3059:
1.28.2.12 skrll 3060: return totlen;
1.1 jakllsch 3061: }
3062:
1.28.2.17 skrll 3063: /* root hub interrupt */
1.1 jakllsch 3064:
3065: static usbd_status
1.28.2.14 skrll 3066: xhci_root_intr_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3067: {
1.28.2.42 skrll 3068: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3069: usbd_status err;
3070:
1.27 skrll 3071: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3072:
1.1 jakllsch 3073: /* Insert last in queue. */
3074: mutex_enter(&sc->sc_lock);
3075: err = usb_insert_transfer(xfer);
3076: mutex_exit(&sc->sc_lock);
3077: if (err)
3078: return err;
3079:
3080: /* Pipe isn't running, start first */
1.28.2.13 skrll 3081: return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3082: }
3083:
1.28.2.20 skrll 3084: /* Wait for roothub port status/change */
1.1 jakllsch 3085: static usbd_status
1.28.2.14 skrll 3086: xhci_root_intr_start(struct usbd_xfer *xfer)
1.1 jakllsch 3087: {
1.28.2.42 skrll 3088: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3089:
1.27 skrll 3090: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3091:
1.1 jakllsch 3092: if (sc->sc_dying)
3093: return USBD_IOERROR;
3094:
3095: mutex_enter(&sc->sc_lock);
3096: sc->sc_intrxfer = xfer;
3097: mutex_exit(&sc->sc_lock);
3098:
3099: return USBD_IN_PROGRESS;
3100: }
3101:
3102: static void
1.28.2.14 skrll 3103: xhci_root_intr_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3104: {
1.28.2.42 skrll 3105: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3106:
1.27 skrll 3107: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3108:
1.1 jakllsch 3109: KASSERT(mutex_owned(&sc->sc_lock));
1.28.2.5 skrll 3110: KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
1.21 skrll 3111:
1.22 skrll 3112: sc->sc_intrxfer = NULL;
3113:
1.28.2.5 skrll 3114: xfer->ux_status = USBD_CANCELLED;
1.1 jakllsch 3115: usb_transfer_complete(xfer);
3116: }
3117:
3118: static void
1.28.2.14 skrll 3119: xhci_root_intr_close(struct usbd_pipe *pipe)
1.1 jakllsch 3120: {
1.28.2.42 skrll 3121: struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.1 jakllsch 3122:
1.27 skrll 3123: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3124:
1.1 jakllsch 3125: KASSERT(mutex_owned(&sc->sc_lock));
3126:
3127: sc->sc_intrxfer = NULL;
3128: }
3129:
3130: static void
1.28.2.14 skrll 3131: xhci_root_intr_done(struct usbd_xfer *xfer)
1.1 jakllsch 3132: {
1.27 skrll 3133: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3134:
1.28.2.5 skrll 3135: xfer->ux_hcpriv = NULL;
1.1 jakllsch 3136: }
3137:
3138: /* -------------- */
3139: /* device control */
3140:
3141: static usbd_status
1.28.2.14 skrll 3142: xhci_device_ctrl_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3143: {
1.28.2.42 skrll 3144: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3145: usbd_status err;
3146:
1.27 skrll 3147: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3148:
1.1 jakllsch 3149: /* Insert last in queue. */
3150: mutex_enter(&sc->sc_lock);
3151: err = usb_insert_transfer(xfer);
3152: mutex_exit(&sc->sc_lock);
3153: if (err)
1.28.2.13 skrll 3154: return err;
1.1 jakllsch 3155:
3156: /* Pipe isn't running, start first */
1.28.2.13 skrll 3157: return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3158: }
3159:
3160: static usbd_status
1.28.2.14 skrll 3161: xhci_device_ctrl_start(struct usbd_xfer *xfer)
1.1 jakllsch 3162: {
1.28.2.42 skrll 3163: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.28.2.5 skrll 3164: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3165: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3166: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
3167: struct xhci_xfer * const xx = (void *)xfer;
1.28.2.5 skrll 3168: usb_device_request_t * const req = &xfer->ux_request;
1.28.2.34 skrll 3169: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 3170: const uint32_t len = UGETW(req->wLength);
1.28.2.5 skrll 3171: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3172: uint64_t parameter;
3173: uint32_t status;
3174: uint32_t control;
3175: u_int i;
3176:
1.27 skrll 3177: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3178: DPRINTFN(12, "req: %04x %04x %04x %04x",
3179: req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue),
3180: UGETW(req->wIndex), UGETW(req->wLength));
1.1 jakllsch 3181:
1.28.2.37 skrll 3182: #if 0 /* event handler does this */
1.1 jakllsch 3183: /* XXX */
3184: if (tr->is_halted) {
1.28.2.19 skrll 3185: DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u",
3186: xfer, xs->xs_idx, dci, 0);
1.28.2.5 skrll 3187: xhci_reset_endpoint(xfer->ux_pipe);
1.1 jakllsch 3188: tr->is_halted = false;
1.28.2.5 skrll 3189: xhci_set_dequeue(xfer->ux_pipe);
1.1 jakllsch 3190: }
1.28.2.37 skrll 3191: #endif
1.1 jakllsch 3192:
3193: /* we rely on the bottom bits for extra info */
3194: KASSERT(((uintptr_t)xfer & 0x3) == 0x0);
3195:
1.28.2.5 skrll 3196: KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0);
1.1 jakllsch 3197:
3198: i = 0;
3199:
3200: /* setup phase */
3201: memcpy(¶meter, req, sizeof(*req));
3202: status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req));
3203: control = ((len == 0) ? XHCI_TRB_3_TRT_NONE :
3204: (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) |
3205: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
3206: XHCI_TRB_3_IDT_BIT;
3207: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3208:
1.28.2.50 skrll 3209: if (len != 0) {
3210: /* data phase */
3211: parameter = DMAADDR(dma, 0);
3212: KASSERT(len <= 0x10000);
3213: status = XHCI_TRB_2_IRQ_SET(0) |
3214: XHCI_TRB_2_TDSZ_SET(1) |
3215: XHCI_TRB_2_BYTES_SET(len);
3216: control = (isread ? XHCI_TRB_3_DIR_IN : 0) |
3217: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
3218: XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT;
3219: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3220:
3221: parameter = (uintptr_t)xfer | 0x3;
3222: status = XHCI_TRB_2_IRQ_SET(0);
3223: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) |
3224: XHCI_TRB_3_IOC_BIT;
3225: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3226: }
1.1 jakllsch 3227:
3228: parameter = 0;
1.28 skrll 3229: status = XHCI_TRB_2_IRQ_SET(0);
1.1 jakllsch 3230: /* the status stage has inverted direction */
1.28 skrll 3231: control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) |
1.1 jakllsch 3232: XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
3233: XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT;
3234: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3235:
3236: parameter = (uintptr_t)xfer | 0x0;
3237: status = XHCI_TRB_2_IRQ_SET(0);
3238: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) |
3239: XHCI_TRB_3_IOC_BIT;
3240: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3241:
3242: mutex_enter(&tr->xr_lock);
3243: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
3244: mutex_exit(&tr->xr_lock);
3245:
3246: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
3247:
1.28.2.5 skrll 3248: if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
3249: callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1.1 jakllsch 3250: xhci_timeout, xfer);
3251: }
3252:
1.28.2.5 skrll 3253: if (sc->sc_bus.ub_usepolling) {
1.27 skrll 3254: DPRINTFN(1, "polling", 0, 0, 0, 0);
1.1 jakllsch 3255: //xhci_waitintr(sc, xfer);
3256: }
3257:
3258: return USBD_IN_PROGRESS;
3259: }
3260:
3261: static void
1.28.2.14 skrll 3262: xhci_device_ctrl_done(struct usbd_xfer *xfer)
1.1 jakllsch 3263: {
1.27 skrll 3264: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3265:
1.28.2.5 skrll 3266: callout_stop(&xfer->ux_callout); /* XXX wrong place */
1.1 jakllsch 3267:
3268: }
3269:
3270: static void
1.28.2.14 skrll 3271: xhci_device_ctrl_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3272: {
1.27 skrll 3273: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.19 skrll 3274:
3275: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 3276: }
3277:
3278: static void
1.28.2.14 skrll 3279: xhci_device_ctrl_close(struct usbd_pipe *pipe)
1.1 jakllsch 3280: {
1.27 skrll 3281: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.19 skrll 3282:
1.28.2.33 skrll 3283: xhci_close_pipe(pipe);
1.1 jakllsch 3284: }
3285:
1.28.2.15 skrll 3286: /* ------------------ */
3287: /* device isochronous */
1.1 jakllsch 3288:
3289: /* ----------- */
3290: /* device bulk */
3291:
3292: static usbd_status
1.28.2.14 skrll 3293: xhci_device_bulk_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3294: {
1.28.2.42 skrll 3295: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3296: usbd_status err;
3297:
1.27 skrll 3298: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3299:
1.1 jakllsch 3300: /* Insert last in queue. */
3301: mutex_enter(&sc->sc_lock);
3302: err = usb_insert_transfer(xfer);
3303: mutex_exit(&sc->sc_lock);
3304: if (err)
3305: return err;
3306:
3307: /*
3308: * Pipe isn't running (otherwise err would be USBD_INPROG),
3309: * so start it first.
3310: */
1.28.2.13 skrll 3311: return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3312: }
3313:
3314: static usbd_status
1.28.2.14 skrll 3315: xhci_device_bulk_start(struct usbd_xfer *xfer)
1.1 jakllsch 3316: {
1.28.2.42 skrll 3317: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.28.2.5 skrll 3318: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3319: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3320: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
3321: struct xhci_xfer * const xx = (void *)xfer;
1.28.2.5 skrll 3322: const uint32_t len = xfer->ux_length;
3323: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3324: uint64_t parameter;
3325: uint32_t status;
3326: uint32_t control;
3327: u_int i = 0;
3328:
1.27 skrll 3329: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3330:
3331: DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0);
1.1 jakllsch 3332:
3333: if (sc->sc_dying)
3334: return USBD_IOERROR;
3335:
1.28.2.5 skrll 3336: KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0);
1.1 jakllsch 3337:
3338: parameter = DMAADDR(dma, 0);
1.11 dsl 3339: /*
1.13 dsl 3340: * XXX: (dsl) The physical buffer must not cross a 64k boundary.
1.11 dsl 3341: * If the user supplied buffer crosses such a boundary then 2
3342: * (or more) TRB should be used.
3343: * If multiple TRB are used the td_size field must be set correctly.
3344: * For v1.0 devices (like ivy bridge) this is the number of usb data
3345: * blocks needed to complete the transfer.
3346: * Setting it to 1 in the last TRB causes an extra zero-length
3347: * data block be sent.
3348: * The earlier documentation differs, I don't know how it behaves.
3349: */
1.1 jakllsch 3350: KASSERT(len <= 0x10000);
3351: status = XHCI_TRB_2_IRQ_SET(0) |
3352: XHCI_TRB_2_TDSZ_SET(1) |
3353: XHCI_TRB_2_BYTES_SET(len);
3354: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
3355: XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT;
3356: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3357:
3358: mutex_enter(&tr->xr_lock);
3359: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
3360: mutex_exit(&tr->xr_lock);
3361:
3362: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
3363:
1.28.2.5 skrll 3364: if (sc->sc_bus.ub_usepolling) {
1.27 skrll 3365: DPRINTFN(1, "polling", 0, 0, 0, 0);
1.1 jakllsch 3366: //xhci_waitintr(sc, xfer);
3367: }
3368:
3369: return USBD_IN_PROGRESS;
3370: }
3371:
3372: static void
1.28.2.14 skrll 3373: xhci_device_bulk_done(struct usbd_xfer *xfer)
1.1 jakllsch 3374: {
1.27 skrll 3375: #ifdef USB_DEBUG
1.28.2.5 skrll 3376: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3377: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.27 skrll 3378: #endif
1.28.2.34 skrll 3379: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 3380:
1.27 skrll 3381: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.1 jakllsch 3382:
1.27 skrll 3383: DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0);
1.1 jakllsch 3384:
1.28.2.5 skrll 3385: callout_stop(&xfer->ux_callout); /* XXX wrong place */
1.1 jakllsch 3386:
1.28.2.5 skrll 3387: usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1.1 jakllsch 3388: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3389: }
3390:
3391: static void
1.28.2.14 skrll 3392: xhci_device_bulk_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3393: {
1.27 skrll 3394: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.19 skrll 3395:
3396: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 3397: }
3398:
3399: static void
1.28.2.14 skrll 3400: xhci_device_bulk_close(struct usbd_pipe *pipe)
1.1 jakllsch 3401: {
1.27 skrll 3402: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.28.2.19 skrll 3403:
1.28.2.33 skrll 3404: xhci_close_pipe(pipe);
1.1 jakllsch 3405: }
3406:
1.28.2.15 skrll 3407: /* ---------------- */
3408: /* device interrupt */
1.1 jakllsch 3409:
3410: static usbd_status
1.28.2.14 skrll 3411: xhci_device_intr_transfer(struct usbd_xfer *xfer)
1.1 jakllsch 3412: {
1.28.2.42 skrll 3413: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3414: usbd_status err;
3415:
1.27 skrll 3416: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3417:
1.1 jakllsch 3418: /* Insert last in queue. */
3419: mutex_enter(&sc->sc_lock);
3420: err = usb_insert_transfer(xfer);
3421: mutex_exit(&sc->sc_lock);
3422: if (err)
3423: return err;
3424:
3425: /*
3426: * Pipe isn't running (otherwise err would be USBD_INPROG),
3427: * so start it first.
3428: */
1.28.2.13 skrll 3429: return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1.1 jakllsch 3430: }
3431:
3432: static usbd_status
1.28.2.14 skrll 3433: xhci_device_intr_start(struct usbd_xfer *xfer)
1.1 jakllsch 3434: {
1.28.2.42 skrll 3435: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.28.2.5 skrll 3436: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3437: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.1 jakllsch 3438: struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr;
3439: struct xhci_xfer * const xx = (void *)xfer;
1.28.2.5 skrll 3440: const uint32_t len = xfer->ux_length;
3441: usb_dma_t * const dma = &xfer->ux_dmabuf;
1.1 jakllsch 3442: uint64_t parameter;
3443: uint32_t status;
3444: uint32_t control;
3445: u_int i = 0;
3446:
1.27 skrll 3447: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3448:
3449: DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0);
1.1 jakllsch 3450:
3451: if (sc->sc_dying)
3452: return USBD_IOERROR;
3453:
1.28.2.5 skrll 3454: KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0);
1.1 jakllsch 3455:
3456: parameter = DMAADDR(dma, 0);
3457: KASSERT(len <= 0x10000);
3458: status = XHCI_TRB_2_IRQ_SET(0) |
3459: XHCI_TRB_2_TDSZ_SET(1) |
3460: XHCI_TRB_2_BYTES_SET(len);
3461: control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
3462: XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT;
3463: xhci_trb_put(&xx->xx_trb[i++], parameter, status, control);
3464:
3465: mutex_enter(&tr->xr_lock);
3466: xhci_ring_put(sc, tr, xfer, xx->xx_trb, i);
3467: mutex_exit(&tr->xr_lock);
3468:
3469: xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
3470:
1.28.2.5 skrll 3471: if (sc->sc_bus.ub_usepolling) {
1.27 skrll 3472: DPRINTFN(1, "polling", 0, 0, 0, 0);
1.1 jakllsch 3473: //xhci_waitintr(sc, xfer);
3474: }
3475:
3476: return USBD_IN_PROGRESS;
3477: }
3478:
3479: static void
1.28.2.14 skrll 3480: xhci_device_intr_done(struct usbd_xfer *xfer)
1.1 jakllsch 3481: {
1.20 pgoyette 3482: struct xhci_softc * const sc __diagused =
1.28.2.42 skrll 3483: XHCI_XFER2SC(xfer);
1.27 skrll 3484: #ifdef USB_DEBUG
1.28.2.5 skrll 3485: struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv;
3486: const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
1.19 ozaki-r 3487: #endif
1.28.2.34 skrll 3488: const int isread = usbd_xfer_isread(xfer);
1.1 jakllsch 3489:
1.27 skrll 3490: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3491:
3492: DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0);
1.1 jakllsch 3493:
1.28.2.5 skrll 3494: KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1.1 jakllsch 3495:
1.28.2.5 skrll 3496: usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1.1 jakllsch 3497: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3498:
3499: #if 0
3500: device_printf(sc->sc_dev, "");
1.28.2.5 skrll 3501: for (size_t i = 0; i < xfer->ux_length; i++) {
3502: printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]);
1.1 jakllsch 3503: }
3504: printf("\n");
3505: #endif
3506:
1.28.2.5 skrll 3507: if (xfer->ux_pipe->up_repeat) {
3508: xfer->ux_status = xhci_device_intr_start(xfer);
1.1 jakllsch 3509: } else {
1.28.2.5 skrll 3510: callout_stop(&xfer->ux_callout); /* XXX */
1.1 jakllsch 3511: }
3512:
3513: }
3514:
3515: static void
1.28.2.14 skrll 3516: xhci_device_intr_abort(struct usbd_xfer *xfer)
1.1 jakllsch 3517: {
1.27 skrll 3518: struct xhci_softc * const sc __diagused =
1.28.2.42 skrll 3519: XHCI_XFER2SC(xfer);
1.27 skrll 3520:
3521: XHCIHIST_FUNC(); XHCIHIST_CALLED();
1.10 skrll 3522:
3523: KASSERT(mutex_owned(&sc->sc_lock));
1.27 skrll 3524: DPRINTFN(15, "%p", xfer, 0, 0, 0);
1.28.2.5 skrll 3525: KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
1.28.2.19 skrll 3526: xhci_abort_xfer(xfer, USBD_CANCELLED);
1.1 jakllsch 3527: }
3528:
3529: static void
1.28.2.14 skrll 3530: xhci_device_intr_close(struct usbd_pipe *pipe)
1.1 jakllsch 3531: {
1.28.2.42 skrll 3532: //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe);
1.27 skrll 3533:
3534: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3535: DPRINTFN(15, "%p", pipe, 0, 0, 0);
3536:
1.28.2.33 skrll 3537: xhci_close_pipe(pipe);
1.1 jakllsch 3538: }
3539:
3540: /* ------------ */
3541:
3542: static void
3543: xhci_timeout(void *addr)
3544: {
3545: struct xhci_xfer * const xx = addr;
1.28.2.18 skrll 3546: struct usbd_xfer * const xfer = &xx->xx_xfer;
1.28.2.42 skrll 3547: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3548:
1.27 skrll 3549: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3550:
1.1 jakllsch 3551: if (sc->sc_dying) {
3552: return;
3553: }
3554:
3555: usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr,
3556: USB_TASKQ_MPSAFE);
1.28.2.5 skrll 3557: usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task,
1.1 jakllsch 3558: USB_TASKQ_HC);
3559: }
3560:
3561: static void
3562: xhci_timeout_task(void *addr)
3563: {
1.28.2.18 skrll 3564: struct usbd_xfer * const xfer = addr;
1.28.2.42 skrll 3565: struct xhci_softc * const sc = XHCI_XFER2SC(xfer);
1.1 jakllsch 3566:
1.27 skrll 3567: XHCIHIST_FUNC(); XHCIHIST_CALLED();
3568:
1.1 jakllsch 3569: mutex_enter(&sc->sc_lock);
3570: #if 0
3571: xhci_abort_xfer(xfer, USBD_TIMEOUT);
3572: #else
1.28.2.5 skrll 3573: xfer->ux_status = USBD_TIMEOUT;
1.1 jakllsch 3574: usb_transfer_complete(xfer);
3575: #endif
3576: mutex_exit(&sc->sc_lock);
3577: }
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