Annotation of src/sys/dev/usb/ehci.c, Revision 1.228
1.228 ! skrll 1: /* $NetBSD: ehci.c,v 1.227 2014/08/05 06:35:24 skrll Exp $ */
1.1 augustss 2:
3: /*
1.190 mrg 4: * Copyright (c) 2004-2012 The NetBSD Foundation, Inc.
1.1 augustss 5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
1.190 mrg 8: * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum,
9: * Jeremy Morse (jeremy.morse@gmail.com), Jared D. McNeill
10: * (jmcneill@invisible.ca) and Matthew R. Green (mrg@eterna.com.au).
1.1 augustss 11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31: * POSSIBILITY OF SUCH DAMAGE.
32: */
33:
34: /*
1.3 augustss 35: * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
1.1 augustss 36: *
1.35 enami 37: * The EHCI 1.0 spec can be found at
1.160 uebayasi 38: * http://www.intel.com/technology/usb/spec.htm
1.7 augustss 39: * and the USB 2.0 spec at
1.160 uebayasi 40: * http://www.usb.org/developers/docs/
1.1 augustss 41: *
42: */
1.4 lukem 43:
1.52 jdolecek 44: /*
45: * TODO:
46: * 1) hold off explorations by companion controllers until ehci has started.
47: *
1.148 cegger 48: * 2) The hub driver needs to handle and schedule the transaction translator,
1.100 augustss 49: * to assign place in frame where different devices get to go. See chapter
1.91 perry 50: * on hubs in USB 2.0 for details.
1.52 jdolecek 51: *
1.164 uebayasi 52: * 3) Command failures are not recovered correctly.
1.148 cegger 53: */
1.52 jdolecek 54:
1.4 lukem 55: #include <sys/cdefs.h>
1.228 ! skrll 56: __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.227 2014/08/05 06:35:24 skrll Exp $");
1.47 augustss 57:
58: #include "ohci.h"
59: #include "uhci.h"
1.1 augustss 60:
61: #include <sys/param.h>
62: #include <sys/systm.h>
63: #include <sys/kernel.h>
1.190 mrg 64: #include <sys/kmem.h>
1.1 augustss 65: #include <sys/device.h>
66: #include <sys/select.h>
67: #include <sys/proc.h>
68: #include <sys/queue.h>
1.126 ad 69: #include <sys/mutex.h>
70: #include <sys/bus.h>
1.187 mrg 71: #include <sys/cpu.h>
1.1 augustss 72:
73: #include <machine/endian.h>
74:
75: #include <dev/usb/usb.h>
76: #include <dev/usb/usbdi.h>
77: #include <dev/usb/usbdivar.h>
78: #include <dev/usb/usb_mem.h>
79: #include <dev/usb/usb_quirks.h>
80:
81: #include <dev/usb/ehcireg.h>
82: #include <dev/usb/ehcivar.h>
1.131 drochner 83: #include <dev/usb/usbroothub_subr.h>
1.1 augustss 84:
85: #ifdef EHCI_DEBUG
1.200 christos 86: static void __printflike(1, 2)
1.190 mrg 87: ehciprintf(const char *fmt, ...)
88: {
89: va_list ap;
90:
91: va_start(ap, fmt);
1.199 christos 92: vprintf(fmt, ap);
1.190 mrg 93: va_end(ap);
94: }
95:
96: #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0)
97: #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0)
1.6 augustss 98: int ehcidebug = 0;
1.1 augustss 99: #else
100: #define DPRINTF(x)
101: #define DPRINTFN(n,x)
102: #endif
103:
1.5 augustss 104: struct ehci_pipe {
105: struct usbd_pipe pipe;
1.55 mycroft 106: int nexttoggle;
107:
1.10 augustss 108: ehci_soft_qh_t *sqh;
109: union {
110: ehci_soft_qtd_t *qtd;
111: /* ehci_soft_itd_t *itd; */
112: } tail;
113: union {
114: /* Control pipe */
115: struct {
116: usb_dma_t reqdma;
117: } ctl;
118: /* Interrupt pipe */
1.78 augustss 119: struct {
120: u_int length;
121: } intr;
1.10 augustss 122: /* Bulk pipe */
123: struct {
124: u_int length;
125: } bulk;
126: /* Iso pipe */
1.139 jmcneill 127: struct {
128: u_int next_frame;
129: u_int cur_xfers;
130: } isoc;
1.10 augustss 131: } u;
1.5 augustss 132: };
133:
134: Static usbd_status ehci_open(usbd_pipe_handle);
135: Static void ehci_poll(struct usbd_bus *);
136: Static void ehci_softintr(void *);
1.11 augustss 137: Static int ehci_intr1(ehci_softc_t *);
1.15 augustss 138: Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
1.18 augustss 139: Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
1.139 jmcneill 140: Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *);
141: Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *);
1.18 augustss 142: Static void ehci_idone(struct ehci_xfer *);
1.15 augustss 143: Static void ehci_timeout(void *);
144: Static void ehci_timeout_task(void *);
1.108 xtraeme 145: Static void ehci_intrlist_timeout(void *);
1.190 mrg 146: Static void ehci_doorbell(void *);
147: Static void ehci_pcd(void *);
1.5 augustss 148:
149: Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
150: Static void ehci_freem(struct usbd_bus *, usb_dma_t *);
151:
152: Static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
153: Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
1.190 mrg 154: Static void ehci_get_lock(struct usbd_bus *, kmutex_t **);
1.5 augustss 155:
156: Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
157: Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
158: Static void ehci_root_ctrl_abort(usbd_xfer_handle);
159: Static void ehci_root_ctrl_close(usbd_pipe_handle);
160: Static void ehci_root_ctrl_done(usbd_xfer_handle);
161:
162: Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
163: Static usbd_status ehci_root_intr_start(usbd_xfer_handle);
164: Static void ehci_root_intr_abort(usbd_xfer_handle);
165: Static void ehci_root_intr_close(usbd_pipe_handle);
166: Static void ehci_root_intr_done(usbd_xfer_handle);
167:
168: Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
169: Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
170: Static void ehci_device_ctrl_abort(usbd_xfer_handle);
171: Static void ehci_device_ctrl_close(usbd_pipe_handle);
172: Static void ehci_device_ctrl_done(usbd_xfer_handle);
173:
174: Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
175: Static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
176: Static void ehci_device_bulk_abort(usbd_xfer_handle);
177: Static void ehci_device_bulk_close(usbd_pipe_handle);
178: Static void ehci_device_bulk_done(usbd_xfer_handle);
179:
180: Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
181: Static usbd_status ehci_device_intr_start(usbd_xfer_handle);
182: Static void ehci_device_intr_abort(usbd_xfer_handle);
183: Static void ehci_device_intr_close(usbd_pipe_handle);
184: Static void ehci_device_intr_done(usbd_xfer_handle);
185:
186: Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
187: Static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
188: Static void ehci_device_isoc_abort(usbd_xfer_handle);
189: Static void ehci_device_isoc_close(usbd_pipe_handle);
190: Static void ehci_device_isoc_done(usbd_xfer_handle);
191:
192: Static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
193: Static void ehci_noop(usbd_pipe_handle pipe);
194:
1.6 augustss 195: Static void ehci_disown(ehci_softc_t *, int, int);
1.5 augustss 196:
1.9 augustss 197: Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
198: Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
199:
200: Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
201: Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
1.25 augustss 202: Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
1.15 augustss 203: ehci_softc_t *, int, int, usbd_xfer_handle,
204: ehci_soft_qtd_t **, ehci_soft_qtd_t **);
1.25 augustss 205: Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
1.18 augustss 206: ehci_soft_qtd_t *);
1.15 augustss 207:
1.139 jmcneill 208: Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc);
209: Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd);
210: Static void ehci_rem_free_itd_chain(ehci_softc_t *sc,
211: struct ehci_xfer *exfer);
212: Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer,
213: usbd_status status);
214:
1.15 augustss 215: Static usbd_status ehci_device_request(usbd_xfer_handle xfer);
1.9 augustss 216:
1.78 augustss 217: Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
218: int ival);
219:
1.190 mrg 220: Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *,
221: ehci_soft_qh_t *);
1.10 augustss 222: Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
223: ehci_soft_qh_t *);
1.23 augustss 224: Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
1.11 augustss 225: Static void ehci_sync_hc(ehci_softc_t *);
1.10 augustss 226:
227: Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
228: Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
1.9 augustss 229:
1.5 augustss 230: #ifdef EHCI_DEBUG
1.18 augustss 231: Static void ehci_dump_regs(ehci_softc_t *);
1.107 augustss 232: void ehci_dump(void);
1.6 augustss 233: Static ehci_softc_t *theehci;
1.15 augustss 234: Static void ehci_dump_link(ehci_link_t, int);
235: Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
1.9 augustss 236: Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
237: Static void ehci_dump_qtd(ehci_qtd_t *);
238: Static void ehci_dump_sqh(ehci_soft_qh_t *);
1.139 jmcneill 239: #if notyet
240: Static void ehci_dump_sitd(struct ehci_soft_itd *itd);
241: Static void ehci_dump_itd(struct ehci_soft_itd *);
242: #endif
1.38 martin 243: #ifdef DIAGNOSTIC
1.141 cegger 244: Static void ehci_dump_exfer(struct ehci_xfer *);
1.5 augustss 245: #endif
1.38 martin 246: #endif
1.5 augustss 247:
1.11 augustss 248: #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
249:
1.5 augustss 250: #define EHCI_INTR_ENDPT 1
251:
1.18 augustss 252: #define ehci_add_intr_list(sc, ex) \
1.153 jmcneill 253: TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext);
254: #define ehci_del_intr_list(sc, ex) \
1.44 augustss 255: do { \
1.153 jmcneill 256: TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \
257: (ex)->inext.tqe_prev = NULL; \
1.44 augustss 258: } while (0)
1.153 jmcneill 259: #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL)
1.18 augustss 260:
1.123 drochner 261: Static const struct usbd_bus_methods ehci_bus_methods = {
1.186 mrg 262: .open_pipe = ehci_open,
263: .soft_intr = ehci_softintr,
264: .do_poll = ehci_poll,
265: .allocm = ehci_allocm,
266: .freem = ehci_freem,
267: .allocx = ehci_allocx,
268: .freex = ehci_freex,
1.190 mrg 269: .get_lock = ehci_get_lock,
1.213 matt 270: .new_device = NULL,
1.5 augustss 271: };
272:
1.123 drochner 273: Static const struct usbd_pipe_methods ehci_root_ctrl_methods = {
1.186 mrg 274: .transfer = ehci_root_ctrl_transfer,
275: .start = ehci_root_ctrl_start,
276: .abort = ehci_root_ctrl_abort,
277: .close = ehci_root_ctrl_close,
278: .cleartoggle = ehci_noop,
279: .done = ehci_root_ctrl_done,
1.5 augustss 280: };
281:
1.123 drochner 282: Static const struct usbd_pipe_methods ehci_root_intr_methods = {
1.186 mrg 283: .transfer = ehci_root_intr_transfer,
284: .start = ehci_root_intr_start,
285: .abort = ehci_root_intr_abort,
286: .close = ehci_root_intr_close,
287: .cleartoggle = ehci_noop,
288: .done = ehci_root_intr_done,
1.5 augustss 289: };
290:
1.123 drochner 291: Static const struct usbd_pipe_methods ehci_device_ctrl_methods = {
1.186 mrg 292: .transfer = ehci_device_ctrl_transfer,
293: .start = ehci_device_ctrl_start,
294: .abort = ehci_device_ctrl_abort,
295: .close = ehci_device_ctrl_close,
296: .cleartoggle = ehci_noop,
297: .done = ehci_device_ctrl_done,
1.5 augustss 298: };
299:
1.123 drochner 300: Static const struct usbd_pipe_methods ehci_device_intr_methods = {
1.186 mrg 301: .transfer = ehci_device_intr_transfer,
302: .start = ehci_device_intr_start,
303: .abort = ehci_device_intr_abort,
304: .close = ehci_device_intr_close,
305: .cleartoggle = ehci_device_clear_toggle,
306: .done = ehci_device_intr_done,
1.5 augustss 307: };
308:
1.123 drochner 309: Static const struct usbd_pipe_methods ehci_device_bulk_methods = {
1.186 mrg 310: .transfer = ehci_device_bulk_transfer,
311: .start = ehci_device_bulk_start,
312: .abort = ehci_device_bulk_abort,
313: .close = ehci_device_bulk_close,
314: .cleartoggle = ehci_device_clear_toggle,
315: .done = ehci_device_bulk_done,
1.5 augustss 316: };
317:
1.123 drochner 318: Static const struct usbd_pipe_methods ehci_device_isoc_methods = {
1.186 mrg 319: .transfer = ehci_device_isoc_transfer,
320: .start = ehci_device_isoc_start,
321: .abort = ehci_device_isoc_abort,
322: .close = ehci_device_isoc_close,
323: .cleartoggle = ehci_noop,
324: .done = ehci_device_isoc_done,
1.5 augustss 325: };
326:
1.123 drochner 327: static const uint8_t revbits[EHCI_MAX_POLLRATE] = {
1.95 augustss 328: 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78,
329: 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c,
330: 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a,
331: 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e,
332: 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79,
333: 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d,
334: 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b,
335: 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f,
1.94 augustss 336: };
337:
1.1 augustss 338: usbd_status
339: ehci_init(ehci_softc_t *sc)
340: {
1.104 christos 341: u_int32_t vers, sparams, cparams, hcr;
1.3 augustss 342: u_int i;
343: usbd_status err;
1.11 augustss 344: ehci_soft_qh_t *sqh;
1.89 augustss 345: u_int ncomp;
1.3 augustss 346:
347: DPRINTF(("ehci_init: start\n"));
1.6 augustss 348: #ifdef EHCI_DEBUG
349: theehci = sc;
350: #endif
1.3 augustss 351:
1.190 mrg 352: mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
353: mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
354: cv_init(&sc->sc_softwake_cv, "ehciab");
355: cv_init(&sc->sc_doorbell, "ehcidi");
356:
1.204 christos 357: sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0,
358: "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL);
359:
1.190 mrg 360: sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
361: ehci_doorbell, sc);
1.211 matt 362: KASSERT(sc->sc_doorbell_si != NULL);
1.190 mrg 363: sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
364: ehci_pcd, sc);
1.211 matt 365: KASSERT(sc->sc_pcd_si != NULL);
1.190 mrg 366:
1.3 augustss 367: sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
368:
1.104 christos 369: vers = EREAD2(sc, EHCI_HCIVERSION);
1.134 drochner 370: aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev),
1.104 christos 371: vers >> 8, vers & 0xff);
1.3 augustss 372:
373: sparams = EREAD4(sc, EHCI_HCSPARAMS);
374: DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
1.6 augustss 375: sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
1.89 augustss 376: ncomp = EHCI_HCS_N_CC(sparams);
377: if (ncomp != sc->sc_ncomp) {
1.121 ad 378: aprint_verbose("%s: wrong number of companions (%d != %d)\n",
1.134 drochner 379: device_xname(sc->sc_dev), ncomp, sc->sc_ncomp);
1.47 augustss 380: #if NOHCI == 0 || NUHCI == 0
381: aprint_error("%s: ohci or uhci probably not configured\n",
1.134 drochner 382: device_xname(sc->sc_dev));
1.47 augustss 383: #endif
1.89 augustss 384: if (ncomp < sc->sc_ncomp)
385: sc->sc_ncomp = ncomp;
1.3 augustss 386: }
387: if (sc->sc_ncomp > 0) {
1.172 matt 388: KASSERT(!(sc->sc_flags & EHCIF_ETTF));
1.41 thorpej 389: aprint_normal("%s: companion controller%s, %d port%s each:",
1.134 drochner 390: device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "",
1.3 augustss 391: EHCI_HCS_N_PCC(sparams),
392: EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
393: for (i = 0; i < sc->sc_ncomp; i++)
1.134 drochner 394: aprint_normal(" %s", device_xname(sc->sc_comps[i]));
1.41 thorpej 395: aprint_normal("\n");
1.3 augustss 396: }
1.5 augustss 397: sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
1.3 augustss 398: cparams = EREAD4(sc, EHCI_HCCPARAMS);
399: DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
1.106 augustss 400: sc->sc_hasppc = EHCI_HCS_PPC(sparams);
1.36 augustss 401:
402: if (EHCI_HCC_64BIT(cparams)) {
403: /* MUST clear segment register if 64 bit capable. */
404: EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
405: }
1.33 augustss 406:
1.3 augustss 407: sc->sc_bus.usbrev = USBREV_2_0;
408:
1.136 drochner 409: usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag,
1.90 fvdl 410: USB_MEM_RESERVE);
411:
1.3 augustss 412: /* Reset the controller */
1.134 drochner 413: DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev)));
1.3 augustss 414: EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
415: usb_delay_ms(&sc->sc_bus, 1);
416: EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
417: for (i = 0; i < 100; i++) {
1.34 augustss 418: usb_delay_ms(&sc->sc_bus, 1);
1.3 augustss 419: hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
420: if (!hcr)
421: break;
422: }
423: if (hcr) {
1.134 drochner 424: aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev));
1.3 augustss 425: return (USBD_IOERROR);
426: }
1.170 kiyohara 427: if (sc->sc_vendor_init)
428: sc->sc_vendor_init(sc);
1.3 augustss 429:
1.172 matt 430: /*
431: * If we are doing embedded transaction translation function, force
432: * the controller to host mode.
433: */
434: if (sc->sc_flags & EHCIF_ETTF) {
435: uint32_t usbmode = EREAD4(sc, EHCI_USBMODE);
436: usbmode &= ~EHCI_USBMODE_CM;
437: usbmode |= EHCI_USBMODE_CM_HOST;
438: EWRITE4(sc, EHCI_USBMODE, usbmode);
439: }
440:
1.78 augustss 441: /* XXX need proper intr scheduling */
442: sc->sc_rand = 96;
443:
1.3 augustss 444: /* frame list size at default, read back what we got and use that */
445: switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
1.78 augustss 446: case 0: sc->sc_flsize = 1024; break;
447: case 1: sc->sc_flsize = 512; break;
448: case 2: sc->sc_flsize = 256; break;
1.3 augustss 449: case 3: return (USBD_IOERROR);
450: }
1.78 augustss 451: err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
452: EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
1.3 augustss 453: if (err)
454: return (err);
1.134 drochner 455: DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize));
1.78 augustss 456: sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
1.139 jmcneill 457:
458: for (i = 0; i < sc->sc_flsize; i++) {
459: sc->sc_flist[i] = EHCI_NULL;
460: }
461:
1.78 augustss 462: EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1.3 augustss 463:
1.190 mrg 464: sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *),
465: KM_SLEEP);
1.139 jmcneill 466: if (sc->sc_softitds == NULL)
467: return ENOMEM;
468: LIST_INIT(&sc->sc_freeitds);
1.153 jmcneill 469: TAILQ_INIT(&sc->sc_intrhead);
1.139 jmcneill 470:
1.5 augustss 471: /* Set up the bus struct. */
472: sc->sc_bus.methods = &ehci_bus_methods;
473: sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
474:
1.6 augustss 475: sc->sc_eintrs = EHCI_NORMAL_INTRS;
476:
1.78 augustss 477: /*
478: * Allocate the interrupt dummy QHs. These are arranged to give poll
479: * intervals that are powers of 2 times 1ms.
480: */
481: for (i = 0; i < EHCI_INTRQHS; i++) {
482: sqh = ehci_alloc_sqh(sc);
483: if (sqh == NULL) {
484: err = USBD_NOMEM;
485: goto bad1;
486: }
487: sc->sc_islots[i].sqh = sqh;
488: }
489: for (i = 0; i < EHCI_INTRQHS; i++) {
490: sqh = sc->sc_islots[i].sqh;
491: if (i == 0) {
492: /* The last (1ms) QH terminates. */
493: sqh->qh.qh_link = EHCI_NULL;
494: sqh->next = NULL;
495: } else {
496: /* Otherwise the next QH has half the poll interval */
497: sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh;
498: sqh->qh.qh_link = htole32(sqh->next->physaddr |
499: EHCI_LINK_QH);
500: }
501: sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
502: sqh->qh.qh_curqtd = EHCI_NULL;
503: sqh->next = NULL;
504: sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
505: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
506: sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
507: sqh->sqtd = NULL;
1.138 bouyer 508: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
509: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.78 augustss 510: }
511: /* Point the frame list at the last level (128ms). */
512: for (i = 0; i < sc->sc_flsize; i++) {
1.94 augustss 513: int j;
514:
515: j = (i & ~(EHCI_MAX_POLLRATE-1)) |
516: revbits[i & (EHCI_MAX_POLLRATE-1)];
517: sc->sc_flist[j] = htole32(EHCI_LINK_QH |
1.78 augustss 518: sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
519: i)].sqh->physaddr);
520: }
1.138 bouyer 521: usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t),
522: BUS_DMASYNC_PREWRITE);
1.78 augustss 523:
1.11 augustss 524: /* Allocate dummy QH that starts the async list. */
525: sqh = ehci_alloc_sqh(sc);
526: if (sqh == NULL) {
1.9 augustss 527: err = USBD_NOMEM;
528: goto bad1;
529: }
1.11 augustss 530: /* Fill the QH */
531: sqh->qh.qh_endp =
532: htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
533: sqh->qh.qh_link =
534: htole32(sqh->physaddr | EHCI_LINK_QH);
535: sqh->qh.qh_curqtd = EHCI_NULL;
536: sqh->next = NULL;
537: /* Fill the overlay qTD */
538: sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
539: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1.26 augustss 540: sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
1.11 augustss 541: sqh->sqtd = NULL;
1.138 bouyer 542: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
543: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.9 augustss 544: #ifdef EHCI_DEBUG
545: if (ehcidebug) {
1.27 enami 546: ehci_dump_sqh(sqh);
1.9 augustss 547: }
548: #endif
549:
550: /* Point to async list */
1.11 augustss 551: sc->sc_async_head = sqh;
552: EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
1.9 augustss 553:
1.190 mrg 554: callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE);
1.10 augustss 555:
1.6 augustss 556: /* Turn on controller */
557: EOWRITE4(sc, EHCI_USBCMD,
1.88 augustss 558: EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
1.6 augustss 559: (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
1.10 augustss 560: EHCI_CMD_ASE |
1.78 augustss 561: EHCI_CMD_PSE |
1.6 augustss 562: EHCI_CMD_RS);
563:
564: /* Take over port ownership */
565: EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
566:
1.8 augustss 567: for (i = 0; i < 100; i++) {
1.34 augustss 568: usb_delay_ms(&sc->sc_bus, 1);
1.8 augustss 569: hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
570: if (!hcr)
571: break;
572: }
573: if (hcr) {
1.134 drochner 574: aprint_error("%s: run timeout\n", device_xname(sc->sc_dev));
1.8 augustss 575: return (USBD_IOERROR);
576: }
577:
1.105 augustss 578: /* Enable interrupts */
579: DPRINTFN(1,("ehci_init: enabling\n"));
580: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
581:
1.5 augustss 582: return (USBD_NORMAL_COMPLETION);
1.9 augustss 583:
584: #if 0
1.11 augustss 585: bad2:
1.15 augustss 586: ehci_free_sqh(sc, sc->sc_async_head);
1.9 augustss 587: #endif
588: bad1:
589: usb_freemem(&sc->sc_bus, &sc->sc_fldma);
590: return (err);
1.1 augustss 591: }
592:
593: int
594: ehci_intr(void *v)
595: {
1.6 augustss 596: ehci_softc_t *sc = v;
1.190 mrg 597: int ret = 0;
1.6 augustss 598:
1.190 mrg 599: if (sc == NULL)
600: return 0;
601:
602: mutex_spin_enter(&sc->sc_intr_lock);
603:
604: if (sc->sc_dying || !device_has_power(sc->sc_dev))
605: goto done;
1.15 augustss 606:
1.6 augustss 607: /* If we get an interrupt while polling, then just ignore it. */
608: if (sc->sc_bus.use_polling) {
1.78 augustss 609: u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
610:
611: if (intrs)
612: EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
1.6 augustss 613: #ifdef DIAGNOSTIC
1.65 mycroft 614: DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n"));
1.6 augustss 615: #endif
1.190 mrg 616: goto done;
1.6 augustss 617: }
618:
1.190 mrg 619: ret = ehci_intr1(sc);
620:
621: done:
622: mutex_spin_exit(&sc->sc_intr_lock);
623: return ret;
1.6 augustss 624: }
625:
626: Static int
627: ehci_intr1(ehci_softc_t *sc)
628: {
629: u_int32_t intrs, eintrs;
630:
631: DPRINTFN(20,("ehci_intr1: enter\n"));
632:
633: /* In case the interrupt occurs before initialization has completed. */
634: if (sc == NULL) {
635: #ifdef DIAGNOSTIC
1.72 augustss 636: printf("ehci_intr1: sc == NULL\n");
1.6 augustss 637: #endif
638: return (0);
639: }
640:
1.190 mrg 641: KASSERT(mutex_owned(&sc->sc_intr_lock));
642:
1.6 augustss 643: intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
644: if (!intrs)
645: return (0);
646:
647: eintrs = intrs & sc->sc_eintrs;
1.72 augustss 648: DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
1.6 augustss 649: sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
650: (u_int)eintrs));
651: if (!eintrs)
652: return (0);
653:
1.68 mycroft 654: EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
1.6 augustss 655: sc->sc_bus.no_intrs++;
1.10 augustss 656: if (eintrs & EHCI_STS_IAA) {
657: DPRINTF(("ehci_intr1: door bell\n"));
1.190 mrg 658: kpreempt_disable();
1.211 matt 659: KASSERT(sc->sc_doorbell_si != NULL);
1.190 mrg 660: softint_schedule(sc->sc_doorbell_si);
661: kpreempt_enable();
1.20 augustss 662: eintrs &= ~EHCI_STS_IAA;
1.10 augustss 663: }
1.18 augustss 664: if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
1.46 augustss 665: DPRINTFN(5,("ehci_intr1: %s %s\n",
666: eintrs & EHCI_STS_INT ? "INT" : "",
667: eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
1.18 augustss 668: usb_schedsoftintr(&sc->sc_bus);
1.21 augustss 669: eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
1.6 augustss 670: }
671: if (eintrs & EHCI_STS_HSE) {
672: printf("%s: unrecoverable error, controller halted\n",
1.134 drochner 673: device_xname(sc->sc_dev));
1.6 augustss 674: /* XXX what else */
675: }
676: if (eintrs & EHCI_STS_PCD) {
1.190 mrg 677: kpreempt_disable();
1.211 matt 678: KASSERT(sc->sc_pcd_si != NULL);
1.190 mrg 679: softint_schedule(sc->sc_pcd_si);
680: kpreempt_enable();
1.6 augustss 681: eintrs &= ~EHCI_STS_PCD;
682: }
683:
684: if (eintrs != 0) {
685: /* Block unprocessed interrupts. */
686: sc->sc_eintrs &= ~eintrs;
687: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
688: printf("%s: blocking intrs 0x%x\n",
1.134 drochner 689: device_xname(sc->sc_dev), eintrs);
1.6 augustss 690: }
691:
692: return (1);
693: }
694:
1.190 mrg 695: Static void
696: ehci_doorbell(void *addr)
697: {
698: ehci_softc_t *sc = addr;
699:
700: mutex_enter(&sc->sc_lock);
701: cv_broadcast(&sc->sc_doorbell);
702: mutex_exit(&sc->sc_lock);
703: }
1.6 augustss 704:
1.164 uebayasi 705: Static void
1.190 mrg 706: ehci_pcd(void *addr)
1.6 augustss 707: {
1.190 mrg 708: ehci_softc_t *sc = addr;
709: usbd_xfer_handle xfer;
1.6 augustss 710: u_char *p;
711: int i, m;
712:
1.190 mrg 713: mutex_enter(&sc->sc_lock);
714: xfer = sc->sc_intrxfer;
715:
1.6 augustss 716: if (xfer == NULL) {
717: /* Just ignore the change. */
1.190 mrg 718: goto done;
1.6 augustss 719: }
720:
1.30 augustss 721: p = KERNADDR(&xfer->dmabuf, 0);
1.6 augustss 722: m = min(sc->sc_noport, xfer->length * 8 - 1);
723: memset(p, 0, xfer->length);
724: for (i = 1; i <= m; i++) {
725: /* Pick out CHANGE bits from the status reg. */
726: if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
727: p[i/8] |= 1 << (i%8);
728: }
729: DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
730: xfer->actlen = xfer->length;
731: xfer->status = USBD_NORMAL_COMPLETION;
732:
733: usb_transfer_complete(xfer);
1.190 mrg 734:
735: done:
736: mutex_exit(&sc->sc_lock);
1.1 augustss 737: }
738:
1.164 uebayasi 739: Static void
1.5 augustss 740: ehci_softintr(void *v)
741: {
1.134 drochner 742: struct usbd_bus *bus = v;
743: ehci_softc_t *sc = bus->hci_private;
1.53 chs 744: struct ehci_xfer *ex, *nextex;
1.18 augustss 745:
1.190 mrg 746: KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
747:
1.187 mrg 748: DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev)));
1.18 augustss 749:
750: /*
751: * The only explanation I can think of for why EHCI is as brain dead
752: * as UHCI interrupt-wise is that Intel was involved in both.
753: * An interrupt just tells us that something is done, we have no
754: * clue what, so we need to scan through all active transfers. :-(
755: */
1.153 jmcneill 756: for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
757: nextex = TAILQ_NEXT(ex, inext);
1.18 augustss 758: ehci_check_intr(sc, ex);
1.53 chs 759: }
1.18 augustss 760:
1.108 xtraeme 761: /* Schedule a callout to catch any dropped transactions. */
762: if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
1.153 jmcneill 763: !TAILQ_EMPTY(&sc->sc_intrhead))
1.190 mrg 764: callout_reset(&sc->sc_tmo_intrlist,
765: hz, ehci_intrlist_timeout, sc);
1.108 xtraeme 766:
1.29 augustss 767: if (sc->sc_softwake) {
768: sc->sc_softwake = 0;
1.190 mrg 769: cv_broadcast(&sc->sc_softwake_cv);
1.29 augustss 770: }
1.18 augustss 771: }
772:
773: /* Check for an interrupt. */
1.164 uebayasi 774: Static void
1.115 christos 775: ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
1.18 augustss 776: {
1.139 jmcneill 777: int attr;
1.18 augustss 778:
1.22 augustss 779: DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
1.18 augustss 780:
1.206 skrll 781: KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1.190 mrg 782:
1.139 jmcneill 783: attr = ex->xfer.pipe->endpoint->edesc->bmAttributes;
784: if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS)
785: ehci_check_itd_intr(sc, ex);
786: else
787: ehci_check_qh_intr(sc, ex);
788:
789: return;
790: }
791:
1.164 uebayasi 792: Static void
1.139 jmcneill 793: ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
794: {
795: ehci_soft_qtd_t *sqtd, *lsqtd;
796: __uint32_t status;
797:
1.206 skrll 798: KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1.190 mrg 799:
1.18 augustss 800: if (ex->sqtdstart == NULL) {
1.139 jmcneill 801: printf("ehci_check_qh_intr: not valid sqtd\n");
1.18 augustss 802: return;
803: }
1.139 jmcneill 804:
1.18 augustss 805: lsqtd = ex->sqtdend;
806: #ifdef DIAGNOSTIC
807: if (lsqtd == NULL) {
1.139 jmcneill 808: printf("ehci_check_qh_intr: lsqtd==0\n");
1.18 augustss 809: return;
810: }
811: #endif
1.33 augustss 812: /*
1.18 augustss 813: * If the last TD is still active we need to check whether there
1.210 skrll 814: * is an error somewhere in the middle, or whether there was a
1.18 augustss 815: * short packet (SPD and not ACTIVE).
816: */
1.138 bouyer 817: usb_syncmem(&lsqtd->dma,
818: lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
819: sizeof(lsqtd->qtd.qtd_status),
820: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.205 tsutsui 821: status = le32toh(lsqtd->qtd.qtd_status);
822: usb_syncmem(&lsqtd->dma,
823: lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
824: sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
825: if (status & EHCI_QTD_ACTIVE) {
1.18 augustss 826: DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
827: for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
1.138 bouyer 828: usb_syncmem(&sqtd->dma,
829: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
830: sizeof(sqtd->qtd.qtd_status),
831: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.18 augustss 832: status = le32toh(sqtd->qtd.qtd_status);
1.138 bouyer 833: usb_syncmem(&sqtd->dma,
834: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
835: sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
1.18 augustss 836: /* If there's an active QTD the xfer isn't done. */
837: if (status & EHCI_QTD_ACTIVE)
838: break;
839: /* Any kind of error makes the xfer done. */
840: if (status & EHCI_QTD_HALTED)
841: goto done;
1.221 skrll 842: /* Handle short packets */
843: if (EHCI_QTD_GET_BYTES(status) != 0) {
844: usbd_pipe_handle pipe = ex->xfer.pipe;
845: usb_endpoint_descriptor_t *ed =
846: pipe->endpoint->edesc;
847: uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes);
848:
849: /*
850: * If we get here for a control transfer then
851: * we need to let the hardware complete the
852: * status phase. That is, we're not done
853: * quite yet.
854: *
855: * Otherwise, we're done.
856: */
857: if (xt == UE_CONTROL) {
858: break;
859: }
1.18 augustss 860: goto done;
1.221 skrll 861: }
1.18 augustss 862: }
863: DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
864: ex, ex->sqtdstart));
865: return;
866: }
867: done:
868: DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
1.171 dyoung 869: callout_stop(&ex->xfer.timeout_handle);
1.18 augustss 870: ehci_idone(ex);
871: }
872:
1.164 uebayasi 873: Static void
1.190 mrg 874: ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
875: {
1.139 jmcneill 876: ehci_soft_itd_t *itd;
877: int i;
878:
1.190 mrg 879: KASSERT(mutex_owned(&sc->sc_lock));
880:
1.153 jmcneill 881: if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue))
882: return;
883:
1.139 jmcneill 884: if (ex->itdstart == NULL) {
885: printf("ehci_check_itd_intr: not valid itd\n");
886: return;
887: }
888:
889: itd = ex->itdend;
890: #ifdef DIAGNOSTIC
891: if (itd == NULL) {
892: printf("ehci_check_itd_intr: itdend == 0\n");
893: return;
894: }
895: #endif
896:
897: /*
1.153 jmcneill 898: * check no active transfers in last itd, meaning we're finished
1.139 jmcneill 899: */
900:
901: usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
902: sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE |
903: BUS_DMASYNC_POSTREAD);
904:
1.168 jakllsch 905: for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1.139 jmcneill 906: if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE)
1.152 jmcneill 907: break;
1.139 jmcneill 908: }
909:
1.168 jakllsch 910: if (i == EHCI_ITD_NUFRAMES) {
1.139 jmcneill 911: goto done; /* All 8 descriptors inactive, it's done */
912: }
913:
914: DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex,
915: ex->itdstart));
916: return;
917: done:
918: DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex));
1.171 dyoung 919: callout_stop(&ex->xfer.timeout_handle);
1.139 jmcneill 920: ehci_idone(ex);
921: }
922:
1.164 uebayasi 923: Static void
1.18 augustss 924: ehci_idone(struct ehci_xfer *ex)
925: {
926: usbd_xfer_handle xfer = &ex->xfer;
927: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
1.190 mrg 928: struct ehci_softc *sc = xfer->pipe->device->bus->hci_private;
1.82 augustss 929: ehci_soft_qtd_t *sqtd, *lsqtd;
930: u_int32_t status = 0, nstatus = 0;
1.18 augustss 931: int actlen;
932:
1.206 skrll 933: KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1.190 mrg 934:
1.22 augustss 935: DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
1.190 mrg 936:
1.18 augustss 937: #ifdef DIAGNOSTIC
1.216 skrll 938: if (ex->isdone) {
1.217 skrll 939: printf("ehci_idone: ex=%p is done!\n", ex);
1.18 augustss 940: #ifdef EHCI_DEBUG
1.216 skrll 941: ehci_dump_exfer(ex);
1.18 augustss 942: #endif
1.216 skrll 943: return;
1.18 augustss 944: }
1.216 skrll 945: ex->isdone = 1;
1.18 augustss 946: #endif
1.217 skrll 947:
1.18 augustss 948: if (xfer->status == USBD_CANCELLED ||
949: xfer->status == USBD_TIMEOUT) {
950: DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
951: return;
952: }
953:
954: #ifdef EHCI_DEBUG
1.23 augustss 955: DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
1.18 augustss 956: if (ehcidebug > 10)
957: ehci_dump_sqtds(ex->sqtdstart);
958: #endif
959:
960: /* The transfer is done, compute actual length and status. */
1.139 jmcneill 961:
962: if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)
963: == UE_ISOCHRONOUS) {
964: /* Isoc transfer */
965: struct ehci_soft_itd *itd;
966: int i, nframes, len, uframes;
967:
968: nframes = 0;
969: actlen = 0;
970:
1.168 jakllsch 971: i = xfer->pipe->endpoint->edesc->bInterval;
972: uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME);
1.139 jmcneill 973:
974: for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) {
975: usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl),
976: sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE |
977: BUS_DMASYNC_POSTREAD);
978:
1.168 jakllsch 979: for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) {
1.139 jmcneill 980: /* XXX - driver didn't fill in the frame full
981: * of uframes. This leads to scheduling
982: * inefficiencies, but working around
983: * this doubles complexity of tracking
984: * an xfer.
985: */
986: if (nframes >= xfer->nframes)
987: break;
988:
989: status = le32toh(itd->itd.itd_ctl[i]);
990: len = EHCI_ITD_GET_LEN(status);
1.155 jmorse 991: if (EHCI_ITD_GET_STATUS(status) != 0)
992: len = 0; /*No valid data on error*/
993:
1.139 jmcneill 994: xfer->frlengths[nframes++] = len;
995: actlen += len;
996: }
997:
998: if (nframes >= xfer->nframes)
999: break;
1.183 jakllsch 1000: }
1.139 jmcneill 1001:
1002: xfer->actlen = actlen;
1003: xfer->status = USBD_NORMAL_COMPLETION;
1004: goto end;
1005: }
1006:
1007: /* Continue processing xfers using queue heads */
1008:
1.82 augustss 1009: lsqtd = ex->sqtdend;
1.18 augustss 1010: actlen = 0;
1.139 jmcneill 1011: for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) {
1.138 bouyer 1012: usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
1013: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.18 augustss 1014: nstatus = le32toh(sqtd->qtd.qtd_status);
1015: if (nstatus & EHCI_QTD_ACTIVE)
1016: break;
1017:
1018: status = nstatus;
1.139 jmcneill 1019: if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
1.18 augustss 1020: actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
1021: }
1.22 augustss 1022:
1.139 jmcneill 1023:
1.91 perry 1024: /*
1.86 augustss 1025: * If there are left over TDs we need to update the toggle.
1026: * The default pipe doesn't need it since control transfers
1027: * start the toggle at 0 every time.
1.117 drochner 1028: * For a short transfer we need to update the toggle for the missing
1029: * packets within the qTD.
1.86 augustss 1030: */
1.117 drochner 1031: if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) &&
1.82 augustss 1032: xfer->pipe->device->default_pipe != xfer->pipe) {
1.117 drochner 1033: DPRINTFN(2, ("ehci_idone: need toggle update "
1034: "status=%08x nstatus=%08x\n", status, nstatus));
1.58 mycroft 1035: #if 0
1036: ehci_dump_sqh(epipe->sqh);
1037: ehci_dump_sqtds(ex->sqtdstart);
1038: #endif
1039: epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus);
1.22 augustss 1040: }
1.18 augustss 1041:
1.23 augustss 1042: DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n",
1.22 augustss 1043: xfer->length, actlen, status));
1.18 augustss 1044: xfer->actlen = actlen;
1.98 augustss 1045: if (status & EHCI_QTD_HALTED) {
1.18 augustss 1046: #ifdef EHCI_DEBUG
1047: char sbuf[128];
1048:
1.156 christos 1049: snprintb(sbuf, sizeof(sbuf),
1.218 skrll 1050: "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE"
1051: "\4XACTERR\3MISSED\2SPLIT\1PING",
1.156 christos 1052: (u_int32_t)status);
1.18 augustss 1053:
1.218 skrll 1054: DPRINTFN(2, ("%s: error, addr=%d, endpt=0x%02x, "
1055: "cerr=%d pid=%d stat=%s\n", __func__,
1056: xfer->pipe->device->address,
1057: xfer->pipe->endpoint->edesc->bEndpointAddress,
1058: EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), sbuf));
1059:
1.23 augustss 1060: if (ehcidebug > 2) {
1061: ehci_dump_sqh(epipe->sqh);
1062: ehci_dump_sqtds(ex->sqtdstart);
1063: }
1.18 augustss 1064: #endif
1.98 augustss 1065: /* low&full speed has an extra error flag */
1066: if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) !=
1067: EHCI_QH_SPEED_HIGH)
1068: status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE;
1069: else
1070: status &= EHCI_QTD_STATERRS;
1.139 jmcneill 1071: if (status == 0) /* no other errors means a stall */ {
1.18 augustss 1072: xfer->status = USBD_STALLED;
1.139 jmcneill 1073: } else {
1.18 augustss 1074: xfer->status = USBD_IOERROR; /* more info XXX */
1.139 jmcneill 1075: }
1.98 augustss 1076: /* XXX need to reset TT on missed microframe */
1077: if (status & EHCI_QTD_MISSEDMICRO) {
1078: printf("%s: missed microframe, TT reset not "
1079: "implemented, hub might be inoperational\n",
1.134 drochner 1080: device_xname(sc->sc_dev));
1.98 augustss 1081: }
1.18 augustss 1082: } else {
1083: xfer->status = USBD_NORMAL_COMPLETION;
1084: }
1085:
1.139 jmcneill 1086: end:
1087: /* XXX transfer_complete memcpys out transfer data (for in endpoints)
1088: * during this call, before methods->done is called: dma sync required
1089: * beforehand? */
1.18 augustss 1090: usb_transfer_complete(xfer);
1.22 augustss 1091: DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
1.5 augustss 1092: }
1093:
1.15 augustss 1094: /*
1095: * Wait here until controller claims to have an interrupt.
1.18 augustss 1096: * Then call ehci_intr and return. Use timeout to avoid waiting
1.15 augustss 1097: * too long.
1098: */
1.164 uebayasi 1099: Static void
1.15 augustss 1100: ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
1101: {
1.97 augustss 1102: int timo;
1.15 augustss 1103: u_int32_t intrs;
1104:
1105: xfer->status = USBD_IN_PROGRESS;
1.97 augustss 1106: for (timo = xfer->timeout; timo >= 0; timo--) {
1.15 augustss 1107: usb_delay_ms(&sc->sc_bus, 1);
1.17 augustss 1108: if (sc->sc_dying)
1109: break;
1.15 augustss 1110: intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
1111: sc->sc_eintrs;
1112: DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
1.70 yamt 1113: #ifdef EHCI_DEBUG
1.15 augustss 1114: if (ehcidebug > 15)
1.18 augustss 1115: ehci_dump_regs(sc);
1.15 augustss 1116: #endif
1117: if (intrs) {
1.190 mrg 1118: mutex_spin_enter(&sc->sc_intr_lock);
1.15 augustss 1119: ehci_intr1(sc);
1.190 mrg 1120: mutex_spin_exit(&sc->sc_intr_lock);
1.15 augustss 1121: if (xfer->status != USBD_IN_PROGRESS)
1122: return;
1123: }
1124: }
1125:
1126: /* Timeout */
1127: DPRINTF(("ehci_waitintr: timeout\n"));
1128: xfer->status = USBD_TIMEOUT;
1.190 mrg 1129: mutex_enter(&sc->sc_lock);
1.15 augustss 1130: usb_transfer_complete(xfer);
1.190 mrg 1131: mutex_exit(&sc->sc_lock);
1.15 augustss 1132: /* XXX should free TD */
1133: }
1134:
1.164 uebayasi 1135: Static void
1.5 augustss 1136: ehci_poll(struct usbd_bus *bus)
1137: {
1.134 drochner 1138: ehci_softc_t *sc = bus->hci_private;
1.5 augustss 1139: #ifdef EHCI_DEBUG
1140: static int last;
1141: int new;
1.6 augustss 1142: new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1.5 augustss 1143: if (new != last) {
1144: DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
1145: last = new;
1146: }
1147: #endif
1148:
1.190 mrg 1149: if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) {
1150: mutex_spin_enter(&sc->sc_intr_lock);
1.5 augustss 1151: ehci_intr1(sc);
1.190 mrg 1152: mutex_spin_exit(&sc->sc_intr_lock);
1153: }
1.5 augustss 1154: }
1155:
1.132 dyoung 1156: void
1157: ehci_childdet(device_t self, device_t child)
1158: {
1159: struct ehci_softc *sc = device_private(self);
1160:
1161: KASSERT(sc->sc_child == child);
1162: sc->sc_child = NULL;
1163: }
1164:
1.1 augustss 1165: int
1166: ehci_detach(struct ehci_softc *sc, int flags)
1167: {
1168: int rv = 0;
1169:
1170: if (sc->sc_child != NULL)
1171: rv = config_detach(sc->sc_child, flags);
1.33 augustss 1172:
1.1 augustss 1173: if (rv != 0)
1174: return (rv);
1175:
1.190 mrg 1176: callout_halt(&sc->sc_tmo_intrlist, NULL);
1177: callout_destroy(&sc->sc_tmo_intrlist);
1178:
1179: /* XXX free other data structures XXX */
1180: if (sc->sc_softitds)
1181: kmem_free(sc->sc_softitds,
1182: sc->sc_flsize * sizeof(ehci_soft_itd_t *));
1183: cv_destroy(&sc->sc_doorbell);
1184: cv_destroy(&sc->sc_softwake_cv);
1185:
1186: #if 0
1187: /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */
1.6 augustss 1188:
1.190 mrg 1189: softint_disestablish(sc->sc_doorbell_si);
1190: softint_disestablish(sc->sc_pcd_si);
1.15 augustss 1191:
1.190 mrg 1192: mutex_destroy(&sc->sc_lock);
1193: mutex_destroy(&sc->sc_intr_lock);
1194: #endif
1195:
1.204 christos 1196: pool_cache_destroy(sc->sc_xferpool);
1.1 augustss 1197:
1.128 jmcneill 1198: EOWRITE4(sc, EHCI_CONFIGFLAG, 0);
1199:
1.1 augustss 1200: return (rv);
1201: }
1202:
1203:
1204: int
1.132 dyoung 1205: ehci_activate(device_t self, enum devact act)
1.1 augustss 1206: {
1.132 dyoung 1207: struct ehci_softc *sc = device_private(self);
1.1 augustss 1208:
1209: switch (act) {
1210: case DVACT_DEACTIVATE:
1.124 kiyohara 1211: sc->sc_dying = 1;
1.163 dyoung 1212: return 0;
1213: default:
1214: return EOPNOTSUPP;
1.1 augustss 1215: }
1216: }
1217:
1.5 augustss 1218: /*
1219: * Handle suspend/resume.
1220: *
1221: * We need to switch to polling mode here, because this routine is
1.73 augustss 1222: * called from an interrupt context. This is all right since we
1.5 augustss 1223: * are almost suspended anyway.
1.127 jmcneill 1224: *
1225: * Note that this power handler isn't to be registered directly; the
1226: * bus glue needs to call out to it.
1.5 augustss 1227: */
1.127 jmcneill 1228: bool
1.166 dyoung 1229: ehci_suspend(device_t dv, const pmf_qual_t *qual)
1.5 augustss 1230: {
1.132 dyoung 1231: ehci_softc_t *sc = device_private(dv);
1.190 mrg 1232: int i;
1.127 jmcneill 1233: uint32_t cmd, hcr;
1234:
1.190 mrg 1235: mutex_spin_enter(&sc->sc_intr_lock);
1.127 jmcneill 1236: sc->sc_bus.use_polling++;
1.190 mrg 1237: mutex_spin_exit(&sc->sc_intr_lock);
1.127 jmcneill 1238:
1239: for (i = 1; i <= sc->sc_noport; i++) {
1.129 jmcneill 1240: cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1.127 jmcneill 1241: if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE)
1242: EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP);
1243: }
1244:
1245: sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
1246:
1247: cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
1248: EOWRITE4(sc, EHCI_USBCMD, cmd);
1249:
1250: for (i = 0; i < 100; i++) {
1251: hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS);
1252: if (hcr == 0)
1253: break;
1.5 augustss 1254:
1.127 jmcneill 1255: usb_delay_ms(&sc->sc_bus, 1);
1256: }
1257: if (hcr != 0)
1.134 drochner 1258: printf("%s: reset timeout\n", device_xname(dv));
1.5 augustss 1259:
1.127 jmcneill 1260: cmd &= ~EHCI_CMD_RS;
1261: EOWRITE4(sc, EHCI_USBCMD, cmd);
1.74 augustss 1262:
1.127 jmcneill 1263: for (i = 0; i < 100; i++) {
1264: hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1265: if (hcr == EHCI_STS_HCH)
1266: break;
1.74 augustss 1267:
1.127 jmcneill 1268: usb_delay_ms(&sc->sc_bus, 1);
1269: }
1270: if (hcr != EHCI_STS_HCH)
1.134 drochner 1271: printf("%s: config timeout\n", device_xname(dv));
1.74 augustss 1272:
1.190 mrg 1273: mutex_spin_enter(&sc->sc_intr_lock);
1.127 jmcneill 1274: sc->sc_bus.use_polling--;
1.190 mrg 1275: mutex_spin_exit(&sc->sc_intr_lock);
1.74 augustss 1276:
1.127 jmcneill 1277: return true;
1278: }
1.74 augustss 1279:
1.127 jmcneill 1280: bool
1.166 dyoung 1281: ehci_resume(device_t dv, const pmf_qual_t *qual)
1.127 jmcneill 1282: {
1.132 dyoung 1283: ehci_softc_t *sc = device_private(dv);
1284: int i;
1.127 jmcneill 1285: uint32_t cmd, hcr;
1.74 augustss 1286:
1.127 jmcneill 1287: /* restore things in case the bios sucks */
1288: EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
1289: EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1290: EOWRITE4(sc, EHCI_ASYNCLISTADDR,
1291: sc->sc_async_head->physaddr | EHCI_LINK_QH);
1.130 jmcneill 1292:
1293: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE);
1.74 augustss 1294:
1.127 jmcneill 1295: EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1.74 augustss 1296:
1.127 jmcneill 1297: hcr = 0;
1298: for (i = 1; i <= sc->sc_noport; i++) {
1.129 jmcneill 1299: cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1.127 jmcneill 1300: if ((cmd & EHCI_PS_PO) == 0 &&
1301: (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
1302: EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR);
1303: hcr = 1;
1.74 augustss 1304: }
1.127 jmcneill 1305: }
1306:
1307: if (hcr) {
1308: usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1309:
1310: for (i = 1; i <= sc->sc_noport; i++) {
1.129 jmcneill 1311: cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1.127 jmcneill 1312: if ((cmd & EHCI_PS_PO) == 0 &&
1313: (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
1314: EOWRITE4(sc, EHCI_PORTSC(i),
1315: cmd & ~EHCI_PS_FPR);
1.74 augustss 1316: }
1.127 jmcneill 1317: }
1318:
1319: EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1.130 jmcneill 1320: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1.74 augustss 1321:
1.127 jmcneill 1322: for (i = 0; i < 100; i++) {
1323: hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1324: if (hcr != EHCI_STS_HCH)
1325: break;
1.74 augustss 1326:
1.127 jmcneill 1327: usb_delay_ms(&sc->sc_bus, 1);
1.5 augustss 1328: }
1.127 jmcneill 1329: if (hcr == EHCI_STS_HCH)
1.134 drochner 1330: printf("%s: config timeout\n", device_xname(dv));
1.127 jmcneill 1331:
1332: return true;
1.5 augustss 1333: }
1334:
1335: /*
1336: * Shut down the controller when the system is going down.
1337: */
1.133 dyoung 1338: bool
1339: ehci_shutdown(device_t self, int flags)
1.5 augustss 1340: {
1.133 dyoung 1341: ehci_softc_t *sc = device_private(self);
1.5 augustss 1342:
1343: DPRINTF(("ehci_shutdown: stopping the HC\n"));
1.8 augustss 1344: EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1345: EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1.133 dyoung 1346: return true;
1.5 augustss 1347: }
1348:
1.164 uebayasi 1349: Static usbd_status
1.5 augustss 1350: ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
1351: {
1.134 drochner 1352: struct ehci_softc *sc = bus->hci_private;
1.25 augustss 1353: usbd_status err;
1.5 augustss 1354:
1.197 prlw1 1355: err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG);
1356: #ifdef EHCI_DEBUG
1357: if (err)
1358: printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n",
1359: usbd_errstr(err), err);
1360: #endif
1.90 fvdl 1361: if (err == USBD_NOMEM)
1362: err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size);
1.25 augustss 1363: #ifdef EHCI_DEBUG
1364: if (err)
1.197 prlw1 1365: printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n",
1366: usbd_errstr(err), err);
1.25 augustss 1367: #endif
1368: return (err);
1.5 augustss 1369: }
1370:
1.164 uebayasi 1371: Static void
1.5 augustss 1372: ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
1373: {
1.134 drochner 1374: struct ehci_softc *sc = bus->hci_private;
1.5 augustss 1375:
1.90 fvdl 1376: if (dma->block->flags & USB_DMA_RESERVE) {
1.134 drochner 1377: usb_reserve_freem(&sc->sc_dma_reserve,
1.90 fvdl 1378: dma);
1379: return;
1380: }
1.5 augustss 1381: usb_freemem(&sc->sc_bus, dma);
1382: }
1383:
1.164 uebayasi 1384: Static usbd_xfer_handle
1.5 augustss 1385: ehci_allocx(struct usbd_bus *bus)
1386: {
1.134 drochner 1387: struct ehci_softc *sc = bus->hci_private;
1.5 augustss 1388: usbd_xfer_handle xfer;
1389:
1.204 christos 1390: xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
1.18 augustss 1391: if (xfer != NULL) {
1.177 tsutsui 1392: memset(xfer, 0, sizeof(struct ehci_xfer));
1.18 augustss 1393: #ifdef DIAGNOSTIC
1.177 tsutsui 1394: EXFER(xfer)->isdone = 1;
1.18 augustss 1395: xfer->busy_free = XFER_BUSY;
1396: #endif
1397: }
1.5 augustss 1398: return (xfer);
1399: }
1400:
1.164 uebayasi 1401: Static void
1.5 augustss 1402: ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1403: {
1.134 drochner 1404: struct ehci_softc *sc = bus->hci_private;
1.5 augustss 1405:
1.18 augustss 1406: #ifdef DIAGNOSTIC
1407: if (xfer->busy_free != XFER_BUSY) {
1408: printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1409: xfer->busy_free);
1410: }
1411: xfer->busy_free = XFER_FREE;
1.177 tsutsui 1412: if (!EXFER(xfer)->isdone) {
1.18 augustss 1413: printf("ehci_freex: !isdone\n");
1414: }
1415: #endif
1.204 christos 1416: pool_cache_put(sc->sc_xferpool, xfer);
1.5 augustss 1417: }
1418:
1419: Static void
1.190 mrg 1420: ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1421: {
1422: struct ehci_softc *sc = bus->hci_private;
1423:
1424: *lock = &sc->sc_lock;
1425: }
1426:
1427: Static void
1.5 augustss 1428: ehci_device_clear_toggle(usbd_pipe_handle pipe)
1429: {
1.15 augustss 1430: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1431:
1.23 augustss 1432: DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1433: epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1.158 sketch 1434: #ifdef EHCI_DEBUG
1.22 augustss 1435: if (ehcidebug)
1436: usbd_dump_pipe(pipe);
1.5 augustss 1437: #endif
1.55 mycroft 1438: epipe->nexttoggle = 0;
1.5 augustss 1439: }
1440:
1441: Static void
1.115 christos 1442: ehci_noop(usbd_pipe_handle pipe)
1.5 augustss 1443: {
1444: }
1445:
1446: #ifdef EHCI_DEBUG
1.164 uebayasi 1447: Static void
1.18 augustss 1448: ehci_dump_regs(ehci_softc_t *sc)
1.5 augustss 1449: {
1.6 augustss 1450: int i;
1451: printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1452: EOREAD4(sc, EHCI_USBCMD),
1453: EOREAD4(sc, EHCI_USBSTS),
1454: EOREAD4(sc, EHCI_USBINTR));
1.29 augustss 1455: printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1.15 augustss 1456: EOREAD4(sc, EHCI_FRINDEX),
1457: EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1458: EOREAD4(sc, EHCI_PERIODICLISTBASE),
1459: EOREAD4(sc, EHCI_ASYNCLISTADDR));
1.6 augustss 1460: for (i = 1; i <= sc->sc_noport; i++)
1.33 augustss 1461: printf("port %d status=0x%08x\n", i,
1.6 augustss 1462: EOREAD4(sc, EHCI_PORTSC(i)));
1.39 martin 1463: }
1464:
1.40 martin 1465: /*
1466: * Unused function - this is meant to be called from a kernel
1467: * debugger.
1468: */
1.39 martin 1469: void
1.157 cegger 1470: ehci_dump(void)
1.39 martin 1471: {
1472: ehci_dump_regs(theehci);
1.6 augustss 1473: }
1474:
1.164 uebayasi 1475: Static void
1.15 augustss 1476: ehci_dump_link(ehci_link_t link, int type)
1.9 augustss 1477: {
1.15 augustss 1478: link = le32toh(link);
1479: printf("0x%08x", link);
1.9 augustss 1480: if (link & EHCI_LINK_TERMINATE)
1.15 augustss 1481: printf("<T>");
1482: else {
1483: printf("<");
1484: if (type) {
1485: switch (EHCI_LINK_TYPE(link)) {
1486: case EHCI_LINK_ITD: printf("ITD"); break;
1487: case EHCI_LINK_QH: printf("QH"); break;
1488: case EHCI_LINK_SITD: printf("SITD"); break;
1489: case EHCI_LINK_FSTN: printf("FSTN"); break;
1.16 augustss 1490: }
1.15 augustss 1491: }
1.9 augustss 1492: printf(">");
1.15 augustss 1493: }
1494: }
1495:
1.164 uebayasi 1496: Static void
1.15 augustss 1497: ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1498: {
1.29 augustss 1499: int i;
1500: u_int32_t stop;
1501:
1502: stop = 0;
1503: for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1.15 augustss 1504: ehci_dump_sqtd(sqtd);
1.138 bouyer 1505: usb_syncmem(&sqtd->dma,
1.195 christos 1506: sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1.138 bouyer 1507: sizeof(sqtd->qtd),
1508: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.72 augustss 1509: stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1.138 bouyer 1510: usb_syncmem(&sqtd->dma,
1.195 christos 1511: sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1.138 bouyer 1512: sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1.29 augustss 1513: }
1514: if (sqtd)
1515: printf("dump aborted, too many TDs\n");
1.9 augustss 1516: }
1517:
1.164 uebayasi 1518: Static void
1.9 augustss 1519: ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1520: {
1.195 christos 1521: usb_syncmem(&sqtd->dma, sqtd->offs,
1.138 bouyer 1522: sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.9 augustss 1523: printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1524: ehci_dump_qtd(&sqtd->qtd);
1.195 christos 1525: usb_syncmem(&sqtd->dma, sqtd->offs,
1.138 bouyer 1526: sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1.9 augustss 1527: }
1528:
1.164 uebayasi 1529: Static void
1.9 augustss 1530: ehci_dump_qtd(ehci_qtd_t *qtd)
1531: {
1532: u_int32_t s;
1.15 augustss 1533: char sbuf[128];
1.9 augustss 1534:
1.15 augustss 1535: printf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1536: printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1.9 augustss 1537: printf("\n");
1.15 augustss 1538: s = le32toh(qtd->qtd_status);
1.156 christos 1539: snprintb(sbuf, sizeof(sbuf),
1540: "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1541: "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s));
1.9 augustss 1542: printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1543: s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1544: EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1.219 skrll 1545: printf(" cerr=%d pid=%d stat=%s\n", EHCI_QTD_GET_CERR(s),
1.15 augustss 1546: EHCI_QTD_GET_PID(s), sbuf);
1.9 augustss 1547: for (s = 0; s < 5; s++)
1.15 augustss 1548: printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1.9 augustss 1549: }
1550:
1.164 uebayasi 1551: Static void
1.9 augustss 1552: ehci_dump_sqh(ehci_soft_qh_t *sqh)
1553: {
1554: ehci_qh_t *qh = &sqh->qh;
1.15 augustss 1555: u_int32_t endp, endphub;
1.9 augustss 1556:
1.195 christos 1557: usb_syncmem(&sqh->dma, sqh->offs,
1.138 bouyer 1558: sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.9 augustss 1559: printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1.15 augustss 1560: printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n");
1561: endp = le32toh(qh->qh_endp);
1562: printf(" endp=0x%08x\n", endp);
1563: printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1564: EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1565: EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1566: EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1567: printf(" mpl=0x%x ctl=%d nrl=%d\n",
1568: EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1569: EHCI_QH_GET_NRL(endp));
1570: endphub = le32toh(qh->qh_endphub);
1571: printf(" endphub=0x%08x\n", endphub);
1572: printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1573: EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1574: EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1575: EHCI_QH_GET_MULT(endphub));
1576: printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n");
1.12 augustss 1577: printf("Overlay qTD:\n");
1.9 augustss 1578: ehci_dump_qtd(&qh->qh_qtd);
1.195 christos 1579: usb_syncmem(&sqh->dma, sqh->offs,
1.138 bouyer 1580: sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
1.9 augustss 1581: }
1582:
1.154 jmcneill 1583: #if notyet
1.164 uebayasi 1584: Static void
1.139 jmcneill 1585: ehci_dump_itd(struct ehci_soft_itd *itd)
1586: {
1587: ehci_isoc_trans_t t;
1588: ehci_isoc_bufr_ptr_t b, b2, b3;
1589: int i;
1590:
1591: printf("ITD: next phys=%X\n", itd->itd.itd_next);
1592:
1.168 jakllsch 1593: for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1.139 jmcneill 1594: t = le32toh(itd->itd.itd_ctl[i]);
1595: printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i,
1596: EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t),
1597: EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t),
1598: EHCI_ITD_GET_OFFS(t));
1599: }
1600: printf("ITDbufr: ");
1.168 jakllsch 1601: for (i = 0; i < EHCI_ITD_NBUFFERS; i++)
1.139 jmcneill 1602: printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])));
1603:
1604: b = le32toh(itd->itd.itd_bufr[0]);
1605: b2 = le32toh(itd->itd.itd_bufr[1]);
1606: b3 = le32toh(itd->itd.itd_bufr[2]);
1607: printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n",
1608: EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2),
1609: EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3));
1610: }
1611:
1.164 uebayasi 1612: Static void
1.139 jmcneill 1613: ehci_dump_sitd(struct ehci_soft_itd *itd)
1614: {
1615: printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n",
1616: itd, itd->u.frame_list.next, itd->u.frame_list.prev,
1617: itd->xfer_next, itd->physaddr, itd->slot);
1618: }
1.154 jmcneill 1619: #endif
1.139 jmcneill 1620:
1.38 martin 1621: #ifdef DIAGNOSTIC
1.164 uebayasi 1622: Static void
1.18 augustss 1623: ehci_dump_exfer(struct ehci_xfer *ex)
1624: {
1.139 jmcneill 1625: printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone);
1.18 augustss 1626: }
1.38 martin 1627: #endif
1.5 augustss 1628: #endif
1629:
1.164 uebayasi 1630: Static usbd_status
1.5 augustss 1631: ehci_open(usbd_pipe_handle pipe)
1632: {
1633: usbd_device_handle dev = pipe->device;
1.134 drochner 1634: ehci_softc_t *sc = dev->bus->hci_private;
1.5 augustss 1635: usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1636: u_int8_t addr = dev->address;
1.209 skrll 1637: u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1.5 augustss 1638: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1.10 augustss 1639: ehci_soft_qh_t *sqh;
1640: usbd_status err;
1.78 augustss 1641: int ival, speed, naks;
1.80 augustss 1642: int hshubaddr, hshubport;
1.5 augustss 1643:
1644: DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1645: pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1646:
1.80 augustss 1647: if (dev->myhsport) {
1.172 matt 1648: /*
1649: * When directly attached FS/LS device while doing embedded
1650: * transaction translations and we are the hub, set the hub
1.191 skrll 1651: * address to 0 (us).
1.172 matt 1652: */
1653: if (!(sc->sc_flags & EHCIF_ETTF)
1654: || (dev->myhsport->parent->address != sc->sc_addr)) {
1655: hshubaddr = dev->myhsport->parent->address;
1656: } else {
1657: hshubaddr = 0;
1658: }
1.80 augustss 1659: hshubport = dev->myhsport->portno;
1660: } else {
1661: hshubaddr = 0;
1662: hshubport = 0;
1663: }
1664:
1.17 augustss 1665: if (sc->sc_dying)
1666: return (USBD_IOERROR);
1667:
1.175 drochner 1668: /* toggle state needed for bulk endpoints */
1669: epipe->nexttoggle = pipe->endpoint->datatoggle;
1.55 mycroft 1670:
1.5 augustss 1671: if (addr == sc->sc_addr) {
1672: switch (ed->bEndpointAddress) {
1673: case USB_CONTROL_ENDPOINT:
1674: pipe->methods = &ehci_root_ctrl_methods;
1675: break;
1676: case UE_DIR_IN | EHCI_INTR_ENDPT:
1677: pipe->methods = &ehci_root_intr_methods;
1678: break;
1679: default:
1.139 jmcneill 1680: DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n",
1681: ed->bEndpointAddress));
1.5 augustss 1682: return (USBD_INVAL);
1683: }
1.10 augustss 1684: return (USBD_NORMAL_COMPLETION);
1685: }
1686:
1.24 augustss 1687: /* XXX All this stuff is only valid for async. */
1.11 augustss 1688: switch (dev->speed) {
1689: case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1690: case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1691: case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1.37 provos 1692: default: panic("ehci_open: bad device speed %d", dev->speed);
1.11 augustss 1693: }
1.99 augustss 1694: if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) {
1.146 jmcneill 1695: aprint_error_dev(sc->sc_dev, "error opening low/full speed "
1696: "isoc endpoint.\n");
1697: aprint_normal_dev(sc->sc_dev, "a low/full speed device is "
1698: "attached to a USB2 hub, and transaction translations are "
1699: "not yet supported.\n");
1700: aprint_normal_dev(sc->sc_dev, "reattach the device to the "
1701: "root hub instead.\n");
1.80 augustss 1702: DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n",
1703: hshubaddr, hshubport));
1.99 augustss 1704: return USBD_INVAL;
1.80 augustss 1705: }
1706:
1.169 msaitoh 1707: /*
1708: * For interrupt transfer, nak throttling must be disabled, but for
1709: * the other transfer type, nak throttling should be enabled from the
1.191 skrll 1710: * viewpoint that avoids the memory thrashing.
1.169 msaitoh 1711: */
1712: naks = (xfertype == UE_INTERRUPT) ? 0
1713: : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0);
1.10 augustss 1714:
1.139 jmcneill 1715: /* Allocate sqh for everything, save isoc xfers */
1716: if (xfertype != UE_ISOCHRONOUS) {
1717: sqh = ehci_alloc_sqh(sc);
1718: if (sqh == NULL)
1719: return (USBD_NOMEM);
1720: /* qh_link filled when the QH is added */
1721: sqh->qh.qh_endp = htole32(
1722: EHCI_QH_SET_ADDR(addr) |
1723: EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
1724: EHCI_QH_SET_EPS(speed) |
1725: EHCI_QH_DTC |
1726: EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1727: (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1728: EHCI_QH_CTL : 0) |
1729: EHCI_QH_SET_NRL(naks)
1730: );
1731: sqh->qh.qh_endphub = htole32(
1732: EHCI_QH_SET_MULT(1) |
1733: EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0)
1734: );
1.167 jakllsch 1735: if (speed != EHCI_QH_SPEED_HIGH)
1736: sqh->qh.qh_endphub |= htole32(
1737: EHCI_QH_SET_PORT(hshubport) |
1738: EHCI_QH_SET_HUBA(hshubaddr) |
1739: EHCI_QH_SET_CMASK(0x08) /* XXX */
1740: );
1.139 jmcneill 1741: sqh->qh.qh_curqtd = EHCI_NULL;
1742: /* Fill the overlay qTD */
1743: sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1744: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1745: sqh->qh.qh_qtd.qtd_status = htole32(0);
1746:
1747: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1748: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1749: epipe->sqh = sqh;
1750: } else {
1751: sqh = NULL;
1752: } /*xfertype == UE_ISOC*/
1.5 augustss 1753:
1.10 augustss 1754: switch (xfertype) {
1755: case UE_CONTROL:
1.33 augustss 1756: err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1.10 augustss 1757: 0, &epipe->u.ctl.reqdma);
1.25 augustss 1758: #ifdef EHCI_DEBUG
1759: if (err)
1760: printf("ehci_open: usb_allocmem()=%d\n", err);
1761: #endif
1.10 augustss 1762: if (err)
1.116 drochner 1763: goto bad;
1.11 augustss 1764: pipe->methods = &ehci_device_ctrl_methods;
1.190 mrg 1765: mutex_enter(&sc->sc_lock);
1766: ehci_add_qh(sc, sqh, sc->sc_async_head);
1767: mutex_exit(&sc->sc_lock);
1.10 augustss 1768: break;
1769: case UE_BULK:
1770: pipe->methods = &ehci_device_bulk_methods;
1.190 mrg 1771: mutex_enter(&sc->sc_lock);
1772: ehci_add_qh(sc, sqh, sc->sc_async_head);
1773: mutex_exit(&sc->sc_lock);
1.10 augustss 1774: break;
1.24 augustss 1775: case UE_INTERRUPT:
1776: pipe->methods = &ehci_device_intr_methods;
1.78 augustss 1777: ival = pipe->interval;
1.116 drochner 1778: if (ival == USBD_DEFAULT_INTERVAL) {
1779: if (speed == EHCI_QH_SPEED_HIGH) {
1780: if (ed->bInterval > 16) {
1781: /*
1782: * illegal with high-speed, but there
1783: * were documentation bugs in the spec,
1784: * so be generous
1785: */
1786: ival = 256;
1787: } else
1788: ival = (1 << (ed->bInterval - 1)) / 8;
1789: } else
1790: ival = ed->bInterval;
1791: }
1792: err = ehci_device_setintr(sc, sqh, ival);
1793: if (err)
1794: goto bad;
1795: break;
1.24 augustss 1796: case UE_ISOCHRONOUS:
1797: pipe->methods = &ehci_device_isoc_methods;
1.142 drochner 1798: if (ed->bInterval == 0 || ed->bInterval > 16) {
1.139 jmcneill 1799: printf("ehci: opening pipe with invalid bInterval\n");
1800: err = USBD_INVAL;
1801: goto bad;
1802: }
1803: if (UGETW(ed->wMaxPacketSize) == 0) {
1804: printf("ehci: zero length endpoint open request\n");
1805: err = USBD_INVAL;
1806: goto bad;
1807: }
1808: epipe->u.isoc.next_frame = 0;
1809: epipe->u.isoc.cur_xfers = 0;
1810: break;
1.10 augustss 1811: default:
1.139 jmcneill 1812: DPRINTF(("ehci: bad xfer type %d\n", xfertype));
1.116 drochner 1813: err = USBD_INVAL;
1814: goto bad;
1.5 augustss 1815: }
1816: return (USBD_NORMAL_COMPLETION);
1817:
1.116 drochner 1818: bad:
1.139 jmcneill 1819: if (sqh != NULL)
1820: ehci_free_sqh(sc, sqh);
1.116 drochner 1821: return (err);
1.10 augustss 1822: }
1823:
1824: /*
1.190 mrg 1825: * Add an ED to the schedule. Called with USB lock held.
1.10 augustss 1826: */
1.164 uebayasi 1827: Static void
1.190 mrg 1828: ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1.10 augustss 1829: {
1830:
1.190 mrg 1831: KASSERT(mutex_owned(&sc->sc_lock));
1832:
1.138 bouyer 1833: usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
1834: sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE);
1.10 augustss 1835: sqh->next = head->next;
1836: sqh->qh.qh_link = head->qh.qh_link;
1.138 bouyer 1837: usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
1838: sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE);
1.10 augustss 1839: head->next = sqh;
1.15 augustss 1840: head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1.138 bouyer 1841: usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
1842: sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE);
1.10 augustss 1843:
1844: #ifdef EHCI_DEBUG
1.22 augustss 1845: if (ehcidebug > 5) {
1.10 augustss 1846: printf("ehci_add_qh:\n");
1847: ehci_dump_sqh(sqh);
1848: }
1.5 augustss 1849: #endif
1850: }
1851:
1.10 augustss 1852: /*
1.190 mrg 1853: * Remove an ED from the schedule. Called with USB lock held.
1.10 augustss 1854: */
1.164 uebayasi 1855: Static void
1.10 augustss 1856: ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1857: {
1.33 augustss 1858: ehci_soft_qh_t *p;
1.10 augustss 1859:
1.190 mrg 1860: KASSERT(mutex_owned(&sc->sc_lock));
1861:
1.10 augustss 1862: /* XXX */
1.42 augustss 1863: for (p = head; p != NULL && p->next != sqh; p = p->next)
1.10 augustss 1864: ;
1865: if (p == NULL)
1.37 provos 1866: panic("ehci_rem_qh: ED not found");
1.138 bouyer 1867: usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
1868: sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE);
1.10 augustss 1869: p->next = sqh->next;
1870: p->qh.qh_link = sqh->qh.qh_link;
1.138 bouyer 1871: usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link),
1872: sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE);
1.10 augustss 1873:
1.11 augustss 1874: ehci_sync_hc(sc);
1875: }
1876:
1.164 uebayasi 1877: Static void
1.23 augustss 1878: ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1879: {
1.85 augustss 1880: int i;
1.87 augustss 1881: u_int32_t status;
1.85 augustss 1882:
1.87 augustss 1883: /* Save toggle bit and ping status. */
1.138 bouyer 1884: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1885: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.87 augustss 1886: status = sqh->qh.qh_qtd.qtd_status &
1887: htole32(EHCI_QTD_TOGGLE_MASK |
1888: EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
1.85 augustss 1889: /* Set HALTED to make hw leave it alone. */
1890: sqh->qh.qh_qtd.qtd_status =
1891: htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
1.138 bouyer 1892: usb_syncmem(&sqh->dma,
1893: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
1894: sizeof(sqh->qh.qh_qtd.qtd_status),
1895: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.23 augustss 1896: sqh->qh.qh_curqtd = 0;
1897: sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1.179 jmcneill 1898: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1.85 augustss 1899: for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
1900: sqh->qh.qh_qtd.qtd_buffer[i] = 0;
1.23 augustss 1901: sqh->sqtd = sqtd;
1.138 bouyer 1902: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1903: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.87 augustss 1904: /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
1905: sqh->qh.qh_qtd.qtd_status = status;
1.138 bouyer 1906: usb_syncmem(&sqh->dma,
1907: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
1908: sizeof(sqh->qh.qh_qtd.qtd_status),
1909: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.23 augustss 1910: }
1911:
1.11 augustss 1912: /*
1913: * Ensure that the HC has released all references to the QH. We do this
1914: * by asking for a Async Advance Doorbell interrupt and then we wait for
1915: * the interrupt.
1916: * To make this easier we first obtain exclusive use of the doorbell.
1917: */
1.164 uebayasi 1918: Static void
1.11 augustss 1919: ehci_sync_hc(ehci_softc_t *sc)
1920: {
1.215 christos 1921: int error __diagused;
1.190 mrg 1922:
1923: KASSERT(mutex_owned(&sc->sc_lock));
1.11 augustss 1924:
1.12 augustss 1925: if (sc->sc_dying) {
1926: DPRINTFN(2,("ehci_sync_hc: dying\n"));
1927: return;
1928: }
1929: DPRINTFN(2,("ehci_sync_hc: enter\n"));
1.10 augustss 1930: /* ask for doorbell */
1931: EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1.15 augustss 1932: DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1933: EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1.190 mrg 1934: error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */
1.15 augustss 1935: DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1936: EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1937: #ifdef DIAGNOSTIC
1938: if (error)
1.190 mrg 1939: printf("ehci_sync_hc: cv_timedwait() = %d\n", error);
1.15 augustss 1940: #endif
1.12 augustss 1941: DPRINTFN(2,("ehci_sync_hc: exit\n"));
1.10 augustss 1942: }
1943:
1.164 uebayasi 1944: Static void
1.139 jmcneill 1945: ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer)
1946: {
1947: struct ehci_soft_itd *itd, *prev;
1948:
1949: prev = NULL;
1950:
1951: if (exfer->itdstart == NULL || exfer->itdend == NULL)
1952: panic("ehci isoc xfer being freed, but with no itd chain\n");
1953:
1954: for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
1955: prev = itd->u.frame_list.prev;
1956: /* Unlink itd from hardware chain, or frame array */
1957: if (prev == NULL) { /* We're at the table head */
1958: sc->sc_softitds[itd->slot] = itd->u.frame_list.next;
1959: sc->sc_flist[itd->slot] = itd->itd.itd_next;
1960: usb_syncmem(&sc->sc_fldma,
1961: sizeof(ehci_link_t) * itd->slot,
1962: sizeof(ehci_link_t),
1963: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1964:
1965: if (itd->u.frame_list.next != NULL)
1966: itd->u.frame_list.next->u.frame_list.prev = NULL;
1967: } else {
1968: /* XXX this part is untested... */
1969: prev->itd.itd_next = itd->itd.itd_next;
1970: usb_syncmem(&itd->dma,
1971: itd->offs + offsetof(ehci_itd_t, itd_next),
1972: sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE);
1973:
1974: prev->u.frame_list.next = itd->u.frame_list.next;
1975: if (itd->u.frame_list.next != NULL)
1976: itd->u.frame_list.next->u.frame_list.prev = prev;
1977: }
1978: }
1979:
1980: prev = NULL;
1981: for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
1982: if (prev != NULL)
1983: ehci_free_itd(sc, prev);
1984: prev = itd;
1985: }
1986: if (prev)
1987: ehci_free_itd(sc, prev);
1988: exfer->itdstart = NULL;
1989: exfer->itdend = NULL;
1990: }
1991:
1.5 augustss 1992: /***********/
1993:
1994: /*
1995: * Data structures and routines to emulate the root hub.
1996: */
1997: Static usb_device_descriptor_t ehci_devd = {
1998: USB_DEVICE_DESCRIPTOR_SIZE,
1999: UDESC_DEVICE, /* type */
2000: {0x00, 0x02}, /* USB version */
2001: UDCLASS_HUB, /* class */
2002: UDSUBCLASS_HUB, /* subclass */
1.11 augustss 2003: UDPROTO_HSHUBSTT, /* protocol */
1.5 augustss 2004: 64, /* max packet */
2005: {0},{0},{0x00,0x01}, /* device id */
2006: 1,2,0, /* string indicies */
2007: 1 /* # of configurations */
2008: };
2009:
1.123 drochner 2010: Static const usb_device_qualifier_t ehci_odevd = {
1.11 augustss 2011: USB_DEVICE_DESCRIPTOR_SIZE,
2012: UDESC_DEVICE_QUALIFIER, /* type */
2013: {0x00, 0x02}, /* USB version */
2014: UDCLASS_HUB, /* class */
2015: UDSUBCLASS_HUB, /* subclass */
2016: UDPROTO_FSHUB, /* protocol */
2017: 64, /* max packet */
2018: 1, /* # of configurations */
2019: 0
2020: };
2021:
1.123 drochner 2022: Static const usb_config_descriptor_t ehci_confd = {
1.5 augustss 2023: USB_CONFIG_DESCRIPTOR_SIZE,
2024: UDESC_CONFIG,
2025: {USB_CONFIG_DESCRIPTOR_SIZE +
2026: USB_INTERFACE_DESCRIPTOR_SIZE +
2027: USB_ENDPOINT_DESCRIPTOR_SIZE},
2028: 1,
2029: 1,
2030: 0,
1.120 drochner 2031: UC_ATTR_MBO | UC_SELF_POWERED,
1.5 augustss 2032: 0 /* max power */
2033: };
2034:
1.123 drochner 2035: Static const usb_interface_descriptor_t ehci_ifcd = {
1.5 augustss 2036: USB_INTERFACE_DESCRIPTOR_SIZE,
2037: UDESC_INTERFACE,
2038: 0,
2039: 0,
2040: 1,
2041: UICLASS_HUB,
2042: UISUBCLASS_HUB,
1.11 augustss 2043: UIPROTO_HSHUBSTT,
1.5 augustss 2044: 0
2045: };
2046:
1.123 drochner 2047: Static const usb_endpoint_descriptor_t ehci_endpd = {
1.5 augustss 2048: USB_ENDPOINT_DESCRIPTOR_SIZE,
2049: UDESC_ENDPOINT,
2050: UE_DIR_IN | EHCI_INTR_ENDPT,
2051: UE_INTERRUPT,
2052: {8, 0}, /* max packet */
1.118 drochner 2053: 12
1.5 augustss 2054: };
2055:
1.123 drochner 2056: Static const usb_hub_descriptor_t ehci_hubd = {
1.5 augustss 2057: USB_HUB_DESCRIPTOR_SIZE,
2058: UDESC_HUB,
2059: 0,
2060: {0,0},
2061: 0,
2062: 0,
1.111 christos 2063: {""},
2064: {""},
1.5 augustss 2065: };
2066:
2067: /*
2068: * Simulate a hardware hub by handling all the necessary requests.
2069: */
2070: Static usbd_status
2071: ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
2072: {
1.190 mrg 2073: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.5 augustss 2074: usbd_status err;
2075:
2076: /* Insert last in queue. */
1.190 mrg 2077: mutex_enter(&sc->sc_lock);
1.5 augustss 2078: err = usb_insert_transfer(xfer);
1.190 mrg 2079: mutex_exit(&sc->sc_lock);
1.5 augustss 2080: if (err)
2081: return (err);
2082:
2083: /* Pipe isn't running, start first */
2084: return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2085: }
2086:
2087: Static usbd_status
2088: ehci_root_ctrl_start(usbd_xfer_handle xfer)
2089: {
1.134 drochner 2090: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.5 augustss 2091: usb_device_request_t *req;
2092: void *buf = NULL;
2093: int port, i;
1.190 mrg 2094: int len, value, index, l, totlen = 0;
1.5 augustss 2095: usb_port_status_t ps;
2096: usb_hub_descriptor_t hubd;
2097: usbd_status err;
2098: u_int32_t v;
2099:
2100: if (sc->sc_dying)
2101: return (USBD_IOERROR);
2102:
2103: #ifdef DIAGNOSTIC
2104: if (!(xfer->rqflags & URQ_REQUEST))
2105: /* XXX panic */
2106: return (USBD_INVAL);
2107: #endif
2108: req = &xfer->request;
2109:
1.72 augustss 2110: DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n",
1.5 augustss 2111: req->bmRequestType, req->bRequest));
2112:
2113: len = UGETW(req->wLength);
2114: value = UGETW(req->wValue);
2115: index = UGETW(req->wIndex);
2116:
2117: if (len != 0)
1.30 augustss 2118: buf = KERNADDR(&xfer->dmabuf, 0);
1.5 augustss 2119:
2120: #define C(x,y) ((x) | ((y) << 8))
2121: switch(C(req->bRequest, req->bmRequestType)) {
2122: case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2123: case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2124: case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1.33 augustss 2125: /*
1.5 augustss 2126: * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2127: * for the integrated root hub.
2128: */
2129: break;
2130: case C(UR_GET_CONFIG, UT_READ_DEVICE):
2131: if (len > 0) {
2132: *(u_int8_t *)buf = sc->sc_conf;
2133: totlen = 1;
2134: }
2135: break;
2136: case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1.72 augustss 2137: DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value));
1.109 christos 2138: if (len == 0)
2139: break;
1.5 augustss 2140: switch(value >> 8) {
2141: case UDESC_DEVICE:
2142: if ((value & 0xff) != 0) {
2143: err = USBD_IOERROR;
2144: goto ret;
2145: }
2146: totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2147: USETW(ehci_devd.idVendor, sc->sc_id_vendor);
2148: memcpy(buf, &ehci_devd, l);
2149: break;
1.33 augustss 2150: /*
1.11 augustss 2151: * We can't really operate at another speed, but the spec says
2152: * we need this descriptor.
2153: */
2154: case UDESC_DEVICE_QUALIFIER:
2155: if ((value & 0xff) != 0) {
2156: err = USBD_IOERROR;
2157: goto ret;
2158: }
2159: totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2160: memcpy(buf, &ehci_odevd, l);
2161: break;
1.33 augustss 2162: /*
1.11 augustss 2163: * We can't really operate at another speed, but the spec says
2164: * we need this descriptor.
2165: */
2166: case UDESC_OTHER_SPEED_CONFIGURATION:
1.5 augustss 2167: case UDESC_CONFIG:
2168: if ((value & 0xff) != 0) {
2169: err = USBD_IOERROR;
2170: goto ret;
2171: }
2172: totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
2173: memcpy(buf, &ehci_confd, l);
1.11 augustss 2174: ((usb_config_descriptor_t *)buf)->bDescriptorType =
2175: value >> 8;
1.5 augustss 2176: buf = (char *)buf + l;
2177: len -= l;
2178: l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
2179: totlen += l;
2180: memcpy(buf, &ehci_ifcd, l);
2181: buf = (char *)buf + l;
2182: len -= l;
2183: l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
2184: totlen += l;
2185: memcpy(buf, &ehci_endpd, l);
2186: break;
2187: case UDESC_STRING:
1.131 drochner 2188: #define sd ((usb_string_descriptor_t *)buf)
1.5 augustss 2189: switch (value & 0xff) {
1.88 augustss 2190: case 0: /* Language table */
1.131 drochner 2191: totlen = usb_makelangtbl(sd, len);
1.88 augustss 2192: break;
1.5 augustss 2193: case 1: /* Vendor */
1.131 drochner 2194: totlen = usb_makestrdesc(sd, len,
2195: sc->sc_vendor);
1.5 augustss 2196: break;
2197: case 2: /* Product */
1.131 drochner 2198: totlen = usb_makestrdesc(sd, len,
2199: "EHCI root hub");
1.5 augustss 2200: break;
2201: }
1.131 drochner 2202: #undef sd
1.5 augustss 2203: break;
2204: default:
2205: err = USBD_IOERROR;
2206: goto ret;
2207: }
2208: break;
2209: case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2210: if (len > 0) {
2211: *(u_int8_t *)buf = 0;
2212: totlen = 1;
2213: }
2214: break;
2215: case C(UR_GET_STATUS, UT_READ_DEVICE):
2216: if (len > 1) {
2217: USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
2218: totlen = 2;
2219: }
2220: break;
2221: case C(UR_GET_STATUS, UT_READ_INTERFACE):
2222: case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2223: if (len > 1) {
2224: USETW(((usb_status_t *)buf)->wStatus, 0);
2225: totlen = 2;
2226: }
2227: break;
2228: case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2229: if (value >= USB_MAX_DEVICES) {
2230: err = USBD_IOERROR;
2231: goto ret;
2232: }
2233: sc->sc_addr = value;
2234: break;
2235: case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2236: if (value != 0 && value != 1) {
2237: err = USBD_IOERROR;
2238: goto ret;
2239: }
2240: sc->sc_conf = value;
2241: break;
2242: case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2243: break;
2244: case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2245: case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2246: case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2247: err = USBD_IOERROR;
2248: goto ret;
2249: case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2250: break;
2251: case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2252: break;
2253: /* Hub requests */
2254: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2255: break;
2256: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1.106 augustss 2257: DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE "
1.5 augustss 2258: "port=%d feature=%d\n",
2259: index, value));
2260: if (index < 1 || index > sc->sc_noport) {
2261: err = USBD_IOERROR;
2262: goto ret;
2263: }
2264: port = EHCI_PORTSC(index);
1.106 augustss 2265: v = EOREAD4(sc, port);
2266: DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2267: v &= ~EHCI_PS_CLEAR;
1.5 augustss 2268: switch(value) {
2269: case UHF_PORT_ENABLE:
2270: EOWRITE4(sc, port, v &~ EHCI_PS_PE);
2271: break;
2272: case UHF_PORT_SUSPEND:
1.137 drochner 2273: if (!(v & EHCI_PS_SUSP)) /* not suspended */
2274: break;
2275: v &= ~EHCI_PS_SUSP;
2276: EOWRITE4(sc, port, v | EHCI_PS_FPR);
2277: /* see USB2 spec ch. 7.1.7.7 */
2278: usb_delay_ms(&sc->sc_bus, 20);
2279: EOWRITE4(sc, port, v);
2280: usb_delay_ms(&sc->sc_bus, 2);
2281: #ifdef DEBUG
2282: v = EOREAD4(sc, port);
2283: if (v & (EHCI_PS_FPR | EHCI_PS_SUSP))
2284: printf("ehci: resume failed: %x\n", v);
2285: #endif
1.5 augustss 2286: break;
2287: case UHF_PORT_POWER:
1.106 augustss 2288: if (sc->sc_hasppc)
2289: EOWRITE4(sc, port, v &~ EHCI_PS_PP);
1.5 augustss 2290: break;
1.14 augustss 2291: case UHF_PORT_TEST:
1.72 augustss 2292: DPRINTFN(2,("ehci_root_ctrl_start: clear port test "
1.14 augustss 2293: "%d\n", index));
2294: break;
2295: case UHF_PORT_INDICATOR:
1.72 augustss 2296: DPRINTFN(2,("ehci_root_ctrl_start: clear port ind "
1.14 augustss 2297: "%d\n", index));
2298: EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
2299: break;
1.5 augustss 2300: case UHF_C_PORT_CONNECTION:
2301: EOWRITE4(sc, port, v | EHCI_PS_CSC);
2302: break;
2303: case UHF_C_PORT_ENABLE:
2304: EOWRITE4(sc, port, v | EHCI_PS_PEC);
2305: break;
2306: case UHF_C_PORT_SUSPEND:
2307: /* how? */
2308: break;
2309: case UHF_C_PORT_OVER_CURRENT:
2310: EOWRITE4(sc, port, v | EHCI_PS_OCC);
2311: break;
2312: case UHF_C_PORT_RESET:
1.106 augustss 2313: sc->sc_isreset[index] = 0;
1.5 augustss 2314: break;
2315: default:
2316: err = USBD_IOERROR;
2317: goto ret;
2318: }
2319: #if 0
2320: switch(value) {
2321: case UHF_C_PORT_CONNECTION:
2322: case UHF_C_PORT_ENABLE:
2323: case UHF_C_PORT_SUSPEND:
2324: case UHF_C_PORT_OVER_CURRENT:
2325: case UHF_C_PORT_RESET:
2326: default:
2327: break;
2328: }
2329: #endif
2330: break;
2331: case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1.109 christos 2332: if (len == 0)
2333: break;
1.51 toshii 2334: if ((value & 0xff) != 0) {
1.5 augustss 2335: err = USBD_IOERROR;
2336: goto ret;
2337: }
2338: hubd = ehci_hubd;
2339: hubd.bNbrPorts = sc->sc_noport;
2340: v = EOREAD4(sc, EHCI_HCSPARAMS);
2341: USETW(hubd.wHubCharacteristics,
1.14 augustss 2342: EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
1.78 augustss 2343: EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS))
1.164 uebayasi 2344: ? UHD_PORT_IND : 0);
1.5 augustss 2345: hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
1.33 augustss 2346: for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1.5 augustss 2347: hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
2348: hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2349: l = min(len, hubd.bDescLength);
2350: totlen = l;
2351: memcpy(buf, &hubd, l);
2352: break;
2353: case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2354: if (len != 4) {
2355: err = USBD_IOERROR;
2356: goto ret;
2357: }
2358: memset(buf, 0, len); /* ? XXX */
2359: totlen = len;
2360: break;
2361: case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1.72 augustss 2362: DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
1.5 augustss 2363: index));
2364: if (index < 1 || index > sc->sc_noport) {
2365: err = USBD_IOERROR;
2366: goto ret;
2367: }
2368: if (len != 4) {
2369: err = USBD_IOERROR;
2370: goto ret;
2371: }
2372: v = EOREAD4(sc, EHCI_PORTSC(index));
1.178 matt 2373: DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v));
1.172 matt 2374:
1.178 matt 2375: i = UPS_HIGH_SPEED;
1.172 matt 2376: if (sc->sc_flags & EHCIF_ETTF) {
2377: /*
2378: * If we are doing embedded transaction translation,
2379: * then directly attached LS/FS devices are reset by
2380: * the EHCI controller itself. PSPD is encoded
1.195 christos 2381: * the same way as in USBSTATUS.
1.172 matt 2382: */
2383: i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED;
2384: }
1.5 augustss 2385: if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
2386: if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
2387: if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
2388: if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
2389: if (v & EHCI_PS_PR) i |= UPS_RESET;
2390: if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
1.170 kiyohara 2391: if (sc->sc_vendor_port_status)
2392: i = sc->sc_vendor_port_status(sc, v, i);
1.5 augustss 2393: USETW(ps.wPortStatus, i);
2394: i = 0;
2395: if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
2396: if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
2397: if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
1.106 augustss 2398: if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
1.5 augustss 2399: USETW(ps.wPortChange, i);
2400: l = min(len, sizeof ps);
2401: memcpy(buf, &ps, l);
2402: totlen = l;
2403: break;
2404: case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2405: err = USBD_IOERROR;
2406: goto ret;
2407: case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2408: break;
2409: case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2410: if (index < 1 || index > sc->sc_noport) {
2411: err = USBD_IOERROR;
2412: goto ret;
2413: }
2414: port = EHCI_PORTSC(index);
1.106 augustss 2415: v = EOREAD4(sc, port);
2416: DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2417: v &= ~EHCI_PS_CLEAR;
1.5 augustss 2418: switch(value) {
2419: case UHF_PORT_ENABLE:
2420: EOWRITE4(sc, port, v | EHCI_PS_PE);
2421: break;
2422: case UHF_PORT_SUSPEND:
2423: EOWRITE4(sc, port, v | EHCI_PS_SUSP);
2424: break;
2425: case UHF_PORT_RESET:
1.72 augustss 2426: DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
1.5 augustss 2427: index));
1.172 matt 2428: if (EHCI_PS_IS_LOWSPEED(v)
2429: && sc->sc_ncomp > 0
2430: && !(sc->sc_flags & EHCIF_ETTF)) {
2431: /*
2432: * Low speed device on non-ETTF controller or
2433: * unaccompanied controller, give up ownership.
2434: */
1.6 augustss 2435: ehci_disown(sc, index, 1);
2436: break;
2437: }
1.8 augustss 2438: /* Start reset sequence. */
2439: v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
1.5 augustss 2440: EOWRITE4(sc, port, v | EHCI_PS_PR);
1.8 augustss 2441: /* Wait for reset to complete. */
1.13 augustss 2442: usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
1.17 augustss 2443: if (sc->sc_dying) {
2444: err = USBD_IOERROR;
2445: goto ret;
2446: }
1.172 matt 2447: /*
1.207 jakllsch 2448: * An embedded transaction translator will automatically
1.172 matt 2449: * terminate the reset sequence so there's no need to
2450: * it.
2451: */
1.178 matt 2452: v = EOREAD4(sc, port);
2453: if (v & EHCI_PS_PR) {
1.172 matt 2454: /* Terminate reset sequence. */
1.173 jmcneill 2455: EOWRITE4(sc, port, v & ~EHCI_PS_PR);
1.172 matt 2456: /* Wait for HC to complete reset. */
2457: usb_delay_ms(&sc->sc_bus,
2458: EHCI_PORT_RESET_COMPLETE);
2459: if (sc->sc_dying) {
2460: err = USBD_IOERROR;
2461: goto ret;
2462: }
1.17 augustss 2463: }
1.172 matt 2464:
1.8 augustss 2465: v = EOREAD4(sc, port);
2466: DPRINTF(("ehci after reset, status=0x%08x\n", v));
2467: if (v & EHCI_PS_PR) {
2468: printf("%s: port reset timeout\n",
1.134 drochner 2469: device_xname(sc->sc_dev));
1.8 augustss 2470: return (USBD_TIMEOUT);
1.5 augustss 2471: }
1.8 augustss 2472: if (!(v & EHCI_PS_PE)) {
1.6 augustss 2473: /* Not a high speed device, give up ownership.*/
2474: ehci_disown(sc, index, 0);
2475: break;
2476: }
1.106 augustss 2477: sc->sc_isreset[index] = 1;
1.8 augustss 2478: DPRINTF(("ehci port %d reset, status = 0x%08x\n",
1.6 augustss 2479: index, v));
1.5 augustss 2480: break;
2481: case UHF_PORT_POWER:
1.72 augustss 2482: DPRINTFN(2,("ehci_root_ctrl_start: set port power "
1.106 augustss 2483: "%d (has PPC = %d)\n", index,
2484: sc->sc_hasppc));
2485: if (sc->sc_hasppc)
2486: EOWRITE4(sc, port, v | EHCI_PS_PP);
1.5 augustss 2487: break;
1.11 augustss 2488: case UHF_PORT_TEST:
1.72 augustss 2489: DPRINTFN(2,("ehci_root_ctrl_start: set port test "
1.11 augustss 2490: "%d\n", index));
2491: break;
2492: case UHF_PORT_INDICATOR:
1.72 augustss 2493: DPRINTFN(2,("ehci_root_ctrl_start: set port ind "
1.11 augustss 2494: "%d\n", index));
1.14 augustss 2495: EOWRITE4(sc, port, v | EHCI_PS_PIC);
1.11 augustss 2496: break;
1.5 augustss 2497: default:
2498: err = USBD_IOERROR;
2499: goto ret;
2500: }
2501: break;
1.11 augustss 2502: case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
2503: case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
2504: case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
2505: case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
2506: break;
1.5 augustss 2507: default:
2508: err = USBD_IOERROR;
2509: goto ret;
2510: }
2511: xfer->actlen = totlen;
2512: err = USBD_NORMAL_COMPLETION;
2513: ret:
1.190 mrg 2514: mutex_enter(&sc->sc_lock);
1.5 augustss 2515: xfer->status = err;
2516: usb_transfer_complete(xfer);
1.190 mrg 2517: mutex_exit(&sc->sc_lock);
1.5 augustss 2518: return (USBD_IN_PROGRESS);
1.6 augustss 2519: }
2520:
1.164 uebayasi 2521: Static void
1.115 christos 2522: ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
1.6 augustss 2523: {
1.24 augustss 2524: int port;
1.6 augustss 2525: u_int32_t v;
2526:
2527: DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
2528: #ifdef DIAGNOSTIC
2529: if (sc->sc_npcomp != 0) {
1.24 augustss 2530: int i = (index-1) / sc->sc_npcomp;
1.6 augustss 2531: if (i >= sc->sc_ncomp)
2532: printf("%s: strange port\n",
1.134 drochner 2533: device_xname(sc->sc_dev));
1.6 augustss 2534: else
2535: printf("%s: handing over %s speed device on "
2536: "port %d to %s\n",
1.134 drochner 2537: device_xname(sc->sc_dev),
1.6 augustss 2538: lowspeed ? "low" : "full",
1.134 drochner 2539: index, device_xname(sc->sc_comps[i]));
1.6 augustss 2540: } else {
1.134 drochner 2541: printf("%s: npcomp == 0\n", device_xname(sc->sc_dev));
1.6 augustss 2542: }
2543: #endif
2544: port = EHCI_PORTSC(index);
2545: v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2546: EOWRITE4(sc, port, v | EHCI_PS_PO);
1.5 augustss 2547: }
2548:
2549: /* Abort a root control request. */
2550: Static void
1.115 christos 2551: ehci_root_ctrl_abort(usbd_xfer_handle xfer)
1.5 augustss 2552: {
2553: /* Nothing to do, all transfers are synchronous. */
2554: }
2555:
2556: /* Close the root pipe. */
2557: Static void
1.115 christos 2558: ehci_root_ctrl_close(usbd_pipe_handle pipe)
1.5 augustss 2559: {
2560: DPRINTF(("ehci_root_ctrl_close\n"));
2561: /* Nothing to do. */
2562: }
2563:
1.164 uebayasi 2564: Static void
1.208 jakllsch 2565: ehci_root_ctrl_done(usbd_xfer_handle xfer)
1.5 augustss 2566: {
1.78 augustss 2567: xfer->hcpriv = NULL;
1.5 augustss 2568: }
2569:
2570: Static usbd_status
2571: ehci_root_intr_transfer(usbd_xfer_handle xfer)
2572: {
1.190 mrg 2573: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.5 augustss 2574: usbd_status err;
2575:
2576: /* Insert last in queue. */
1.190 mrg 2577: mutex_enter(&sc->sc_lock);
1.5 augustss 2578: err = usb_insert_transfer(xfer);
1.190 mrg 2579: mutex_exit(&sc->sc_lock);
1.5 augustss 2580: if (err)
2581: return (err);
2582:
2583: /* Pipe isn't running, start first */
2584: return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2585: }
2586:
2587: Static usbd_status
2588: ehci_root_intr_start(usbd_xfer_handle xfer)
2589: {
2590: usbd_pipe_handle pipe = xfer->pipe;
1.134 drochner 2591: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.5 augustss 2592:
2593: if (sc->sc_dying)
2594: return (USBD_IOERROR);
2595:
1.190 mrg 2596: mutex_enter(&sc->sc_lock);
1.5 augustss 2597: sc->sc_intrxfer = xfer;
1.190 mrg 2598: mutex_exit(&sc->sc_lock);
1.5 augustss 2599:
2600: return (USBD_IN_PROGRESS);
2601: }
2602:
2603: /* Abort a root interrupt request. */
2604: Static void
2605: ehci_root_intr_abort(usbd_xfer_handle xfer)
2606: {
1.190 mrg 2607: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.5 augustss 2608:
1.190 mrg 2609: KASSERT(mutex_owned(&sc->sc_lock));
1.227 skrll 2610: KASSERT(xfer->pipe->intrxfer == xfer);
2611:
2612: sc->sc_intrxfer = NULL;
2613:
1.5 augustss 2614: xfer->status = USBD_CANCELLED;
2615: usb_transfer_complete(xfer);
2616: }
2617:
2618: /* Close the root pipe. */
2619: Static void
2620: ehci_root_intr_close(usbd_pipe_handle pipe)
2621: {
1.134 drochner 2622: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.33 augustss 2623:
1.190 mrg 2624: KASSERT(mutex_owned(&sc->sc_lock));
2625:
1.5 augustss 2626: DPRINTF(("ehci_root_intr_close\n"));
2627:
2628: sc->sc_intrxfer = NULL;
2629: }
2630:
1.164 uebayasi 2631: Static void
1.208 jakllsch 2632: ehci_root_intr_done(usbd_xfer_handle xfer)
1.5 augustss 2633: {
1.78 augustss 2634: xfer->hcpriv = NULL;
1.9 augustss 2635: }
2636:
2637: /************************/
2638:
1.164 uebayasi 2639: Static ehci_soft_qh_t *
1.9 augustss 2640: ehci_alloc_sqh(ehci_softc_t *sc)
2641: {
2642: ehci_soft_qh_t *sqh;
2643: usbd_status err;
2644: int i, offs;
2645: usb_dma_t dma;
2646:
2647: if (sc->sc_freeqhs == NULL) {
2648: DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
2649: err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2650: EHCI_PAGE_SIZE, &dma);
1.25 augustss 2651: #ifdef EHCI_DEBUG
2652: if (err)
2653: printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
2654: #endif
1.9 augustss 2655: if (err)
1.11 augustss 2656: return (NULL);
1.9 augustss 2657: for(i = 0; i < EHCI_SQH_CHUNK; i++) {
2658: offs = i * EHCI_SQH_SIZE;
1.30 augustss 2659: sqh = KERNADDR(&dma, offs);
1.31 augustss 2660: sqh->physaddr = DMAADDR(&dma, offs);
1.138 bouyer 2661: sqh->dma = dma;
2662: sqh->offs = offs;
1.9 augustss 2663: sqh->next = sc->sc_freeqhs;
2664: sc->sc_freeqhs = sqh;
2665: }
2666: }
2667: sqh = sc->sc_freeqhs;
2668: sc->sc_freeqhs = sqh->next;
2669: memset(&sqh->qh, 0, sizeof(ehci_qh_t));
1.11 augustss 2670: sqh->next = NULL;
1.9 augustss 2671: return (sqh);
2672: }
2673:
1.164 uebayasi 2674: Static void
1.9 augustss 2675: ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2676: {
2677: sqh->next = sc->sc_freeqhs;
2678: sc->sc_freeqhs = sqh;
2679: }
2680:
1.164 uebayasi 2681: Static ehci_soft_qtd_t *
1.9 augustss 2682: ehci_alloc_sqtd(ehci_softc_t *sc)
2683: {
1.190 mrg 2684: ehci_soft_qtd_t *sqtd = NULL;
1.9 augustss 2685: usbd_status err;
2686: int i, offs;
2687: usb_dma_t dma;
2688:
2689: if (sc->sc_freeqtds == NULL) {
2690: DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
1.190 mrg 2691:
1.9 augustss 2692: err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
2693: EHCI_PAGE_SIZE, &dma);
1.25 augustss 2694: #ifdef EHCI_DEBUG
2695: if (err)
2696: printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
2697: #endif
1.9 augustss 2698: if (err)
1.190 mrg 2699: goto done;
2700:
1.9 augustss 2701: for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2702: offs = i * EHCI_SQTD_SIZE;
1.30 augustss 2703: sqtd = KERNADDR(&dma, offs);
1.31 augustss 2704: sqtd->physaddr = DMAADDR(&dma, offs);
1.138 bouyer 2705: sqtd->dma = dma;
2706: sqtd->offs = offs;
1.190 mrg 2707:
1.9 augustss 2708: sqtd->nextqtd = sc->sc_freeqtds;
2709: sc->sc_freeqtds = sqtd;
2710: }
2711: }
2712:
2713: sqtd = sc->sc_freeqtds;
2714: sc->sc_freeqtds = sqtd->nextqtd;
2715: memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2716: sqtd->nextqtd = NULL;
2717: sqtd->xfer = NULL;
2718:
1.190 mrg 2719: done:
1.9 augustss 2720: return (sqtd);
2721: }
2722:
1.164 uebayasi 2723: Static void
1.9 augustss 2724: ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2725: {
2726:
1.206 skrll 2727: KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1.190 mrg 2728:
1.9 augustss 2729: sqtd->nextqtd = sc->sc_freeqtds;
2730: sc->sc_freeqtds = sqtd;
2731: }
2732:
1.164 uebayasi 2733: Static usbd_status
1.25 augustss 2734: ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
1.15 augustss 2735: int alen, int rd, usbd_xfer_handle xfer,
2736: ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2737: {
2738: ehci_soft_qtd_t *next, *cur;
1.197 prlw1 2739: ehci_physaddr_t nextphys;
1.15 augustss 2740: u_int32_t qtdstatus;
1.55 mycroft 2741: int len, curlen, mps;
2742: int i, tog;
1.197 prlw1 2743: int pages, pageoffs;
2744: bus_size_t curoffs;
2745: vaddr_t va, va_offs;
1.15 augustss 2746: usb_dma_t *dma = &xfer->dmabuf;
1.102 augustss 2747: u_int16_t flags = xfer->flags;
1.197 prlw1 2748: paddr_t a;
1.15 augustss 2749:
1.25 augustss 2750: DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
1.15 augustss 2751:
2752: len = alen;
1.67 mycroft 2753: qtdstatus = EHCI_QTD_ACTIVE |
1.15 augustss 2754: EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2755: EHCI_QTD_SET_CERR(3)
2756: /* IOC set below */
2757: /* BYTES set below */
1.67 mycroft 2758: ;
1.55 mycroft 2759: mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2760: tog = epipe->nexttoggle;
1.64 mycroft 2761: qtdstatus |= EHCI_QTD_SET_TOGGLE(tog);
1.15 augustss 2762:
2763: cur = ehci_alloc_sqtd(sc);
1.25 augustss 2764: *sp = cur;
1.15 augustss 2765: if (cur == NULL)
2766: goto nomem;
1.138 bouyer 2767:
2768: usb_syncmem(dma, 0, alen,
2769: rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1.197 prlw1 2770: curoffs = 0;
1.15 augustss 2771: for (;;) {
1.26 augustss 2772: /* The EHCI hardware can handle at most 5 pages. */
1.197 prlw1 2773: va_offs = (vaddr_t)KERNADDR(dma, curoffs);
2774: va_offs = EHCI_PAGE_OFFSET(va_offs);
2775: if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) {
1.15 augustss 2776: /* we can handle it in this QTD */
1.197 prlw1 2777: curlen = len - curoffs;
1.15 augustss 2778: } else {
2779: /* must use multiple TDs, fill as much as possible. */
1.197 prlw1 2780: curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs;
2781:
1.15 augustss 2782: /* the length must be a multiple of the max size */
1.55 mycroft 2783: curlen -= curlen % mps;
1.25 augustss 2784: DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, "
2785: "curlen=%d\n", curlen));
1.15 augustss 2786: #ifdef DIAGNOSTIC
2787: if (curlen == 0)
1.103 augustss 2788: panic("ehci_alloc_sqtd_chain: curlen == 0");
1.15 augustss 2789: #endif
2790: }
1.201 mbalmer 2791: DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%d "
1.202 christos 2792: "curoffs=%zu\n", len, curlen, (size_t)curoffs));
1.15 augustss 2793:
1.102 augustss 2794: /*
1.110 blymn 2795: * Allocate another transfer if there's more data left,
2796: * or if force last short transfer flag is set and we're
1.102 augustss 2797: * allocating a multiple of the max packet size.
2798: */
1.197 prlw1 2799:
2800: if (curoffs + curlen != len ||
1.102 augustss 2801: ((curlen % mps) == 0 && !rd && curlen != 0 &&
2802: (flags & USBD_FORCE_SHORT_XFER))) {
1.15 augustss 2803: next = ehci_alloc_sqtd(sc);
2804: if (next == NULL)
2805: goto nomem;
1.66 mycroft 2806: nextphys = htole32(next->physaddr);
1.15 augustss 2807: } else {
2808: next = NULL;
2809: nextphys = EHCI_NULL;
2810: }
2811:
1.197 prlw1 2812: /* Find number of pages we'll be using, insert dma addresses */
2813: pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12;
2814: KASSERT(pages <= EHCI_QTD_NBUFFERS);
2815: pageoffs = EHCI_PAGE(curoffs);
2816: for (i = 0; i < pages; i++) {
2817: a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE);
2818: cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000);
2819: /* Cast up to avoid compiler warnings */
2820: cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32);
1.15 augustss 2821: }
1.197 prlw1 2822:
2823: /* First buffer pointer requires a page offset to start at */
2824: va = (vaddr_t)KERNADDR(dma, curoffs);
2825: cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va));
2826:
1.15 augustss 2827: cur->nextqtd = next;
1.66 mycroft 2828: cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys;
1.15 augustss 2829: cur->qtd.qtd_status =
1.67 mycroft 2830: htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen));
1.15 augustss 2831: cur->xfer = xfer;
1.18 augustss 2832: cur->len = curlen;
1.138 bouyer 2833:
1.200 christos 2834: DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08zx end=0x%08zx\n",
2835: (size_t)curoffs, (size_t)(curoffs + curlen)));
1.197 prlw1 2836:
1.55 mycroft 2837: /* adjust the toggle based on the number of packets in this
2838: qtd */
2839: if (((curlen + mps - 1) / mps) & 1) {
2840: tog ^= 1;
1.64 mycroft 2841: qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
1.55 mycroft 2842: }
1.102 augustss 2843: if (next == NULL)
1.15 augustss 2844: break;
1.138 bouyer 2845: usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
2846: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.25 augustss 2847: DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
1.174 drochner 2848: if (len)
1.197 prlw1 2849: curoffs += curlen;
1.15 augustss 2850: cur = next;
2851: }
2852: cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
1.138 bouyer 2853: usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
2854: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 2855: *ep = cur;
1.55 mycroft 2856: epipe->nexttoggle = tog;
1.15 augustss 2857:
1.29 augustss 2858: DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2859: *sp, *ep));
2860:
1.15 augustss 2861: return (USBD_NORMAL_COMPLETION);
2862:
2863: nomem:
2864: /* XXX free chain */
1.25 augustss 2865: DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
1.15 augustss 2866: return (USBD_NOMEM);
2867: }
2868:
1.18 augustss 2869: Static void
1.25 augustss 2870: ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
1.18 augustss 2871: ehci_soft_qtd_t *sqtdend)
2872: {
2873: ehci_soft_qtd_t *p;
1.25 augustss 2874: int i;
1.18 augustss 2875:
1.29 augustss 2876: DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
2877: sqtd, sqtdend));
2878:
1.25 augustss 2879: for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
1.18 augustss 2880: p = sqtd->nextqtd;
2881: ehci_free_sqtd(sc, sqtd);
2882: }
2883: }
2884:
1.164 uebayasi 2885: Static ehci_soft_itd_t *
1.139 jmcneill 2886: ehci_alloc_itd(ehci_softc_t *sc)
2887: {
2888: struct ehci_soft_itd *itd, *freeitd;
2889: usbd_status err;
1.190 mrg 2890: int i, offs, frindex, previndex;
1.139 jmcneill 2891: usb_dma_t dma;
2892:
1.192 mrg 2893: mutex_enter(&sc->sc_lock);
1.139 jmcneill 2894:
2895: /* Find an itd that wasn't freed this frame or last frame. This can
2896: * discard itds that were freed before frindex wrapped around
2897: * XXX - can this lead to thrashing? Could fix by enabling wrap-around
2898: * interrupt and fiddling with list when that happens */
2899: frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3;
2900: previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize;
2901:
2902: freeitd = NULL;
2903: LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) {
2904: if (itd == NULL)
2905: break;
2906: if (itd->slot != frindex && itd->slot != previndex) {
2907: freeitd = itd;
2908: break;
2909: }
2910: }
2911:
2912: if (freeitd == NULL) {
2913: DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n"));
2914: err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK,
2915: EHCI_PAGE_SIZE, &dma);
2916:
2917: if (err) {
2918: DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err));
1.192 mrg 2919: mutex_exit(&sc->sc_lock);
1.139 jmcneill 2920: return NULL;
2921: }
2922:
2923: for (i = 0; i < EHCI_ITD_CHUNK; i++) {
2924: offs = i * EHCI_ITD_SIZE;
2925: itd = KERNADDR(&dma, offs);
2926: itd->physaddr = DMAADDR(&dma, offs);
1.183 jakllsch 2927: itd->dma = dma;
1.139 jmcneill 2928: itd->offs = offs;
2929: LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
2930: }
2931: freeitd = LIST_FIRST(&sc->sc_freeitds);
2932: }
2933:
2934: itd = freeitd;
2935: LIST_REMOVE(itd, u.free_list);
2936: memset(&itd->itd, 0, sizeof(ehci_itd_t));
2937: usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next),
2938: sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE |
2939: BUS_DMASYNC_PREREAD);
2940:
2941: itd->u.frame_list.next = NULL;
2942: itd->u.frame_list.prev = NULL;
2943: itd->xfer_next = NULL;
2944: itd->slot = 0;
2945:
1.192 mrg 2946: mutex_exit(&sc->sc_lock);
2947:
1.139 jmcneill 2948: return itd;
2949: }
2950:
1.164 uebayasi 2951: Static void
1.139 jmcneill 2952: ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd)
2953: {
2954:
1.190 mrg 2955: KASSERT(mutex_owned(&sc->sc_lock));
2956:
1.150 jmcneill 2957: LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
1.139 jmcneill 2958: }
2959:
1.15 augustss 2960: /****************/
2961:
1.9 augustss 2962: /*
1.10 augustss 2963: * Close a reqular pipe.
2964: * Assumes that there are no pending transactions.
2965: */
1.164 uebayasi 2966: Static void
1.10 augustss 2967: ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2968: {
2969: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1.134 drochner 2970: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.10 augustss 2971: ehci_soft_qh_t *sqh = epipe->sqh;
2972:
1.190 mrg 2973: KASSERT(mutex_owned(&sc->sc_lock));
2974:
1.10 augustss 2975: ehci_rem_qh(sc, sqh, head);
2976: ehci_free_sqh(sc, epipe->sqh);
2977: }
2978:
1.33 augustss 2979: /*
1.10 augustss 2980: * Abort a device request.
2981: * If this routine is called at splusb() it guarantees that the request
2982: * will be removed from the hardware scheduling and that the callback
2983: * for it will be called with USBD_CANCELLED status.
2984: * It's impossible to guarantee that the requested transfer will not
2985: * have happened since the hardware runs concurrently.
2986: * If the transaction has already happened we rely on the ordinary
2987: * interrupt processing to process it.
1.26 augustss 2988: * XXX This is most probably wrong.
1.190 mrg 2989: * XXXMRG this doesn't make sense anymore.
1.10 augustss 2990: */
1.164 uebayasi 2991: Static void
1.10 augustss 2992: ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2993: {
1.26 augustss 2994: #define exfer EXFER(xfer)
1.10 augustss 2995: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
1.134 drochner 2996: ehci_softc_t *sc = epipe->pipe.device->bus->hci_private;
1.26 augustss 2997: ehci_soft_qh_t *sqh = epipe->sqh;
2998: ehci_soft_qtd_t *sqtd;
2999: ehci_physaddr_t cur;
3000: u_int32_t qhstatus;
3001: int hit;
1.96 augustss 3002: int wake;
1.10 augustss 3003:
1.24 augustss 3004: DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
1.10 augustss 3005:
1.190 mrg 3006: KASSERT(mutex_owned(&sc->sc_lock));
3007:
1.17 augustss 3008: if (sc->sc_dying) {
3009: /* If we're dying, just do the software part. */
3010: xfer->status = status; /* make software ignore it */
1.171 dyoung 3011: callout_stop(&xfer->timeout_handle);
1.17 augustss 3012: usb_transfer_complete(xfer);
3013: return;
3014: }
3015:
1.187 mrg 3016: if (cpu_intr_p() || cpu_softintr_p())
1.37 provos 3017: panic("ehci_abort_xfer: not in process context");
1.10 augustss 3018:
1.11 augustss 3019: /*
1.96 augustss 3020: * If an abort is already in progress then just wait for it to
3021: * complete and return.
3022: */
3023: if (xfer->hcflags & UXFER_ABORTING) {
3024: DPRINTFN(2, ("ehci_abort_xfer: already aborting\n"));
3025: #ifdef DIAGNOSTIC
3026: if (status == USBD_TIMEOUT)
3027: printf("ehci_abort_xfer: TIMEOUT while aborting\n");
3028: #endif
3029: /* Override the status which might be USBD_TIMEOUT. */
3030: xfer->status = status;
3031: DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
3032: xfer->hcflags |= UXFER_ABORTWAIT;
3033: while (xfer->hcflags & UXFER_ABORTING)
1.190 mrg 3034: cv_wait(&xfer->hccv, &sc->sc_lock);
1.96 augustss 3035: return;
3036: }
3037: xfer->hcflags |= UXFER_ABORTING;
3038:
3039: /*
1.11 augustss 3040: * Step 1: Make interrupt routine and hardware ignore xfer.
3041: */
3042: xfer->status = status; /* make software ignore it */
1.171 dyoung 3043: callout_stop(&xfer->timeout_handle);
1.138 bouyer 3044:
3045: usb_syncmem(&sqh->dma,
3046: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3047: sizeof(sqh->qh.qh_qtd.qtd_status),
3048: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.26 augustss 3049: qhstatus = sqh->qh.qh_qtd.qtd_status;
3050: sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
1.138 bouyer 3051: usb_syncmem(&sqh->dma,
3052: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3053: sizeof(sqh->qh.qh_qtd.qtd_status),
3054: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 3055: for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
1.138 bouyer 3056: usb_syncmem(&sqtd->dma,
3057: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
3058: sizeof(sqtd->qtd.qtd_status),
3059: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.26 augustss 3060: sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
1.138 bouyer 3061: usb_syncmem(&sqtd->dma,
3062: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
3063: sizeof(sqtd->qtd.qtd_status),
3064: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 3065: if (sqtd == exfer->sqtdend)
3066: break;
3067: }
1.11 augustss 3068:
1.33 augustss 3069: /*
1.11 augustss 3070: * Step 2: Wait until we know hardware has finished any possible
3071: * use of the xfer. Also make sure the soft interrupt routine
3072: * has run.
3073: */
1.26 augustss 3074: ehci_sync_hc(sc);
1.29 augustss 3075: sc->sc_softwake = 1;
3076: usb_schedsoftintr(&sc->sc_bus);
1.190 mrg 3077: cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
1.33 augustss 3078:
3079: /*
1.11 augustss 3080: * Step 3: Remove any vestiges of the xfer from the hardware.
3081: * The complication here is that the hardware may have executed
3082: * beyond the xfer we're trying to abort. So as we're scanning
3083: * the TDs of this xfer we check if the hardware points to
3084: * any of them.
3085: */
1.138 bouyer 3086:
3087: usb_syncmem(&sqh->dma,
3088: sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3089: sizeof(sqh->qh.qh_curqtd),
3090: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.26 augustss 3091: cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
3092: hit = 0;
3093: for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
3094: hit |= cur == sqtd->physaddr;
3095: if (sqtd == exfer->sqtdend)
3096: break;
3097: }
3098: sqtd = sqtd->nextqtd;
3099: /* Zap curqtd register if hardware pointed inside the xfer. */
3100: if (hit && sqtd != NULL) {
3101: DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr));
3102: sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
1.138 bouyer 3103: usb_syncmem(&sqh->dma,
3104: sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3105: sizeof(sqh->qh.qh_curqtd),
3106: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 3107: sqh->qh.qh_qtd.qtd_status = qhstatus;
1.138 bouyer 3108: usb_syncmem(&sqh->dma,
3109: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3110: sizeof(sqh->qh.qh_qtd.qtd_status),
3111: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 3112: } else {
3113: DPRINTFN(1,("ehci_abort_xfer: no hit\n"));
3114: }
1.11 augustss 3115:
3116: /*
1.26 augustss 3117: * Step 4: Execute callback.
1.11 augustss 3118: */
1.18 augustss 3119: #ifdef DIAGNOSTIC
1.26 augustss 3120: exfer->isdone = 1;
1.18 augustss 3121: #endif
1.96 augustss 3122: wake = xfer->hcflags & UXFER_ABORTWAIT;
3123: xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
1.11 augustss 3124: usb_transfer_complete(xfer);
1.190 mrg 3125: if (wake) {
3126: cv_broadcast(&xfer->hccv);
3127: }
1.11 augustss 3128:
1.190 mrg 3129: KASSERT(mutex_owned(&sc->sc_lock));
1.26 augustss 3130: #undef exfer
1.10 augustss 3131: }
3132:
1.164 uebayasi 3133: Static void
1.139 jmcneill 3134: ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status)
3135: {
3136: ehci_isoc_trans_t trans_status;
3137: struct ehci_pipe *epipe;
3138: struct ehci_xfer *exfer;
3139: ehci_softc_t *sc;
3140: struct ehci_soft_itd *itd;
1.190 mrg 3141: int i, wake;
1.139 jmcneill 3142:
3143: epipe = (struct ehci_pipe *) xfer->pipe;
3144: exfer = EXFER(xfer);
3145: sc = epipe->pipe.device->bus->hci_private;
3146:
3147: DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe));
3148:
1.190 mrg 3149: KASSERT(mutex_owned(&sc->sc_lock));
3150:
1.139 jmcneill 3151: if (sc->sc_dying) {
3152: xfer->status = status;
1.171 dyoung 3153: callout_stop(&xfer->timeout_handle);
1.139 jmcneill 3154: usb_transfer_complete(xfer);
3155: return;
3156: }
3157:
3158: if (xfer->hcflags & UXFER_ABORTING) {
3159: DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n"));
3160:
3161: #ifdef DIAGNOSTIC
3162: if (status == USBD_TIMEOUT)
1.190 mrg 3163: printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n");
1.139 jmcneill 3164: #endif
3165:
3166: xfer->status = status;
1.190 mrg 3167: DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n"));
1.139 jmcneill 3168: xfer->hcflags |= UXFER_ABORTWAIT;
3169: while (xfer->hcflags & UXFER_ABORTING)
1.190 mrg 3170: cv_wait(&xfer->hccv, &sc->sc_lock);
3171: goto done;
1.139 jmcneill 3172: }
3173: xfer->hcflags |= UXFER_ABORTING;
3174:
3175: xfer->status = status;
1.171 dyoung 3176: callout_stop(&xfer->timeout_handle);
1.139 jmcneill 3177:
3178: for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
3179: usb_syncmem(&itd->dma,
3180: itd->offs + offsetof(ehci_itd_t, itd_ctl),
3181: sizeof(itd->itd.itd_ctl),
3182: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3183:
3184: for (i = 0; i < 8; i++) {
3185: trans_status = le32toh(itd->itd.itd_ctl[i]);
3186: trans_status &= ~EHCI_ITD_ACTIVE;
3187: itd->itd.itd_ctl[i] = htole32(trans_status);
3188: }
3189:
3190: usb_syncmem(&itd->dma,
3191: itd->offs + offsetof(ehci_itd_t, itd_ctl),
3192: sizeof(itd->itd.itd_ctl),
3193: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3194: }
3195:
3196: sc->sc_softwake = 1;
3197: usb_schedsoftintr(&sc->sc_bus);
1.190 mrg 3198: cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
1.139 jmcneill 3199:
3200: #ifdef DIAGNOSTIC
3201: exfer->isdone = 1;
3202: #endif
3203: wake = xfer->hcflags & UXFER_ABORTWAIT;
3204: xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
3205: usb_transfer_complete(xfer);
1.190 mrg 3206: if (wake) {
3207: cv_broadcast(&xfer->hccv);
3208: }
1.139 jmcneill 3209:
1.190 mrg 3210: done:
3211: KASSERT(mutex_owned(&sc->sc_lock));
1.139 jmcneill 3212: return;
3213: }
3214:
1.164 uebayasi 3215: Static void
1.15 augustss 3216: ehci_timeout(void *addr)
3217: {
3218: struct ehci_xfer *exfer = addr;
1.17 augustss 3219: struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
1.134 drochner 3220: ehci_softc_t *sc = epipe->pipe.device->bus->hci_private;
1.15 augustss 3221:
3222: DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
1.158 sketch 3223: #ifdef EHCI_DEBUG
1.26 augustss 3224: if (ehcidebug > 1)
1.22 augustss 3225: usbd_dump_pipe(exfer->xfer.pipe);
3226: #endif
1.15 augustss 3227:
1.17 augustss 3228: if (sc->sc_dying) {
1.190 mrg 3229: mutex_enter(&sc->sc_lock);
1.17 augustss 3230: ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
1.190 mrg 3231: mutex_exit(&sc->sc_lock);
1.17 augustss 3232: return;
3233: }
3234:
1.15 augustss 3235: /* Execute the abort in a process context. */
1.203 jmcneill 3236: usb_init_task(&exfer->abort_task, ehci_timeout_task, addr,
3237: USB_TASKQ_MPSAFE);
1.114 joerg 3238: usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task,
3239: USB_TASKQ_HC);
1.15 augustss 3240: }
3241:
1.164 uebayasi 3242: Static void
1.15 augustss 3243: ehci_timeout_task(void *addr)
3244: {
3245: usbd_xfer_handle xfer = addr;
1.190 mrg 3246: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.15 augustss 3247:
3248: DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
3249:
1.190 mrg 3250: mutex_enter(&sc->sc_lock);
1.15 augustss 3251: ehci_abort_xfer(xfer, USBD_TIMEOUT);
1.190 mrg 3252: mutex_exit(&sc->sc_lock);
1.15 augustss 3253: }
3254:
1.5 augustss 3255: /************************/
3256:
1.10 augustss 3257: Static usbd_status
3258: ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
3259: {
1.190 mrg 3260: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.10 augustss 3261: usbd_status err;
3262:
3263: /* Insert last in queue. */
1.190 mrg 3264: mutex_enter(&sc->sc_lock);
1.10 augustss 3265: err = usb_insert_transfer(xfer);
1.190 mrg 3266: mutex_exit(&sc->sc_lock);
1.10 augustss 3267: if (err)
3268: return (err);
3269:
3270: /* Pipe isn't running, start first */
3271: return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3272: }
3273:
1.12 augustss 3274: Static usbd_status
3275: ehci_device_ctrl_start(usbd_xfer_handle xfer)
3276: {
1.134 drochner 3277: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.15 augustss 3278: usbd_status err;
3279:
3280: if (sc->sc_dying)
3281: return (USBD_IOERROR);
3282:
3283: #ifdef DIAGNOSTIC
3284: if (!(xfer->rqflags & URQ_REQUEST)) {
3285: /* XXX panic */
3286: printf("ehci_device_ctrl_transfer: not a request\n");
3287: return (USBD_INVAL);
3288: }
3289: #endif
3290:
3291: err = ehci_device_request(xfer);
1.190 mrg 3292: if (err) {
1.15 augustss 3293: return (err);
1.190 mrg 3294: }
1.15 augustss 3295:
3296: if (sc->sc_bus.use_polling)
3297: ehci_waitintr(sc, xfer);
1.190 mrg 3298:
1.15 augustss 3299: return (USBD_IN_PROGRESS);
1.12 augustss 3300: }
1.10 augustss 3301:
1.164 uebayasi 3302: Static void
1.10 augustss 3303: ehci_device_ctrl_done(usbd_xfer_handle xfer)
3304: {
1.18 augustss 3305: struct ehci_xfer *ex = EXFER(xfer);
1.134 drochner 3306: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.138 bouyer 3307: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3308: usb_device_request_t *req = &xfer->request;
3309: int len = UGETW(req->wLength);
3310: int rd = req->bmRequestType & UT_READ;
1.18 augustss 3311:
1.10 augustss 3312: DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
3313:
1.220 skrll 3314: KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1.190 mrg 3315:
1.10 augustss 3316: #ifdef DIAGNOSTIC
3317: if (!(xfer->rqflags & URQ_REQUEST)) {
1.37 provos 3318: panic("ehci_ctrl_done: not a request");
1.10 augustss 3319: }
3320: #endif
1.18 augustss 3321:
1.44 augustss 3322: if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
1.153 jmcneill 3323: ehci_del_intr_list(sc, ex); /* remove from active list */
1.25 augustss 3324: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
1.138 bouyer 3325: usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req,
3326: BUS_DMASYNC_POSTWRITE);
3327: if (len)
3328: usb_syncmem(&xfer->dmabuf, 0, len,
3329: rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.25 augustss 3330: }
1.18 augustss 3331:
1.25 augustss 3332: DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
1.10 augustss 3333: }
3334:
3335: /* Abort a device control request. */
3336: Static void
3337: ehci_device_ctrl_abort(usbd_xfer_handle xfer)
3338: {
3339: DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
3340: ehci_abort_xfer(xfer, USBD_CANCELLED);
3341: }
3342:
3343: /* Close a device control pipe. */
3344: Static void
3345: ehci_device_ctrl_close(usbd_pipe_handle pipe)
3346: {
1.134 drochner 3347: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.10 augustss 3348: /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
3349:
1.190 mrg 3350: KASSERT(mutex_owned(&sc->sc_lock));
3351:
1.10 augustss 3352: DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
1.190 mrg 3353:
1.11 augustss 3354: ehci_close_pipe(pipe, sc->sc_async_head);
1.15 augustss 3355: }
3356:
1.164 uebayasi 3357: Static usbd_status
1.15 augustss 3358: ehci_device_request(usbd_xfer_handle xfer)
3359: {
1.18 augustss 3360: #define exfer EXFER(xfer)
1.15 augustss 3361: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3362: usb_device_request_t *req = &xfer->request;
3363: usbd_device_handle dev = epipe->pipe.device;
1.134 drochner 3364: ehci_softc_t *sc = dev->bus->hci_private;
1.15 augustss 3365: ehci_soft_qtd_t *setup, *stat, *next;
3366: ehci_soft_qh_t *sqh;
3367: int isread;
3368: int len;
3369: usbd_status err;
3370:
3371: isread = req->bmRequestType & UT_READ;
3372: len = UGETW(req->wLength);
3373:
1.72 augustss 3374: DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, "
1.15 augustss 3375: "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
3376: req->bmRequestType, req->bRequest, UGETW(req->wValue),
1.225 skrll 3377: UGETW(req->wIndex), len, dev->address,
1.15 augustss 3378: epipe->pipe.endpoint->edesc->bEndpointAddress));
3379:
3380: setup = ehci_alloc_sqtd(sc);
3381: if (setup == NULL) {
3382: err = USBD_NOMEM;
3383: goto bad1;
3384: }
3385: stat = ehci_alloc_sqtd(sc);
3386: if (stat == NULL) {
3387: err = USBD_NOMEM;
3388: goto bad2;
3389: }
3390:
1.190 mrg 3391: mutex_enter(&sc->sc_lock);
3392:
1.15 augustss 3393: sqh = epipe->sqh;
3394:
1.225 skrll 3395: KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->address,
3396: "address QH %d pipe %d\n",
3397: EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->address);
3398: KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) ==
3399: UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize),
3400: "MPS QH %d pipe %d\n",
3401: EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)),
3402: UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize));
1.15 augustss 3403:
3404: /* Set up data transaction */
3405: if (len != 0) {
3406: ehci_soft_qtd_t *end;
3407:
1.55 mycroft 3408: /* Start toggle at 1. */
3409: epipe->nexttoggle = 1;
1.25 augustss 3410: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
1.15 augustss 3411: &next, &end);
3412: if (err)
3413: goto bad3;
1.83 augustss 3414: end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
1.15 augustss 3415: end->nextqtd = stat;
1.214 skrll 3416: end->qtd.qtd_next = end->qtd.qtd_altnext =
3417: htole32(stat->physaddr);
1.138 bouyer 3418: usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
3419: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 3420: } else {
3421: next = stat;
3422: }
3423:
1.30 augustss 3424: memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req);
1.138 bouyer 3425: usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
1.15 augustss 3426:
1.55 mycroft 3427: /* Clear toggle */
1.15 augustss 3428: setup->qtd.qtd_status = htole32(
1.26 augustss 3429: EHCI_QTD_ACTIVE |
1.15 augustss 3430: EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
3431: EHCI_QTD_SET_CERR(3) |
1.64 mycroft 3432: EHCI_QTD_SET_TOGGLE(0) |
1.15 augustss 3433: EHCI_QTD_SET_BYTES(sizeof *req)
3434: );
1.31 augustss 3435: setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
1.48 mycroft 3436: setup->qtd.qtd_buffer_hi[0] = 0;
1.15 augustss 3437: setup->nextqtd = next;
3438: setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
3439: setup->xfer = xfer;
1.18 augustss 3440: setup->len = sizeof *req;
1.138 bouyer 3441: usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd),
3442: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 3443:
3444: stat->qtd.qtd_status = htole32(
1.26 augustss 3445: EHCI_QTD_ACTIVE |
1.15 augustss 3446: EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3447: EHCI_QTD_SET_CERR(3) |
1.64 mycroft 3448: EHCI_QTD_SET_TOGGLE(1) |
1.15 augustss 3449: EHCI_QTD_IOC
3450: );
3451: stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
1.48 mycroft 3452: stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
1.15 augustss 3453: stat->nextqtd = NULL;
3454: stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
3455: stat->xfer = xfer;
1.18 augustss 3456: stat->len = 0;
1.138 bouyer 3457: usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd),
3458: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 3459:
3460: #ifdef EHCI_DEBUG
1.23 augustss 3461: if (ehcidebug > 5) {
1.15 augustss 3462: DPRINTF(("ehci_device_request:\n"));
3463: ehci_dump_sqh(sqh);
3464: ehci_dump_sqtds(setup);
3465: }
3466: #endif
3467:
1.18 augustss 3468: exfer->sqtdstart = setup;
3469: exfer->sqtdend = stat;
3470: #ifdef DIAGNOSTIC
3471: if (!exfer->isdone) {
3472: printf("ehci_device_request: not done, exfer=%p\n", exfer);
3473: }
3474: exfer->isdone = 0;
3475: #endif
3476:
1.15 augustss 3477: /* Insert qTD in QH list. */
1.138 bouyer 3478: ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */
1.15 augustss 3479: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.190 mrg 3480: callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
3481: ehci_timeout, xfer);
1.15 augustss 3482: }
1.18 augustss 3483: ehci_add_intr_list(sc, exfer);
3484: xfer->status = USBD_IN_PROGRESS;
1.190 mrg 3485: mutex_exit(&sc->sc_lock);
1.15 augustss 3486:
1.17 augustss 3487: #ifdef EHCI_DEBUG
1.15 augustss 3488: if (ehcidebug > 10) {
3489: DPRINTF(("ehci_device_request: status=%x\n",
3490: EOREAD4(sc, EHCI_USBSTS)));
1.23 augustss 3491: delay(10000);
1.18 augustss 3492: ehci_dump_regs(sc);
1.15 augustss 3493: ehci_dump_sqh(sc->sc_async_head);
3494: ehci_dump_sqh(sqh);
3495: ehci_dump_sqtds(setup);
3496: }
3497: #endif
3498:
3499: return (USBD_NORMAL_COMPLETION);
3500:
3501: bad3:
1.190 mrg 3502: mutex_exit(&sc->sc_lock);
1.15 augustss 3503: ehci_free_sqtd(sc, stat);
3504: bad2:
3505: ehci_free_sqtd(sc, setup);
3506: bad1:
1.25 augustss 3507: DPRINTFN(-1,("ehci_device_request: no memory\n"));
1.190 mrg 3508: mutex_enter(&sc->sc_lock);
1.25 augustss 3509: xfer->status = err;
3510: usb_transfer_complete(xfer);
1.190 mrg 3511: mutex_exit(&sc->sc_lock);
1.15 augustss 3512: return (err);
1.18 augustss 3513: #undef exfer
1.10 augustss 3514: }
3515:
1.108 xtraeme 3516: /*
3517: * Some EHCI chips from VIA seem to trigger interrupts before writing back the
3518: * qTD status, or miss signalling occasionally under heavy load. If the host
3519: * machine is too fast, we we can miss transaction completion - when we scan
3520: * the active list the transaction still seems to be active. This generally
3521: * exhibits itself as a umass stall that never recovers.
3522: *
3523: * We work around this behaviour by setting up this callback after any softintr
3524: * that completes with transactions still pending, giving us another chance to
3525: * check for completion after the writeback has taken place.
3526: */
1.164 uebayasi 3527: Static void
1.108 xtraeme 3528: ehci_intrlist_timeout(void *arg)
3529: {
3530: ehci_softc_t *sc = arg;
3531:
3532: DPRINTF(("ehci_intrlist_timeout\n"));
3533: usb_schedsoftintr(&sc->sc_bus);
3534: }
3535:
1.10 augustss 3536: /************************/
1.5 augustss 3537:
1.19 augustss 3538: Static usbd_status
3539: ehci_device_bulk_transfer(usbd_xfer_handle xfer)
3540: {
1.190 mrg 3541: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.19 augustss 3542: usbd_status err;
3543:
3544: /* Insert last in queue. */
1.190 mrg 3545: mutex_enter(&sc->sc_lock);
1.19 augustss 3546: err = usb_insert_transfer(xfer);
1.190 mrg 3547: mutex_exit(&sc->sc_lock);
1.19 augustss 3548: if (err)
3549: return (err);
3550:
3551: /* Pipe isn't running, start first */
3552: return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3553: }
3554:
1.164 uebayasi 3555: Static usbd_status
1.19 augustss 3556: ehci_device_bulk_start(usbd_xfer_handle xfer)
3557: {
3558: #define exfer EXFER(xfer)
3559: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3560: usbd_device_handle dev = epipe->pipe.device;
1.134 drochner 3561: ehci_softc_t *sc = dev->bus->hci_private;
1.19 augustss 3562: ehci_soft_qtd_t *data, *dataend;
3563: ehci_soft_qh_t *sqh;
3564: usbd_status err;
3565: int len, isread, endpt;
3566:
1.72 augustss 3567: DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n",
1.19 augustss 3568: xfer, xfer->length, xfer->flags));
3569:
3570: if (sc->sc_dying)
3571: return (USBD_IOERROR);
3572:
3573: #ifdef DIAGNOSTIC
3574: if (xfer->rqflags & URQ_REQUEST)
1.72 augustss 3575: panic("ehci_device_bulk_start: a request");
1.19 augustss 3576: #endif
3577:
1.190 mrg 3578: mutex_enter(&sc->sc_lock);
3579:
1.19 augustss 3580: len = xfer->length;
3581: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3582: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3583: sqh = epipe->sqh;
3584:
3585: epipe->u.bulk.length = len;
3586:
1.25 augustss 3587: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
1.19 augustss 3588: &dataend);
1.25 augustss 3589: if (err) {
3590: DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n"));
3591: xfer->status = err;
3592: usb_transfer_complete(xfer);
1.190 mrg 3593: mutex_exit(&sc->sc_lock);
1.19 augustss 3594: return (err);
1.25 augustss 3595: }
1.19 augustss 3596:
3597: #ifdef EHCI_DEBUG
1.23 augustss 3598: if (ehcidebug > 5) {
1.72 augustss 3599: DPRINTF(("ehci_device_bulk_start: data(1)\n"));
1.23 augustss 3600: ehci_dump_sqh(sqh);
1.19 augustss 3601: ehci_dump_sqtds(data);
3602: }
3603: #endif
3604:
3605: /* Set up interrupt info. */
3606: exfer->sqtdstart = data;
3607: exfer->sqtdend = dataend;
3608: #ifdef DIAGNOSTIC
3609: if (!exfer->isdone) {
1.72 augustss 3610: printf("ehci_device_bulk_start: not done, ex=%p\n", exfer);
1.19 augustss 3611: }
3612: exfer->isdone = 0;
3613: #endif
3614:
1.138 bouyer 3615: ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
1.19 augustss 3616: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.190 mrg 3617: callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
3618: ehci_timeout, xfer);
1.19 augustss 3619: }
3620: ehci_add_intr_list(sc, exfer);
3621: xfer->status = USBD_IN_PROGRESS;
1.190 mrg 3622: mutex_exit(&sc->sc_lock);
1.19 augustss 3623:
3624: #ifdef EHCI_DEBUG
3625: if (ehcidebug > 10) {
1.72 augustss 3626: DPRINTF(("ehci_device_bulk_start: data(2)\n"));
1.23 augustss 3627: delay(10000);
1.72 augustss 3628: DPRINTF(("ehci_device_bulk_start: data(3)\n"));
1.23 augustss 3629: ehci_dump_regs(sc);
1.29 augustss 3630: #if 0
3631: printf("async_head:\n");
1.23 augustss 3632: ehci_dump_sqh(sc->sc_async_head);
1.29 augustss 3633: #endif
3634: printf("sqh:\n");
1.23 augustss 3635: ehci_dump_sqh(sqh);
1.19 augustss 3636: ehci_dump_sqtds(data);
3637: }
3638: #endif
3639:
3640: if (sc->sc_bus.use_polling)
3641: ehci_waitintr(sc, xfer);
3642:
3643: return (USBD_IN_PROGRESS);
3644: #undef exfer
3645: }
3646:
3647: Static void
3648: ehci_device_bulk_abort(usbd_xfer_handle xfer)
3649: {
3650: DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
3651: ehci_abort_xfer(xfer, USBD_CANCELLED);
3652: }
3653:
1.33 augustss 3654: /*
1.19 augustss 3655: * Close a device bulk pipe.
3656: */
3657: Static void
3658: ehci_device_bulk_close(usbd_pipe_handle pipe)
3659: {
1.134 drochner 3660: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.175 drochner 3661: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1.19 augustss 3662:
1.190 mrg 3663: KASSERT(mutex_owned(&sc->sc_lock));
3664:
1.19 augustss 3665: DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
1.175 drochner 3666: pipe->endpoint->datatoggle = epipe->nexttoggle;
1.19 augustss 3667: ehci_close_pipe(pipe, sc->sc_async_head);
3668: }
3669:
1.164 uebayasi 3670: Static void
1.19 augustss 3671: ehci_device_bulk_done(usbd_xfer_handle xfer)
3672: {
3673: struct ehci_xfer *ex = EXFER(xfer);
1.134 drochner 3674: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.138 bouyer 3675: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3676: int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3677: int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
1.19 augustss 3678:
1.33 augustss 3679: DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
1.19 augustss 3680: xfer, xfer->actlen));
3681:
1.190 mrg 3682: KASSERT(mutex_owned(&sc->sc_lock));
3683:
1.44 augustss 3684: if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
1.153 jmcneill 3685: ehci_del_intr_list(sc, ex); /* remove from active list */
1.44 augustss 3686: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
1.138 bouyer 3687: usb_syncmem(&xfer->dmabuf, 0, xfer->length,
3688: rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.25 augustss 3689: }
1.19 augustss 3690:
3691: DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
3692: }
1.5 augustss 3693:
1.10 augustss 3694: /************************/
3695:
1.78 augustss 3696: Static usbd_status
3697: ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
3698: {
3699: struct ehci_soft_islot *isp;
3700: int islot, lev;
3701:
3702: /* Find a poll rate that is large enough. */
3703: for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
3704: if (EHCI_ILEV_IVAL(lev) <= ival)
3705: break;
3706:
3707: /* Pick an interrupt slot at the right level. */
3708: /* XXX could do better than picking at random */
3709: sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize;
3710: islot = EHCI_IQHIDX(lev, sc->sc_rand);
3711:
3712: sqh->islot = islot;
3713: isp = &sc->sc_islots[islot];
1.190 mrg 3714: mutex_enter(&sc->sc_lock);
3715: ehci_add_qh(sc, sqh, isp->sqh);
3716: mutex_exit(&sc->sc_lock);
1.78 augustss 3717:
3718: return (USBD_NORMAL_COMPLETION);
3719: }
3720:
3721: Static usbd_status
3722: ehci_device_intr_transfer(usbd_xfer_handle xfer)
3723: {
1.190 mrg 3724: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.78 augustss 3725: usbd_status err;
3726:
3727: /* Insert last in queue. */
1.190 mrg 3728: mutex_enter(&sc->sc_lock);
1.78 augustss 3729: err = usb_insert_transfer(xfer);
1.190 mrg 3730: mutex_exit(&sc->sc_lock);
1.78 augustss 3731: if (err)
3732: return (err);
3733:
3734: /*
3735: * Pipe isn't running (otherwise err would be USBD_INPROG),
3736: * so start it first.
3737: */
3738: return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3739: }
3740:
3741: Static usbd_status
3742: ehci_device_intr_start(usbd_xfer_handle xfer)
3743: {
3744: #define exfer EXFER(xfer)
3745: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3746: usbd_device_handle dev = xfer->pipe->device;
1.134 drochner 3747: ehci_softc_t *sc = dev->bus->hci_private;
1.78 augustss 3748: ehci_soft_qtd_t *data, *dataend;
3749: ehci_soft_qh_t *sqh;
3750: usbd_status err;
3751: int len, isread, endpt;
3752:
3753: DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n",
3754: xfer, xfer->length, xfer->flags));
3755:
3756: if (sc->sc_dying)
3757: return (USBD_IOERROR);
3758:
3759: #ifdef DIAGNOSTIC
3760: if (xfer->rqflags & URQ_REQUEST)
3761: panic("ehci_device_intr_start: a request");
3762: #endif
3763:
1.190 mrg 3764: mutex_enter(&sc->sc_lock);
3765:
1.78 augustss 3766: len = xfer->length;
3767: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3768: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3769: sqh = epipe->sqh;
3770:
3771: epipe->u.intr.length = len;
3772:
3773: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
3774: &dataend);
3775: if (err) {
3776: DPRINTFN(-1, ("ehci_device_intr_start: no memory\n"));
3777: xfer->status = err;
3778: usb_transfer_complete(xfer);
1.190 mrg 3779: mutex_exit(&sc->sc_lock);
1.78 augustss 3780: return (err);
3781: }
3782:
3783: #ifdef EHCI_DEBUG
3784: if (ehcidebug > 5) {
3785: DPRINTF(("ehci_device_intr_start: data(1)\n"));
3786: ehci_dump_sqh(sqh);
3787: ehci_dump_sqtds(data);
3788: }
3789: #endif
3790:
3791: /* Set up interrupt info. */
3792: exfer->sqtdstart = data;
3793: exfer->sqtdend = dataend;
3794: #ifdef DIAGNOSTIC
3795: if (!exfer->isdone) {
3796: printf("ehci_device_intr_start: not done, ex=%p\n", exfer);
3797: }
3798: exfer->isdone = 0;
3799: #endif
3800:
1.138 bouyer 3801: ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
1.78 augustss 3802: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.190 mrg 3803: callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
3804: ehci_timeout, xfer);
1.78 augustss 3805: }
3806: ehci_add_intr_list(sc, exfer);
3807: xfer->status = USBD_IN_PROGRESS;
1.190 mrg 3808: mutex_exit(&sc->sc_lock);
1.78 augustss 3809:
3810: #ifdef EHCI_DEBUG
3811: if (ehcidebug > 10) {
3812: DPRINTF(("ehci_device_intr_start: data(2)\n"));
3813: delay(10000);
3814: DPRINTF(("ehci_device_intr_start: data(3)\n"));
3815: ehci_dump_regs(sc);
3816: printf("sqh:\n");
3817: ehci_dump_sqh(sqh);
3818: ehci_dump_sqtds(data);
3819: }
3820: #endif
3821:
3822: if (sc->sc_bus.use_polling)
3823: ehci_waitintr(sc, xfer);
3824:
3825: return (USBD_IN_PROGRESS);
3826: #undef exfer
3827: }
3828:
3829: Static void
3830: ehci_device_intr_abort(usbd_xfer_handle xfer)
3831: {
3832: DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer));
1.227 skrll 3833: KASSERT(xfer->pipe->intrxfer == xfer);
3834:
1.139 jmcneill 3835: /*
3836: * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance
1.180 wiz 3837: * async doorbell. That's dependent on the async list, wheras
1.139 jmcneill 3838: * intr xfers are periodic, should not use this?
3839: */
1.78 augustss 3840: ehci_abort_xfer(xfer, USBD_CANCELLED);
3841: }
3842:
3843: Static void
3844: ehci_device_intr_close(usbd_pipe_handle pipe)
3845: {
1.134 drochner 3846: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.78 augustss 3847: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3848: struct ehci_soft_islot *isp;
3849:
1.190 mrg 3850: KASSERT(mutex_owned(&sc->sc_lock));
3851:
1.78 augustss 3852: isp = &sc->sc_islots[epipe->sqh->islot];
3853: ehci_close_pipe(pipe, isp->sqh);
3854: }
3855:
3856: Static void
3857: ehci_device_intr_done(usbd_xfer_handle xfer)
3858: {
3859: #define exfer EXFER(xfer)
3860: struct ehci_xfer *ex = EXFER(xfer);
1.134 drochner 3861: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.78 augustss 3862: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3863: ehci_soft_qtd_t *data, *dataend;
3864: ehci_soft_qh_t *sqh;
3865: usbd_status err;
1.190 mrg 3866: int len, isread, endpt;
1.78 augustss 3867:
3868: DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n",
3869: xfer, xfer->actlen));
3870:
1.206 skrll 3871: KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1.190 mrg 3872:
1.78 augustss 3873: if (xfer->pipe->repeat) {
3874: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3875:
3876: len = epipe->u.intr.length;
3877: xfer->length = len;
3878: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3879: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
1.138 bouyer 3880: usb_syncmem(&xfer->dmabuf, 0, len,
3881: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.78 augustss 3882: sqh = epipe->sqh;
3883:
3884: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3885: &data, &dataend);
3886: if (err) {
3887: DPRINTFN(-1, ("ehci_device_intr_done: no memory\n"));
3888: xfer->status = err;
3889: return;
3890: }
3891:
3892: /* Set up interrupt info. */
3893: exfer->sqtdstart = data;
3894: exfer->sqtdend = dataend;
3895: #ifdef DIAGNOSTIC
3896: if (!exfer->isdone) {
3897: printf("ehci_device_intr_done: not done, ex=%p\n",
3898: exfer);
3899: }
3900: exfer->isdone = 0;
3901: #endif
3902:
1.138 bouyer 3903: ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
1.78 augustss 3904: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.190 mrg 3905: callout_reset(&xfer->timeout_handle,
3906: mstohz(xfer->timeout), ehci_timeout, xfer);
1.78 augustss 3907: }
3908:
3909: xfer->status = USBD_IN_PROGRESS;
3910: } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
1.153 jmcneill 3911: ehci_del_intr_list(sc, ex); /* remove from active list */
1.78 augustss 3912: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
1.138 bouyer 3913: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3914: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3915: usb_syncmem(&xfer->dmabuf, 0, xfer->length,
3916: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.78 augustss 3917: }
3918: #undef exfer
3919: }
1.10 augustss 3920:
3921: /************************/
1.5 augustss 3922:
1.113 christos 3923: Static usbd_status
1.115 christos 3924: ehci_device_isoc_transfer(usbd_xfer_handle xfer)
1.113 christos 3925: {
1.190 mrg 3926: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.139 jmcneill 3927: usbd_status err;
3928:
1.190 mrg 3929: mutex_enter(&sc->sc_lock);
1.139 jmcneill 3930: err = usb_insert_transfer(xfer);
1.190 mrg 3931: mutex_exit(&sc->sc_lock);
1.139 jmcneill 3932: if (err && err != USBD_IN_PROGRESS)
3933: return err;
3934:
3935: return ehci_device_isoc_start(xfer);
1.113 christos 3936: }
1.139 jmcneill 3937:
1.113 christos 3938: Static usbd_status
1.115 christos 3939: ehci_device_isoc_start(usbd_xfer_handle xfer)
1.113 christos 3940: {
1.139 jmcneill 3941: struct ehci_pipe *epipe;
3942: ehci_softc_t *sc;
3943: struct ehci_xfer *exfer;
3944: ehci_soft_itd_t *itd, *prev, *start, *stop;
3945: usb_dma_t *dma_buf;
1.142 drochner 3946: int i, j, k, frames, uframes, ufrperframe;
1.190 mrg 3947: int trans_count, offs, total_length;
1.139 jmcneill 3948: int frindex;
3949:
3950: start = NULL;
3951: prev = NULL;
3952: itd = NULL;
3953: trans_count = 0;
3954: total_length = 0;
3955: exfer = (struct ehci_xfer *) xfer;
3956: sc = xfer->pipe->device->bus->hci_private;
3957: epipe = (struct ehci_pipe *)xfer->pipe;
3958:
3959: /*
3960: * To allow continuous transfers, above we start all transfers
3961: * immediately. However, we're still going to get usbd_start_next call
3962: * this when another xfer completes. So, check if this is already
3963: * in progress or not
3964: */
3965:
3966: if (exfer->itdstart != NULL)
3967: return USBD_IN_PROGRESS;
3968:
3969: DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n",
3970: xfer, xfer->length, xfer->flags));
3971:
3972: if (sc->sc_dying)
3973: return USBD_IOERROR;
3974:
3975: /*
3976: * To avoid complication, don't allow a request right now that'll span
3977: * the entire frame table. To within 4 frames, to allow some leeway
3978: * on either side of where the hc currently is.
3979: */
3980: if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) *
3981: xfer->nframes >= (sc->sc_flsize - 4) * 8) {
3982: printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n");
3983: return USBD_INVAL;
3984: }
3985:
3986: #ifdef DIAGNOSTIC
3987: if (xfer->rqflags & URQ_REQUEST)
3988: panic("ehci_device_isoc_start: request\n");
3989:
3990: if (!exfer->isdone)
3991: printf("ehci_device_isoc_start: not done, ex = %p\n", exfer);
3992: exfer->isdone = 0;
3993: #endif
3994:
3995: /*
3996: * Step 1: Allocate and initialize itds, how many do we need?
3997: * One per transfer if interval >= 8 microframes, fewer if we use
3998: * multiple microframes per frame.
3999: */
4000:
4001: i = epipe->pipe.endpoint->edesc->bInterval;
4002: if (i > 16 || i == 0) {
4003: /* Spec page 271 says intervals > 16 are invalid */
4004: DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i));
4005: return USBD_INVAL;
4006: }
4007:
1.168 jakllsch 4008: ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1)));
1.142 drochner 4009: frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe;
1.168 jakllsch 4010: uframes = USB_UFRAMES_PER_FRAME / ufrperframe;
1.142 drochner 4011:
1.139 jmcneill 4012: if (frames == 0) {
4013: DPRINTF(("ehci_device_isoc_start: frames == 0\n"));
4014: return USBD_INVAL;
4015: }
4016:
4017: dma_buf = &xfer->dmabuf;
4018: offs = 0;
4019:
4020: for (i = 0; i < frames; i++) {
4021: int froffs = offs;
4022: itd = ehci_alloc_itd(sc);
4023:
4024: if (prev != NULL) {
4025: prev->itd.itd_next =
4026: htole32(itd->physaddr | EHCI_LINK_ITD);
4027: usb_syncmem(&itd->dma,
4028: itd->offs + offsetof(ehci_itd_t, itd_next),
4029: sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE);
4030:
4031: prev->xfer_next = itd;
1.183 jakllsch 4032: } else {
1.139 jmcneill 4033: start = itd;
4034: }
4035:
4036: /*
4037: * Step 1.5, initialize uframes
4038: */
1.168 jakllsch 4039: for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) {
1.139 jmcneill 4040: /* Calculate which page in the list this starts in */
4041: int addr = DMAADDR(dma_buf, froffs);
4042: addr = EHCI_PAGE_OFFSET(addr);
4043: addr += (offs - froffs);
4044: addr = EHCI_PAGE(addr);
4045: addr /= EHCI_PAGE_SIZE;
4046:
4047: /* This gets the initial offset into the first page,
4048: * looks how far further along the current uframe
4049: * offset is. Works out how many pages that is.
4050: */
4051:
4052: itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE |
1.195 christos 4053: EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) |
1.139 jmcneill 4054: EHCI_ITD_SET_PG(addr) |
4055: EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs))));
4056:
4057: total_length += xfer->frlengths[trans_count];
4058: offs += xfer->frlengths[trans_count];
4059: trans_count++;
4060:
4061: if (trans_count >= xfer->nframes) { /*Set IOC*/
4062: itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC);
1.145 drochner 4063: break;
1.139 jmcneill 4064: }
1.195 christos 4065: }
1.139 jmcneill 4066:
4067: /* Step 1.75, set buffer pointers. To simplify matters, all
4068: * pointers are filled out for the next 7 hardware pages in
4069: * the dma block, so no need to worry what pages to cover
4070: * and what to not.
4071: */
4072:
1.168 jakllsch 4073: for (j = 0; j < EHCI_ITD_NBUFFERS; j++) {
1.139 jmcneill 4074: /*
4075: * Don't try to lookup a page that's past the end
4076: * of buffer
4077: */
4078: int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j));
4079: if (page_offs >= dma_buf->block->size)
4080: break;
4081:
1.181 mrg 4082: unsigned long long page = DMAADDR(dma_buf, page_offs);
1.139 jmcneill 4083: page = EHCI_PAGE(page);
4084: itd->itd.itd_bufr[j] =
1.155 jmorse 4085: htole32(EHCI_ITD_SET_BPTR(page));
4086: itd->itd.itd_bufr_hi[j] =
4087: htole32(page >> 32);
1.139 jmcneill 4088: }
4089:
4090: /*
4091: * Other special values
4092: */
4093:
4094: k = epipe->pipe.endpoint->edesc->bEndpointAddress;
4095: itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) |
4096: EHCI_ITD_SET_DADDR(epipe->pipe.device->address));
4097:
4098: k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress))
4099: ? 1 : 0;
1.149 jmcneill 4100: j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
1.139 jmcneill 4101: itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) |
4102: EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j)));
4103:
4104: /* FIXME: handle invalid trans */
1.195 christos 4105: itd->itd.itd_bufr[2] |=
1.139 jmcneill 4106: htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1));
4107:
4108: usb_syncmem(&itd->dma,
4109: itd->offs + offsetof(ehci_itd_t, itd_next),
4110: sizeof(ehci_itd_t),
4111: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4112:
4113: prev = itd;
4114: } /* End of frame */
4115:
4116: stop = itd;
4117: stop->xfer_next = NULL;
4118: exfer->isoc_len = total_length;
4119:
1.155 jmorse 4120: usb_syncmem(&exfer->xfer.dmabuf, 0, total_length,
4121: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4122:
1.139 jmcneill 4123: /*
4124: * Part 2: Transfer descriptors have now been set up, now they must
4125: * be scheduled into the period frame list. Erk. Not wanting to
4126: * complicate matters, transfer is denied if the transfer spans
4127: * more than the period frame list.
4128: */
4129:
1.190 mrg 4130: mutex_enter(&sc->sc_lock);
1.139 jmcneill 4131:
4132: /* Start inserting frames */
4133: if (epipe->u.isoc.cur_xfers > 0) {
4134: frindex = epipe->u.isoc.next_frame;
4135: } else {
4136: frindex = EOREAD4(sc, EHCI_FRINDEX);
4137: frindex = frindex >> 3; /* Erase microframe index */
4138: frindex += 2;
4139: }
4140:
4141: if (frindex >= sc->sc_flsize)
4142: frindex &= (sc->sc_flsize - 1);
4143:
1.168 jakllsch 4144: /* What's the frame interval? */
4145: i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1));
4146: if (i / USB_UFRAMES_PER_FRAME == 0)
1.139 jmcneill 4147: i = 1;
4148: else
1.168 jakllsch 4149: i /= USB_UFRAMES_PER_FRAME;
1.139 jmcneill 4150:
4151: itd = start;
4152: for (j = 0; j < frames; j++) {
4153: if (itd == NULL)
4154: panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n");
4155:
4156: itd->itd.itd_next = sc->sc_flist[frindex];
4157: if (itd->itd.itd_next == 0)
4158: /* FIXME: frindex table gets initialized to NULL
4159: * or EHCI_NULL? */
1.162 uebayasi 4160: itd->itd.itd_next = EHCI_NULL;
1.139 jmcneill 4161:
4162: usb_syncmem(&itd->dma,
4163: itd->offs + offsetof(ehci_itd_t, itd_next),
4164: sizeof(itd->itd.itd_next),
4165: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4166:
4167: sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr);
4168:
4169: usb_syncmem(&sc->sc_fldma,
4170: sizeof(ehci_link_t) * frindex,
4171: sizeof(ehci_link_t),
4172: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4173:
4174: itd->u.frame_list.next = sc->sc_softitds[frindex];
4175: sc->sc_softitds[frindex] = itd;
4176: if (itd->u.frame_list.next != NULL)
4177: itd->u.frame_list.next->u.frame_list.prev = itd;
4178: itd->slot = frindex;
4179: itd->u.frame_list.prev = NULL;
4180:
4181: frindex += i;
4182: if (frindex >= sc->sc_flsize)
4183: frindex -= sc->sc_flsize;
4184:
4185: itd = itd->xfer_next;
4186: }
4187:
4188: epipe->u.isoc.cur_xfers++;
4189: epipe->u.isoc.next_frame = frindex;
4190:
4191: exfer->itdstart = start;
4192: exfer->itdend = stop;
4193: exfer->sqtdstart = NULL;
1.226 skrll 4194: exfer->sqtdend = NULL;
1.139 jmcneill 4195:
4196: ehci_add_intr_list(sc, exfer);
4197: xfer->status = USBD_IN_PROGRESS;
4198: xfer->done = 0;
1.190 mrg 4199: mutex_exit(&sc->sc_lock);
1.139 jmcneill 4200:
4201: if (sc->sc_bus.use_polling) {
4202: printf("Starting ehci isoc xfer with polling. Bad idea?\n");
4203: ehci_waitintr(sc, xfer);
4204: }
4205:
4206: return USBD_IN_PROGRESS;
1.113 christos 4207: }
1.139 jmcneill 4208:
1.113 christos 4209: Static void
1.115 christos 4210: ehci_device_isoc_abort(usbd_xfer_handle xfer)
1.113 christos 4211: {
1.139 jmcneill 4212: DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer));
4213: ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
1.113 christos 4214: }
1.139 jmcneill 4215:
1.113 christos 4216: Static void
1.115 christos 4217: ehci_device_isoc_close(usbd_pipe_handle pipe)
1.113 christos 4218: {
1.146 jmcneill 4219: DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n"));
1.113 christos 4220: }
1.139 jmcneill 4221:
1.113 christos 4222: Static void
1.115 christos 4223: ehci_device_isoc_done(usbd_xfer_handle xfer)
1.113 christos 4224: {
1.139 jmcneill 4225: struct ehci_xfer *exfer;
4226: ehci_softc_t *sc;
4227: struct ehci_pipe *epipe;
4228:
4229: exfer = EXFER(xfer);
4230: sc = xfer->pipe->device->bus->hci_private;
4231: epipe = (struct ehci_pipe *) xfer->pipe;
4232:
1.190 mrg 4233: KASSERT(mutex_owned(&sc->sc_lock));
4234:
1.139 jmcneill 4235: epipe->u.isoc.cur_xfers--;
4236: if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) {
1.153 jmcneill 4237: ehci_del_intr_list(sc, exfer);
1.139 jmcneill 4238: ehci_rem_free_itd_chain(sc, exfer);
4239: }
4240:
4241: usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE |
4242: BUS_DMASYNC_POSTREAD);
4243:
1.113 christos 4244: }
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