Annotation of src/sys/dev/usb/ehci.c, Revision 1.183.2.1
1.183.2.1! riz 1: /* $NetBSD: ehci.c,v 1.183 2011/12/23 00:51:43 jakllsch Exp $ */
1.1 augustss 2:
3: /*
1.147 hubertf 4: * Copyright (c) 2004-2008 The NetBSD Foundation, Inc.
1.1 augustss 5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
1.147 hubertf 8: * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and
9: * Jeremy Morse (jeremy.morse@gmail.com).
1.1 augustss 10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30: * POSSIBILITY OF SUCH DAMAGE.
31: */
32:
33: /*
1.3 augustss 34: * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
1.1 augustss 35: *
1.35 enami 36: * The EHCI 1.0 spec can be found at
1.160 uebayasi 37: * http://www.intel.com/technology/usb/spec.htm
1.7 augustss 38: * and the USB 2.0 spec at
1.160 uebayasi 39: * http://www.usb.org/developers/docs/
1.1 augustss 40: *
41: */
1.4 lukem 42:
1.52 jdolecek 43: /*
44: * TODO:
45: * 1) hold off explorations by companion controllers until ehci has started.
46: *
1.148 cegger 47: * 2) The hub driver needs to handle and schedule the transaction translator,
1.100 augustss 48: * to assign place in frame where different devices get to go. See chapter
1.91 perry 49: * on hubs in USB 2.0 for details.
1.52 jdolecek 50: *
1.164 uebayasi 51: * 3) Command failures are not recovered correctly.
1.148 cegger 52: */
1.52 jdolecek 53:
1.4 lukem 54: #include <sys/cdefs.h>
1.183.2.1! riz 55: __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.183 2011/12/23 00:51:43 jakllsch Exp $");
1.47 augustss 56:
57: #include "ohci.h"
58: #include "uhci.h"
1.178 matt 59: #include "opt_usb.h"
1.1 augustss 60:
61: #include <sys/param.h>
62: #include <sys/systm.h>
63: #include <sys/kernel.h>
64: #include <sys/malloc.h>
65: #include <sys/device.h>
66: #include <sys/select.h>
67: #include <sys/proc.h>
68: #include <sys/queue.h>
1.126 ad 69: #include <sys/mutex.h>
70: #include <sys/bus.h>
1.1 augustss 71:
72: #include <machine/endian.h>
73:
74: #include <dev/usb/usb.h>
75: #include <dev/usb/usbdi.h>
76: #include <dev/usb/usbdivar.h>
77: #include <dev/usb/usb_mem.h>
78: #include <dev/usb/usb_quirks.h>
79:
80: #include <dev/usb/ehcireg.h>
81: #include <dev/usb/ehcivar.h>
1.131 drochner 82: #include <dev/usb/usbroothub_subr.h>
1.1 augustss 83:
84: #ifdef EHCI_DEBUG
1.73 augustss 85: #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0)
86: #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0)
1.6 augustss 87: int ehcidebug = 0;
1.1 augustss 88: #else
89: #define DPRINTF(x)
90: #define DPRINTFN(n,x)
91: #endif
92:
1.5 augustss 93: struct ehci_pipe {
94: struct usbd_pipe pipe;
1.55 mycroft 95: int nexttoggle;
96:
1.10 augustss 97: ehci_soft_qh_t *sqh;
98: union {
99: ehci_soft_qtd_t *qtd;
100: /* ehci_soft_itd_t *itd; */
101: } tail;
102: union {
103: /* Control pipe */
104: struct {
105: usb_dma_t reqdma;
106: u_int length;
107: } ctl;
108: /* Interrupt pipe */
1.78 augustss 109: struct {
110: u_int length;
111: } intr;
1.10 augustss 112: /* Bulk pipe */
113: struct {
114: u_int length;
115: } bulk;
116: /* Iso pipe */
1.139 jmcneill 117: struct {
118: u_int next_frame;
119: u_int cur_xfers;
120: } isoc;
1.10 augustss 121: } u;
1.5 augustss 122: };
123:
124: Static usbd_status ehci_open(usbd_pipe_handle);
125: Static void ehci_poll(struct usbd_bus *);
126: Static void ehci_softintr(void *);
1.11 augustss 127: Static int ehci_intr1(ehci_softc_t *);
1.15 augustss 128: Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
1.18 augustss 129: Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
1.139 jmcneill 130: Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *);
131: Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *);
1.18 augustss 132: Static void ehci_idone(struct ehci_xfer *);
1.15 augustss 133: Static void ehci_timeout(void *);
134: Static void ehci_timeout_task(void *);
1.108 xtraeme 135: Static void ehci_intrlist_timeout(void *);
1.5 augustss 136:
137: Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
138: Static void ehci_freem(struct usbd_bus *, usb_dma_t *);
139:
140: Static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
141: Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
142:
143: Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
144: Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
145: Static void ehci_root_ctrl_abort(usbd_xfer_handle);
146: Static void ehci_root_ctrl_close(usbd_pipe_handle);
147: Static void ehci_root_ctrl_done(usbd_xfer_handle);
148:
149: Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
150: Static usbd_status ehci_root_intr_start(usbd_xfer_handle);
151: Static void ehci_root_intr_abort(usbd_xfer_handle);
152: Static void ehci_root_intr_close(usbd_pipe_handle);
153: Static void ehci_root_intr_done(usbd_xfer_handle);
154:
155: Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
156: Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
157: Static void ehci_device_ctrl_abort(usbd_xfer_handle);
158: Static void ehci_device_ctrl_close(usbd_pipe_handle);
159: Static void ehci_device_ctrl_done(usbd_xfer_handle);
160:
161: Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
162: Static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
163: Static void ehci_device_bulk_abort(usbd_xfer_handle);
164: Static void ehci_device_bulk_close(usbd_pipe_handle);
165: Static void ehci_device_bulk_done(usbd_xfer_handle);
166:
167: Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
168: Static usbd_status ehci_device_intr_start(usbd_xfer_handle);
169: Static void ehci_device_intr_abort(usbd_xfer_handle);
170: Static void ehci_device_intr_close(usbd_pipe_handle);
171: Static void ehci_device_intr_done(usbd_xfer_handle);
172:
173: Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
174: Static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
175: Static void ehci_device_isoc_abort(usbd_xfer_handle);
176: Static void ehci_device_isoc_close(usbd_pipe_handle);
177: Static void ehci_device_isoc_done(usbd_xfer_handle);
178:
179: Static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
180: Static void ehci_noop(usbd_pipe_handle pipe);
181:
1.6 augustss 182: Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
183: Static void ehci_disown(ehci_softc_t *, int, int);
1.5 augustss 184:
1.9 augustss 185: Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
186: Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
187:
188: Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
189: Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
1.25 augustss 190: Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
1.15 augustss 191: ehci_softc_t *, int, int, usbd_xfer_handle,
192: ehci_soft_qtd_t **, ehci_soft_qtd_t **);
1.25 augustss 193: Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
1.18 augustss 194: ehci_soft_qtd_t *);
1.15 augustss 195:
1.139 jmcneill 196: Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc);
197: Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd);
198: Static void ehci_rem_free_itd_chain(ehci_softc_t *sc,
199: struct ehci_xfer *exfer);
200: Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer,
201: usbd_status status);
202:
1.15 augustss 203: Static usbd_status ehci_device_request(usbd_xfer_handle xfer);
1.9 augustss 204:
1.78 augustss 205: Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
206: int ival);
207:
1.10 augustss 208: Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
209: Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
210: ehci_soft_qh_t *);
1.23 augustss 211: Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
1.11 augustss 212: Static void ehci_sync_hc(ehci_softc_t *);
1.10 augustss 213:
214: Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
215: Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
1.9 augustss 216:
1.5 augustss 217: #ifdef EHCI_DEBUG
1.18 augustss 218: Static void ehci_dump_regs(ehci_softc_t *);
1.107 augustss 219: void ehci_dump(void);
1.6 augustss 220: Static ehci_softc_t *theehci;
1.15 augustss 221: Static void ehci_dump_link(ehci_link_t, int);
222: Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
1.9 augustss 223: Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
224: Static void ehci_dump_qtd(ehci_qtd_t *);
225: Static void ehci_dump_sqh(ehci_soft_qh_t *);
1.139 jmcneill 226: #if notyet
227: Static void ehci_dump_sitd(struct ehci_soft_itd *itd);
228: Static void ehci_dump_itd(struct ehci_soft_itd *);
229: #endif
1.38 martin 230: #ifdef DIAGNOSTIC
1.141 cegger 231: Static void ehci_dump_exfer(struct ehci_xfer *);
1.5 augustss 232: #endif
1.38 martin 233: #endif
1.5 augustss 234:
1.11 augustss 235: #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
236:
1.5 augustss 237: #define EHCI_INTR_ENDPT 1
238:
1.18 augustss 239: #define ehci_add_intr_list(sc, ex) \
1.153 jmcneill 240: TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext);
241: #define ehci_del_intr_list(sc, ex) \
1.44 augustss 242: do { \
1.153 jmcneill 243: TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \
244: (ex)->inext.tqe_prev = NULL; \
1.44 augustss 245: } while (0)
1.153 jmcneill 246: #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL)
1.18 augustss 247:
1.123 drochner 248: Static const struct usbd_bus_methods ehci_bus_methods = {
1.5 augustss 249: ehci_open,
250: ehci_softintr,
251: ehci_poll,
252: ehci_allocm,
253: ehci_freem,
254: ehci_allocx,
255: ehci_freex,
256: };
257:
1.123 drochner 258: Static const struct usbd_pipe_methods ehci_root_ctrl_methods = {
1.5 augustss 259: ehci_root_ctrl_transfer,
260: ehci_root_ctrl_start,
261: ehci_root_ctrl_abort,
262: ehci_root_ctrl_close,
263: ehci_noop,
264: ehci_root_ctrl_done,
265: };
266:
1.123 drochner 267: Static const struct usbd_pipe_methods ehci_root_intr_methods = {
1.5 augustss 268: ehci_root_intr_transfer,
269: ehci_root_intr_start,
270: ehci_root_intr_abort,
271: ehci_root_intr_close,
272: ehci_noop,
273: ehci_root_intr_done,
274: };
275:
1.123 drochner 276: Static const struct usbd_pipe_methods ehci_device_ctrl_methods = {
1.5 augustss 277: ehci_device_ctrl_transfer,
278: ehci_device_ctrl_start,
279: ehci_device_ctrl_abort,
280: ehci_device_ctrl_close,
281: ehci_noop,
282: ehci_device_ctrl_done,
283: };
284:
1.123 drochner 285: Static const struct usbd_pipe_methods ehci_device_intr_methods = {
1.5 augustss 286: ehci_device_intr_transfer,
287: ehci_device_intr_start,
288: ehci_device_intr_abort,
289: ehci_device_intr_close,
290: ehci_device_clear_toggle,
291: ehci_device_intr_done,
292: };
293:
1.123 drochner 294: Static const struct usbd_pipe_methods ehci_device_bulk_methods = {
1.5 augustss 295: ehci_device_bulk_transfer,
296: ehci_device_bulk_start,
297: ehci_device_bulk_abort,
298: ehci_device_bulk_close,
299: ehci_device_clear_toggle,
300: ehci_device_bulk_done,
301: };
302:
1.123 drochner 303: Static const struct usbd_pipe_methods ehci_device_isoc_methods = {
1.5 augustss 304: ehci_device_isoc_transfer,
305: ehci_device_isoc_start,
306: ehci_device_isoc_abort,
307: ehci_device_isoc_close,
308: ehci_noop,
309: ehci_device_isoc_done,
310: };
311:
1.123 drochner 312: static const uint8_t revbits[EHCI_MAX_POLLRATE] = {
1.95 augustss 313: 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78,
314: 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c,
315: 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a,
316: 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e,
317: 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79,
318: 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d,
319: 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b,
320: 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f,
1.94 augustss 321: };
322:
1.1 augustss 323: usbd_status
324: ehci_init(ehci_softc_t *sc)
325: {
1.104 christos 326: u_int32_t vers, sparams, cparams, hcr;
1.3 augustss 327: u_int i;
328: usbd_status err;
1.11 augustss 329: ehci_soft_qh_t *sqh;
1.89 augustss 330: u_int ncomp;
1.3 augustss 331:
332: DPRINTF(("ehci_init: start\n"));
1.6 augustss 333: #ifdef EHCI_DEBUG
334: theehci = sc;
335: #endif
1.3 augustss 336:
337: sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
338:
1.104 christos 339: vers = EREAD2(sc, EHCI_HCIVERSION);
1.134 drochner 340: aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev),
1.104 christos 341: vers >> 8, vers & 0xff);
1.3 augustss 342:
343: sparams = EREAD4(sc, EHCI_HCSPARAMS);
344: DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
1.6 augustss 345: sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
1.89 augustss 346: ncomp = EHCI_HCS_N_CC(sparams);
347: if (ncomp != sc->sc_ncomp) {
1.121 ad 348: aprint_verbose("%s: wrong number of companions (%d != %d)\n",
1.134 drochner 349: device_xname(sc->sc_dev), ncomp, sc->sc_ncomp);
1.47 augustss 350: #if NOHCI == 0 || NUHCI == 0
351: aprint_error("%s: ohci or uhci probably not configured\n",
1.134 drochner 352: device_xname(sc->sc_dev));
1.47 augustss 353: #endif
1.89 augustss 354: if (ncomp < sc->sc_ncomp)
355: sc->sc_ncomp = ncomp;
1.3 augustss 356: }
357: if (sc->sc_ncomp > 0) {
1.172 matt 358: KASSERT(!(sc->sc_flags & EHCIF_ETTF));
1.41 thorpej 359: aprint_normal("%s: companion controller%s, %d port%s each:",
1.134 drochner 360: device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "",
1.3 augustss 361: EHCI_HCS_N_PCC(sparams),
362: EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
363: for (i = 0; i < sc->sc_ncomp; i++)
1.134 drochner 364: aprint_normal(" %s", device_xname(sc->sc_comps[i]));
1.41 thorpej 365: aprint_normal("\n");
1.3 augustss 366: }
1.5 augustss 367: sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
1.3 augustss 368: cparams = EREAD4(sc, EHCI_HCCPARAMS);
369: DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
1.106 augustss 370: sc->sc_hasppc = EHCI_HCS_PPC(sparams);
1.36 augustss 371:
372: if (EHCI_HCC_64BIT(cparams)) {
373: /* MUST clear segment register if 64 bit capable. */
374: EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
375: }
1.33 augustss 376:
1.3 augustss 377: sc->sc_bus.usbrev = USBREV_2_0;
378:
1.136 drochner 379: usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag,
1.90 fvdl 380: USB_MEM_RESERVE);
381:
1.3 augustss 382: /* Reset the controller */
1.134 drochner 383: DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev)));
1.3 augustss 384: EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
385: usb_delay_ms(&sc->sc_bus, 1);
386: EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
387: for (i = 0; i < 100; i++) {
1.34 augustss 388: usb_delay_ms(&sc->sc_bus, 1);
1.3 augustss 389: hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
390: if (!hcr)
391: break;
392: }
393: if (hcr) {
1.134 drochner 394: aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev));
1.3 augustss 395: return (USBD_IOERROR);
396: }
1.170 kiyohara 397: if (sc->sc_vendor_init)
398: sc->sc_vendor_init(sc);
1.3 augustss 399:
1.172 matt 400: /*
401: * If we are doing embedded transaction translation function, force
402: * the controller to host mode.
403: */
404: if (sc->sc_flags & EHCIF_ETTF) {
405: uint32_t usbmode = EREAD4(sc, EHCI_USBMODE);
406: usbmode &= ~EHCI_USBMODE_CM;
407: usbmode |= EHCI_USBMODE_CM_HOST;
408: EWRITE4(sc, EHCI_USBMODE, usbmode);
409: }
410:
1.78 augustss 411: /* XXX need proper intr scheduling */
412: sc->sc_rand = 96;
413:
1.3 augustss 414: /* frame list size at default, read back what we got and use that */
415: switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
1.78 augustss 416: case 0: sc->sc_flsize = 1024; break;
417: case 1: sc->sc_flsize = 512; break;
418: case 2: sc->sc_flsize = 256; break;
1.3 augustss 419: case 3: return (USBD_IOERROR);
420: }
1.78 augustss 421: err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
422: EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
1.3 augustss 423: if (err)
424: return (err);
1.134 drochner 425: DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize));
1.78 augustss 426: sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
1.139 jmcneill 427:
428: for (i = 0; i < sc->sc_flsize; i++) {
429: sc->sc_flist[i] = EHCI_NULL;
430: }
431:
1.78 augustss 432: EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1.3 augustss 433:
1.139 jmcneill 434: sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *),
1.144 drochner 435: M_USB, M_NOWAIT | M_ZERO);
1.139 jmcneill 436: if (sc->sc_softitds == NULL)
437: return ENOMEM;
438: LIST_INIT(&sc->sc_freeitds);
1.153 jmcneill 439: TAILQ_INIT(&sc->sc_intrhead);
440: mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB);
1.139 jmcneill 441:
1.5 augustss 442: /* Set up the bus struct. */
443: sc->sc_bus.methods = &ehci_bus_methods;
444: sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
445:
1.6 augustss 446: sc->sc_eintrs = EHCI_NORMAL_INTRS;
447:
1.78 augustss 448: /*
449: * Allocate the interrupt dummy QHs. These are arranged to give poll
450: * intervals that are powers of 2 times 1ms.
451: */
452: for (i = 0; i < EHCI_INTRQHS; i++) {
453: sqh = ehci_alloc_sqh(sc);
454: if (sqh == NULL) {
455: err = USBD_NOMEM;
456: goto bad1;
457: }
458: sc->sc_islots[i].sqh = sqh;
459: }
460: for (i = 0; i < EHCI_INTRQHS; i++) {
461: sqh = sc->sc_islots[i].sqh;
462: if (i == 0) {
463: /* The last (1ms) QH terminates. */
464: sqh->qh.qh_link = EHCI_NULL;
465: sqh->next = NULL;
466: } else {
467: /* Otherwise the next QH has half the poll interval */
468: sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh;
469: sqh->qh.qh_link = htole32(sqh->next->physaddr |
470: EHCI_LINK_QH);
471: }
472: sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
473: sqh->qh.qh_curqtd = EHCI_NULL;
474: sqh->next = NULL;
475: sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
476: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
477: sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
478: sqh->sqtd = NULL;
1.138 bouyer 479: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
480: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.78 augustss 481: }
482: /* Point the frame list at the last level (128ms). */
483: for (i = 0; i < sc->sc_flsize; i++) {
1.94 augustss 484: int j;
485:
486: j = (i & ~(EHCI_MAX_POLLRATE-1)) |
487: revbits[i & (EHCI_MAX_POLLRATE-1)];
488: sc->sc_flist[j] = htole32(EHCI_LINK_QH |
1.78 augustss 489: sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
490: i)].sqh->physaddr);
491: }
1.138 bouyer 492: usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t),
493: BUS_DMASYNC_PREWRITE);
1.78 augustss 494:
1.11 augustss 495: /* Allocate dummy QH that starts the async list. */
496: sqh = ehci_alloc_sqh(sc);
497: if (sqh == NULL) {
1.9 augustss 498: err = USBD_NOMEM;
499: goto bad1;
500: }
1.11 augustss 501: /* Fill the QH */
502: sqh->qh.qh_endp =
503: htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
504: sqh->qh.qh_link =
505: htole32(sqh->physaddr | EHCI_LINK_QH);
506: sqh->qh.qh_curqtd = EHCI_NULL;
507: sqh->next = NULL;
508: /* Fill the overlay qTD */
509: sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
510: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1.26 augustss 511: sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
1.11 augustss 512: sqh->sqtd = NULL;
1.138 bouyer 513: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
514: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.9 augustss 515: #ifdef EHCI_DEBUG
516: if (ehcidebug) {
1.27 enami 517: ehci_dump_sqh(sqh);
1.9 augustss 518: }
519: #endif
520:
521: /* Point to async list */
1.11 augustss 522: sc->sc_async_head = sqh;
523: EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
1.9 augustss 524:
1.161 uebayasi 525: callout_init(&(sc->sc_tmo_intrlist), 0);
1.9 augustss 526:
1.126 ad 527: mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE);
1.10 augustss 528:
1.6 augustss 529: /* Turn on controller */
530: EOWRITE4(sc, EHCI_USBCMD,
1.88 augustss 531: EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
1.6 augustss 532: (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
1.10 augustss 533: EHCI_CMD_ASE |
1.78 augustss 534: EHCI_CMD_PSE |
1.6 augustss 535: EHCI_CMD_RS);
536:
537: /* Take over port ownership */
538: EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
539:
1.8 augustss 540: for (i = 0; i < 100; i++) {
1.34 augustss 541: usb_delay_ms(&sc->sc_bus, 1);
1.8 augustss 542: hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
543: if (!hcr)
544: break;
545: }
546: if (hcr) {
1.134 drochner 547: aprint_error("%s: run timeout\n", device_xname(sc->sc_dev));
1.8 augustss 548: return (USBD_IOERROR);
549: }
550:
1.105 augustss 551: /* Enable interrupts */
552: DPRINTFN(1,("ehci_init: enabling\n"));
553: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
554:
1.5 augustss 555: return (USBD_NORMAL_COMPLETION);
1.9 augustss 556:
557: #if 0
1.11 augustss 558: bad2:
1.15 augustss 559: ehci_free_sqh(sc, sc->sc_async_head);
1.9 augustss 560: #endif
561: bad1:
562: usb_freemem(&sc->sc_bus, &sc->sc_fldma);
563: return (err);
1.1 augustss 564: }
565:
566: int
567: ehci_intr(void *v)
568: {
1.6 augustss 569: ehci_softc_t *sc = v;
570:
1.134 drochner 571: if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev))
1.15 augustss 572: return (0);
573:
1.6 augustss 574: /* If we get an interrupt while polling, then just ignore it. */
575: if (sc->sc_bus.use_polling) {
1.78 augustss 576: u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
577:
578: if (intrs)
579: EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
1.6 augustss 580: #ifdef DIAGNOSTIC
1.65 mycroft 581: DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n"));
1.6 augustss 582: #endif
583: return (0);
584: }
585:
1.33 augustss 586: return (ehci_intr1(sc));
1.6 augustss 587: }
588:
589: Static int
590: ehci_intr1(ehci_softc_t *sc)
591: {
592: u_int32_t intrs, eintrs;
593:
594: DPRINTFN(20,("ehci_intr1: enter\n"));
595:
596: /* In case the interrupt occurs before initialization has completed. */
597: if (sc == NULL) {
598: #ifdef DIAGNOSTIC
1.72 augustss 599: printf("ehci_intr1: sc == NULL\n");
1.6 augustss 600: #endif
601: return (0);
602: }
603:
604: intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
605: if (!intrs)
606: return (0);
607:
608: eintrs = intrs & sc->sc_eintrs;
1.72 augustss 609: DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
1.6 augustss 610: sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
611: (u_int)eintrs));
612: if (!eintrs)
613: return (0);
614:
1.68 mycroft 615: EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
1.6 augustss 616: sc->sc_bus.intr_context++;
617: sc->sc_bus.no_intrs++;
1.10 augustss 618: if (eintrs & EHCI_STS_IAA) {
619: DPRINTF(("ehci_intr1: door bell\n"));
1.11 augustss 620: wakeup(&sc->sc_async_head);
1.20 augustss 621: eintrs &= ~EHCI_STS_IAA;
1.10 augustss 622: }
1.18 augustss 623: if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
1.46 augustss 624: DPRINTFN(5,("ehci_intr1: %s %s\n",
625: eintrs & EHCI_STS_INT ? "INT" : "",
626: eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
1.18 augustss 627: usb_schedsoftintr(&sc->sc_bus);
1.21 augustss 628: eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
1.6 augustss 629: }
630: if (eintrs & EHCI_STS_HSE) {
631: printf("%s: unrecoverable error, controller halted\n",
1.134 drochner 632: device_xname(sc->sc_dev));
1.6 augustss 633: /* XXX what else */
634: }
635: if (eintrs & EHCI_STS_PCD) {
636: ehci_pcd(sc, sc->sc_intrxfer);
637: eintrs &= ~EHCI_STS_PCD;
638: }
639:
640: sc->sc_bus.intr_context--;
641:
642: if (eintrs != 0) {
643: /* Block unprocessed interrupts. */
644: sc->sc_eintrs &= ~eintrs;
645: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
646: printf("%s: blocking intrs 0x%x\n",
1.134 drochner 647: device_xname(sc->sc_dev), eintrs);
1.6 augustss 648: }
649:
650: return (1);
651: }
652:
653:
1.164 uebayasi 654: Static void
1.6 augustss 655: ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
656: {
657: usbd_pipe_handle pipe;
658: u_char *p;
659: int i, m;
660:
661: if (xfer == NULL) {
662: /* Just ignore the change. */
663: return;
664: }
665:
666: pipe = xfer->pipe;
667:
1.30 augustss 668: p = KERNADDR(&xfer->dmabuf, 0);
1.6 augustss 669: m = min(sc->sc_noport, xfer->length * 8 - 1);
670: memset(p, 0, xfer->length);
671: for (i = 1; i <= m; i++) {
672: /* Pick out CHANGE bits from the status reg. */
673: if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
674: p[i/8] |= 1 << (i%8);
675: }
676: DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
677: xfer->actlen = xfer->length;
678: xfer->status = USBD_NORMAL_COMPLETION;
679:
680: usb_transfer_complete(xfer);
1.1 augustss 681: }
682:
1.164 uebayasi 683: Static void
1.5 augustss 684: ehci_softintr(void *v)
685: {
1.134 drochner 686: struct usbd_bus *bus = v;
687: ehci_softc_t *sc = bus->hci_private;
1.53 chs 688: struct ehci_xfer *ex, *nextex;
1.18 augustss 689:
1.134 drochner 690: DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev),
1.18 augustss 691: sc->sc_bus.intr_context));
692:
693: sc->sc_bus.intr_context++;
694:
695: /*
696: * The only explanation I can think of for why EHCI is as brain dead
697: * as UHCI interrupt-wise is that Intel was involved in both.
698: * An interrupt just tells us that something is done, we have no
699: * clue what, so we need to scan through all active transfers. :-(
700: */
1.153 jmcneill 701: for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
702: nextex = TAILQ_NEXT(ex, inext);
1.18 augustss 703: ehci_check_intr(sc, ex);
1.53 chs 704: }
1.18 augustss 705:
1.108 xtraeme 706: /* Schedule a callout to catch any dropped transactions. */
707: if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
1.153 jmcneill 708: !TAILQ_EMPTY(&sc->sc_intrhead))
1.161 uebayasi 709: callout_reset(&(sc->sc_tmo_intrlist),
1.159 dyoung 710: (hz), (ehci_intrlist_timeout), (sc));
1.108 xtraeme 711:
1.77 augustss 712: #ifdef USB_USE_SOFTINTR
1.29 augustss 713: if (sc->sc_softwake) {
714: sc->sc_softwake = 0;
715: wakeup(&sc->sc_softwake);
716: }
1.77 augustss 717: #endif /* USB_USE_SOFTINTR */
1.29 augustss 718:
1.18 augustss 719: sc->sc_bus.intr_context--;
720: }
721:
722: /* Check for an interrupt. */
1.164 uebayasi 723: Static void
1.115 christos 724: ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
1.18 augustss 725: {
1.139 jmcneill 726: int attr;
1.18 augustss 727:
1.22 augustss 728: DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
1.18 augustss 729:
1.139 jmcneill 730: attr = ex->xfer.pipe->endpoint->edesc->bmAttributes;
731: if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS)
732: ehci_check_itd_intr(sc, ex);
733: else
734: ehci_check_qh_intr(sc, ex);
735:
736: return;
737: }
738:
1.164 uebayasi 739: Static void
1.139 jmcneill 740: ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
741: {
742: ehci_soft_qtd_t *sqtd, *lsqtd;
743: __uint32_t status;
744:
1.18 augustss 745: if (ex->sqtdstart == NULL) {
1.139 jmcneill 746: printf("ehci_check_qh_intr: not valid sqtd\n");
1.18 augustss 747: return;
748: }
1.139 jmcneill 749:
1.18 augustss 750: lsqtd = ex->sqtdend;
751: #ifdef DIAGNOSTIC
752: if (lsqtd == NULL) {
1.139 jmcneill 753: printf("ehci_check_qh_intr: lsqtd==0\n");
1.18 augustss 754: return;
755: }
756: #endif
1.33 augustss 757: /*
1.18 augustss 758: * If the last TD is still active we need to check whether there
759: * is a an error somewhere in the middle, or whether there was a
760: * short packet (SPD and not ACTIVE).
761: */
1.138 bouyer 762: usb_syncmem(&lsqtd->dma,
763: lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
764: sizeof(lsqtd->qtd.qtd_status),
765: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.183.2.1! riz 766: status = le32toh(lsqtd->qtd.qtd_status);
! 767: usb_syncmem(&lsqtd->dma,
! 768: lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
! 769: sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
! 770: if (status & EHCI_QTD_ACTIVE) {
1.18 augustss 771: DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
772: for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
1.138 bouyer 773: usb_syncmem(&sqtd->dma,
774: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
775: sizeof(sqtd->qtd.qtd_status),
776: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.18 augustss 777: status = le32toh(sqtd->qtd.qtd_status);
1.138 bouyer 778: usb_syncmem(&sqtd->dma,
779: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
780: sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
1.18 augustss 781: /* If there's an active QTD the xfer isn't done. */
782: if (status & EHCI_QTD_ACTIVE)
783: break;
784: /* Any kind of error makes the xfer done. */
785: if (status & EHCI_QTD_HALTED)
786: goto done;
787: /* We want short packets, and it is short: it's done */
1.58 mycroft 788: if (EHCI_QTD_GET_BYTES(status) != 0)
1.18 augustss 789: goto done;
790: }
791: DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
792: ex, ex->sqtdstart));
793: return;
794: }
795: done:
796: DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
1.171 dyoung 797: callout_stop(&ex->xfer.timeout_handle);
1.18 augustss 798: ehci_idone(ex);
799: }
800:
1.164 uebayasi 801: Static void
1.139 jmcneill 802: ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) {
803: ehci_soft_itd_t *itd;
804: int i;
805:
1.153 jmcneill 806: if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue))
807: return;
808:
1.139 jmcneill 809: if (ex->itdstart == NULL) {
810: printf("ehci_check_itd_intr: not valid itd\n");
811: return;
812: }
813:
814: itd = ex->itdend;
815: #ifdef DIAGNOSTIC
816: if (itd == NULL) {
817: printf("ehci_check_itd_intr: itdend == 0\n");
818: return;
819: }
820: #endif
821:
822: /*
1.153 jmcneill 823: * check no active transfers in last itd, meaning we're finished
1.139 jmcneill 824: */
825:
826: usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
827: sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE |
828: BUS_DMASYNC_POSTREAD);
829:
1.168 jakllsch 830: for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1.139 jmcneill 831: if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE)
1.152 jmcneill 832: break;
1.139 jmcneill 833: }
834:
1.168 jakllsch 835: if (i == EHCI_ITD_NUFRAMES) {
1.139 jmcneill 836: goto done; /* All 8 descriptors inactive, it's done */
837: }
838:
839: DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex,
840: ex->itdstart));
841: return;
842: done:
843: DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex));
1.171 dyoung 844: callout_stop(&ex->xfer.timeout_handle);
1.139 jmcneill 845: ehci_idone(ex);
846: }
847:
1.164 uebayasi 848: Static void
1.18 augustss 849: ehci_idone(struct ehci_xfer *ex)
850: {
851: usbd_xfer_handle xfer = &ex->xfer;
852: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
1.82 augustss 853: ehci_soft_qtd_t *sqtd, *lsqtd;
854: u_int32_t status = 0, nstatus = 0;
1.18 augustss 855: int actlen;
856:
1.22 augustss 857: DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
1.18 augustss 858: #ifdef DIAGNOSTIC
859: {
860: int s = splhigh();
861: if (ex->isdone) {
862: splx(s);
863: #ifdef EHCI_DEBUG
864: printf("ehci_idone: ex is done!\n ");
865: ehci_dump_exfer(ex);
866: #else
867: printf("ehci_idone: ex=%p is done!\n", ex);
868: #endif
869: return;
870: }
871: ex->isdone = 1;
872: splx(s);
873: }
874: #endif
875: if (xfer->status == USBD_CANCELLED ||
876: xfer->status == USBD_TIMEOUT) {
877: DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
878: return;
879: }
880:
881: #ifdef EHCI_DEBUG
1.23 augustss 882: DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
1.18 augustss 883: if (ehcidebug > 10)
884: ehci_dump_sqtds(ex->sqtdstart);
885: #endif
886:
887: /* The transfer is done, compute actual length and status. */
1.139 jmcneill 888:
889: if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)
890: == UE_ISOCHRONOUS) {
891: /* Isoc transfer */
892: struct ehci_soft_itd *itd;
893: int i, nframes, len, uframes;
894:
895: nframes = 0;
896: actlen = 0;
897:
1.168 jakllsch 898: i = xfer->pipe->endpoint->edesc->bInterval;
899: uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME);
1.139 jmcneill 900:
901: for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) {
902: usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl),
903: sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE |
904: BUS_DMASYNC_POSTREAD);
905:
1.168 jakllsch 906: for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) {
1.139 jmcneill 907: /* XXX - driver didn't fill in the frame full
908: * of uframes. This leads to scheduling
909: * inefficiencies, but working around
910: * this doubles complexity of tracking
911: * an xfer.
912: */
913: if (nframes >= xfer->nframes)
914: break;
915:
916: status = le32toh(itd->itd.itd_ctl[i]);
917: len = EHCI_ITD_GET_LEN(status);
1.155 jmorse 918: if (EHCI_ITD_GET_STATUS(status) != 0)
919: len = 0; /*No valid data on error*/
920:
1.139 jmcneill 921: xfer->frlengths[nframes++] = len;
922: actlen += len;
923: }
924:
925: if (nframes >= xfer->nframes)
926: break;
1.183 jakllsch 927: }
1.139 jmcneill 928:
929: xfer->actlen = actlen;
930: xfer->status = USBD_NORMAL_COMPLETION;
931: goto end;
932: }
933:
934: /* Continue processing xfers using queue heads */
935:
1.82 augustss 936: lsqtd = ex->sqtdend;
1.18 augustss 937: actlen = 0;
1.139 jmcneill 938: for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) {
1.138 bouyer 939: usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
940: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.18 augustss 941: nstatus = le32toh(sqtd->qtd.qtd_status);
942: if (nstatus & EHCI_QTD_ACTIVE)
943: break;
944:
945: status = nstatus;
1.139 jmcneill 946: if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
1.18 augustss 947: actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
948: }
1.22 augustss 949:
1.139 jmcneill 950:
1.91 perry 951: /*
1.86 augustss 952: * If there are left over TDs we need to update the toggle.
953: * The default pipe doesn't need it since control transfers
954: * start the toggle at 0 every time.
1.117 drochner 955: * For a short transfer we need to update the toggle for the missing
956: * packets within the qTD.
1.86 augustss 957: */
1.117 drochner 958: if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) &&
1.82 augustss 959: xfer->pipe->device->default_pipe != xfer->pipe) {
1.117 drochner 960: DPRINTFN(2, ("ehci_idone: need toggle update "
961: "status=%08x nstatus=%08x\n", status, nstatus));
1.58 mycroft 962: #if 0
963: ehci_dump_sqh(epipe->sqh);
964: ehci_dump_sqtds(ex->sqtdstart);
965: #endif
966: epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus);
1.22 augustss 967: }
1.18 augustss 968:
1.23 augustss 969: DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n",
1.22 augustss 970: xfer->length, actlen, status));
1.18 augustss 971: xfer->actlen = actlen;
1.98 augustss 972: if (status & EHCI_QTD_HALTED) {
1.18 augustss 973: #ifdef EHCI_DEBUG
974: char sbuf[128];
975:
1.156 christos 976: snprintb(sbuf, sizeof(sbuf),
977: "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE",
978: (u_int32_t)status);
1.18 augustss 979:
1.98 augustss 980: DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, "
1.18 augustss 981: "status 0x%s\n",
982: xfer->pipe->device->address,
983: xfer->pipe->endpoint->edesc->bEndpointAddress,
984: sbuf));
1.23 augustss 985: if (ehcidebug > 2) {
986: ehci_dump_sqh(epipe->sqh);
987: ehci_dump_sqtds(ex->sqtdstart);
988: }
1.18 augustss 989: #endif
1.98 augustss 990: /* low&full speed has an extra error flag */
991: if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) !=
992: EHCI_QH_SPEED_HIGH)
993: status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE;
994: else
995: status &= EHCI_QTD_STATERRS;
1.139 jmcneill 996: if (status == 0) /* no other errors means a stall */ {
1.18 augustss 997: xfer->status = USBD_STALLED;
1.139 jmcneill 998: } else {
1.18 augustss 999: xfer->status = USBD_IOERROR; /* more info XXX */
1.139 jmcneill 1000: }
1.98 augustss 1001: /* XXX need to reset TT on missed microframe */
1002: if (status & EHCI_QTD_MISSEDMICRO) {
1.134 drochner 1003: ehci_softc_t *sc =
1004: xfer->pipe->device->bus->hci_private;
1.98 augustss 1005:
1006: printf("%s: missed microframe, TT reset not "
1007: "implemented, hub might be inoperational\n",
1.134 drochner 1008: device_xname(sc->sc_dev));
1.98 augustss 1009: }
1.18 augustss 1010: } else {
1011: xfer->status = USBD_NORMAL_COMPLETION;
1012: }
1013:
1.139 jmcneill 1014: end:
1015: /* XXX transfer_complete memcpys out transfer data (for in endpoints)
1016: * during this call, before methods->done is called: dma sync required
1017: * beforehand? */
1.18 augustss 1018: usb_transfer_complete(xfer);
1.22 augustss 1019: DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
1.5 augustss 1020: }
1021:
1.15 augustss 1022: /*
1023: * Wait here until controller claims to have an interrupt.
1.18 augustss 1024: * Then call ehci_intr and return. Use timeout to avoid waiting
1.15 augustss 1025: * too long.
1026: */
1.164 uebayasi 1027: Static void
1.15 augustss 1028: ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
1029: {
1.97 augustss 1030: int timo;
1.15 augustss 1031: u_int32_t intrs;
1032:
1033: xfer->status = USBD_IN_PROGRESS;
1.97 augustss 1034: for (timo = xfer->timeout; timo >= 0; timo--) {
1.15 augustss 1035: usb_delay_ms(&sc->sc_bus, 1);
1.17 augustss 1036: if (sc->sc_dying)
1037: break;
1.15 augustss 1038: intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
1039: sc->sc_eintrs;
1040: DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
1.70 yamt 1041: #ifdef EHCI_DEBUG
1.15 augustss 1042: if (ehcidebug > 15)
1.18 augustss 1043: ehci_dump_regs(sc);
1.15 augustss 1044: #endif
1045: if (intrs) {
1046: ehci_intr1(sc);
1047: if (xfer->status != USBD_IN_PROGRESS)
1048: return;
1049: }
1050: }
1051:
1052: /* Timeout */
1053: DPRINTF(("ehci_waitintr: timeout\n"));
1054: xfer->status = USBD_TIMEOUT;
1055: usb_transfer_complete(xfer);
1056: /* XXX should free TD */
1057: }
1058:
1.164 uebayasi 1059: Static void
1.5 augustss 1060: ehci_poll(struct usbd_bus *bus)
1061: {
1.134 drochner 1062: ehci_softc_t *sc = bus->hci_private;
1.5 augustss 1063: #ifdef EHCI_DEBUG
1064: static int last;
1065: int new;
1.6 augustss 1066: new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1.5 augustss 1067: if (new != last) {
1068: DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
1069: last = new;
1070: }
1071: #endif
1072:
1.6 augustss 1073: if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs)
1.5 augustss 1074: ehci_intr1(sc);
1075: }
1076:
1.132 dyoung 1077: void
1078: ehci_childdet(device_t self, device_t child)
1079: {
1080: struct ehci_softc *sc = device_private(self);
1081:
1082: KASSERT(sc->sc_child == child);
1083: sc->sc_child = NULL;
1084: }
1085:
1.1 augustss 1086: int
1087: ehci_detach(struct ehci_softc *sc, int flags)
1088: {
1089: int rv = 0;
1090:
1091: if (sc->sc_child != NULL)
1092: rv = config_detach(sc->sc_child, flags);
1.33 augustss 1093:
1.1 augustss 1094: if (rv != 0)
1095: return (rv);
1096:
1.171 dyoung 1097: callout_stop(&sc->sc_tmo_intrlist);
1.6 augustss 1098:
1.17 augustss 1099: usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
1.15 augustss 1100:
1.1 augustss 1101: /* XXX free other data structures XXX */
1.126 ad 1102: mutex_destroy(&sc->sc_doorbell_lock);
1.153 jmcneill 1103: mutex_destroy(&sc->sc_intrhead_lock);
1.1 augustss 1104:
1.128 jmcneill 1105: EOWRITE4(sc, EHCI_CONFIGFLAG, 0);
1106:
1.1 augustss 1107: return (rv);
1108: }
1109:
1110:
1111: int
1.132 dyoung 1112: ehci_activate(device_t self, enum devact act)
1.1 augustss 1113: {
1.132 dyoung 1114: struct ehci_softc *sc = device_private(self);
1.1 augustss 1115:
1116: switch (act) {
1117: case DVACT_DEACTIVATE:
1.124 kiyohara 1118: sc->sc_dying = 1;
1.163 dyoung 1119: return 0;
1120: default:
1121: return EOPNOTSUPP;
1.1 augustss 1122: }
1123: }
1124:
1.5 augustss 1125: /*
1126: * Handle suspend/resume.
1127: *
1128: * We need to switch to polling mode here, because this routine is
1.73 augustss 1129: * called from an interrupt context. This is all right since we
1.5 augustss 1130: * are almost suspended anyway.
1.127 jmcneill 1131: *
1132: * Note that this power handler isn't to be registered directly; the
1133: * bus glue needs to call out to it.
1.5 augustss 1134: */
1.127 jmcneill 1135: bool
1.166 dyoung 1136: ehci_suspend(device_t dv, const pmf_qual_t *qual)
1.5 augustss 1137: {
1.132 dyoung 1138: ehci_softc_t *sc = device_private(dv);
1.127 jmcneill 1139: int i, s;
1140: uint32_t cmd, hcr;
1141:
1142: s = splhardusb();
1143:
1144: sc->sc_bus.use_polling++;
1145:
1146: for (i = 1; i <= sc->sc_noport; i++) {
1.129 jmcneill 1147: cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1.127 jmcneill 1148: if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE)
1149: EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP);
1150: }
1151:
1152: sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
1153:
1154: cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
1155: EOWRITE4(sc, EHCI_USBCMD, cmd);
1156:
1157: for (i = 0; i < 100; i++) {
1158: hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS);
1159: if (hcr == 0)
1160: break;
1.5 augustss 1161:
1.127 jmcneill 1162: usb_delay_ms(&sc->sc_bus, 1);
1163: }
1164: if (hcr != 0)
1.134 drochner 1165: printf("%s: reset timeout\n", device_xname(dv));
1.5 augustss 1166:
1.127 jmcneill 1167: cmd &= ~EHCI_CMD_RS;
1168: EOWRITE4(sc, EHCI_USBCMD, cmd);
1.74 augustss 1169:
1.127 jmcneill 1170: for (i = 0; i < 100; i++) {
1171: hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1172: if (hcr == EHCI_STS_HCH)
1173: break;
1.74 augustss 1174:
1.127 jmcneill 1175: usb_delay_ms(&sc->sc_bus, 1);
1176: }
1177: if (hcr != EHCI_STS_HCH)
1.134 drochner 1178: printf("%s: config timeout\n", device_xname(dv));
1.74 augustss 1179:
1.127 jmcneill 1180: sc->sc_bus.use_polling--;
1181: splx(s);
1.74 augustss 1182:
1.127 jmcneill 1183: return true;
1184: }
1.74 augustss 1185:
1.127 jmcneill 1186: bool
1.166 dyoung 1187: ehci_resume(device_t dv, const pmf_qual_t *qual)
1.127 jmcneill 1188: {
1.132 dyoung 1189: ehci_softc_t *sc = device_private(dv);
1190: int i;
1.127 jmcneill 1191: uint32_t cmd, hcr;
1.74 augustss 1192:
1.127 jmcneill 1193: /* restore things in case the bios sucks */
1194: EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
1195: EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1196: EOWRITE4(sc, EHCI_ASYNCLISTADDR,
1197: sc->sc_async_head->physaddr | EHCI_LINK_QH);
1.130 jmcneill 1198:
1199: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE);
1.74 augustss 1200:
1.127 jmcneill 1201: EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1.74 augustss 1202:
1.127 jmcneill 1203: hcr = 0;
1204: for (i = 1; i <= sc->sc_noport; i++) {
1.129 jmcneill 1205: cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1.127 jmcneill 1206: if ((cmd & EHCI_PS_PO) == 0 &&
1207: (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
1208: EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR);
1209: hcr = 1;
1.74 augustss 1210: }
1.127 jmcneill 1211: }
1212:
1213: if (hcr) {
1214: usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1215:
1216: for (i = 1; i <= sc->sc_noport; i++) {
1.129 jmcneill 1217: cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1.127 jmcneill 1218: if ((cmd & EHCI_PS_PO) == 0 &&
1219: (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
1220: EOWRITE4(sc, EHCI_PORTSC(i),
1221: cmd & ~EHCI_PS_FPR);
1.74 augustss 1222: }
1.127 jmcneill 1223: }
1224:
1225: EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1.130 jmcneill 1226: EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1.74 augustss 1227:
1.127 jmcneill 1228: for (i = 0; i < 100; i++) {
1229: hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1230: if (hcr != EHCI_STS_HCH)
1231: break;
1.74 augustss 1232:
1.127 jmcneill 1233: usb_delay_ms(&sc->sc_bus, 1);
1.5 augustss 1234: }
1.127 jmcneill 1235: if (hcr == EHCI_STS_HCH)
1.134 drochner 1236: printf("%s: config timeout\n", device_xname(dv));
1.127 jmcneill 1237:
1238: return true;
1.5 augustss 1239: }
1240:
1241: /*
1242: * Shut down the controller when the system is going down.
1243: */
1.133 dyoung 1244: bool
1245: ehci_shutdown(device_t self, int flags)
1.5 augustss 1246: {
1.133 dyoung 1247: ehci_softc_t *sc = device_private(self);
1.5 augustss 1248:
1249: DPRINTF(("ehci_shutdown: stopping the HC\n"));
1.8 augustss 1250: EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1251: EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1.133 dyoung 1252: return true;
1.5 augustss 1253: }
1254:
1.164 uebayasi 1255: Static usbd_status
1.5 augustss 1256: ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
1257: {
1.134 drochner 1258: struct ehci_softc *sc = bus->hci_private;
1.25 augustss 1259: usbd_status err;
1.5 augustss 1260:
1.25 augustss 1261: err = usb_allocmem(&sc->sc_bus, size, 0, dma);
1.90 fvdl 1262: if (err == USBD_NOMEM)
1263: err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size);
1.25 augustss 1264: #ifdef EHCI_DEBUG
1265: if (err)
1266: printf("ehci_allocm: usb_allocmem()=%d\n", err);
1267: #endif
1268: return (err);
1.5 augustss 1269: }
1270:
1.164 uebayasi 1271: Static void
1.5 augustss 1272: ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
1273: {
1.134 drochner 1274: struct ehci_softc *sc = bus->hci_private;
1.5 augustss 1275:
1.90 fvdl 1276: if (dma->block->flags & USB_DMA_RESERVE) {
1.134 drochner 1277: usb_reserve_freem(&sc->sc_dma_reserve,
1.90 fvdl 1278: dma);
1279: return;
1280: }
1.5 augustss 1281: usb_freemem(&sc->sc_bus, dma);
1282: }
1283:
1.164 uebayasi 1284: Static usbd_xfer_handle
1.5 augustss 1285: ehci_allocx(struct usbd_bus *bus)
1286: {
1.134 drochner 1287: struct ehci_softc *sc = bus->hci_private;
1.5 augustss 1288: usbd_xfer_handle xfer;
1289:
1290: xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
1.28 augustss 1291: if (xfer != NULL) {
1.32 lukem 1292: SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
1.28 augustss 1293: #ifdef DIAGNOSTIC
1294: if (xfer->busy_free != XFER_FREE) {
1.72 augustss 1295: printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer,
1.28 augustss 1296: xfer->busy_free);
1297: }
1298: #endif
1299: } else {
1.177 tsutsui 1300: xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT);
1.28 augustss 1301: }
1.18 augustss 1302: if (xfer != NULL) {
1.177 tsutsui 1303: memset(xfer, 0, sizeof(struct ehci_xfer));
1.18 augustss 1304: #ifdef DIAGNOSTIC
1.177 tsutsui 1305: EXFER(xfer)->isdone = 1;
1.18 augustss 1306: xfer->busy_free = XFER_BUSY;
1307: #endif
1308: }
1.5 augustss 1309: return (xfer);
1310: }
1311:
1.164 uebayasi 1312: Static void
1.5 augustss 1313: ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1314: {
1.134 drochner 1315: struct ehci_softc *sc = bus->hci_private;
1.5 augustss 1316:
1.18 augustss 1317: #ifdef DIAGNOSTIC
1318: if (xfer->busy_free != XFER_BUSY) {
1319: printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1320: xfer->busy_free);
1321: }
1322: xfer->busy_free = XFER_FREE;
1.177 tsutsui 1323: if (!EXFER(xfer)->isdone) {
1.18 augustss 1324: printf("ehci_freex: !isdone\n");
1325: }
1326: #endif
1.5 augustss 1327: SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
1328: }
1329:
1330: Static void
1331: ehci_device_clear_toggle(usbd_pipe_handle pipe)
1332: {
1.15 augustss 1333: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1334:
1.23 augustss 1335: DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1336: epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1.158 sketch 1337: #ifdef EHCI_DEBUG
1.22 augustss 1338: if (ehcidebug)
1339: usbd_dump_pipe(pipe);
1.5 augustss 1340: #endif
1.55 mycroft 1341: epipe->nexttoggle = 0;
1.5 augustss 1342: }
1343:
1344: Static void
1.115 christos 1345: ehci_noop(usbd_pipe_handle pipe)
1.5 augustss 1346: {
1347: }
1348:
1349: #ifdef EHCI_DEBUG
1.164 uebayasi 1350: Static void
1.18 augustss 1351: ehci_dump_regs(ehci_softc_t *sc)
1.5 augustss 1352: {
1.6 augustss 1353: int i;
1354: printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1355: EOREAD4(sc, EHCI_USBCMD),
1356: EOREAD4(sc, EHCI_USBSTS),
1357: EOREAD4(sc, EHCI_USBINTR));
1.29 augustss 1358: printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1.15 augustss 1359: EOREAD4(sc, EHCI_FRINDEX),
1360: EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1361: EOREAD4(sc, EHCI_PERIODICLISTBASE),
1362: EOREAD4(sc, EHCI_ASYNCLISTADDR));
1.6 augustss 1363: for (i = 1; i <= sc->sc_noport; i++)
1.33 augustss 1364: printf("port %d status=0x%08x\n", i,
1.6 augustss 1365: EOREAD4(sc, EHCI_PORTSC(i)));
1.39 martin 1366: }
1367:
1.40 martin 1368: /*
1369: * Unused function - this is meant to be called from a kernel
1370: * debugger.
1371: */
1.39 martin 1372: void
1.157 cegger 1373: ehci_dump(void)
1.39 martin 1374: {
1375: ehci_dump_regs(theehci);
1.6 augustss 1376: }
1377:
1.164 uebayasi 1378: Static void
1.15 augustss 1379: ehci_dump_link(ehci_link_t link, int type)
1.9 augustss 1380: {
1.15 augustss 1381: link = le32toh(link);
1382: printf("0x%08x", link);
1.9 augustss 1383: if (link & EHCI_LINK_TERMINATE)
1.15 augustss 1384: printf("<T>");
1385: else {
1386: printf("<");
1387: if (type) {
1388: switch (EHCI_LINK_TYPE(link)) {
1389: case EHCI_LINK_ITD: printf("ITD"); break;
1390: case EHCI_LINK_QH: printf("QH"); break;
1391: case EHCI_LINK_SITD: printf("SITD"); break;
1392: case EHCI_LINK_FSTN: printf("FSTN"); break;
1.16 augustss 1393: }
1.15 augustss 1394: }
1.9 augustss 1395: printf(">");
1.15 augustss 1396: }
1397: }
1398:
1.164 uebayasi 1399: Static void
1.15 augustss 1400: ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1401: {
1.29 augustss 1402: int i;
1403: u_int32_t stop;
1404:
1405: stop = 0;
1406: for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1.15 augustss 1407: ehci_dump_sqtd(sqtd);
1.138 bouyer 1408: usb_syncmem(&sqtd->dma,
1.183 jakllsch 1409: sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1.138 bouyer 1410: sizeof(sqtd->qtd),
1411: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.72 augustss 1412: stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1.138 bouyer 1413: usb_syncmem(&sqtd->dma,
1.183 jakllsch 1414: sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1.138 bouyer 1415: sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1.29 augustss 1416: }
1417: if (sqtd)
1418: printf("dump aborted, too many TDs\n");
1.9 augustss 1419: }
1420:
1.164 uebayasi 1421: Static void
1.9 augustss 1422: ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1423: {
1.183 jakllsch 1424: usb_syncmem(&sqtd->dma, sqtd->offs,
1.138 bouyer 1425: sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.9 augustss 1426: printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1427: ehci_dump_qtd(&sqtd->qtd);
1.183 jakllsch 1428: usb_syncmem(&sqtd->dma, sqtd->offs,
1.138 bouyer 1429: sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1.9 augustss 1430: }
1431:
1.164 uebayasi 1432: Static void
1.9 augustss 1433: ehci_dump_qtd(ehci_qtd_t *qtd)
1434: {
1435: u_int32_t s;
1.15 augustss 1436: char sbuf[128];
1.9 augustss 1437:
1.15 augustss 1438: printf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1439: printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1.9 augustss 1440: printf("\n");
1.15 augustss 1441: s = le32toh(qtd->qtd_status);
1.156 christos 1442: snprintb(sbuf, sizeof(sbuf),
1443: "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1444: "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s));
1.9 augustss 1445: printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1446: s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1447: EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1.15 augustss 1448: printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1449: EHCI_QTD_GET_PID(s), sbuf);
1.9 augustss 1450: for (s = 0; s < 5; s++)
1.15 augustss 1451: printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1.9 augustss 1452: }
1453:
1.164 uebayasi 1454: Static void
1.9 augustss 1455: ehci_dump_sqh(ehci_soft_qh_t *sqh)
1456: {
1457: ehci_qh_t *qh = &sqh->qh;
1.15 augustss 1458: u_int32_t endp, endphub;
1.9 augustss 1459:
1.183 jakllsch 1460: usb_syncmem(&sqh->dma, sqh->offs,
1.138 bouyer 1461: sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.9 augustss 1462: printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1.15 augustss 1463: printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n");
1464: endp = le32toh(qh->qh_endp);
1465: printf(" endp=0x%08x\n", endp);
1466: printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1467: EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1468: EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1469: EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1470: printf(" mpl=0x%x ctl=%d nrl=%d\n",
1471: EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1472: EHCI_QH_GET_NRL(endp));
1473: endphub = le32toh(qh->qh_endphub);
1474: printf(" endphub=0x%08x\n", endphub);
1475: printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1476: EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1477: EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1478: EHCI_QH_GET_MULT(endphub));
1479: printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n");
1.12 augustss 1480: printf("Overlay qTD:\n");
1.9 augustss 1481: ehci_dump_qtd(&qh->qh_qtd);
1.183 jakllsch 1482: usb_syncmem(&sqh->dma, sqh->offs,
1.138 bouyer 1483: sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
1.9 augustss 1484: }
1485:
1.154 jmcneill 1486: #if notyet
1.164 uebayasi 1487: Static void
1.139 jmcneill 1488: ehci_dump_itd(struct ehci_soft_itd *itd)
1489: {
1490: ehci_isoc_trans_t t;
1491: ehci_isoc_bufr_ptr_t b, b2, b3;
1492: int i;
1493:
1494: printf("ITD: next phys=%X\n", itd->itd.itd_next);
1495:
1.168 jakllsch 1496: for (i = 0; i < EHCI_ITD_NUFRAMES; i++) {
1.139 jmcneill 1497: t = le32toh(itd->itd.itd_ctl[i]);
1498: printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i,
1499: EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t),
1500: EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t),
1501: EHCI_ITD_GET_OFFS(t));
1502: }
1503: printf("ITDbufr: ");
1.168 jakllsch 1504: for (i = 0; i < EHCI_ITD_NBUFFERS; i++)
1.139 jmcneill 1505: printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])));
1506:
1507: b = le32toh(itd->itd.itd_bufr[0]);
1508: b2 = le32toh(itd->itd.itd_bufr[1]);
1509: b3 = le32toh(itd->itd.itd_bufr[2]);
1510: printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n",
1511: EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2),
1512: EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3));
1513: }
1514:
1.164 uebayasi 1515: Static void
1.139 jmcneill 1516: ehci_dump_sitd(struct ehci_soft_itd *itd)
1517: {
1518: printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n",
1519: itd, itd->u.frame_list.next, itd->u.frame_list.prev,
1520: itd->xfer_next, itd->physaddr, itd->slot);
1521: }
1.154 jmcneill 1522: #endif
1.139 jmcneill 1523:
1.38 martin 1524: #ifdef DIAGNOSTIC
1.164 uebayasi 1525: Static void
1.18 augustss 1526: ehci_dump_exfer(struct ehci_xfer *ex)
1527: {
1.139 jmcneill 1528: printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone);
1.18 augustss 1529: }
1.38 martin 1530: #endif
1.5 augustss 1531: #endif
1532:
1.164 uebayasi 1533: Static usbd_status
1.5 augustss 1534: ehci_open(usbd_pipe_handle pipe)
1535: {
1536: usbd_device_handle dev = pipe->device;
1.134 drochner 1537: ehci_softc_t *sc = dev->bus->hci_private;
1.5 augustss 1538: usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1539: u_int8_t addr = dev->address;
1540: u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1541: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1.10 augustss 1542: ehci_soft_qh_t *sqh;
1543: usbd_status err;
1544: int s;
1.78 augustss 1545: int ival, speed, naks;
1.80 augustss 1546: int hshubaddr, hshubport;
1.5 augustss 1547:
1548: DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1549: pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1550:
1.80 augustss 1551: if (dev->myhsport) {
1.172 matt 1552: /*
1553: * When directly attached FS/LS device while doing embedded
1554: * transaction translations and we are the hub, set the hub
1555: * adddress to 0 (us).
1556: */
1557: if (!(sc->sc_flags & EHCIF_ETTF)
1558: || (dev->myhsport->parent->address != sc->sc_addr)) {
1559: hshubaddr = dev->myhsport->parent->address;
1560: } else {
1561: hshubaddr = 0;
1562: }
1.80 augustss 1563: hshubport = dev->myhsport->portno;
1564: } else {
1565: hshubaddr = 0;
1566: hshubport = 0;
1567: }
1568:
1.17 augustss 1569: if (sc->sc_dying)
1570: return (USBD_IOERROR);
1571:
1.175 drochner 1572: /* toggle state needed for bulk endpoints */
1573: epipe->nexttoggle = pipe->endpoint->datatoggle;
1.55 mycroft 1574:
1.5 augustss 1575: if (addr == sc->sc_addr) {
1576: switch (ed->bEndpointAddress) {
1577: case USB_CONTROL_ENDPOINT:
1578: pipe->methods = &ehci_root_ctrl_methods;
1579: break;
1580: case UE_DIR_IN | EHCI_INTR_ENDPT:
1581: pipe->methods = &ehci_root_intr_methods;
1582: break;
1583: default:
1.139 jmcneill 1584: DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n",
1585: ed->bEndpointAddress));
1.5 augustss 1586: return (USBD_INVAL);
1587: }
1.10 augustss 1588: return (USBD_NORMAL_COMPLETION);
1589: }
1590:
1.24 augustss 1591: /* XXX All this stuff is only valid for async. */
1.11 augustss 1592: switch (dev->speed) {
1593: case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1594: case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1595: case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1.37 provos 1596: default: panic("ehci_open: bad device speed %d", dev->speed);
1.11 augustss 1597: }
1.99 augustss 1598: if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) {
1.146 jmcneill 1599: aprint_error_dev(sc->sc_dev, "error opening low/full speed "
1600: "isoc endpoint.\n");
1601: aprint_normal_dev(sc->sc_dev, "a low/full speed device is "
1602: "attached to a USB2 hub, and transaction translations are "
1603: "not yet supported.\n");
1604: aprint_normal_dev(sc->sc_dev, "reattach the device to the "
1605: "root hub instead.\n");
1.80 augustss 1606: DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n",
1607: hshubaddr, hshubport));
1.99 augustss 1608: return USBD_INVAL;
1.80 augustss 1609: }
1610:
1.169 msaitoh 1611: /*
1612: * For interrupt transfer, nak throttling must be disabled, but for
1613: * the other transfer type, nak throttling should be enabled from the
1614: * veiwpoint that avoids the memory thrashing.
1615: */
1616: naks = (xfertype == UE_INTERRUPT) ? 0
1617: : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0);
1.10 augustss 1618:
1.139 jmcneill 1619: /* Allocate sqh for everything, save isoc xfers */
1620: if (xfertype != UE_ISOCHRONOUS) {
1621: sqh = ehci_alloc_sqh(sc);
1622: if (sqh == NULL)
1623: return (USBD_NOMEM);
1624: /* qh_link filled when the QH is added */
1625: sqh->qh.qh_endp = htole32(
1626: EHCI_QH_SET_ADDR(addr) |
1627: EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
1628: EHCI_QH_SET_EPS(speed) |
1629: EHCI_QH_DTC |
1630: EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1631: (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1632: EHCI_QH_CTL : 0) |
1633: EHCI_QH_SET_NRL(naks)
1634: );
1635: sqh->qh.qh_endphub = htole32(
1636: EHCI_QH_SET_MULT(1) |
1637: EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0)
1638: );
1.167 jakllsch 1639: if (speed != EHCI_QH_SPEED_HIGH)
1640: sqh->qh.qh_endphub |= htole32(
1641: EHCI_QH_SET_PORT(hshubport) |
1642: EHCI_QH_SET_HUBA(hshubaddr) |
1643: EHCI_QH_SET_CMASK(0x08) /* XXX */
1644: );
1.139 jmcneill 1645: sqh->qh.qh_curqtd = EHCI_NULL;
1646: /* Fill the overlay qTD */
1647: sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1648: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1649: sqh->qh.qh_qtd.qtd_status = htole32(0);
1650:
1651: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1652: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1653: epipe->sqh = sqh;
1654: } else {
1655: sqh = NULL;
1656: } /*xfertype == UE_ISOC*/
1.5 augustss 1657:
1.10 augustss 1658: switch (xfertype) {
1659: case UE_CONTROL:
1.33 augustss 1660: err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1.10 augustss 1661: 0, &epipe->u.ctl.reqdma);
1.25 augustss 1662: #ifdef EHCI_DEBUG
1663: if (err)
1664: printf("ehci_open: usb_allocmem()=%d\n", err);
1665: #endif
1.10 augustss 1666: if (err)
1.116 drochner 1667: goto bad;
1.11 augustss 1668: pipe->methods = &ehci_device_ctrl_methods;
1.10 augustss 1669: s = splusb();
1.11 augustss 1670: ehci_add_qh(sqh, sc->sc_async_head);
1.10 augustss 1671: splx(s);
1672: break;
1673: case UE_BULK:
1674: pipe->methods = &ehci_device_bulk_methods;
1675: s = splusb();
1.11 augustss 1676: ehci_add_qh(sqh, sc->sc_async_head);
1.10 augustss 1677: splx(s);
1678: break;
1.24 augustss 1679: case UE_INTERRUPT:
1680: pipe->methods = &ehci_device_intr_methods;
1.78 augustss 1681: ival = pipe->interval;
1.116 drochner 1682: if (ival == USBD_DEFAULT_INTERVAL) {
1683: if (speed == EHCI_QH_SPEED_HIGH) {
1684: if (ed->bInterval > 16) {
1685: /*
1686: * illegal with high-speed, but there
1687: * were documentation bugs in the spec,
1688: * so be generous
1689: */
1690: ival = 256;
1691: } else
1692: ival = (1 << (ed->bInterval - 1)) / 8;
1693: } else
1694: ival = ed->bInterval;
1695: }
1696: err = ehci_device_setintr(sc, sqh, ival);
1697: if (err)
1698: goto bad;
1699: break;
1.24 augustss 1700: case UE_ISOCHRONOUS:
1701: pipe->methods = &ehci_device_isoc_methods;
1.142 drochner 1702: if (ed->bInterval == 0 || ed->bInterval > 16) {
1.139 jmcneill 1703: printf("ehci: opening pipe with invalid bInterval\n");
1704: err = USBD_INVAL;
1705: goto bad;
1706: }
1707: if (UGETW(ed->wMaxPacketSize) == 0) {
1708: printf("ehci: zero length endpoint open request\n");
1709: err = USBD_INVAL;
1710: goto bad;
1711: }
1712: epipe->u.isoc.next_frame = 0;
1713: epipe->u.isoc.cur_xfers = 0;
1714: break;
1.10 augustss 1715: default:
1.139 jmcneill 1716: DPRINTF(("ehci: bad xfer type %d\n", xfertype));
1.116 drochner 1717: err = USBD_INVAL;
1718: goto bad;
1.5 augustss 1719: }
1720: return (USBD_NORMAL_COMPLETION);
1721:
1.116 drochner 1722: bad:
1.139 jmcneill 1723: if (sqh != NULL)
1724: ehci_free_sqh(sc, sqh);
1.116 drochner 1725: return (err);
1.10 augustss 1726: }
1727:
1728: /*
1729: * Add an ED to the schedule. Called at splusb().
1730: */
1.164 uebayasi 1731: Static void
1.10 augustss 1732: ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1733: {
1734: SPLUSBCHECK;
1735:
1.138 bouyer 1736: usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
1737: sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE);
1.10 augustss 1738: sqh->next = head->next;
1739: sqh->qh.qh_link = head->qh.qh_link;
1.138 bouyer 1740: usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
1741: sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE);
1.10 augustss 1742: head->next = sqh;
1.15 augustss 1743: head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1.138 bouyer 1744: usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
1745: sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE);
1.10 augustss 1746:
1747: #ifdef EHCI_DEBUG
1.22 augustss 1748: if (ehcidebug > 5) {
1.10 augustss 1749: printf("ehci_add_qh:\n");
1750: ehci_dump_sqh(sqh);
1751: }
1.5 augustss 1752: #endif
1753: }
1754:
1.10 augustss 1755: /*
1756: * Remove an ED from the schedule. Called at splusb().
1757: */
1.164 uebayasi 1758: Static void
1.10 augustss 1759: ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1760: {
1.33 augustss 1761: ehci_soft_qh_t *p;
1.10 augustss 1762:
1763: SPLUSBCHECK;
1764: /* XXX */
1.42 augustss 1765: for (p = head; p != NULL && p->next != sqh; p = p->next)
1.10 augustss 1766: ;
1767: if (p == NULL)
1.37 provos 1768: panic("ehci_rem_qh: ED not found");
1.138 bouyer 1769: usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
1770: sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE);
1.10 augustss 1771: p->next = sqh->next;
1772: p->qh.qh_link = sqh->qh.qh_link;
1.138 bouyer 1773: usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link),
1774: sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE);
1.10 augustss 1775:
1.11 augustss 1776: ehci_sync_hc(sc);
1777: }
1778:
1.164 uebayasi 1779: Static void
1.23 augustss 1780: ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1781: {
1.85 augustss 1782: int i;
1.87 augustss 1783: u_int32_t status;
1.85 augustss 1784:
1.87 augustss 1785: /* Save toggle bit and ping status. */
1.138 bouyer 1786: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1787: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.87 augustss 1788: status = sqh->qh.qh_qtd.qtd_status &
1789: htole32(EHCI_QTD_TOGGLE_MASK |
1790: EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
1.85 augustss 1791: /* Set HALTED to make hw leave it alone. */
1792: sqh->qh.qh_qtd.qtd_status =
1793: htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
1.138 bouyer 1794: usb_syncmem(&sqh->dma,
1795: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
1796: sizeof(sqh->qh.qh_qtd.qtd_status),
1797: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.23 augustss 1798: sqh->qh.qh_curqtd = 0;
1799: sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1.179 jmcneill 1800: sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1.85 augustss 1801: for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
1802: sqh->qh.qh_qtd.qtd_buffer[i] = 0;
1.23 augustss 1803: sqh->sqtd = sqtd;
1.138 bouyer 1804: usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1805: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.87 augustss 1806: /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
1807: sqh->qh.qh_qtd.qtd_status = status;
1.138 bouyer 1808: usb_syncmem(&sqh->dma,
1809: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
1810: sizeof(sqh->qh.qh_qtd.qtd_status),
1811: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.23 augustss 1812: }
1813:
1.11 augustss 1814: /*
1815: * Ensure that the HC has released all references to the QH. We do this
1816: * by asking for a Async Advance Doorbell interrupt and then we wait for
1817: * the interrupt.
1818: * To make this easier we first obtain exclusive use of the doorbell.
1819: */
1.164 uebayasi 1820: Static void
1.11 augustss 1821: ehci_sync_hc(ehci_softc_t *sc)
1822: {
1.15 augustss 1823: int s, error;
1.11 augustss 1824:
1.12 augustss 1825: if (sc->sc_dying) {
1826: DPRINTFN(2,("ehci_sync_hc: dying\n"));
1827: return;
1828: }
1829: DPRINTFN(2,("ehci_sync_hc: enter\n"));
1.126 ad 1830: mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */
1.10 augustss 1831: s = splhardusb();
1832: /* ask for doorbell */
1833: EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1.15 augustss 1834: DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1835: EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1836: error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */
1837: DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1838: EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1.10 augustss 1839: splx(s);
1.126 ad 1840: mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */
1.15 augustss 1841: #ifdef DIAGNOSTIC
1842: if (error)
1843: printf("ehci_sync_hc: tsleep() = %d\n", error);
1844: #endif
1.12 augustss 1845: DPRINTFN(2,("ehci_sync_hc: exit\n"));
1.10 augustss 1846: }
1847:
1.139 jmcneill 1848: /*Call at splusb*/
1.164 uebayasi 1849: Static void
1.139 jmcneill 1850: ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer)
1851: {
1852: struct ehci_soft_itd *itd, *prev;
1853:
1854: prev = NULL;
1855:
1856: if (exfer->itdstart == NULL || exfer->itdend == NULL)
1857: panic("ehci isoc xfer being freed, but with no itd chain\n");
1858:
1859: for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
1860: prev = itd->u.frame_list.prev;
1861: /* Unlink itd from hardware chain, or frame array */
1862: if (prev == NULL) { /* We're at the table head */
1863: sc->sc_softitds[itd->slot] = itd->u.frame_list.next;
1864: sc->sc_flist[itd->slot] = itd->itd.itd_next;
1865: usb_syncmem(&sc->sc_fldma,
1866: sizeof(ehci_link_t) * itd->slot,
1867: sizeof(ehci_link_t),
1868: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1869:
1870: if (itd->u.frame_list.next != NULL)
1871: itd->u.frame_list.next->u.frame_list.prev = NULL;
1872: } else {
1873: /* XXX this part is untested... */
1874: prev->itd.itd_next = itd->itd.itd_next;
1875: usb_syncmem(&itd->dma,
1876: itd->offs + offsetof(ehci_itd_t, itd_next),
1877: sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE);
1878:
1879: prev->u.frame_list.next = itd->u.frame_list.next;
1880: if (itd->u.frame_list.next != NULL)
1881: itd->u.frame_list.next->u.frame_list.prev = prev;
1882: }
1883: }
1884:
1885: prev = NULL;
1886: for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
1887: if (prev != NULL)
1888: ehci_free_itd(sc, prev);
1889: prev = itd;
1890: }
1891: if (prev)
1892: ehci_free_itd(sc, prev);
1893: exfer->itdstart = NULL;
1894: exfer->itdend = NULL;
1895: }
1896:
1.5 augustss 1897: /***********/
1898:
1899: /*
1900: * Data structures and routines to emulate the root hub.
1901: */
1902: Static usb_device_descriptor_t ehci_devd = {
1903: USB_DEVICE_DESCRIPTOR_SIZE,
1904: UDESC_DEVICE, /* type */
1905: {0x00, 0x02}, /* USB version */
1906: UDCLASS_HUB, /* class */
1907: UDSUBCLASS_HUB, /* subclass */
1.11 augustss 1908: UDPROTO_HSHUBSTT, /* protocol */
1.5 augustss 1909: 64, /* max packet */
1910: {0},{0},{0x00,0x01}, /* device id */
1911: 1,2,0, /* string indicies */
1912: 1 /* # of configurations */
1913: };
1914:
1.123 drochner 1915: Static const usb_device_qualifier_t ehci_odevd = {
1.11 augustss 1916: USB_DEVICE_DESCRIPTOR_SIZE,
1917: UDESC_DEVICE_QUALIFIER, /* type */
1918: {0x00, 0x02}, /* USB version */
1919: UDCLASS_HUB, /* class */
1920: UDSUBCLASS_HUB, /* subclass */
1921: UDPROTO_FSHUB, /* protocol */
1922: 64, /* max packet */
1923: 1, /* # of configurations */
1924: 0
1925: };
1926:
1.123 drochner 1927: Static const usb_config_descriptor_t ehci_confd = {
1.5 augustss 1928: USB_CONFIG_DESCRIPTOR_SIZE,
1929: UDESC_CONFIG,
1930: {USB_CONFIG_DESCRIPTOR_SIZE +
1931: USB_INTERFACE_DESCRIPTOR_SIZE +
1932: USB_ENDPOINT_DESCRIPTOR_SIZE},
1933: 1,
1934: 1,
1935: 0,
1.120 drochner 1936: UC_ATTR_MBO | UC_SELF_POWERED,
1.5 augustss 1937: 0 /* max power */
1938: };
1939:
1.123 drochner 1940: Static const usb_interface_descriptor_t ehci_ifcd = {
1.5 augustss 1941: USB_INTERFACE_DESCRIPTOR_SIZE,
1942: UDESC_INTERFACE,
1943: 0,
1944: 0,
1945: 1,
1946: UICLASS_HUB,
1947: UISUBCLASS_HUB,
1.11 augustss 1948: UIPROTO_HSHUBSTT,
1.5 augustss 1949: 0
1950: };
1951:
1.123 drochner 1952: Static const usb_endpoint_descriptor_t ehci_endpd = {
1.5 augustss 1953: USB_ENDPOINT_DESCRIPTOR_SIZE,
1954: UDESC_ENDPOINT,
1955: UE_DIR_IN | EHCI_INTR_ENDPT,
1956: UE_INTERRUPT,
1957: {8, 0}, /* max packet */
1.118 drochner 1958: 12
1.5 augustss 1959: };
1960:
1.123 drochner 1961: Static const usb_hub_descriptor_t ehci_hubd = {
1.5 augustss 1962: USB_HUB_DESCRIPTOR_SIZE,
1963: UDESC_HUB,
1964: 0,
1965: {0,0},
1966: 0,
1967: 0,
1.111 christos 1968: {""},
1969: {""},
1.5 augustss 1970: };
1971:
1972: /*
1973: * Simulate a hardware hub by handling all the necessary requests.
1974: */
1975: Static usbd_status
1976: ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
1977: {
1978: usbd_status err;
1979:
1980: /* Insert last in queue. */
1981: err = usb_insert_transfer(xfer);
1982: if (err)
1983: return (err);
1984:
1985: /* Pipe isn't running, start first */
1986: return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1987: }
1988:
1989: Static usbd_status
1990: ehci_root_ctrl_start(usbd_xfer_handle xfer)
1991: {
1.134 drochner 1992: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.5 augustss 1993: usb_device_request_t *req;
1994: void *buf = NULL;
1995: int port, i;
1996: int s, len, value, index, l, totlen = 0;
1997: usb_port_status_t ps;
1998: usb_hub_descriptor_t hubd;
1999: usbd_status err;
2000: u_int32_t v;
2001:
2002: if (sc->sc_dying)
2003: return (USBD_IOERROR);
2004:
2005: #ifdef DIAGNOSTIC
2006: if (!(xfer->rqflags & URQ_REQUEST))
2007: /* XXX panic */
2008: return (USBD_INVAL);
2009: #endif
2010: req = &xfer->request;
2011:
1.72 augustss 2012: DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n",
1.5 augustss 2013: req->bmRequestType, req->bRequest));
2014:
2015: len = UGETW(req->wLength);
2016: value = UGETW(req->wValue);
2017: index = UGETW(req->wIndex);
2018:
2019: if (len != 0)
1.30 augustss 2020: buf = KERNADDR(&xfer->dmabuf, 0);
1.5 augustss 2021:
2022: #define C(x,y) ((x) | ((y) << 8))
2023: switch(C(req->bRequest, req->bmRequestType)) {
2024: case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2025: case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2026: case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1.33 augustss 2027: /*
1.5 augustss 2028: * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2029: * for the integrated root hub.
2030: */
2031: break;
2032: case C(UR_GET_CONFIG, UT_READ_DEVICE):
2033: if (len > 0) {
2034: *(u_int8_t *)buf = sc->sc_conf;
2035: totlen = 1;
2036: }
2037: break;
2038: case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1.72 augustss 2039: DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value));
1.109 christos 2040: if (len == 0)
2041: break;
1.5 augustss 2042: switch(value >> 8) {
2043: case UDESC_DEVICE:
2044: if ((value & 0xff) != 0) {
2045: err = USBD_IOERROR;
2046: goto ret;
2047: }
2048: totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2049: USETW(ehci_devd.idVendor, sc->sc_id_vendor);
2050: memcpy(buf, &ehci_devd, l);
2051: break;
1.33 augustss 2052: /*
1.11 augustss 2053: * We can't really operate at another speed, but the spec says
2054: * we need this descriptor.
2055: */
2056: case UDESC_DEVICE_QUALIFIER:
2057: if ((value & 0xff) != 0) {
2058: err = USBD_IOERROR;
2059: goto ret;
2060: }
2061: totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2062: memcpy(buf, &ehci_odevd, l);
2063: break;
1.33 augustss 2064: /*
1.11 augustss 2065: * We can't really operate at another speed, but the spec says
2066: * we need this descriptor.
2067: */
2068: case UDESC_OTHER_SPEED_CONFIGURATION:
1.5 augustss 2069: case UDESC_CONFIG:
2070: if ((value & 0xff) != 0) {
2071: err = USBD_IOERROR;
2072: goto ret;
2073: }
2074: totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
2075: memcpy(buf, &ehci_confd, l);
1.11 augustss 2076: ((usb_config_descriptor_t *)buf)->bDescriptorType =
2077: value >> 8;
1.5 augustss 2078: buf = (char *)buf + l;
2079: len -= l;
2080: l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
2081: totlen += l;
2082: memcpy(buf, &ehci_ifcd, l);
2083: buf = (char *)buf + l;
2084: len -= l;
2085: l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
2086: totlen += l;
2087: memcpy(buf, &ehci_endpd, l);
2088: break;
2089: case UDESC_STRING:
1.131 drochner 2090: #define sd ((usb_string_descriptor_t *)buf)
1.5 augustss 2091: switch (value & 0xff) {
1.88 augustss 2092: case 0: /* Language table */
1.131 drochner 2093: totlen = usb_makelangtbl(sd, len);
1.88 augustss 2094: break;
1.5 augustss 2095: case 1: /* Vendor */
1.131 drochner 2096: totlen = usb_makestrdesc(sd, len,
2097: sc->sc_vendor);
1.5 augustss 2098: break;
2099: case 2: /* Product */
1.131 drochner 2100: totlen = usb_makestrdesc(sd, len,
2101: "EHCI root hub");
1.5 augustss 2102: break;
2103: }
1.131 drochner 2104: #undef sd
1.5 augustss 2105: break;
2106: default:
2107: err = USBD_IOERROR;
2108: goto ret;
2109: }
2110: break;
2111: case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2112: if (len > 0) {
2113: *(u_int8_t *)buf = 0;
2114: totlen = 1;
2115: }
2116: break;
2117: case C(UR_GET_STATUS, UT_READ_DEVICE):
2118: if (len > 1) {
2119: USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
2120: totlen = 2;
2121: }
2122: break;
2123: case C(UR_GET_STATUS, UT_READ_INTERFACE):
2124: case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2125: if (len > 1) {
2126: USETW(((usb_status_t *)buf)->wStatus, 0);
2127: totlen = 2;
2128: }
2129: break;
2130: case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2131: if (value >= USB_MAX_DEVICES) {
2132: err = USBD_IOERROR;
2133: goto ret;
2134: }
2135: sc->sc_addr = value;
2136: break;
2137: case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2138: if (value != 0 && value != 1) {
2139: err = USBD_IOERROR;
2140: goto ret;
2141: }
2142: sc->sc_conf = value;
2143: break;
2144: case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2145: break;
2146: case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2147: case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2148: case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2149: err = USBD_IOERROR;
2150: goto ret;
2151: case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2152: break;
2153: case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2154: break;
2155: /* Hub requests */
2156: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2157: break;
2158: case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1.106 augustss 2159: DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE "
1.5 augustss 2160: "port=%d feature=%d\n",
2161: index, value));
2162: if (index < 1 || index > sc->sc_noport) {
2163: err = USBD_IOERROR;
2164: goto ret;
2165: }
2166: port = EHCI_PORTSC(index);
1.106 augustss 2167: v = EOREAD4(sc, port);
2168: DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2169: v &= ~EHCI_PS_CLEAR;
1.5 augustss 2170: switch(value) {
2171: case UHF_PORT_ENABLE:
2172: EOWRITE4(sc, port, v &~ EHCI_PS_PE);
2173: break;
2174: case UHF_PORT_SUSPEND:
1.137 drochner 2175: if (!(v & EHCI_PS_SUSP)) /* not suspended */
2176: break;
2177: v &= ~EHCI_PS_SUSP;
2178: EOWRITE4(sc, port, v | EHCI_PS_FPR);
2179: /* see USB2 spec ch. 7.1.7.7 */
2180: usb_delay_ms(&sc->sc_bus, 20);
2181: EOWRITE4(sc, port, v);
2182: usb_delay_ms(&sc->sc_bus, 2);
2183: #ifdef DEBUG
2184: v = EOREAD4(sc, port);
2185: if (v & (EHCI_PS_FPR | EHCI_PS_SUSP))
2186: printf("ehci: resume failed: %x\n", v);
2187: #endif
1.5 augustss 2188: break;
2189: case UHF_PORT_POWER:
1.106 augustss 2190: if (sc->sc_hasppc)
2191: EOWRITE4(sc, port, v &~ EHCI_PS_PP);
1.5 augustss 2192: break;
1.14 augustss 2193: case UHF_PORT_TEST:
1.72 augustss 2194: DPRINTFN(2,("ehci_root_ctrl_start: clear port test "
1.14 augustss 2195: "%d\n", index));
2196: break;
2197: case UHF_PORT_INDICATOR:
1.72 augustss 2198: DPRINTFN(2,("ehci_root_ctrl_start: clear port ind "
1.14 augustss 2199: "%d\n", index));
2200: EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
2201: break;
1.5 augustss 2202: case UHF_C_PORT_CONNECTION:
2203: EOWRITE4(sc, port, v | EHCI_PS_CSC);
2204: break;
2205: case UHF_C_PORT_ENABLE:
2206: EOWRITE4(sc, port, v | EHCI_PS_PEC);
2207: break;
2208: case UHF_C_PORT_SUSPEND:
2209: /* how? */
2210: break;
2211: case UHF_C_PORT_OVER_CURRENT:
2212: EOWRITE4(sc, port, v | EHCI_PS_OCC);
2213: break;
2214: case UHF_C_PORT_RESET:
1.106 augustss 2215: sc->sc_isreset[index] = 0;
1.5 augustss 2216: break;
2217: default:
2218: err = USBD_IOERROR;
2219: goto ret;
2220: }
2221: #if 0
2222: switch(value) {
2223: case UHF_C_PORT_CONNECTION:
2224: case UHF_C_PORT_ENABLE:
2225: case UHF_C_PORT_SUSPEND:
2226: case UHF_C_PORT_OVER_CURRENT:
2227: case UHF_C_PORT_RESET:
2228: default:
2229: break;
2230: }
2231: #endif
2232: break;
2233: case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1.109 christos 2234: if (len == 0)
2235: break;
1.51 toshii 2236: if ((value & 0xff) != 0) {
1.5 augustss 2237: err = USBD_IOERROR;
2238: goto ret;
2239: }
2240: hubd = ehci_hubd;
2241: hubd.bNbrPorts = sc->sc_noport;
2242: v = EOREAD4(sc, EHCI_HCSPARAMS);
2243: USETW(hubd.wHubCharacteristics,
1.14 augustss 2244: EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
1.78 augustss 2245: EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS))
1.164 uebayasi 2246: ? UHD_PORT_IND : 0);
1.5 augustss 2247: hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
1.33 augustss 2248: for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1.5 augustss 2249: hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
2250: hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2251: l = min(len, hubd.bDescLength);
2252: totlen = l;
2253: memcpy(buf, &hubd, l);
2254: break;
2255: case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2256: if (len != 4) {
2257: err = USBD_IOERROR;
2258: goto ret;
2259: }
2260: memset(buf, 0, len); /* ? XXX */
2261: totlen = len;
2262: break;
2263: case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1.72 augustss 2264: DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
1.5 augustss 2265: index));
2266: if (index < 1 || index > sc->sc_noport) {
2267: err = USBD_IOERROR;
2268: goto ret;
2269: }
2270: if (len != 4) {
2271: err = USBD_IOERROR;
2272: goto ret;
2273: }
2274: v = EOREAD4(sc, EHCI_PORTSC(index));
1.178 matt 2275: DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v));
1.172 matt 2276:
1.178 matt 2277: i = UPS_HIGH_SPEED;
2278: #if 0
1.172 matt 2279: if (sc->sc_flags & EHCIF_ETTF) {
2280: /*
2281: * If we are doing embedded transaction translation,
2282: * then directly attached LS/FS devices are reset by
2283: * the EHCI controller itself. PSPD is encoded
1.183 jakllsch 2284: * the same way as in USBSTATUS.
1.172 matt 2285: */
2286: i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED;
2287: }
1.178 matt 2288: #endif
1.5 augustss 2289: if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
2290: if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
2291: if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
2292: if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
2293: if (v & EHCI_PS_PR) i |= UPS_RESET;
2294: if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
1.170 kiyohara 2295: if (sc->sc_vendor_port_status)
2296: i = sc->sc_vendor_port_status(sc, v, i);
1.5 augustss 2297: USETW(ps.wPortStatus, i);
2298: i = 0;
2299: if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
2300: if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
2301: if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
1.106 augustss 2302: if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
1.5 augustss 2303: USETW(ps.wPortChange, i);
2304: l = min(len, sizeof ps);
2305: memcpy(buf, &ps, l);
2306: totlen = l;
2307: break;
2308: case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2309: err = USBD_IOERROR;
2310: goto ret;
2311: case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2312: break;
2313: case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2314: if (index < 1 || index > sc->sc_noport) {
2315: err = USBD_IOERROR;
2316: goto ret;
2317: }
2318: port = EHCI_PORTSC(index);
1.106 augustss 2319: v = EOREAD4(sc, port);
2320: DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2321: v &= ~EHCI_PS_CLEAR;
1.5 augustss 2322: switch(value) {
2323: case UHF_PORT_ENABLE:
2324: EOWRITE4(sc, port, v | EHCI_PS_PE);
2325: break;
2326: case UHF_PORT_SUSPEND:
2327: EOWRITE4(sc, port, v | EHCI_PS_SUSP);
2328: break;
2329: case UHF_PORT_RESET:
1.72 augustss 2330: DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
1.5 augustss 2331: index));
1.172 matt 2332: if (EHCI_PS_IS_LOWSPEED(v)
2333: && sc->sc_ncomp > 0
2334: && !(sc->sc_flags & EHCIF_ETTF)) {
2335: /*
2336: * Low speed device on non-ETTF controller or
2337: * unaccompanied controller, give up ownership.
2338: */
1.6 augustss 2339: ehci_disown(sc, index, 1);
2340: break;
2341: }
1.8 augustss 2342: /* Start reset sequence. */
2343: v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
1.5 augustss 2344: EOWRITE4(sc, port, v | EHCI_PS_PR);
1.8 augustss 2345: /* Wait for reset to complete. */
1.13 augustss 2346: usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
1.17 augustss 2347: if (sc->sc_dying) {
2348: err = USBD_IOERROR;
2349: goto ret;
2350: }
1.172 matt 2351: /*
2352: * An embedded transaction translater will automatically
2353: * terminate the reset sequence so there's no need to
2354: * it.
2355: */
1.178 matt 2356: v = EOREAD4(sc, port);
2357: if (v & EHCI_PS_PR) {
1.172 matt 2358: /* Terminate reset sequence. */
1.173 jmcneill 2359: EOWRITE4(sc, port, v & ~EHCI_PS_PR);
1.172 matt 2360: /* Wait for HC to complete reset. */
2361: usb_delay_ms(&sc->sc_bus,
2362: EHCI_PORT_RESET_COMPLETE);
2363: if (sc->sc_dying) {
2364: err = USBD_IOERROR;
2365: goto ret;
2366: }
1.17 augustss 2367: }
1.172 matt 2368:
1.8 augustss 2369: v = EOREAD4(sc, port);
2370: DPRINTF(("ehci after reset, status=0x%08x\n", v));
2371: if (v & EHCI_PS_PR) {
2372: printf("%s: port reset timeout\n",
1.134 drochner 2373: device_xname(sc->sc_dev));
1.8 augustss 2374: return (USBD_TIMEOUT);
1.5 augustss 2375: }
1.8 augustss 2376: if (!(v & EHCI_PS_PE)) {
1.6 augustss 2377: /* Not a high speed device, give up ownership.*/
2378: ehci_disown(sc, index, 0);
2379: break;
2380: }
1.106 augustss 2381: sc->sc_isreset[index] = 1;
1.8 augustss 2382: DPRINTF(("ehci port %d reset, status = 0x%08x\n",
1.6 augustss 2383: index, v));
1.5 augustss 2384: break;
2385: case UHF_PORT_POWER:
1.72 augustss 2386: DPRINTFN(2,("ehci_root_ctrl_start: set port power "
1.106 augustss 2387: "%d (has PPC = %d)\n", index,
2388: sc->sc_hasppc));
2389: if (sc->sc_hasppc)
2390: EOWRITE4(sc, port, v | EHCI_PS_PP);
1.5 augustss 2391: break;
1.11 augustss 2392: case UHF_PORT_TEST:
1.72 augustss 2393: DPRINTFN(2,("ehci_root_ctrl_start: set port test "
1.11 augustss 2394: "%d\n", index));
2395: break;
2396: case UHF_PORT_INDICATOR:
1.72 augustss 2397: DPRINTFN(2,("ehci_root_ctrl_start: set port ind "
1.11 augustss 2398: "%d\n", index));
1.14 augustss 2399: EOWRITE4(sc, port, v | EHCI_PS_PIC);
1.11 augustss 2400: break;
1.5 augustss 2401: default:
2402: err = USBD_IOERROR;
2403: goto ret;
2404: }
2405: break;
1.11 augustss 2406: case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
2407: case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
2408: case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
2409: case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
2410: break;
1.5 augustss 2411: default:
2412: err = USBD_IOERROR;
2413: goto ret;
2414: }
2415: xfer->actlen = totlen;
2416: err = USBD_NORMAL_COMPLETION;
2417: ret:
2418: xfer->status = err;
2419: s = splusb();
2420: usb_transfer_complete(xfer);
2421: splx(s);
2422: return (USBD_IN_PROGRESS);
1.6 augustss 2423: }
2424:
1.164 uebayasi 2425: Static void
1.115 christos 2426: ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
1.6 augustss 2427: {
1.24 augustss 2428: int port;
1.6 augustss 2429: u_int32_t v;
2430:
2431: DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
2432: #ifdef DIAGNOSTIC
2433: if (sc->sc_npcomp != 0) {
1.24 augustss 2434: int i = (index-1) / sc->sc_npcomp;
1.6 augustss 2435: if (i >= sc->sc_ncomp)
2436: printf("%s: strange port\n",
1.134 drochner 2437: device_xname(sc->sc_dev));
1.6 augustss 2438: else
2439: printf("%s: handing over %s speed device on "
2440: "port %d to %s\n",
1.134 drochner 2441: device_xname(sc->sc_dev),
1.6 augustss 2442: lowspeed ? "low" : "full",
1.134 drochner 2443: index, device_xname(sc->sc_comps[i]));
1.6 augustss 2444: } else {
1.134 drochner 2445: printf("%s: npcomp == 0\n", device_xname(sc->sc_dev));
1.6 augustss 2446: }
2447: #endif
2448: port = EHCI_PORTSC(index);
2449: v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2450: EOWRITE4(sc, port, v | EHCI_PS_PO);
1.5 augustss 2451: }
2452:
2453: /* Abort a root control request. */
2454: Static void
1.115 christos 2455: ehci_root_ctrl_abort(usbd_xfer_handle xfer)
1.5 augustss 2456: {
2457: /* Nothing to do, all transfers are synchronous. */
2458: }
2459:
2460: /* Close the root pipe. */
2461: Static void
1.115 christos 2462: ehci_root_ctrl_close(usbd_pipe_handle pipe)
1.5 augustss 2463: {
2464: DPRINTF(("ehci_root_ctrl_close\n"));
2465: /* Nothing to do. */
2466: }
2467:
1.164 uebayasi 2468: Static void
1.5 augustss 2469: ehci_root_intr_done(usbd_xfer_handle xfer)
2470: {
1.78 augustss 2471: xfer->hcpriv = NULL;
1.5 augustss 2472: }
2473:
2474: Static usbd_status
2475: ehci_root_intr_transfer(usbd_xfer_handle xfer)
2476: {
2477: usbd_status err;
2478:
2479: /* Insert last in queue. */
2480: err = usb_insert_transfer(xfer);
2481: if (err)
2482: return (err);
2483:
2484: /* Pipe isn't running, start first */
2485: return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2486: }
2487:
2488: Static usbd_status
2489: ehci_root_intr_start(usbd_xfer_handle xfer)
2490: {
2491: usbd_pipe_handle pipe = xfer->pipe;
1.134 drochner 2492: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.5 augustss 2493:
2494: if (sc->sc_dying)
2495: return (USBD_IOERROR);
2496:
2497: sc->sc_intrxfer = xfer;
2498:
2499: return (USBD_IN_PROGRESS);
2500: }
2501:
2502: /* Abort a root interrupt request. */
2503: Static void
2504: ehci_root_intr_abort(usbd_xfer_handle xfer)
2505: {
2506: int s;
2507:
2508: if (xfer->pipe->intrxfer == xfer) {
2509: DPRINTF(("ehci_root_intr_abort: remove\n"));
2510: xfer->pipe->intrxfer = NULL;
2511: }
2512: xfer->status = USBD_CANCELLED;
2513: s = splusb();
2514: usb_transfer_complete(xfer);
2515: splx(s);
2516: }
2517:
2518: /* Close the root pipe. */
2519: Static void
2520: ehci_root_intr_close(usbd_pipe_handle pipe)
2521: {
1.134 drochner 2522: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.33 augustss 2523:
1.5 augustss 2524: DPRINTF(("ehci_root_intr_close\n"));
2525:
2526: sc->sc_intrxfer = NULL;
2527: }
2528:
1.164 uebayasi 2529: Static void
1.5 augustss 2530: ehci_root_ctrl_done(usbd_xfer_handle xfer)
2531: {
1.78 augustss 2532: xfer->hcpriv = NULL;
1.9 augustss 2533: }
2534:
2535: /************************/
2536:
1.164 uebayasi 2537: Static ehci_soft_qh_t *
1.9 augustss 2538: ehci_alloc_sqh(ehci_softc_t *sc)
2539: {
2540: ehci_soft_qh_t *sqh;
2541: usbd_status err;
2542: int i, offs;
2543: usb_dma_t dma;
2544:
2545: if (sc->sc_freeqhs == NULL) {
2546: DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
2547: err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2548: EHCI_PAGE_SIZE, &dma);
1.25 augustss 2549: #ifdef EHCI_DEBUG
2550: if (err)
2551: printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
2552: #endif
1.9 augustss 2553: if (err)
1.11 augustss 2554: return (NULL);
1.9 augustss 2555: for(i = 0; i < EHCI_SQH_CHUNK; i++) {
2556: offs = i * EHCI_SQH_SIZE;
1.30 augustss 2557: sqh = KERNADDR(&dma, offs);
1.31 augustss 2558: sqh->physaddr = DMAADDR(&dma, offs);
1.138 bouyer 2559: sqh->dma = dma;
2560: sqh->offs = offs;
1.9 augustss 2561: sqh->next = sc->sc_freeqhs;
2562: sc->sc_freeqhs = sqh;
2563: }
2564: }
2565: sqh = sc->sc_freeqhs;
2566: sc->sc_freeqhs = sqh->next;
2567: memset(&sqh->qh, 0, sizeof(ehci_qh_t));
1.11 augustss 2568: sqh->next = NULL;
1.9 augustss 2569: return (sqh);
2570: }
2571:
1.164 uebayasi 2572: Static void
1.9 augustss 2573: ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2574: {
2575: sqh->next = sc->sc_freeqhs;
2576: sc->sc_freeqhs = sqh;
2577: }
2578:
1.164 uebayasi 2579: Static ehci_soft_qtd_t *
1.9 augustss 2580: ehci_alloc_sqtd(ehci_softc_t *sc)
2581: {
2582: ehci_soft_qtd_t *sqtd;
2583: usbd_status err;
2584: int i, offs;
2585: usb_dma_t dma;
2586: int s;
2587:
2588: if (sc->sc_freeqtds == NULL) {
2589: DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
2590: err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
2591: EHCI_PAGE_SIZE, &dma);
1.25 augustss 2592: #ifdef EHCI_DEBUG
2593: if (err)
2594: printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
2595: #endif
1.9 augustss 2596: if (err)
2597: return (NULL);
2598: s = splusb();
2599: for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2600: offs = i * EHCI_SQTD_SIZE;
1.30 augustss 2601: sqtd = KERNADDR(&dma, offs);
1.31 augustss 2602: sqtd->physaddr = DMAADDR(&dma, offs);
1.138 bouyer 2603: sqtd->dma = dma;
2604: sqtd->offs = offs;
1.9 augustss 2605: sqtd->nextqtd = sc->sc_freeqtds;
2606: sc->sc_freeqtds = sqtd;
2607: }
2608: splx(s);
2609: }
2610:
2611: s = splusb();
2612: sqtd = sc->sc_freeqtds;
2613: sc->sc_freeqtds = sqtd->nextqtd;
2614: memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2615: sqtd->nextqtd = NULL;
2616: sqtd->xfer = NULL;
2617: splx(s);
2618:
2619: return (sqtd);
2620: }
2621:
1.164 uebayasi 2622: Static void
1.9 augustss 2623: ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2624: {
2625: int s;
2626:
2627: s = splusb();
2628: sqtd->nextqtd = sc->sc_freeqtds;
2629: sc->sc_freeqtds = sqtd;
2630: splx(s);
2631: }
2632:
1.164 uebayasi 2633: Static usbd_status
1.25 augustss 2634: ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
1.15 augustss 2635: int alen, int rd, usbd_xfer_handle xfer,
2636: ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2637: {
2638: ehci_soft_qtd_t *next, *cur;
1.22 augustss 2639: ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys;
1.15 augustss 2640: u_int32_t qtdstatus;
1.55 mycroft 2641: int len, curlen, mps;
2642: int i, tog;
1.15 augustss 2643: usb_dma_t *dma = &xfer->dmabuf;
1.102 augustss 2644: u_int16_t flags = xfer->flags;
1.15 augustss 2645:
1.25 augustss 2646: DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
1.15 augustss 2647:
2648: len = alen;
1.31 augustss 2649: dataphys = DMAADDR(dma, 0);
1.22 augustss 2650: dataphyslastpage = EHCI_PAGE(dataphys + len - 1);
1.67 mycroft 2651: qtdstatus = EHCI_QTD_ACTIVE |
1.15 augustss 2652: EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2653: EHCI_QTD_SET_CERR(3)
2654: /* IOC set below */
2655: /* BYTES set below */
1.67 mycroft 2656: ;
1.55 mycroft 2657: mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2658: tog = epipe->nexttoggle;
1.64 mycroft 2659: qtdstatus |= EHCI_QTD_SET_TOGGLE(tog);
1.15 augustss 2660:
2661: cur = ehci_alloc_sqtd(sc);
1.25 augustss 2662: *sp = cur;
1.15 augustss 2663: if (cur == NULL)
2664: goto nomem;
1.138 bouyer 2665:
2666: usb_syncmem(dma, 0, alen,
2667: rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1.15 augustss 2668: for (;;) {
1.22 augustss 2669: dataphyspage = EHCI_PAGE(dataphys);
1.26 augustss 2670: /* The EHCI hardware can handle at most 5 pages. */
1.33 augustss 2671: if (dataphyslastpage - dataphyspage <
1.26 augustss 2672: EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) {
1.15 augustss 2673: /* we can handle it in this QTD */
2674: curlen = len;
2675: } else {
2676: /* must use multiple TDs, fill as much as possible. */
1.33 augustss 2677: curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE -
1.22 augustss 2678: EHCI_PAGE_OFFSET(dataphys);
1.25 augustss 2679: #ifdef DIAGNOSTIC
2680: if (curlen > len) {
1.26 augustss 2681: printf("ehci_alloc_sqtd_chain: curlen=0x%x "
2682: "len=0x%x offs=0x%x\n", curlen, len,
2683: EHCI_PAGE_OFFSET(dataphys));
2684: printf("lastpage=0x%x page=0x%x phys=0x%x\n",
2685: dataphyslastpage, dataphyspage,
2686: dataphys);
1.25 augustss 2687: curlen = len;
2688: }
2689: #endif
1.15 augustss 2690: /* the length must be a multiple of the max size */
1.55 mycroft 2691: curlen -= curlen % mps;
1.25 augustss 2692: DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, "
2693: "curlen=%d\n", curlen));
1.15 augustss 2694: #ifdef DIAGNOSTIC
2695: if (curlen == 0)
1.103 augustss 2696: panic("ehci_alloc_sqtd_chain: curlen == 0");
1.15 augustss 2697: #endif
2698: }
1.25 augustss 2699: DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x "
1.22 augustss 2700: "dataphyslastpage=0x%08x len=%d curlen=%d\n",
2701: dataphys, dataphyslastpage,
1.15 augustss 2702: len, curlen));
2703: len -= curlen;
2704:
1.102 augustss 2705: /*
1.110 blymn 2706: * Allocate another transfer if there's more data left,
2707: * or if force last short transfer flag is set and we're
1.102 augustss 2708: * allocating a multiple of the max packet size.
2709: */
2710: if (len != 0 ||
2711: ((curlen % mps) == 0 && !rd && curlen != 0 &&
2712: (flags & USBD_FORCE_SHORT_XFER))) {
1.15 augustss 2713: next = ehci_alloc_sqtd(sc);
2714: if (next == NULL)
2715: goto nomem;
1.66 mycroft 2716: nextphys = htole32(next->physaddr);
1.15 augustss 2717: } else {
2718: next = NULL;
2719: nextphys = EHCI_NULL;
2720: }
2721:
1.110 blymn 2722: for (i = 0; i * EHCI_PAGE_SIZE <
1.103 augustss 2723: curlen + EHCI_PAGE_OFFSET(dataphys); i++) {
1.15 augustss 2724: ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE;
2725: if (i != 0) /* use offset only in first buffer */
2726: a = EHCI_PAGE(a);
2727: cur->qtd.qtd_buffer[i] = htole32(a);
1.48 mycroft 2728: cur->qtd.qtd_buffer_hi[i] = 0;
1.25 augustss 2729: #ifdef DIAGNOSTIC
2730: if (i >= EHCI_QTD_NBUFFERS) {
2731: printf("ehci_alloc_sqtd_chain: i=%d\n", i);
2732: goto nomem;
2733: }
2734: #endif
1.15 augustss 2735: }
2736: cur->nextqtd = next;
1.66 mycroft 2737: cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys;
1.15 augustss 2738: cur->qtd.qtd_status =
1.67 mycroft 2739: htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen));
1.15 augustss 2740: cur->xfer = xfer;
1.18 augustss 2741: cur->len = curlen;
1.138 bouyer 2742:
1.29 augustss 2743: DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n",
2744: dataphys, dataphys + curlen));
1.55 mycroft 2745: /* adjust the toggle based on the number of packets in this
2746: qtd */
2747: if (((curlen + mps - 1) / mps) & 1) {
2748: tog ^= 1;
1.64 mycroft 2749: qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
1.55 mycroft 2750: }
1.102 augustss 2751: if (next == NULL)
1.15 augustss 2752: break;
1.138 bouyer 2753: usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
2754: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.25 augustss 2755: DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
1.174 drochner 2756: if (len)
2757: dataphys += curlen;
1.15 augustss 2758: cur = next;
2759: }
2760: cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
1.138 bouyer 2761: usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
2762: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 2763: *ep = cur;
1.55 mycroft 2764: epipe->nexttoggle = tog;
1.15 augustss 2765:
1.29 augustss 2766: DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2767: *sp, *ep));
2768:
1.15 augustss 2769: return (USBD_NORMAL_COMPLETION);
2770:
2771: nomem:
2772: /* XXX free chain */
1.25 augustss 2773: DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
1.15 augustss 2774: return (USBD_NOMEM);
2775: }
2776:
1.18 augustss 2777: Static void
1.25 augustss 2778: ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
1.18 augustss 2779: ehci_soft_qtd_t *sqtdend)
2780: {
2781: ehci_soft_qtd_t *p;
1.25 augustss 2782: int i;
1.18 augustss 2783:
1.29 augustss 2784: DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
2785: sqtd, sqtdend));
2786:
1.25 augustss 2787: for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
1.18 augustss 2788: p = sqtd->nextqtd;
2789: ehci_free_sqtd(sc, sqtd);
2790: }
2791: }
2792:
1.164 uebayasi 2793: Static ehci_soft_itd_t *
1.139 jmcneill 2794: ehci_alloc_itd(ehci_softc_t *sc)
2795: {
2796: struct ehci_soft_itd *itd, *freeitd;
2797: usbd_status err;
2798: int i, s, offs, frindex, previndex;
2799: usb_dma_t dma;
2800:
2801: s = splusb();
2802:
2803: /* Find an itd that wasn't freed this frame or last frame. This can
2804: * discard itds that were freed before frindex wrapped around
2805: * XXX - can this lead to thrashing? Could fix by enabling wrap-around
2806: * interrupt and fiddling with list when that happens */
2807: frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3;
2808: previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize;
2809:
2810: freeitd = NULL;
2811: LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) {
2812: if (itd == NULL)
2813: break;
2814: if (itd->slot != frindex && itd->slot != previndex) {
2815: freeitd = itd;
2816: break;
2817: }
2818: }
2819:
2820: if (freeitd == NULL) {
2821: DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n"));
2822: err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK,
2823: EHCI_PAGE_SIZE, &dma);
2824:
2825: if (err) {
2826: DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err));
2827: return NULL;
2828: }
2829:
2830: for (i = 0; i < EHCI_ITD_CHUNK; i++) {
2831: offs = i * EHCI_ITD_SIZE;
2832: itd = KERNADDR(&dma, offs);
2833: itd->physaddr = DMAADDR(&dma, offs);
1.183 jakllsch 2834: itd->dma = dma;
1.139 jmcneill 2835: itd->offs = offs;
2836: LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
2837: }
2838: freeitd = LIST_FIRST(&sc->sc_freeitds);
2839: }
2840:
2841: itd = freeitd;
2842: LIST_REMOVE(itd, u.free_list);
2843: memset(&itd->itd, 0, sizeof(ehci_itd_t));
2844: usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next),
2845: sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE |
2846: BUS_DMASYNC_PREREAD);
2847:
2848: itd->u.frame_list.next = NULL;
2849: itd->u.frame_list.prev = NULL;
2850: itd->xfer_next = NULL;
2851: itd->slot = 0;
2852: splx(s);
2853:
2854: return itd;
2855: }
2856:
1.164 uebayasi 2857: Static void
1.139 jmcneill 2858: ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd)
2859: {
2860: int s;
2861:
2862: s = splusb();
1.150 jmcneill 2863: LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
1.139 jmcneill 2864: splx(s);
2865: }
2866:
1.15 augustss 2867: /****************/
2868:
1.9 augustss 2869: /*
1.10 augustss 2870: * Close a reqular pipe.
2871: * Assumes that there are no pending transactions.
2872: */
1.164 uebayasi 2873: Static void
1.10 augustss 2874: ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2875: {
2876: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1.134 drochner 2877: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.10 augustss 2878: ehci_soft_qh_t *sqh = epipe->sqh;
2879: int s;
2880:
2881: s = splusb();
2882: ehci_rem_qh(sc, sqh, head);
2883: splx(s);
2884: ehci_free_sqh(sc, epipe->sqh);
2885: }
2886:
1.33 augustss 2887: /*
1.10 augustss 2888: * Abort a device request.
2889: * If this routine is called at splusb() it guarantees that the request
2890: * will be removed from the hardware scheduling and that the callback
2891: * for it will be called with USBD_CANCELLED status.
2892: * It's impossible to guarantee that the requested transfer will not
2893: * have happened since the hardware runs concurrently.
2894: * If the transaction has already happened we rely on the ordinary
2895: * interrupt processing to process it.
1.26 augustss 2896: * XXX This is most probably wrong.
1.10 augustss 2897: */
1.164 uebayasi 2898: Static void
1.10 augustss 2899: ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2900: {
1.26 augustss 2901: #define exfer EXFER(xfer)
1.10 augustss 2902: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
1.134 drochner 2903: ehci_softc_t *sc = epipe->pipe.device->bus->hci_private;
1.26 augustss 2904: ehci_soft_qh_t *sqh = epipe->sqh;
2905: ehci_soft_qtd_t *sqtd;
2906: ehci_physaddr_t cur;
2907: u_int32_t qhstatus;
1.11 augustss 2908: int s;
1.26 augustss 2909: int hit;
1.96 augustss 2910: int wake;
1.10 augustss 2911:
1.24 augustss 2912: DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
1.10 augustss 2913:
1.17 augustss 2914: if (sc->sc_dying) {
2915: /* If we're dying, just do the software part. */
2916: s = splusb();
2917: xfer->status = status; /* make software ignore it */
1.171 dyoung 2918: callout_stop(&xfer->timeout_handle);
1.17 augustss 2919: usb_transfer_complete(xfer);
2920: splx(s);
2921: return;
2922: }
2923:
1.139 jmcneill 2924: if (xfer->device->bus->intr_context)
1.37 provos 2925: panic("ehci_abort_xfer: not in process context");
1.10 augustss 2926:
1.11 augustss 2927: /*
1.96 augustss 2928: * If an abort is already in progress then just wait for it to
2929: * complete and return.
2930: */
2931: if (xfer->hcflags & UXFER_ABORTING) {
2932: DPRINTFN(2, ("ehci_abort_xfer: already aborting\n"));
2933: #ifdef DIAGNOSTIC
2934: if (status == USBD_TIMEOUT)
2935: printf("ehci_abort_xfer: TIMEOUT while aborting\n");
2936: #endif
2937: /* Override the status which might be USBD_TIMEOUT. */
2938: xfer->status = status;
2939: DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
2940: xfer->hcflags |= UXFER_ABORTWAIT;
2941: while (xfer->hcflags & UXFER_ABORTING)
2942: tsleep(&xfer->hcflags, PZERO, "ehciaw", 0);
2943: return;
2944: }
2945: xfer->hcflags |= UXFER_ABORTING;
2946:
2947: /*
1.11 augustss 2948: * Step 1: Make interrupt routine and hardware ignore xfer.
2949: */
2950: s = splusb();
2951: xfer->status = status; /* make software ignore it */
1.171 dyoung 2952: callout_stop(&xfer->timeout_handle);
1.138 bouyer 2953:
2954: usb_syncmem(&sqh->dma,
2955: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2956: sizeof(sqh->qh.qh_qtd.qtd_status),
2957: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.26 augustss 2958: qhstatus = sqh->qh.qh_qtd.qtd_status;
2959: sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
1.138 bouyer 2960: usb_syncmem(&sqh->dma,
2961: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2962: sizeof(sqh->qh.qh_qtd.qtd_status),
2963: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 2964: for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
1.138 bouyer 2965: usb_syncmem(&sqtd->dma,
2966: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
2967: sizeof(sqtd->qtd.qtd_status),
2968: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.26 augustss 2969: sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
1.138 bouyer 2970: usb_syncmem(&sqtd->dma,
2971: sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
2972: sizeof(sqtd->qtd.qtd_status),
2973: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 2974: if (sqtd == exfer->sqtdend)
2975: break;
2976: }
1.11 augustss 2977: splx(s);
2978:
1.33 augustss 2979: /*
1.11 augustss 2980: * Step 2: Wait until we know hardware has finished any possible
2981: * use of the xfer. Also make sure the soft interrupt routine
2982: * has run.
2983: */
1.26 augustss 2984: ehci_sync_hc(sc);
1.29 augustss 2985: s = splusb();
1.77 augustss 2986: #ifdef USB_USE_SOFTINTR
1.29 augustss 2987: sc->sc_softwake = 1;
1.77 augustss 2988: #endif /* USB_USE_SOFTINTR */
1.29 augustss 2989: usb_schedsoftintr(&sc->sc_bus);
1.77 augustss 2990: #ifdef USB_USE_SOFTINTR
1.29 augustss 2991: tsleep(&sc->sc_softwake, PZERO, "ehciab", 0);
1.77 augustss 2992: #endif /* USB_USE_SOFTINTR */
1.29 augustss 2993: splx(s);
1.33 augustss 2994:
2995: /*
1.11 augustss 2996: * Step 3: Remove any vestiges of the xfer from the hardware.
2997: * The complication here is that the hardware may have executed
2998: * beyond the xfer we're trying to abort. So as we're scanning
2999: * the TDs of this xfer we check if the hardware points to
3000: * any of them.
3001: */
3002: s = splusb(); /* XXX why? */
1.138 bouyer 3003:
3004: usb_syncmem(&sqh->dma,
3005: sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3006: sizeof(sqh->qh.qh_curqtd),
3007: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1.26 augustss 3008: cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
3009: hit = 0;
3010: for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
3011: hit |= cur == sqtd->physaddr;
3012: if (sqtd == exfer->sqtdend)
3013: break;
3014: }
3015: sqtd = sqtd->nextqtd;
3016: /* Zap curqtd register if hardware pointed inside the xfer. */
3017: if (hit && sqtd != NULL) {
3018: DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr));
3019: sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
1.138 bouyer 3020: usb_syncmem(&sqh->dma,
3021: sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
3022: sizeof(sqh->qh.qh_curqtd),
3023: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 3024: sqh->qh.qh_qtd.qtd_status = qhstatus;
1.138 bouyer 3025: usb_syncmem(&sqh->dma,
3026: sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
3027: sizeof(sqh->qh.qh_qtd.qtd_status),
3028: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.26 augustss 3029: } else {
3030: DPRINTFN(1,("ehci_abort_xfer: no hit\n"));
3031: }
1.11 augustss 3032:
3033: /*
1.26 augustss 3034: * Step 4: Execute callback.
1.11 augustss 3035: */
1.18 augustss 3036: #ifdef DIAGNOSTIC
1.26 augustss 3037: exfer->isdone = 1;
1.18 augustss 3038: #endif
1.96 augustss 3039: wake = xfer->hcflags & UXFER_ABORTWAIT;
3040: xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
1.11 augustss 3041: usb_transfer_complete(xfer);
1.96 augustss 3042: if (wake)
3043: wakeup(&xfer->hcflags);
1.11 augustss 3044:
3045: splx(s);
1.26 augustss 3046: #undef exfer
1.10 augustss 3047: }
3048:
1.164 uebayasi 3049: Static void
1.139 jmcneill 3050: ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status)
3051: {
3052: ehci_isoc_trans_t trans_status;
3053: struct ehci_pipe *epipe;
3054: struct ehci_xfer *exfer;
3055: ehci_softc_t *sc;
3056: struct ehci_soft_itd *itd;
3057: int s, i, wake;
3058:
3059: epipe = (struct ehci_pipe *) xfer->pipe;
3060: exfer = EXFER(xfer);
3061: sc = epipe->pipe.device->bus->hci_private;
3062:
3063: DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe));
3064:
3065: if (sc->sc_dying) {
3066: s = splusb();
3067: xfer->status = status;
1.171 dyoung 3068: callout_stop(&xfer->timeout_handle);
1.139 jmcneill 3069: usb_transfer_complete(xfer);
3070: splx(s);
3071: return;
3072: }
3073:
3074: if (xfer->hcflags & UXFER_ABORTING) {
3075: DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n"));
3076:
3077: #ifdef DIAGNOSTIC
3078: if (status == USBD_TIMEOUT)
3079: printf("ehci_abort_xfer: TIMEOUT while aborting\n");
3080: #endif
3081:
3082: xfer->status = status;
3083: DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
3084: xfer->hcflags |= UXFER_ABORTWAIT;
3085: while (xfer->hcflags & UXFER_ABORTING)
3086: tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0);
3087: return;
3088: }
3089: xfer->hcflags |= UXFER_ABORTING;
3090:
3091: xfer->status = status;
1.171 dyoung 3092: callout_stop(&xfer->timeout_handle);
1.139 jmcneill 3093:
3094: s = splusb();
3095: for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
3096: usb_syncmem(&itd->dma,
3097: itd->offs + offsetof(ehci_itd_t, itd_ctl),
3098: sizeof(itd->itd.itd_ctl),
3099: BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3100:
3101: for (i = 0; i < 8; i++) {
3102: trans_status = le32toh(itd->itd.itd_ctl[i]);
3103: trans_status &= ~EHCI_ITD_ACTIVE;
3104: itd->itd.itd_ctl[i] = htole32(trans_status);
3105: }
3106:
3107: usb_syncmem(&itd->dma,
3108: itd->offs + offsetof(ehci_itd_t, itd_ctl),
3109: sizeof(itd->itd.itd_ctl),
3110: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3111: }
3112: splx(s);
3113:
3114: s = splusb();
3115: #ifdef USB_USE_SOFTINTR
3116: sc->sc_softwake = 1;
3117: #endif /* USB_USE_SOFTINTR */
3118: usb_schedsoftintr(&sc->sc_bus);
3119: #ifdef USB_USE_SOFTINTR
3120: tsleep(&sc->sc_softwake, PZERO, "ehciab", 0);
3121: #endif /* USB_USE_SOFTINTR */
3122: splx(s);
3123:
3124: #ifdef DIAGNOSTIC
3125: exfer->isdone = 1;
3126: #endif
3127: wake = xfer->hcflags & UXFER_ABORTWAIT;
3128: xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
3129: usb_transfer_complete(xfer);
3130: if (wake)
3131: wakeup(&xfer->hcflags);
3132:
3133: return;
3134: }
3135:
1.164 uebayasi 3136: Static void
1.15 augustss 3137: ehci_timeout(void *addr)
3138: {
3139: struct ehci_xfer *exfer = addr;
1.17 augustss 3140: struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
1.134 drochner 3141: ehci_softc_t *sc = epipe->pipe.device->bus->hci_private;
1.15 augustss 3142:
3143: DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
1.158 sketch 3144: #ifdef EHCI_DEBUG
1.26 augustss 3145: if (ehcidebug > 1)
1.22 augustss 3146: usbd_dump_pipe(exfer->xfer.pipe);
3147: #endif
1.15 augustss 3148:
1.17 augustss 3149: if (sc->sc_dying) {
3150: ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
3151: return;
3152: }
3153:
1.15 augustss 3154: /* Execute the abort in a process context. */
1.177 tsutsui 3155: usb_init_task(&exfer->abort_task, ehci_timeout_task, addr);
1.114 joerg 3156: usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task,
3157: USB_TASKQ_HC);
1.15 augustss 3158: }
3159:
1.164 uebayasi 3160: Static void
1.15 augustss 3161: ehci_timeout_task(void *addr)
3162: {
3163: usbd_xfer_handle xfer = addr;
3164: int s;
3165:
3166: DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
3167:
3168: s = splusb();
3169: ehci_abort_xfer(xfer, USBD_TIMEOUT);
3170: splx(s);
3171: }
3172:
1.5 augustss 3173: /************************/
3174:
1.10 augustss 3175: Static usbd_status
3176: ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
3177: {
3178: usbd_status err;
3179:
3180: /* Insert last in queue. */
3181: err = usb_insert_transfer(xfer);
3182: if (err)
3183: return (err);
3184:
3185: /* Pipe isn't running, start first */
3186: return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3187: }
3188:
1.12 augustss 3189: Static usbd_status
3190: ehci_device_ctrl_start(usbd_xfer_handle xfer)
3191: {
1.134 drochner 3192: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.15 augustss 3193: usbd_status err;
3194:
3195: if (sc->sc_dying)
3196: return (USBD_IOERROR);
3197:
3198: #ifdef DIAGNOSTIC
3199: if (!(xfer->rqflags & URQ_REQUEST)) {
3200: /* XXX panic */
3201: printf("ehci_device_ctrl_transfer: not a request\n");
3202: return (USBD_INVAL);
3203: }
3204: #endif
3205:
3206: err = ehci_device_request(xfer);
3207: if (err)
3208: return (err);
3209:
3210: if (sc->sc_bus.use_polling)
3211: ehci_waitintr(sc, xfer);
3212: return (USBD_IN_PROGRESS);
1.12 augustss 3213: }
1.10 augustss 3214:
1.164 uebayasi 3215: Static void
1.10 augustss 3216: ehci_device_ctrl_done(usbd_xfer_handle xfer)
3217: {
1.18 augustss 3218: struct ehci_xfer *ex = EXFER(xfer);
1.134 drochner 3219: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.138 bouyer 3220: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3221: usb_device_request_t *req = &xfer->request;
3222: int len = UGETW(req->wLength);
3223: int rd = req->bmRequestType & UT_READ;
1.18 augustss 3224:
1.10 augustss 3225: DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
3226:
3227: #ifdef DIAGNOSTIC
3228: if (!(xfer->rqflags & URQ_REQUEST)) {
1.37 provos 3229: panic("ehci_ctrl_done: not a request");
1.10 augustss 3230: }
3231: #endif
1.18 augustss 3232:
1.153 jmcneill 3233: mutex_enter(&sc->sc_intrhead_lock);
1.44 augustss 3234: if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
1.153 jmcneill 3235: ehci_del_intr_list(sc, ex); /* remove from active list */
1.25 augustss 3236: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
1.138 bouyer 3237: usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req,
3238: BUS_DMASYNC_POSTWRITE);
3239: if (len)
3240: usb_syncmem(&xfer->dmabuf, 0, len,
3241: rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.25 augustss 3242: }
1.153 jmcneill 3243: mutex_exit(&sc->sc_intrhead_lock);
1.18 augustss 3244:
1.25 augustss 3245: DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
1.10 augustss 3246: }
3247:
3248: /* Abort a device control request. */
3249: Static void
3250: ehci_device_ctrl_abort(usbd_xfer_handle xfer)
3251: {
3252: DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
3253: ehci_abort_xfer(xfer, USBD_CANCELLED);
3254: }
3255:
3256: /* Close a device control pipe. */
3257: Static void
3258: ehci_device_ctrl_close(usbd_pipe_handle pipe)
3259: {
1.134 drochner 3260: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.10 augustss 3261: /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
3262:
3263: DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
1.11 augustss 3264: ehci_close_pipe(pipe, sc->sc_async_head);
1.15 augustss 3265: }
3266:
1.164 uebayasi 3267: Static usbd_status
1.15 augustss 3268: ehci_device_request(usbd_xfer_handle xfer)
3269: {
1.18 augustss 3270: #define exfer EXFER(xfer)
1.15 augustss 3271: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3272: usb_device_request_t *req = &xfer->request;
3273: usbd_device_handle dev = epipe->pipe.device;
1.134 drochner 3274: ehci_softc_t *sc = dev->bus->hci_private;
1.15 augustss 3275: int addr = dev->address;
3276: ehci_soft_qtd_t *setup, *stat, *next;
3277: ehci_soft_qh_t *sqh;
3278: int isread;
3279: int len;
3280: usbd_status err;
3281: int s;
3282:
3283: isread = req->bmRequestType & UT_READ;
3284: len = UGETW(req->wLength);
3285:
1.72 augustss 3286: DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, "
1.15 augustss 3287: "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
3288: req->bmRequestType, req->bRequest, UGETW(req->wValue),
1.33 augustss 3289: UGETW(req->wIndex), len, addr,
1.15 augustss 3290: epipe->pipe.endpoint->edesc->bEndpointAddress));
3291:
3292: setup = ehci_alloc_sqtd(sc);
3293: if (setup == NULL) {
3294: err = USBD_NOMEM;
3295: goto bad1;
3296: }
3297: stat = ehci_alloc_sqtd(sc);
3298: if (stat == NULL) {
3299: err = USBD_NOMEM;
3300: goto bad2;
3301: }
3302:
3303: sqh = epipe->sqh;
3304: epipe->u.ctl.length = len;
3305:
1.62 mycroft 3306: /* Update device address and length since they may have changed
3307: during the setup of the control pipe in usbd_new_device(). */
1.15 augustss 3308: /* XXX This only needs to be done once, but it's too early in open. */
3309: /* XXXX Should not touch ED here! */
1.33 augustss 3310: sqh->qh.qh_endp =
1.55 mycroft 3311: (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) |
1.15 augustss 3312: htole32(
3313: EHCI_QH_SET_ADDR(addr) |
3314: EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize))
3315: );
3316:
3317: /* Set up data transaction */
3318: if (len != 0) {
3319: ehci_soft_qtd_t *end;
3320:
1.55 mycroft 3321: /* Start toggle at 1. */
3322: epipe->nexttoggle = 1;
1.25 augustss 3323: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
1.15 augustss 3324: &next, &end);
3325: if (err)
3326: goto bad3;
1.83 augustss 3327: end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
1.15 augustss 3328: end->nextqtd = stat;
1.33 augustss 3329: end->qtd.qtd_next =
1.15 augustss 3330: end->qtd.qtd_altnext = htole32(stat->physaddr);
1.138 bouyer 3331: usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
3332: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 3333: } else {
3334: next = stat;
3335: }
3336:
1.30 augustss 3337: memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req);
1.138 bouyer 3338: usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
1.15 augustss 3339:
1.55 mycroft 3340: /* Clear toggle */
1.15 augustss 3341: setup->qtd.qtd_status = htole32(
1.26 augustss 3342: EHCI_QTD_ACTIVE |
1.15 augustss 3343: EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
3344: EHCI_QTD_SET_CERR(3) |
1.64 mycroft 3345: EHCI_QTD_SET_TOGGLE(0) |
1.15 augustss 3346: EHCI_QTD_SET_BYTES(sizeof *req)
3347: );
1.31 augustss 3348: setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
1.48 mycroft 3349: setup->qtd.qtd_buffer_hi[0] = 0;
1.15 augustss 3350: setup->nextqtd = next;
3351: setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
3352: setup->xfer = xfer;
1.18 augustss 3353: setup->len = sizeof *req;
1.138 bouyer 3354: usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd),
3355: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 3356:
3357: stat->qtd.qtd_status = htole32(
1.26 augustss 3358: EHCI_QTD_ACTIVE |
1.15 augustss 3359: EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3360: EHCI_QTD_SET_CERR(3) |
1.64 mycroft 3361: EHCI_QTD_SET_TOGGLE(1) |
1.15 augustss 3362: EHCI_QTD_IOC
3363: );
3364: stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
1.48 mycroft 3365: stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
1.15 augustss 3366: stat->nextqtd = NULL;
3367: stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
3368: stat->xfer = xfer;
1.18 augustss 3369: stat->len = 0;
1.138 bouyer 3370: usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd),
3371: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1.15 augustss 3372:
3373: #ifdef EHCI_DEBUG
1.23 augustss 3374: if (ehcidebug > 5) {
1.15 augustss 3375: DPRINTF(("ehci_device_request:\n"));
3376: ehci_dump_sqh(sqh);
3377: ehci_dump_sqtds(setup);
3378: }
3379: #endif
3380:
1.18 augustss 3381: exfer->sqtdstart = setup;
3382: exfer->sqtdend = stat;
3383: #ifdef DIAGNOSTIC
3384: if (!exfer->isdone) {
3385: printf("ehci_device_request: not done, exfer=%p\n", exfer);
3386: }
3387: exfer->isdone = 0;
3388: #endif
3389:
1.15 augustss 3390: /* Insert qTD in QH list. */
3391: s = splusb();
1.138 bouyer 3392: ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */
1.15 augustss 3393: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.159 dyoung 3394: callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)),
3395: (ehci_timeout), (xfer));
1.15 augustss 3396: }
1.153 jmcneill 3397: mutex_enter(&sc->sc_intrhead_lock);
1.18 augustss 3398: ehci_add_intr_list(sc, exfer);
1.153 jmcneill 3399: mutex_exit(&sc->sc_intrhead_lock);
1.18 augustss 3400: xfer->status = USBD_IN_PROGRESS;
1.15 augustss 3401: splx(s);
3402:
1.17 augustss 3403: #ifdef EHCI_DEBUG
1.15 augustss 3404: if (ehcidebug > 10) {
3405: DPRINTF(("ehci_device_request: status=%x\n",
3406: EOREAD4(sc, EHCI_USBSTS)));
1.23 augustss 3407: delay(10000);
1.18 augustss 3408: ehci_dump_regs(sc);
1.15 augustss 3409: ehci_dump_sqh(sc->sc_async_head);
3410: ehci_dump_sqh(sqh);
3411: ehci_dump_sqtds(setup);
3412: }
3413: #endif
3414:
3415: return (USBD_NORMAL_COMPLETION);
3416:
3417: bad3:
3418: ehci_free_sqtd(sc, stat);
3419: bad2:
3420: ehci_free_sqtd(sc, setup);
3421: bad1:
1.25 augustss 3422: DPRINTFN(-1,("ehci_device_request: no memory\n"));
3423: xfer->status = err;
3424: usb_transfer_complete(xfer);
1.15 augustss 3425: return (err);
1.18 augustss 3426: #undef exfer
1.10 augustss 3427: }
3428:
1.108 xtraeme 3429: /*
3430: * Some EHCI chips from VIA seem to trigger interrupts before writing back the
3431: * qTD status, or miss signalling occasionally under heavy load. If the host
3432: * machine is too fast, we we can miss transaction completion - when we scan
3433: * the active list the transaction still seems to be active. This generally
3434: * exhibits itself as a umass stall that never recovers.
3435: *
3436: * We work around this behaviour by setting up this callback after any softintr
3437: * that completes with transactions still pending, giving us another chance to
3438: * check for completion after the writeback has taken place.
3439: */
1.164 uebayasi 3440: Static void
1.108 xtraeme 3441: ehci_intrlist_timeout(void *arg)
3442: {
3443: ehci_softc_t *sc = arg;
3444: int s = splusb();
3445:
3446: DPRINTF(("ehci_intrlist_timeout\n"));
3447: usb_schedsoftintr(&sc->sc_bus);
3448:
3449: splx(s);
3450: }
3451:
1.10 augustss 3452: /************************/
1.5 augustss 3453:
1.19 augustss 3454: Static usbd_status
3455: ehci_device_bulk_transfer(usbd_xfer_handle xfer)
3456: {
3457: usbd_status err;
3458:
3459: /* Insert last in queue. */
3460: err = usb_insert_transfer(xfer);
3461: if (err)
3462: return (err);
3463:
3464: /* Pipe isn't running, start first */
3465: return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3466: }
3467:
1.164 uebayasi 3468: Static usbd_status
1.19 augustss 3469: ehci_device_bulk_start(usbd_xfer_handle xfer)
3470: {
3471: #define exfer EXFER(xfer)
3472: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3473: usbd_device_handle dev = epipe->pipe.device;
1.134 drochner 3474: ehci_softc_t *sc = dev->bus->hci_private;
1.19 augustss 3475: ehci_soft_qtd_t *data, *dataend;
3476: ehci_soft_qh_t *sqh;
3477: usbd_status err;
3478: int len, isread, endpt;
3479: int s;
3480:
1.72 augustss 3481: DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n",
1.19 augustss 3482: xfer, xfer->length, xfer->flags));
3483:
3484: if (sc->sc_dying)
3485: return (USBD_IOERROR);
3486:
3487: #ifdef DIAGNOSTIC
3488: if (xfer->rqflags & URQ_REQUEST)
1.72 augustss 3489: panic("ehci_device_bulk_start: a request");
1.19 augustss 3490: #endif
3491:
3492: len = xfer->length;
3493: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3494: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3495: sqh = epipe->sqh;
3496:
3497: epipe->u.bulk.length = len;
3498:
1.25 augustss 3499: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
1.19 augustss 3500: &dataend);
1.25 augustss 3501: if (err) {
3502: DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n"));
3503: xfer->status = err;
3504: usb_transfer_complete(xfer);
1.19 augustss 3505: return (err);
1.25 augustss 3506: }
1.19 augustss 3507:
3508: #ifdef EHCI_DEBUG
1.23 augustss 3509: if (ehcidebug > 5) {
1.72 augustss 3510: DPRINTF(("ehci_device_bulk_start: data(1)\n"));
1.23 augustss 3511: ehci_dump_sqh(sqh);
1.19 augustss 3512: ehci_dump_sqtds(data);
3513: }
3514: #endif
3515:
3516: /* Set up interrupt info. */
3517: exfer->sqtdstart = data;
3518: exfer->sqtdend = dataend;
3519: #ifdef DIAGNOSTIC
3520: if (!exfer->isdone) {
1.72 augustss 3521: printf("ehci_device_bulk_start: not done, ex=%p\n", exfer);
1.19 augustss 3522: }
3523: exfer->isdone = 0;
3524: #endif
3525:
3526: s = splusb();
1.138 bouyer 3527: ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
1.19 augustss 3528: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.159 dyoung 3529: callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)),
3530: (ehci_timeout), (xfer));
1.19 augustss 3531: }
1.153 jmcneill 3532: mutex_enter(&sc->sc_intrhead_lock);
1.19 augustss 3533: ehci_add_intr_list(sc, exfer);
1.153 jmcneill 3534: mutex_exit(&sc->sc_intrhead_lock);
1.19 augustss 3535: xfer->status = USBD_IN_PROGRESS;
3536: splx(s);
3537:
3538: #ifdef EHCI_DEBUG
3539: if (ehcidebug > 10) {
1.72 augustss 3540: DPRINTF(("ehci_device_bulk_start: data(2)\n"));
1.23 augustss 3541: delay(10000);
1.72 augustss 3542: DPRINTF(("ehci_device_bulk_start: data(3)\n"));
1.23 augustss 3543: ehci_dump_regs(sc);
1.29 augustss 3544: #if 0
3545: printf("async_head:\n");
1.23 augustss 3546: ehci_dump_sqh(sc->sc_async_head);
1.29 augustss 3547: #endif
3548: printf("sqh:\n");
1.23 augustss 3549: ehci_dump_sqh(sqh);
1.19 augustss 3550: ehci_dump_sqtds(data);
3551: }
3552: #endif
3553:
3554: if (sc->sc_bus.use_polling)
3555: ehci_waitintr(sc, xfer);
3556:
3557: return (USBD_IN_PROGRESS);
3558: #undef exfer
3559: }
3560:
3561: Static void
3562: ehci_device_bulk_abort(usbd_xfer_handle xfer)
3563: {
3564: DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
3565: ehci_abort_xfer(xfer, USBD_CANCELLED);
3566: }
3567:
1.33 augustss 3568: /*
1.19 augustss 3569: * Close a device bulk pipe.
3570: */
3571: Static void
3572: ehci_device_bulk_close(usbd_pipe_handle pipe)
3573: {
1.134 drochner 3574: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.175 drochner 3575: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1.19 augustss 3576:
3577: DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
1.175 drochner 3578: pipe->endpoint->datatoggle = epipe->nexttoggle;
1.19 augustss 3579: ehci_close_pipe(pipe, sc->sc_async_head);
3580: }
3581:
1.164 uebayasi 3582: Static void
1.19 augustss 3583: ehci_device_bulk_done(usbd_xfer_handle xfer)
3584: {
3585: struct ehci_xfer *ex = EXFER(xfer);
1.134 drochner 3586: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.138 bouyer 3587: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3588: int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3589: int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
1.19 augustss 3590:
1.33 augustss 3591: DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
1.19 augustss 3592: xfer, xfer->actlen));
3593:
1.153 jmcneill 3594: mutex_enter(&sc->sc_intrhead_lock);
1.44 augustss 3595: if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
1.153 jmcneill 3596: ehci_del_intr_list(sc, ex); /* remove from active list */
1.44 augustss 3597: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
1.138 bouyer 3598: usb_syncmem(&xfer->dmabuf, 0, xfer->length,
3599: rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.25 augustss 3600: }
1.153 jmcneill 3601: mutex_exit(&sc->sc_intrhead_lock);
1.19 augustss 3602:
3603: DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
3604: }
1.5 augustss 3605:
1.10 augustss 3606: /************************/
3607:
1.78 augustss 3608: Static usbd_status
3609: ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
3610: {
3611: struct ehci_soft_islot *isp;
3612: int islot, lev;
3613:
3614: /* Find a poll rate that is large enough. */
3615: for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
3616: if (EHCI_ILEV_IVAL(lev) <= ival)
3617: break;
3618:
3619: /* Pick an interrupt slot at the right level. */
3620: /* XXX could do better than picking at random */
3621: sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize;
3622: islot = EHCI_IQHIDX(lev, sc->sc_rand);
3623:
3624: sqh->islot = islot;
3625: isp = &sc->sc_islots[islot];
3626: ehci_add_qh(sqh, isp->sqh);
3627:
3628: return (USBD_NORMAL_COMPLETION);
3629: }
3630:
3631: Static usbd_status
3632: ehci_device_intr_transfer(usbd_xfer_handle xfer)
3633: {
3634: usbd_status err;
3635:
3636: /* Insert last in queue. */
3637: err = usb_insert_transfer(xfer);
3638: if (err)
3639: return (err);
3640:
3641: /*
3642: * Pipe isn't running (otherwise err would be USBD_INPROG),
3643: * so start it first.
3644: */
3645: return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3646: }
3647:
3648: Static usbd_status
3649: ehci_device_intr_start(usbd_xfer_handle xfer)
3650: {
3651: #define exfer EXFER(xfer)
3652: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3653: usbd_device_handle dev = xfer->pipe->device;
1.134 drochner 3654: ehci_softc_t *sc = dev->bus->hci_private;
1.78 augustss 3655: ehci_soft_qtd_t *data, *dataend;
3656: ehci_soft_qh_t *sqh;
3657: usbd_status err;
3658: int len, isread, endpt;
3659: int s;
3660:
3661: DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n",
3662: xfer, xfer->length, xfer->flags));
3663:
3664: if (sc->sc_dying)
3665: return (USBD_IOERROR);
3666:
3667: #ifdef DIAGNOSTIC
3668: if (xfer->rqflags & URQ_REQUEST)
3669: panic("ehci_device_intr_start: a request");
3670: #endif
3671:
3672: len = xfer->length;
3673: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3674: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3675: sqh = epipe->sqh;
3676:
3677: epipe->u.intr.length = len;
3678:
3679: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
3680: &dataend);
3681: if (err) {
3682: DPRINTFN(-1, ("ehci_device_intr_start: no memory\n"));
3683: xfer->status = err;
3684: usb_transfer_complete(xfer);
3685: return (err);
3686: }
3687:
3688: #ifdef EHCI_DEBUG
3689: if (ehcidebug > 5) {
3690: DPRINTF(("ehci_device_intr_start: data(1)\n"));
3691: ehci_dump_sqh(sqh);
3692: ehci_dump_sqtds(data);
3693: }
3694: #endif
3695:
3696: /* Set up interrupt info. */
3697: exfer->sqtdstart = data;
3698: exfer->sqtdend = dataend;
3699: #ifdef DIAGNOSTIC
3700: if (!exfer->isdone) {
3701: printf("ehci_device_intr_start: not done, ex=%p\n", exfer);
3702: }
3703: exfer->isdone = 0;
3704: #endif
3705:
3706: s = splusb();
1.138 bouyer 3707: ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
1.78 augustss 3708: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.161 uebayasi 3709: callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)),
1.159 dyoung 3710: (ehci_timeout), (xfer));
1.78 augustss 3711: }
1.153 jmcneill 3712: mutex_enter(&sc->sc_intrhead_lock);
1.78 augustss 3713: ehci_add_intr_list(sc, exfer);
1.153 jmcneill 3714: mutex_exit(&sc->sc_intrhead_lock);
1.78 augustss 3715: xfer->status = USBD_IN_PROGRESS;
3716: splx(s);
3717:
3718: #ifdef EHCI_DEBUG
3719: if (ehcidebug > 10) {
3720: DPRINTF(("ehci_device_intr_start: data(2)\n"));
3721: delay(10000);
3722: DPRINTF(("ehci_device_intr_start: data(3)\n"));
3723: ehci_dump_regs(sc);
3724: printf("sqh:\n");
3725: ehci_dump_sqh(sqh);
3726: ehci_dump_sqtds(data);
3727: }
3728: #endif
3729:
3730: if (sc->sc_bus.use_polling)
3731: ehci_waitintr(sc, xfer);
3732:
3733: return (USBD_IN_PROGRESS);
3734: #undef exfer
3735: }
3736:
3737: Static void
3738: ehci_device_intr_abort(usbd_xfer_handle xfer)
3739: {
3740: DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer));
3741: if (xfer->pipe->intrxfer == xfer) {
3742: DPRINTFN(1, ("echi_device_intr_abort: remove\n"));
3743: xfer->pipe->intrxfer = NULL;
3744: }
1.139 jmcneill 3745: /*
3746: * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance
1.180 wiz 3747: * async doorbell. That's dependent on the async list, wheras
1.139 jmcneill 3748: * intr xfers are periodic, should not use this?
3749: */
1.78 augustss 3750: ehci_abort_xfer(xfer, USBD_CANCELLED);
3751: }
3752:
3753: Static void
3754: ehci_device_intr_close(usbd_pipe_handle pipe)
3755: {
1.134 drochner 3756: ehci_softc_t *sc = pipe->device->bus->hci_private;
1.78 augustss 3757: struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3758: struct ehci_soft_islot *isp;
3759:
3760: isp = &sc->sc_islots[epipe->sqh->islot];
3761: ehci_close_pipe(pipe, isp->sqh);
3762: }
3763:
3764: Static void
3765: ehci_device_intr_done(usbd_xfer_handle xfer)
3766: {
3767: #define exfer EXFER(xfer)
3768: struct ehci_xfer *ex = EXFER(xfer);
1.134 drochner 3769: ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1.78 augustss 3770: struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3771: ehci_soft_qtd_t *data, *dataend;
3772: ehci_soft_qh_t *sqh;
3773: usbd_status err;
3774: int len, isread, endpt, s;
3775:
3776: DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n",
3777: xfer, xfer->actlen));
3778:
1.153 jmcneill 3779: mutex_enter(&sc->sc_intrhead_lock);
1.78 augustss 3780: if (xfer->pipe->repeat) {
3781: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3782:
3783: len = epipe->u.intr.length;
3784: xfer->length = len;
3785: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3786: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
1.138 bouyer 3787: usb_syncmem(&xfer->dmabuf, 0, len,
3788: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.78 augustss 3789: sqh = epipe->sqh;
3790:
3791: err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3792: &data, &dataend);
3793: if (err) {
3794: DPRINTFN(-1, ("ehci_device_intr_done: no memory\n"));
3795: xfer->status = err;
1.153 jmcneill 3796: mutex_exit(&sc->sc_intrhead_lock);
1.78 augustss 3797: return;
3798: }
3799:
3800: /* Set up interrupt info. */
3801: exfer->sqtdstart = data;
3802: exfer->sqtdend = dataend;
3803: #ifdef DIAGNOSTIC
3804: if (!exfer->isdone) {
3805: printf("ehci_device_intr_done: not done, ex=%p\n",
3806: exfer);
3807: }
3808: exfer->isdone = 0;
3809: #endif
3810:
3811: s = splusb();
1.138 bouyer 3812: ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
1.78 augustss 3813: if (xfer->timeout && !sc->sc_bus.use_polling) {
1.161 uebayasi 3814: callout_reset(&(xfer->timeout_handle),
1.159 dyoung 3815: (mstohz(xfer->timeout)), (ehci_timeout), (xfer));
1.78 augustss 3816: }
3817: splx(s);
3818:
3819: xfer->status = USBD_IN_PROGRESS;
3820: } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
1.153 jmcneill 3821: ehci_del_intr_list(sc, ex); /* remove from active list */
1.78 augustss 3822: ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
1.138 bouyer 3823: endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3824: isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3825: usb_syncmem(&xfer->dmabuf, 0, xfer->length,
3826: isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1.78 augustss 3827: }
1.153 jmcneill 3828: mutex_exit(&sc->sc_intrhead_lock);
1.78 augustss 3829: #undef exfer
3830: }
1.10 augustss 3831:
3832: /************************/
1.5 augustss 3833:
1.113 christos 3834: Static usbd_status
1.115 christos 3835: ehci_device_isoc_transfer(usbd_xfer_handle xfer)
1.113 christos 3836: {
1.139 jmcneill 3837: usbd_status err;
3838:
3839: err = usb_insert_transfer(xfer);
3840: if (err && err != USBD_IN_PROGRESS)
3841: return err;
3842:
3843: return ehci_device_isoc_start(xfer);
1.113 christos 3844: }
1.139 jmcneill 3845:
1.113 christos 3846: Static usbd_status
1.115 christos 3847: ehci_device_isoc_start(usbd_xfer_handle xfer)
1.113 christos 3848: {
1.139 jmcneill 3849: struct ehci_pipe *epipe;
3850: usbd_device_handle dev;
3851: ehci_softc_t *sc;
3852: struct ehci_xfer *exfer;
3853: ehci_soft_itd_t *itd, *prev, *start, *stop;
3854: usb_dma_t *dma_buf;
1.142 drochner 3855: int i, j, k, frames, uframes, ufrperframe;
1.139 jmcneill 3856: int s, trans_count, offs, total_length;
3857: int frindex;
3858:
3859: start = NULL;
3860: prev = NULL;
3861: itd = NULL;
3862: trans_count = 0;
3863: total_length = 0;
3864: exfer = (struct ehci_xfer *) xfer;
3865: sc = xfer->pipe->device->bus->hci_private;
3866: dev = xfer->pipe->device;
3867: epipe = (struct ehci_pipe *)xfer->pipe;
3868:
3869: /*
3870: * To allow continuous transfers, above we start all transfers
3871: * immediately. However, we're still going to get usbd_start_next call
3872: * this when another xfer completes. So, check if this is already
3873: * in progress or not
3874: */
3875:
3876: if (exfer->itdstart != NULL)
3877: return USBD_IN_PROGRESS;
3878:
3879: DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n",
3880: xfer, xfer->length, xfer->flags));
3881:
3882: if (sc->sc_dying)
3883: return USBD_IOERROR;
3884:
3885: /*
3886: * To avoid complication, don't allow a request right now that'll span
3887: * the entire frame table. To within 4 frames, to allow some leeway
3888: * on either side of where the hc currently is.
3889: */
3890: if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) *
3891: xfer->nframes >= (sc->sc_flsize - 4) * 8) {
3892: printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n");
3893: return USBD_INVAL;
3894: }
3895:
3896: #ifdef DIAGNOSTIC
3897: if (xfer->rqflags & URQ_REQUEST)
3898: panic("ehci_device_isoc_start: request\n");
3899:
3900: if (!exfer->isdone)
3901: printf("ehci_device_isoc_start: not done, ex = %p\n", exfer);
3902: exfer->isdone = 0;
3903: #endif
3904:
3905: /*
3906: * Step 1: Allocate and initialize itds, how many do we need?
3907: * One per transfer if interval >= 8 microframes, fewer if we use
3908: * multiple microframes per frame.
3909: */
3910:
3911: i = epipe->pipe.endpoint->edesc->bInterval;
3912: if (i > 16 || i == 0) {
3913: /* Spec page 271 says intervals > 16 are invalid */
3914: DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i));
3915: return USBD_INVAL;
3916: }
3917:
1.168 jakllsch 3918: ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1)));
1.142 drochner 3919: frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe;
1.168 jakllsch 3920: uframes = USB_UFRAMES_PER_FRAME / ufrperframe;
1.142 drochner 3921:
1.139 jmcneill 3922: if (frames == 0) {
3923: DPRINTF(("ehci_device_isoc_start: frames == 0\n"));
3924: return USBD_INVAL;
3925: }
3926:
3927: dma_buf = &xfer->dmabuf;
3928: offs = 0;
3929:
3930: for (i = 0; i < frames; i++) {
3931: int froffs = offs;
3932: itd = ehci_alloc_itd(sc);
3933:
3934: if (prev != NULL) {
3935: prev->itd.itd_next =
3936: htole32(itd->physaddr | EHCI_LINK_ITD);
3937: usb_syncmem(&itd->dma,
3938: itd->offs + offsetof(ehci_itd_t, itd_next),
3939: sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE);
3940:
3941: prev->xfer_next = itd;
1.183 jakllsch 3942: } else {
1.139 jmcneill 3943: start = itd;
3944: }
3945:
3946: /*
3947: * Step 1.5, initialize uframes
3948: */
1.168 jakllsch 3949: for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) {
1.139 jmcneill 3950: /* Calculate which page in the list this starts in */
3951: int addr = DMAADDR(dma_buf, froffs);
3952: addr = EHCI_PAGE_OFFSET(addr);
3953: addr += (offs - froffs);
3954: addr = EHCI_PAGE(addr);
3955: addr /= EHCI_PAGE_SIZE;
3956:
3957: /* This gets the initial offset into the first page,
3958: * looks how far further along the current uframe
3959: * offset is. Works out how many pages that is.
3960: */
3961:
3962: itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE |
1.183 jakllsch 3963: EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) |
1.139 jmcneill 3964: EHCI_ITD_SET_PG(addr) |
3965: EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs))));
3966:
3967: total_length += xfer->frlengths[trans_count];
3968: offs += xfer->frlengths[trans_count];
3969: trans_count++;
3970:
3971: if (trans_count >= xfer->nframes) { /*Set IOC*/
3972: itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC);
1.145 drochner 3973: break;
1.139 jmcneill 3974: }
1.183 jakllsch 3975: }
1.139 jmcneill 3976:
3977: /* Step 1.75, set buffer pointers. To simplify matters, all
3978: * pointers are filled out for the next 7 hardware pages in
3979: * the dma block, so no need to worry what pages to cover
3980: * and what to not.
3981: */
3982:
1.168 jakllsch 3983: for (j = 0; j < EHCI_ITD_NBUFFERS; j++) {
1.139 jmcneill 3984: /*
3985: * Don't try to lookup a page that's past the end
3986: * of buffer
3987: */
3988: int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j));
3989: if (page_offs >= dma_buf->block->size)
3990: break;
3991:
1.181 mrg 3992: unsigned long long page = DMAADDR(dma_buf, page_offs);
1.139 jmcneill 3993: page = EHCI_PAGE(page);
3994: itd->itd.itd_bufr[j] =
1.155 jmorse 3995: htole32(EHCI_ITD_SET_BPTR(page));
3996: itd->itd.itd_bufr_hi[j] =
3997: htole32(page >> 32);
1.139 jmcneill 3998: }
3999:
4000: /*
4001: * Other special values
4002: */
4003:
4004: k = epipe->pipe.endpoint->edesc->bEndpointAddress;
4005: itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) |
4006: EHCI_ITD_SET_DADDR(epipe->pipe.device->address));
4007:
4008: k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress))
4009: ? 1 : 0;
1.149 jmcneill 4010: j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
1.139 jmcneill 4011: itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) |
4012: EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j)));
4013:
4014: /* FIXME: handle invalid trans */
1.183 jakllsch 4015: itd->itd.itd_bufr[2] |=
1.139 jmcneill 4016: htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1));
4017:
4018: usb_syncmem(&itd->dma,
4019: itd->offs + offsetof(ehci_itd_t, itd_next),
4020: sizeof(ehci_itd_t),
4021: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4022:
4023: prev = itd;
4024: } /* End of frame */
4025:
4026: stop = itd;
4027: stop->xfer_next = NULL;
4028: exfer->isoc_len = total_length;
4029:
1.155 jmorse 4030: usb_syncmem(&exfer->xfer.dmabuf, 0, total_length,
4031: BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4032:
1.139 jmcneill 4033: /*
4034: * Part 2: Transfer descriptors have now been set up, now they must
4035: * be scheduled into the period frame list. Erk. Not wanting to
4036: * complicate matters, transfer is denied if the transfer spans
4037: * more than the period frame list.
4038: */
4039:
4040: s = splusb();
4041:
4042: /* Start inserting frames */
4043: if (epipe->u.isoc.cur_xfers > 0) {
4044: frindex = epipe->u.isoc.next_frame;
4045: } else {
4046: frindex = EOREAD4(sc, EHCI_FRINDEX);
4047: frindex = frindex >> 3; /* Erase microframe index */
4048: frindex += 2;
4049: }
4050:
4051: if (frindex >= sc->sc_flsize)
4052: frindex &= (sc->sc_flsize - 1);
4053:
1.168 jakllsch 4054: /* What's the frame interval? */
4055: i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1));
4056: if (i / USB_UFRAMES_PER_FRAME == 0)
1.139 jmcneill 4057: i = 1;
4058: else
1.168 jakllsch 4059: i /= USB_UFRAMES_PER_FRAME;
1.139 jmcneill 4060:
4061: itd = start;
4062: for (j = 0; j < frames; j++) {
4063: if (itd == NULL)
4064: panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n");
4065:
4066: itd->itd.itd_next = sc->sc_flist[frindex];
4067: if (itd->itd.itd_next == 0)
4068: /* FIXME: frindex table gets initialized to NULL
4069: * or EHCI_NULL? */
1.162 uebayasi 4070: itd->itd.itd_next = EHCI_NULL;
1.139 jmcneill 4071:
4072: usb_syncmem(&itd->dma,
4073: itd->offs + offsetof(ehci_itd_t, itd_next),
4074: sizeof(itd->itd.itd_next),
4075: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4076:
4077: sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr);
4078:
4079: usb_syncmem(&sc->sc_fldma,
4080: sizeof(ehci_link_t) * frindex,
4081: sizeof(ehci_link_t),
4082: BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4083:
4084: itd->u.frame_list.next = sc->sc_softitds[frindex];
4085: sc->sc_softitds[frindex] = itd;
4086: if (itd->u.frame_list.next != NULL)
4087: itd->u.frame_list.next->u.frame_list.prev = itd;
4088: itd->slot = frindex;
4089: itd->u.frame_list.prev = NULL;
4090:
4091: frindex += i;
4092: if (frindex >= sc->sc_flsize)
4093: frindex -= sc->sc_flsize;
4094:
4095: itd = itd->xfer_next;
4096: }
4097:
4098: epipe->u.isoc.cur_xfers++;
4099: epipe->u.isoc.next_frame = frindex;
4100:
4101: exfer->itdstart = start;
4102: exfer->itdend = stop;
4103: exfer->sqtdstart = NULL;
4104: exfer->sqtdstart = NULL;
4105:
1.153 jmcneill 4106: mutex_enter(&sc->sc_intrhead_lock);
1.139 jmcneill 4107: ehci_add_intr_list(sc, exfer);
1.153 jmcneill 4108: mutex_exit(&sc->sc_intrhead_lock);
1.139 jmcneill 4109: xfer->status = USBD_IN_PROGRESS;
4110: xfer->done = 0;
4111: splx(s);
4112:
4113: if (sc->sc_bus.use_polling) {
4114: printf("Starting ehci isoc xfer with polling. Bad idea?\n");
4115: ehci_waitintr(sc, xfer);
4116: }
4117:
4118: return USBD_IN_PROGRESS;
1.113 christos 4119: }
1.139 jmcneill 4120:
1.113 christos 4121: Static void
1.115 christos 4122: ehci_device_isoc_abort(usbd_xfer_handle xfer)
1.113 christos 4123: {
1.139 jmcneill 4124: DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer));
4125: ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
1.113 christos 4126: }
1.139 jmcneill 4127:
1.113 christos 4128: Static void
1.115 christos 4129: ehci_device_isoc_close(usbd_pipe_handle pipe)
1.113 christos 4130: {
1.146 jmcneill 4131: DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n"));
1.113 christos 4132: }
1.139 jmcneill 4133:
1.113 christos 4134: Static void
1.115 christos 4135: ehci_device_isoc_done(usbd_xfer_handle xfer)
1.113 christos 4136: {
1.139 jmcneill 4137: struct ehci_xfer *exfer;
4138: ehci_softc_t *sc;
4139: struct ehci_pipe *epipe;
4140: int s;
4141:
4142: exfer = EXFER(xfer);
4143: sc = xfer->pipe->device->bus->hci_private;
4144: epipe = (struct ehci_pipe *) xfer->pipe;
4145:
4146: s = splusb();
4147: epipe->u.isoc.cur_xfers--;
1.153 jmcneill 4148: mutex_enter(&sc->sc_intrhead_lock);
1.139 jmcneill 4149: if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) {
1.153 jmcneill 4150: ehci_del_intr_list(sc, exfer);
1.139 jmcneill 4151: ehci_rem_free_itd_chain(sc, exfer);
4152: }
1.153 jmcneill 4153: mutex_exit(&sc->sc_intrhead_lock);
1.139 jmcneill 4154: splx(s);
4155:
4156: usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE |
4157: BUS_DMASYNC_POSTREAD);
4158:
1.113 christos 4159: }
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