CVS log for src/sys/dev/sdmmc/sdhc.c

Up to [cvs.NetBSD.org] / src / sys / dev / sdmmc

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

If the ACPI flag "non-removable" is present and true for an SD/MMC
slot, then set a new flag on that slot to indicate that the media
is non-removable.  Make sdhc_card_detect always return true for a
slot if its non-removable media flag is set.

This change lets the kernel automatically configure the
permanently-installed MMC slot on the NXP LX2160-based HoneyComb
LX2 board.

Pull up following revision(s) (requested by jmcneill in ticket #561):

	etc/etc.evbppc/Makefile.inc: revision 1.15
	sys/arch/evbppc/wii/dev/wiifb.c: revision 1.1
	sys/arch/evbppc/wii/dev/wiifb.c: revision 1.2
	sys/arch/evbppc/wii/dev/bwdsp.c: revision 1.1
	sys/arch/evbppc/wii/dev/wiifb.c: revision 1.3
	sys/arch/evbppc/wii/dev/bwdsp.c: revision 1.2
	distrib/utils/embedded/files/evbppc_wii_icon.png: revision 1.1
	usr.sbin/sysinst/arch/evbppc/md.h: revision 1.4
	sys/arch/evbppc/wii/dev/wiifb.c: revision 1.4
	sys/arch/evbppc/wii/dev/viio.h: revision 1.1
	sys/arch/evbppc/wii/dev/wiifb.c: revision 1.5
	sys/arch/evbppc/wii/dev/mainbus.h: revision 1.1
	distrib/utils/embedded/conf/wii.conf: revision 1.1
	distrib/utils/embedded/conf/wii.conf: revision 1.2
	distrib/utils/embedded/conf/wii.conf: revision 1.3
	sys/dev/sdmmc/sdhcvar.h: revision 1.34
	sys/dev/sdmmc/sdhc.c: revision 1.118
	sys/arch/evbppc/wii/dev/resetbtn.c: revision 1.1
	distrib/utils/embedded/conf/evbppc.conf: revision 1.1
	sys/dev/wsfb/genfb.c: revision 1.91
	sys/arch/evbppc/wii/dev/resetbtn.c: revision 1.2
	sys/dev/wscons/wsconsio.h: revision 1.127
	sys/arch/powerpc/oea/oea_machdep.c: revision 1.85
	sys/arch/evbppc/wii/dev/hollywood.h: revision 1.1
	sys/arch/evbppc/conf/std.wii: revision 1.1
	sys/arch/evbppc/wii/dev/hollywood.h: revision 1.2
	sys/arch/evbppc/wii/dev/hollywood.c: revision 1.1
	sys/arch/evbppc/conf/std.wii: revision 1.2
	sys/arch/evbppc/wii/dev/hollywood.c: revision 1.2
	sys/arch/evbppc/conf/std.wii: revision 1.3
	sys/arch/powerpc/oea/cpu_subr.c: revision 1.109
	sys/arch/evbppc/wii/wii_mmuinit.S: revision 1.1
	sys/dev/usb/usb.h: revision 1.124
	sys/arch/evbppc/wii/machdep.c: revision 1.1
	sys/arch/evbppc/wii/dev/rtcsram.c: revision 1.1
	sys/arch/powerpc/include/oea/hid.h: revision 1.14
	sys/arch/evbppc/wii/mainbus.c: revision 1.1
	sys/arch/evbppc/wii/machdep.c: revision 1.2
	sys/arch/evbppc/wii/dev/ehci_hollywood.c: revision 1.1
	sys/arch/evbppc/wii/mainbus.c: revision 1.2
	sys/arch/evbppc/wii/machdep.c: revision 1.3
	sys/arch/evbppc/wii/dev/ehci_hollywood.c: revision 1.2
	sys/arch/evbppc/wii/mainbus.c: revision 1.3
	sys/arch/evbppc/wii/machdep.c: revision 1.4
	sys/arch/evbppc/wii/dev/hwgpio.c: revision 1.1
	sys/arch/evbppc/wii/dev/sdhc_hollywood.c: revision 1.1
	sys/arch/evbppc/wii/dev/sdhc_hollywood.c: revision 1.2
	sys/arch/evbppc/wii/wii_locore.S: revision 1.1
	sys/arch/evbppc/conf/files.wii: revision 1.1
	sys/arch/evbppc/wii/wii_locore.S: revision 1.2
	sys/arch/evbppc/include/wii.h: revision 1.1
	sys/arch/evbppc/conf/files.wii: revision 1.2
	sys/arch/evbppc/wii/dev/exi.c: revision 1.1
	sys/arch/evbppc/include/wii.h: revision 1.2
	sys/arch/evbppc/conf/files.wii: revision 1.3
	sys/arch/powerpc/powerpc/clock.c: revision 1.18
	sys/arch/evbppc/include/wii.h: revision 1.3
	sys/arch/evbppc/conf/files.wii: revision 1.4
	sys/arch/evbppc/include/wii.h: revision 1.4
	sys/arch/evbppc/wii/dev/exi.h: revision 1.1
	sys/arch/evbppc/wii/dev/avenc.c: revision 1.1
	sys/arch/evbppc/include/wii.h: revision 1.5
	sys/arch/evbppc/include/wii.h: revision 1.6
	sys/arch/evbppc/include/wii.h: revision 1.7
	sys/arch/evbppc/wii/dev/avenc.h: revision 1.1
	distrib/utils/embedded/mkimage: revision 1.79
	sys/arch/evbppc/conf/WII: revision 1.1
	sys/arch/evbppc/conf/INSTALL_WII: revision 1.1
	distrib/utils/embedded/files/evbppc_wii_meta.xml: revision 1.1
	sys/arch/evbppc/wii/dev/vireg.h: revision 1.1
	sys/arch/evbppc/conf/WII: revision 1.2
	distrib/utils/embedded/files/evbppc_wii_meta.xml: revision 1.2
	sys/arch/evbppc/wii/dev/vireg.h: revision 1.2
	sys/arch/evbppc/conf/WII: revision 1.3
	sys/arch/evbppc/conf/WII: revision 1.4
	usr.sbin/sysinst/arch/evbppc/md.c: revision 1.11
	sys/arch/evbppc/wii/dev/ohci_hollywood.c: revision 1.1
	sys/dev/usb/ehcivar.h: revision 1.52
	sys/arch/evbppc/wii/pic_pi.c: revision 1.1
	sys/arch/evbppc/wii/dev/ohci_hollywood.c: revision 1.2
	etc/etc.evbppc/ttys: revision 1.8
	sys/arch/evbppc/wii/dev/bwai.c: revision 1.1
	sys/arch/evbppc/wii/dev/bwai.c: revision 1.2
	sys/arch/evbppc/wii/dev/bwai.c: revision 1.3
	sys/arch/evbppc/wii/autoconf.c: revision 1.1
	sys/arch/evbppc/conf/Makefile.wii.inc: revision 1.1
	sys/arch/evbppc/wii/dev/bwai.h: revision 1.1
	sys/arch/evbppc/wii/autoconf.c: revision 1.2
	sys/arch/evbppc/conf/Makefile.wii.inc: revision 1.2

powerpc: oea: Fix prefetchable mappings
Prefetchable mappings need PMAP_NOCACHE to get write-combine semantics.
powerpc: oea: Decode IBM750CL L2 cache information.
sdmmc: add support for optional delay after register write
wscons: Add HOLLYWOOD display and YUY2 pixel format types
wsfb: add support for optional "devcmap" property
A hardware driver can supply a pointer to a 16x 32-bit array to override
the default rasops device colour map in the "devcmap" property.
ehci: add EHCIF_32BIT_ACCESS flag to force 32-bit MMIO
fix comments: HID0 ICFI/DCFI are "flash invalidate", not "flush invalidate"
powerpc: fix delay for large (> ~5sec) values
When calculating the target timebase, promote '1000' on the RHS to ULL
to force 64-bit calculation, otherwise 'n * 1000' will overflow.
usb: increase USB_PORT_RESET_RECOVERY from 10ms to 20ms
I changed this from 250ms to 10ms back in 2021 based on a similar FreeBSD
change, but it seems to be a bit too aggressive for some platforms.
evbppc: Add initial support for the Nintendo Wii
wii: support RB_POWERDOWN
build fix: use dd with count=1 for compat with NetBSD dd(1)
wii: Add NTSC 480p support.
In addition to this, add VIIO_{GET,SET}REGS ioctl support to allow for
poking at video interface registers from userland. This is helpful for
debugging display issues.
wii: Add 128x48 icon to SD card image
wii: Fix a comment
wii: Add drivers for Broadway DSP and Audio interface.
0: [*] audio0 @ bwdsp0: Broadway DSP
       playback: 16, 2ch, 48000Hz
       record:   unavailable
       (P-) slinear_be 16/16, 2ch, { 48000 }
wii: Add screenblank support.
wii: Use screen dimming register for screen blanking.
wii: Add GPIO, I2C, and basic A/V encoder driver.
wii: Use A/V encoder volume controls instead of using a software filter.
wii: Simply DSP driver - no interrupt handler required.
wii: provide device names to intr_establish
wii$ intrctl list
interrupt id      CPU0  device name(s)
pi irq 14        64769* hollywood0
hollywood irq 36  5872* ehci0
hollywood irq 39 58907* sdhc0
hollywood irq 40     4* sdhc1
hollywood irq 49     0* resetbtn0
pi irq 5             0* bwai0
wii: Add support for passing boot options to the kernel.
wii: Add External interface bus and RTC support
wii: Remove objcopy after kernel build.
HBC will do the right thing.
Add wsvt25 entries (off by default) for ttyE0-ttyE3.
Add support for "PAL" (576i) mode on Wii.

sdmmc: add support for optional delay after register write

Select DMA mode after programming the ADMA base address register(s).

The Arasan SDHCI 8.9a found in the Xilinx Zynq-7000 SoC requires this
sequence to avoid sporadic transfer errors.

Disable ADMA2 on Ricoh SDHCI controllers.

PR# 57015

sdhc: Retire SDHC_FLAG_USE_ADMA2 flag.

ADMA2 support in sdhc is mature now, so no need for it to be opt-in.

sdhc: avoid taking adaptive mutex while holding spin mutex

the clock_bus pre- and post- callbacks used in sdhc_bus_clock_ddr()
are called with a spin mutex held, and the new sdhc@acpi ends up
calling into (sleeping) ACPI code, triggering lockdebug assertion.

introduce an adaptive mutex that is held around these callbacks,
and reduce the spin mutex held time in sdhc_bus_clock_ddr().

sdhc: High speed support capability flag applies to eMMC too.

Pull up the following revisions (all via patch), requested by msaitoh
in ticket #1713:

	sys/dev/sdmmc/sdhc.c				1.110, 1.112
	sys/dev/sdmmc/sdmmc_mem.c			1.74
	sys/dev/pci/sdhc_pci.c				1.18

- Support 64bit BAR.
- Use unsigned to avoid undefined behavior in hwrite[12]() and
  sdmmc_mem_sd_switch().
- Fix typo in comment.

Pull up the followin revisions (all via patch), requested by msaitoh
in ticket #1383:

	sys/dev/sdmmc/sdhc.c				1.110, 1.112
	sys/dev/sdmmc/sdmmc_mem.c			1.74
	sys/dev/pci/sdhc_pci.c				1.18

- Support 64bit BAR.
- Use unsigned to avoid undefined behavior in hwrite[12]() and
  sdmmc_mem_sd_switch().
- Fix typo in comment.

s/suport/support/ in comment.

Merge thorpej-cfargs2.

Adapt to CFARGS().

Sync w/ HEAD.

sync with head

 Use unsigned to avoid undefined behavior in hwrite[12](). Found by kUBSan.

Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
  actually needed.
- Don't be explicit about what interface attribute is attaching if
  the device only has one.  (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
  situations, making is visibly easier to see when indirect config is
  in play, and allowing for future change in semantics.  (As of now,
  this is just a wrapper around config_match(), but that is an
  implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance.  This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

Sync with HEAD.

Give config_found() the same variadic arguments treatment as
config_search().  This commit only adds the CFARG_EOL sentinel
to the existing config_found() calls.  Conversion of config_found_sm_loc()
and config_found_ia() call sites will be in subsequent commits.

Enable block count only for count > 0.
Don't enable autostop when command sets new flag SCF_NO_STOP.

Pull up following revision(s) (requested by msaitoh in ticket #1592):

	sys/dev/sdmmc/sdhc.c: revision 1.107
	sys/dev/sdmmc/sdhcreg.h: revision 1.21

Identify SDHC 4.1 and 4.2. From {DragonFly,Free}BSD.

Pull up following revision(s) (requested by msaitoh in ticket #1021):

	sys/dev/sdmmc/sdhc.c: revision 1.107
	sys/dev/sdmmc/sdhcreg.h: revision 1.21

Identify SDHC 4.1 and 4.2. From {DragonFly,Free}BSD.

Identify SDHC 4.1 and 4.2. From {DragonFly,Free}BSD.

Mostly merge changes from HEAD upto 20200411

Pull up following revision(s) (requested by mrg in ticket #717):

	sys/dev/fdt/dwcmmc_fdt.c			1.11
	sys/dev/ic/bwfm.c				1.15-1.18
	sys/dev/ic/bwfmreg.h				1.4-1.6
	sys/dev/ic/bwfmvar.h				1.4,1.5
	sys/dev/ic/dwc_mmc.c				1.21,1.22
	sys/dev/ic/dwc_mmc_reg.h			1.8,1.9,1.12,1.13
	sys/dev/pcmcia/pcmciareg.h			1.11
	sys/dev/sdmmc/if_bwfm_sdio.c			1.4,1.6-1.12
	sys/dev/sdmmc/if_bwfm_sdio.h			1.1,1.2
	sys/dev/sdmmc/sdhc.c				1.105,1.106
	sys/dev/sdmmc/sdmmc.c				1.37,1.39
	sys/dev/sdmmc/sdmmc_cis.c			1.6,1.8
	sys/dev/sdmmc/sdmmc_io.c			1.15-1.19
	sys/dev/sdmmc/sdmmc_ioreg.h			1.4,1.5
	sys/dev/sdmmc/sdmmc_mem.c			1.69-1.71
	sys/dev/sdmmc/sdmmcdevs				1.5-1.8
	sys/dev/sdmmc/sdmmcvar.h			1.31,1.33,1.34
	sys/net/if_media.h				1.66

Add Broadcom devices
 -
Fix typo
 -
add PCMCIA_CISTPL_SDIO definition.
 -
From OpenBSD:
- move event handling to workqueue
- check for save/restore capability
 -
Tag work queue as MPsafe and increase length.
 -
Juse use bpf_mtap(), the 802.11 encapsulation is handled by firmware.
 -
From OpenBSD:
- support block length per function
- add functions to read/write regions
 -
Decode (but not use) SDIO tuple in CIS.
 -
Fix locking.
 -
Add more SDIO defines (partially from version 3.0).
 -
From OpenBSD:
- All the missing pieces (firmware load, chip setup, protocol handling)
TX queue and interrupt handling via sdmmc_task.
 -
Fix locking.
 -
Fix packet parsing.
 -
Add parser for original firmware config files.
 -
tagging work queue as MPSAFE was premature. Revert.
 -
SD_IO_RW_EXTENDED is a data transfer command, so set ADTC flag instead of AC
Use correct function to verify if a task has been queued. Avoids race
that can corrupt the task queue.
 -
More register definitions.
 -
Add IFM_IEEE80211_VHT subtype, IFM_IEEE80211_11AC operating mode, and missing descriptions
 -
If firmware is connected in HT or VHT mode, report it to SIOCGIFMEDIA
 -
white space police.

Skip setting power when the voltage doesn't change.
Also increase some timeouts.
 -
Add and use sdmmc_pause to avoid long-term busy waits.
 -
Add sdio abort function.
 -
Additional error messages.
 -
Print parameters for SDIO devices.
 -
Minor cosmetics.
 -
Simplyfy sdmmc_io_set_blocklen function signature by dropping the
extra softc pointer. Aligns with OpenBSD.
 -
Missing commit for sdio abort function.
 -
More code from OpenBSD
 -
no need to splnet() when enqueing packets
 -
explicit structure padding
 -
make internal functions static
 -
also prepare for GPIO interrupts.
 -
Avoid warnings for tautological shifts as sole conditional.
 -
Follow the Linux driver an use the FDT "compatible" property to build a
filename for the nvram config file, fall back to the standard filename.
E.g.
[Caching 123 nodes and 1093 properties]
compatible              73696e6f 766f6970 2c627069 2d6d322d   "sinovoip,bpi-m2-
            0010:       7a65726f 00...... ........ ........   zero"
            0015:       616c6c77 696e6e65 722c7375 6e38692d   "allwinner,sun8i-
            0025:       68322d70 6c757300 ........ ........   h2-plus"
interrupt-parent        00000001 ........ ........ ........   ....
model                   42616e61 6e612050 69204250 492d4d32   "Banana Pi BPI-M2
            0010:       2d5a6572 6f00.... ........ ........   -Zero"
name                    00...... ........ ........ ........   ""
serial-number           30326330 30303432 65636431 36376566   02c00042ecd167ef
            0010:       00...... ........ ........ ........   .
-rw-r--r--  1 root  wheel     875 Nov  2 12:06 brcmfmac43430-sdio.AP6212.txt
lrwxr-xr-x  1 root  wheel      29 Dec 30 16:19 brcmfmac43430-sdio.sinovoip,bpi-m2-zero.txt -> brcmfmac43430-sdio.AP6212.txt
-rw-r--r--  1 root  wheel     874 Jun 30  2019 brcmfmac43430-sdio.raspberrypi,3-model-b.txt
-rw-r--r--  1 root  wheel    1864 Jun 30  2019 brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt
lrwxr-xr-x  1 root  wheel      29 Dec 30 11:24 brcmfmac43455-sdio.raspberrypi,4-model-b-plus.txt -> brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt
 -
Add product ID for Broadcom BCM43455
 -
Use correct firmware for BCM43456
 -
size check was backwards.
 -
Be less noisy for some commands.
 -
Fix DWC_MMC_INT_SDIO_INT bit
 -
dwc_mmc fixes:
 - Rockchip uses a different SDIO int bit, so take this into consideration
 - Avoid unnecessary resets and always wait for resets to complete
 - kpause instead of delay while holding spinlock
 - Do not attempt autostop for SD_IO_RW_EXTENDED commands
 - Allow for sub-blklen byte counts for single block transfers
  -
More SDIO stability and performance fixes

Avoid warnings for tautological shifts as sole conditional.

Skip setting power when the voltage doesn't change.
Also increase some timeouts.

Add SDHC flags.

+ SDHC_FLAG_BROKEN_ADMA2_ZEROLEN
  Broken ADMA2 Zero length descriptor.
  Can't 64K Byte data transfer.
+ SDHC_FLAG_NO_1_8_V
  Support no 1.8V Supply.
  Disable UHS-I bus speed mode (SDR50, DDR50, SDR104).

If switching to fixed sampling clock, do not return an error to the sdmmc layer.

Sync with HEAD

Add vendor callback for post-bus clock ops and add SDHC_FLAG_STOP_WITH_TC flag

Pull up following revision(s) (requested by ryo in ticket #468):
	sys/dev/sdmmc/sdhcreg.h: revision 1.19
	sys/dev/sdmmc/sdhc.c: revision 1.101
fix problem for ESDHC/USDHC due to change of r1.96
on ESDHC/USDHC, even if the iosize is less than SDHC_HOST_CTL_VERSION,
specver must be an appropriate value.

update from HEAD

Sync with HEAD

fix problem for ESDHC/USDHC due to change of r1.96

on ESDHC/USDHC, even if the iosize is less than SDHC_HOST_CTL_VERSION,
specver must be an appropriate value.

Sync with HEAD

Add a vendor callback for setting signal voltage.

Sync with HEAD

Sync with HEAD

sdhc(4): hardware reset support for Intel eMMC controller

sdhc(4), sdmmc(4): Added MMC HS DDR52 support.

Sync with HEAD

Add flags SDHC_FLAG_NO_AUTO_STOP and SDHC_FLAG_NO_BUSY_INTR.

Don't access SDHC_HOST_CTL_VERSION, if iosize less than this.

Sync with HEAD

Use 1.65-1.95 voltage window for 1.8V support.

Sync with HEAD

Please more delay, if timeout in sdhc_wait_intr().

Sync with HEAD

add support iMX6 uSDHC
- some UHS-I/SDR104 card are not stable
- eMMC doesn't work yet

fix typo. use pmask for SDHC_PRESENT_STATE.

Sync with HEAD (as of 26th Dec)

Pull up following revision(s) (requested by jmcneill in ticket #1022):
	sys/dev/sdmmc/sdhc.c: revision 1.89
	sys/arch/arm/omap/omap3_sdhc.c: revision 1.19
	sys/dev/sdmmc/sdhcvar.h: revision 1.25
	sys/arch/evbarm/beagle/beagle_machdep.c: revision 1.62
allow vendor specific code to hook into bus width changes
Support 8-bit eMMC for TI AM335x. On my BeagleBone Black,
Before: 134217728 bytes transferred in 9.410 secs (14263307 bytes/sec)
After:  134217728 bytes transferred in 7.518 secs (17852850 bytes/sec)
enable 8-bit mode on AM335X SDMMC2

Also wait for DAT when sending RSP_BSY commands. Fixes PR 50388.

fix timeout path in soft reset when building with SDHC_DEBUG

allow vendor specific code to hook into bus width changes

support hiding command timeout messages with a new command flag and use this
when probing for cards. Should fix PR 50302.

Sync with HEAD

The iMX uSDHC controller doesn't have an interrupt error status flag,
the bit position is reserved and reads as value 0.
- Fake the flag if any of the error bits is set.
- uSDHC supports the 32bit access, the 16bit path doesn't need that quirk.

Don't test flags from error value in status value. Instead test the
error interrupt status.

fix DPRINTF parameters

Ignore data inhibit for commands that do not use the DAT line.
Do a soft reset when the inhibit condition persists for better
error recovery.

Simplify interrupt handling and print errors reported by the controller.

Add more specific debug messages for timeout errors.

Protect the whole tuning operation including the register setup.

Add a quirk for Ricoh 5U823 controller. Operation with a 100MHz
bus clock for SDR50 seems to be unstable, reduce frequency one notch
(effectively down to 66MHz with divisor = 3).

don't hold intr_lock while calling sdhc_execute_tuning

support re-tuning modes 1 and 2

Implement SDHC sampling clock tuning procedure.

lock more hardware accesses

Add SDHC_FLAG_POLL_CARD_DET flag which lets the bus glue request polling
instead of standard SDHC card insert / detach events.

Add support for DDR50 transfer modes.

better error message

don't select SDR12 mode if we are <= 400 kHz

dont confuse signaling voltage and bus voltage

let SDHC_FLAG_HOSTCAPS override SDHC_CAPABILITIES2 as well

add support for UHS-I modes on capable 3.0+ controllers

bus_dma_segment_t ds_addr is bus_addr_t not paddr_t (another case of it)

bus_dma_segment_t ds_addr is bus_addr_t not paddr_t

Be more verbose about error conditions.

correct (the commented out) calculation of bus frequency.

return MMC_OCR_HCS bit from host_ocr if the controller supports high-speed mode

Simplify sdhc(4) locking

print "platform DMA" instead of "SDMA" when using external DMA engine

Add ADMA2 support, which enables scatter gather DMA for data transfers on
controllers that support it.

Remove unnecessary #include

Add a SDHC_FLAG_NO_TIMEOUT quirk to handle spurious timeouts on Tegra K1
during data transfers. While here, increase the soft timeout for DMA
transfers from 1s to 3s.

Use C99 designated initializers.

No functional change.

Sync with HEAD

support 8-bit mode for SDHC 3.0+ controllers

print some useful information at attach time

Add SDHC_FLAG_SINGLE_POWER_WRITE flag, that tells the driver to update
the SDHC_POWER_CTL register with a single write rather than in multiple
steps. Required for Tegra K1 SDHC.

support SDHC 4.0, allow for overriding clk base frequency

Pull up following revision(s) (requested by bouyer in ticket #703):
	sys/dev/sdmmc/sdhcvar.h: revision 1.16
	sys/dev/sdmmc/sdhc.c: revision 1.55
Add a new SDHC_FLAG, SDHC_FLAG_EXTDMA_DMAEN, which request that the
SDHC_DMA_ENABLE bit be set in the command, even if we're using an
external DMA engine. Needed by the upcoming DMA support for AM335x
(beaglebone).

Add a new SDHC_FLAG, SDHC_FLAG_EXTDMA_DMAEN, which request that the
SDHC_DMA_ENABLE bit be set in the command, even if we're using an
external DMA engine. Needed by the upcoming DMA support for AM335x
(beaglebone).

Sync with HEAD

Pull up following revision(s) (requested by nonaka in ticket #577):
	sys/arch/powerpc/booke/dev/pq3sdhc.c: revision 1.6
	sys/dev/sdmmc/sdhc.c: revision 1.54
	sys/dev/sdmmc/sdmmc.c: revision 1.24
eSDHC has no DMA_BOUNDARY in BLOCK_SIZE register.
So clear multi segment DMA transfer support bit.
--
fix to simulate multi-segment dma transfer for pq3sdhc(4).
--
pq3sdhc: Enable DMA transfer.

eSDHC has no DMA_BOUNDARY in BLOCK_SIZE register.
So clear multi segment DMA transfer support bit.

Don't clear other bits. pq3sdhc is set more bits.

Pull up following revision(s) (requested by nonaka in ticket #460):
	sys/dev/sdmmc/sdhcreg.h: revision 1.12
	sys/dev/sdmmc/sdhc.c: revision 1.52
eSDHC has non standard Host Controller Version Register offset.

eSDHC has non standard Host Controller Version Register offset.

Pull up following revision(s) (requested by skrll in ticket #129):
	sys/dev/sdmmc/sdhcvar.h: revision 1.15
	sys/dev/sdmmc/sdhc.c: revision 1.51
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.19
Pass sdhc_softc instead of sdhc_host to sc_vendor_transfer_data_dma,
since the vendor specific code has no access to it otherwise,
but can easily do device_private(sdhc_softc->sc_dev).

pass sdhc_softc instead of sdhc_host to sc_vendor_transfer_data_dma, since the vendor specific code has no visibility into struct sdhc_host and can easily do device_private(sdhc_softc->sc_dev)

Pull up following revision(s) (requested by skrll in ticket #127):
	sys/dev/sdmmc/sdhc.c: revision 1.50
Fix divisor calculation for SDHC 3.0.

Pull up following revision(s) (requested by skrll in ticket #126):
	sys/arch/evbarm/rpi/rpi_machdep.c: revision 1.47
	sys/arch/arm/broadcom/bcm2835reg.h: revision 1.12
	sys/arch/evbarm/conf/RPI: revision 1.52
	sys/arch/evbarm/conf/RPI: revision 1.53
	sys/arch/evbarm/conf/RPI: revision 1.54
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.10
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.11
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.12
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.13
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.14
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.15
	sys/arch/arm/broadcom/bcm2835_dmac.c: revision 1.3
	sys/arch/arm/broadcom/bcm2835_dmac.c: revision 1.4
	sys/arch/arm/broadcom/bcm2835_dmac.h: revision 1.2
	sys/arch/arm/broadcom/bcm2835_dmac.c: revision 1.5
	sys/arch/arm/broadcom/bcm2835_emmc.c: revision 1.18
	sys/arch/arm/broadcom/bcm2835_dmac.h: revision 1.3
	sys/arch/arm/broadcom/bcm2835_dmac.c: revision 1.6
	sys/arch/arm/broadcom/bcm2835_dmac.c: revision 1.7
	sys/arch/arm/broadcom/bcm2835_dmac.c: revision 1.8
	sys/arch/arm/broadcom/bcm2835_dmac.c: revision 1.9
	sys/arch/arm/broadcom/files.bcm2835: revision 1.23
	sys/dev/sdmmc/sdhc.c: revision 1.45
	sys/dev/sdmmc/sdhc.c: revision 1.46
	sys/dev/sdmmc/sdhc.c: revision 1.47
	sys/dev/sdmmc/sdhcvar.h: revision 1.14
Various RPI DMAC and sdhc improvements.

Fix divisor calculation for SDHC 3.0.
1/1   -> 0
1/2   -> 1
1/4   -> 2
...
1/2*N -> N

Pull up following revision(s) (requested by jmcneill in ticket #124):
	sys/dev/sdmmc/sdhc.c: revision 1.49
Correct clk div calculation for SD 3.0 controllers.

correct clk div calculation for SD 3.0 controllers

Pull up following revision(s) (requested by jmcneill in ticket #123):
	sys/dev/sdmmc/sdhc.c: revision 1.48
Don't check slot type for pre-3.0 controllers, the bits were reserved at
the time. If an older controller advertises 1.8V support, just use it.
This fixes high-speed mode support for me on BeagleBone Black.

Don't check slot type for pre-3.0 controllers, the bits were reserved at
the time. If an older controller advertises 1.8V support, just use it.
This fixes high-speed mode support for me on BeagleBone Black.

When doing vendor dma transfer wait for SDHC_TRANSFER_COMPLETE.

From jmcneill@ with some layout changes from me.

Avoid NULL deref when sdhc(4) attaches via config_interrupts().

Allow sdhc(4) to use a non-integrated DMA engine.

Rebase to HEAD as of a few days ago.

Rebase.

eSDHC Controller doesn't have "Host SDMA Buffer Boundary" bit field

HAS_CGM -> HAVE_CGM (like current)
Add 32BIT_ACCESS

turn off debug

resync with head

Pull up following revision(s) (requested by skrll in ticket #813):

etc/MAKEDEV.tmpl					1.160
etc/etc.evbarm/MAKEDEV.conf				1.9
external/broadcom/rpi-firmware/dist/LICENCE.broadcom	1.1
external/broadcom/rpi-firmware/dist/bootcode.bin	1.1
external/broadcom/rpi-firmware/dist/bootcode.bin	1.2
external/broadcom/rpi-firmware/dist/fixup.dat		1.1
external/broadcom/rpi-firmware/dist/fixup.dat		1.2
external/broadcom/rpi-firmware/dist/fixup_cd.dat	1.1
external/broadcom/rpi-firmware/dist/fixup_cd.dat	1.2
external/broadcom/rpi-firmware/dist/start.elf		1.1
external/broadcom/rpi-firmware/dist/start.elf		1.2
external/broadcom/rpi-firmware/dist/start_cd.elf	1.1
external/broadcom/rpi-firmware/dist/start_cd.elf	1.2
sys/arch/arm/broadcom/bcm2835_bsc.c			1.1 via patch
sys/arch/arm/broadcom/bcm2835_bscreg.h			1.1 via patch
sys/arch/arm/broadcom/bcm2835_dotg.c			1.1 via patch
sys/arch/arm/broadcom/bcm2835_emmc.c			1.7 via patch
sys/arch/arm/broadcom/bcm2835_genfb.c			1.4 via patch
sys/arch/arm/broadcom/bcm2835_gpio_subr.c		1.2 via patch
sys/arch/arm/broadcom/bcm2835_gpio_subr.h		1.1 via patch
sys/arch/arm/broadcom/bcm2835_gpioreg.h			1.1 via patch
sys/arch/arm/broadcom/bcm2835_intr.c			1.3 via patch
sys/arch/arm/broadcom/bcm2835_mbox.c			1.5 via patch
sys/arch/arm/broadcom/bcm2835_mbox.h			1.4 via patch
sys/arch/arm/broadcom/bcm2835_obio.c			1.17 via patch
sys/arch/arm/broadcom/bcm2835_pm.c			1.2 via patch
sys/arch/arm/broadcom/bcm2835_rng.c			1.3 via patch
sys/arch/arm/broadcom/bcm2835_space.c			1.5 via patch
sys/arch/arm/broadcom/bcm2835_spi.c			1.1 via patch
sys/arch/arm/broadcom/bcm2835_spireg.h			1.1 via patch
sys/arch/arm/broadcom/bcm2835_tmr.c			1.3 via patch
sys/arch/arm/broadcom/bcm2835reg.h			1.10 via patch
sys/arch/arm/broadcom/files.bcm2835			1.14 via patch
sys/arch/evbarm/conf/RPI				1.23 via patch
sys/arch/evbarm/conf/files.rpi				1.3 via patch
sys/arch/evbarm/conf/mk.rpi				1.2 via patch
sys/arch/evbarm/conf/std.rpi				1.4 via patch
sys/arch/evbarm/rpi/rpi_machdep.c			1.34 via patch
sys/arch/evbarm/rpi/rpi_start.S				1.7 via patch
sys/arch/evbarm/rpi/rpi_vcmbox.c			1.2 via patch
sys/arch/evbarm/rpi/vcio.h				1.1 via patch
sys/arch/evbarm/rpi/vcprop.h				1.7 via patch
sys/conf/files						patch
sys/dev/sdmmc/sdhc.c					1.43
sys/dev/sdmmc/sdhcvar.h					1.13
sys/dev/usb/dwc_otg.c					1.45 via patch
sys/dev/usb/dwc_otgreg.h				1.5 via patch
sys/dev/usb/dwc_otgvar.h				1.11 via patch
sys/dev/usb/files.usb					1.126 via patch
sys/dev/usb/if_smsc.c					1.7 via patch
sys/dev/usb/if_smscreg.h				1.1 via patch
sys/dev/usb/if_smscvar.h				1.1 via patch
sys/dev/usb/usbdevices.config				patch
sys/dev/usb/usbdevs					1.633 via patch
sys/dev/usb/usbdevs.h					regen
sys/dev/usb/usbdevs_data.h				regen
sys/dev/wscons/wsconsio.h				1.105,1.107 via patch
sys/dev/wscons/wsdisplayvar.h				1.50
sys/dev/wscons/wsdisplay_util.c				1.2
sys/dev/videomode/edid.c				1.12 via patch

	Greatly improved Raspberry Pi support.  USB and onboard
	Ethernet should work.
	[skrll, ticket #813]

sync with head

sync with (a bit old) head

add SDHC_FLAG_NO_HS_BIT flag to prevent sdhc driver from setting the SDHC_HIGH_SPEED bit in SDHC_HOST_CTL, required to get many high speed cards working on rpi

If the command protocol calls for a trailing busy signal,
wait (up to 10 seconds) for it to be released.

Find correct slot index in sdhc_cfprint().

sys/dev/sdmmc/sdhc.c				patch
sys/dev/sdmmc/sdhcreg.h				patch

	Support SDHC version 3 clocks.
	[skrll, ticket #759]

SDHC_VOLTAGE_SUPP_1_8V is only valid in the presence of SDHC_EMBEDDED_SLOT.
Fixes probing of full-size 1GB Toshiba card made in 2008 that fails to
respond with a 1.8V supply.  (JMB389 (in TS-RDF1) host claims
SDHC_VOLTAGE_SUPP_1_8V but does not claim SDHC_EMBEDDED_SLOT.)

SMC_CAPS_DMA without SMC_CAPS_MULTI_SEG_DMA means we as a host driver only
can support one segment per operation.  This is not the case with SDHCI SDMA,
the only SDHCI DMA mechanism we currently support in sdhc(4).  Should fix
corrupt data on DMA-enabled SDHCI controllers claiming conformance to a SDHCI
Specification other than 1.0.

Add support for SDHCI 3.0 bus clock generation, which unlike 1.0 and 2.0
has support for non-power-of-two divisors from 1 to 1023. Additionally
restore finding the correct power-of-two divisor for standard-compliant
pre-3.0 SDHCI parts.  Also, calculate minimum divided clock for the
clkmsk-quirk parts correctly.

XXX Will future standard-compliant SDHCI versions have a SDHCI 3.0
backwards-compatible clock generator, or just SDHCI 1.0/2.0?

If we get a SDMA boundary-crossing interrupt at the end of the final
segment, the transfer is not implicitly complete; we still need to wait
for the transfer complete interrupt so that we can issue new commands
successfully.

This fixes the problem my Ricoh R5C822 was having where all writes after
a larger (64KiB) write were failing because we attempted to issue CMD13
(to check the status of the aformentioned write) too soon afterwards.

I suspect this fix to apply to other Ricoh SDHCI controllers I've heard
people have had trouble with.  Sorry I didn't look at this sooner.

Change sdhc_detach so that it detaches all host controllers at once.
This should make multiple slot controllers, for example those with
a controller on more than one PCI/CardBus BAR, detach with fewer bugs.
Tested with as-of-yet-uncommited sdhc_pci changes on a single-host
ExpressCard JMicron JMB38[89].

Implement TI AM335x's SDHC reset quirk.  Beaglebone SDHC works now!

On the AM335x, we first must wait for the controller to acknowledge
the reset; then we can wait for the reset to complete.

I believe this quirk also applies to the OMAP4 ES, but I don't have
one of those to test and we don't seem to have an obvious conditional
for it anyway.

This quirk may work for controllers that don't require it too, but I
am nervous about doing it by default because if we miss the reset
acknowledgement, then we'll just time out even though everything is
really hunky-dory.

Also, for all sdhc, don't bother writing 0 in sdhc_soft_reset while
waiting for the reset to complete; there is no need.

ok matt

Add sc_vendor_bus_clock hook
From jmcneill.

Avoid the 16-bit read in sdhc_host_found for 32-bit-only devices.

This change makes sdhc_host_found allocate hp up front before showing
the identification, in order to avoid having to open-code a copy of
HREAD2 before hp is available.

Resync to 2012-11-19 00:00:00 UTC

sync with head

Support omap3 SDHC driver.  tested on OVERO only.

Don't use const foo const as type, one const is enough.

Support deciphering SDHCv3 clock rates.

Pull up revisions:
  src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
  src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
  src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
  src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
  src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
  src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
  src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
  src/sys/arch/arm/arm32/cpu.c revision 1.79
  src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
  src/sys/arch/arm/arm32/pmap.c revision 1.229
  src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
  src/sys/arch/arm/include/cpu.h revision 1.64
  src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
  src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
  src/sys/arch/arm/conf/files.arm revision 1.106
  src/sys/arch/arm/include/cpufunc.h revision 1.57
  src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
  src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
  src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
  src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
  src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
  src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
  src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
  src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
  src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
  src/sys/arch/evbarm/Makefile revision 1.9
  src/sys/arch/evbarm/conf/RPI revision 1.1
  src/sys/arch/evbarm/conf/files.rpi revision 1.1
  src/sys/arch/evbarm/conf/mk.rpi revision 1.1
  src/sys/arch/evbarm/conf/std.rpi revision 1.1
  src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
  src/sys/arch/evbarm/rpi/rpi.h revision 1.1
  src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
  src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
  src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).

don't mix #define<TAB> and #define<SPACE> in a file.

avoid warning with options PLCOM_DEBUG for INTEGRATOR.

Rename register values. No functional change - same code before and after.

Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.

Replace the simple_lock with a kmutex_t.  Update the locking to match
com(4) in the few places it didn't already.

DOH.  Replace a line that got accidently deleted in the last commit.

device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t

Add the 'Z' to the 1176 cpu product name.

ok matt@

Fix locking botch introduced in 1.36.

Fix a KASSERT. From/OK'ed by matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

Add the documented ARM11[37]6 Auxiliary control register defines.

Add support for the ARM1176JZS

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Provide a method for attachments to specify capabilites.

Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.

Tested on a RaspberryPi.

PL010 not tested.

Initial commit of support for the RaspberryPI (www.raspberrypi.org)

This is enough for serial console via the gpio header pins and to get to
multiuser.

A huge thank you to Matt Thomas for all his help.

Add RPI to KERNEL_SETS

Remove #if 0 code.

Pull up revisions:
  src/sys/dev/sdmmc/sdhc.c revisions 1.16,1.20,1.21,1.22,1.23 via patch,1.25
  src/sys/dev/sdmmc/sdhcreg.h revision 1.8
  src/sys/dev/sdmmc/sdmmc_mem.c revisions 1.21,1.22
  src/sys/dev/sdmmc/sdmmcreg.h revisions 1.10,1.11,1.12
(requested by matt in ticket 441).

SDHCI byte swaps the BE response on the wire into LE registers.
As we always want response data in LE, use bus_space_read_stream.
Additonally, read response data in 1 or 4 4-byte chunks, instead of
one 4-byte chunk or 15 1-byte chunks.

bus_space_*_stream_N() functions are not universally available.
Provite alternate implementation for when they are unavailable.

Handle interrupt acknowledgement in the SDHC_FLAG_32BIT_ACCESS case in
the same way as non-SDHC_FLAG_32BIT_ACCESS case.

If there was an error in 32-bit mode, just set ERROR_INTERRUPT otherwise
see if matched anything we care about.

Add use of watermark register when PIO to an ESDHC.  After every kill or
drain of watermask words, pause a bit to give time for the fifo to recover.
Always the command response in BE byteorder.  Rewrite __bitfield to deal
with this.

Responses are actually in host order (except SCR which is return in
big endian so that's convert to host order).

Fix comments about __bitfield.

Make PIO on normal SDHC devices work correctly on big-endian machines.
Add locking around interrupt manipulation (it should now be MP safe).

Only SDHC 1.0 controllers can do that fucky MULTI_SEG stuff.

sdhc(4) currently only implements support for the SDHC 1.0 DMA mechanism, so
only enable in that case.

MULTI_SEG does not for ESDHC.  (Don't know how it works at all on any SDHC
but ...)

Responses are actually in host order (except SCR which is return in
big endian so that's convert to host order).

Provide a method for attachments to specify capabilites.

Add use of watermark register when PIO to an ESDHC.  After every kill or
drain of watermask words, pause a bit to give time for the fifo to recover.
Always the command response in BE byteorder.  Rewrite __bitfield to deal
with this.

If there was an error in 32-bit mode, just set ERROR_INTERRUPT otherwise
see if matched anything we care about.

Handle interrupt acknowledgement in the SDHC_FLAG_32BIT_ACCESS case in
the same way as non-SDHC_FLAG_32BIT_ACCESS case.

bus_space_*_stream_N() functions are not universally available.
Provite alternate implementation for when they are unavailable.

Completely rework (and enable) SDHC 1.0 DMA data transfer.

While without a large physically-contiguous buffer the performance
suffers severly, this should still be better than PIO.

No need to panic on failure to find a divisor.
Additionally, add commented out calculation of actual clock frequency.

SDHC can have multiple slots, note which slot a specific sdmmc(4) attaches to.

SDHCI byte swaps the BE response on the wire into LE registers.
As we always want response data in LE, use bus_space_read_stream.
Additonally, read response data in 1 or 4 4-byte chunks, instead of
one 4-byte chunk or 15 1-byte chunks.

Always enable and set block count register.  We never do infinite transfers.
The old way seemed to be causing issues on a R5C822, at least with DMA enabled.

Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).

Pull up following revision(s) (requested by matt in ticket #254):
	sys/arch/powerpc/booke/dev/pq3sdhc.c: revision 1.4
	sys/dev/sdmmc/sdhc.c: revision 1.11
	sys/dev/sdmmc/sdhc.c: revision 1.13
Use the new 32-bit and ESDHC support in sdhc.c
Support 32-bit only access to the SDHC registers.
Add support for FreeScale "Enhanced" SDHC port.
Add support for CGM mode (XLP and BCM2835 (Arason)).
Do not read past array end, found by gcc -O3.
This could cause to HWRITE4() a bad value, but maybe last 2 bytes are
probably ignored by hardware anyway.

sync with head

sync to latest -current.

Do not read past array end, found by gcc -O3.
This could cause to HWRITE4() a bad value, but maybe last 2 bytes are
probably ignored by hardware anyway.

sync to -current

sync to -current

sync to latest -current.

Added Ricoh 5U822/5U823 SD/MMC Controller support.

sync to -current.

Support 32-bit only access to the SDHC registers.
Add support for FreeScale "Enhanced" SDHC port.
Add support for CGM mode (XLP and BCM2835 (Arason)).

merge to -current.

Use "opt_sdmmc.h" for SDHC_DEBUG.

Sync/merge with changes from matt-nb5-pq3

Add support for >63MHZ speeds.
Add support for extended clock division via CGM.

Backport flash/nand/nor subsystem from -HEAD.

Add some inital changes for the Freescale eSDHC.

sync with head

Sync with HEAD (-D20101022).

sync with head

Support change Open-drain/Push-pull by bus_rod().

sync with head.

sync with head

Sync with HEAD.

sync to netbsd-5

file sdhc.c was added on branch matt-nb5-mips64 on 2010-04-21 00:27:52 +0000

Added sdhc at cardbus support.

sync with head

A pointer typedef entails trading too much flexibility to declare const
and non-const types, and the kernel uses both const and non-const
PMF qualifiers and device suspensors, so change the pmf_qual_t and
device_suspensor_t typedefs from "pointers to const" to non-pointer,
non-const types.

According to SD Host Controller Simplified Specification Version 2.00, 2.2.10.
Host Control Register (Offset 028h), the "Data Transfer Width" bit is in Host
Control Register (Offset 028h), not Power Control Register (Offset 029h).

Expand PMF_FN_* macros.

Pull up the following revisions(s) (requested by jmcneill in ticket #1044):
	distrib/sets/lists/man/mi:		patch
	share/man/man4/Makefile:		patch
	sys/arch/amd64/conf/files.amd64:	1.67
	sys/arch/i386/conf/files.i386:		1.349
	sys/conf/files				1.945
	share/man/man4/sdmmc.4:			1.1-1.4
	sys/dev/sdmmc/Makefile.sdmmcdevs	1.1
	sys/dev/sdmmc/devlist2h.awk		1.1
	sys/dev/sdmmc/files.sdmmc		1.1-1.2
	sys/dev/sdmmc/ld_sdmmc.c		1.1-1.3
	sys/dev/sdmmc/sbt.c			1.1-1.2
	sys/dev/sdmmc/sdhc.c			1.1-1.3
	sys/dev/sdmmc/sdhcreg.h			1.1
	sys/dev/sdmmc/sdhcvar.h			1.1
	sys/dev/sdmmc/sdmmc.c			1.1
	sys/dev/sdmmc/sdmmc_cis.c		1.1
	sys/dev/sdmmc/sdmmc_io.c		1.1
	sys/dev/sdmmc/sdmmc_ioreg.h		1.1
	sys/dev/sdmmc/sdmmc_mem.c		1.1-1.2
	sys/dev/sdmmc/sdmmcchip.h		1.1
	sys/dev/sdmmc/sdmmcdevs			1.1
	sys/dev/sdmmc/sdmmcdevs.h		1.1-1.2
	sys/dev/sdmmc/sdmmcreg.h		1.1-1.3
	sys/dev/sdmmc/sdmmcvar.h		1.1

Add sdmmc framework

file sdhc.c was added on branch netbsd-5 on 2009-10-07 15:41:13 +0000

Typo in comment.

Sync with HEAD.

sync with head

fix crash with LOCKDEBUG+DIAGNOSTIC kernels:

sdhc_bus_clock() calls mutex_enter().
then in DIAGNOSTIC section, sdhc_bus_clock() calls sdhc_card_detect().
sdhc_card_detect() calls mutex_enter() on the same mutex again.
when LOCKDEBUG is enabled, you get

Mutex error: lockdebug_wantlock: locking against myself

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Sync with HEAD.

file sdhc.c was added on branch jym-xensuspend on 2009-05-13 17:21:29 +0000

file sdhc.c was added on branch yamt-nfs-mp on 2009-05-04 08:13:18 +0000

file sdhc.c was added on branch nick-hppapmap on 2009-04-28 07:36:33 +0000

Added SD/MMC support from OpenBSD.
tested on i386, amd64 at current-users ML by pgoyette@.
tested on zaurus by myself.