Annotation of src/sys/dev/pcmcia/if_xi.c, Revision 1.80.14.1
1.80.14.1! pgoyette 1: /* $NetBSD: if_xi.c,v 1.81 2018/06/22 04:17:42 msaitoh Exp $ */
1.1 gmcgarry 2: /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */
1.5 thorpej 3:
4: /*
1.39 mycroft 5: * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Charles M. Hannum.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
1.5 thorpej 20: */
1.1 gmcgarry 21:
22: /*
23: * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas
24: * All rights reserved.
25: *
26: * Redistribution and use in source and binary forms, with or without
27: * modification, are permitted provided that the following conditions
28: * are met:
29: * 1. Redistributions of source code must retain the above copyright
30: * notice, this list of conditions and the following disclaimer.
31: * 2. Redistributions in binary form must reproduce the above copyright
32: * notice, this list of conditions and the following disclaimer in the
33: * documentation and/or other materials provided with the distribution.
34: * 3. All advertising materials mentioning features or use of this software
35: * must display the following acknowledgement:
36: * This product includes software developed by Niklas Hallqvist,
37: * Brandon Creighton and Job de Haas.
38: * 4. The name of the author may not be used to endorse or promote products
39: * derived from this software without specific prior written permission
40: *
41: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
42: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
44: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
45: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
46: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51: */
52:
53: /*
54: * A driver for Xircom CreditCard PCMCIA Ethernet adapters.
55: */
56:
1.18 lukem 57: #include <sys/cdefs.h>
1.80.14.1! pgoyette 58: __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.81 2018/06/22 04:17:42 msaitoh Exp $");
1.1 gmcgarry 59:
60: #include "opt_inet.h"
61:
62: #include <sys/param.h>
63: #include <sys/systm.h>
64: #include <sys/device.h>
65: #include <sys/ioctl.h>
66: #include <sys/mbuf.h>
67: #include <sys/malloc.h>
68: #include <sys/socket.h>
1.47 mycroft 69: #include <sys/kernel.h>
70: #include <sys/proc.h>
1.1 gmcgarry 71:
72: #include <net/if.h>
73: #include <net/if_dl.h>
74: #include <net/if_media.h>
75: #include <net/if_types.h>
76: #include <net/if_ether.h>
1.80.14.1! pgoyette 77: #include <net/bpf.h>
1.1 gmcgarry 78:
79: #ifdef INET
80: #include <netinet/in.h>
81: #include <netinet/in_systm.h>
82: #include <netinet/in_var.h>
83: #include <netinet/ip.h>
84: #include <netinet/if_inarp.h>
85: #endif
86:
87: /*
88: * Maximum number of bytes to read per interrupt. Linux recommends
89: * somewhere between 2000-22000.
90: * XXX This is currently a hard maximum.
91: */
92: #define MAX_BYTES_INTR 12000
93:
94: #include <dev/mii/mii.h>
95: #include <dev/mii/miivar.h>
96:
97: #include <dev/pcmcia/pcmciareg.h>
98: #include <dev/pcmcia/pcmciavar.h>
99: #include <dev/pcmcia/pcmciadevs.h>
100:
101: #include <dev/pcmcia/if_xireg.h>
1.39 mycroft 102: #include <dev/pcmcia/if_xivar.h>
1.1 gmcgarry 103:
104: #ifdef __GNUC__
1.54 perry 105: #define INLINE inline
1.1 gmcgarry 106: #else
107: #define INLINE
108: #endif /* __GNUC__ */
109:
1.39 mycroft 110: #define XIDEBUG
1.40 mycroft 111: #define XIDEBUG_VALUE 0
1.35 mycroft 112:
1.1 gmcgarry 113: #ifdef XIDEBUG
114: #define DPRINTF(cat, x) if (xidebug & (cat)) printf x
115:
1.39 mycroft 116: #define XID_CONFIG 0x01
117: #define XID_MII 0x02
118: #define XID_INTR 0x04
119: #define XID_FIFO 0x08
120: #define XID_MCAST 0x10
1.1 gmcgarry 121:
122: #ifdef XIDEBUG_VALUE
123: int xidebug = XIDEBUG_VALUE;
124: #else
125: int xidebug = 0;
126: #endif
127: #else
128: #define DPRINTF(cat, x) (void)0
129: #endif
130:
1.39 mycroft 131: #define STATIC
1.1 gmcgarry 132:
1.51 perry 133: STATIC int xi_enable(struct xi_softc *);
134: STATIC void xi_disable(struct xi_softc *);
135: STATIC void xi_cycle_power(struct xi_softc *);
1.60 christos 136: STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *);
1.51 perry 137: STATIC void xi_full_reset(struct xi_softc *);
138: STATIC void xi_init(struct xi_softc *);
1.60 christos 139: STATIC int xi_ioctl(struct ifnet *, u_long, void *);
1.67 cegger 140: STATIC int xi_mdi_read(device_t, int, int);
141: STATIC void xi_mdi_write(device_t, int, int, int);
1.51 perry 142: STATIC int xi_mediachange(struct ifnet *);
143: STATIC u_int16_t xi_get(struct xi_softc *);
144: STATIC void xi_reset(struct xi_softc *);
145: STATIC void xi_set_address(struct xi_softc *);
146: STATIC void xi_start(struct ifnet *);
1.73 matt 147: STATIC void xi_statchg(struct ifnet *);
1.51 perry 148: STATIC void xi_stop(struct xi_softc *);
149: STATIC void xi_watchdog(struct ifnet *);
1.3 gmcgarry 150:
1.39 mycroft 151: void
1.66 dsl 152: xi_attach(struct xi_softc *sc, u_int8_t *myea)
1.1 gmcgarry 153: {
154: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
155:
1.39 mycroft 156: #if 0
1.1 gmcgarry 157: /*
1.11 gmcgarry 158: * Configuration as advised by DINGO documentation.
1.1 gmcgarry 159: * Dingo has some extra configuration registers in the CCR space.
160: */
1.39 mycroft 161: if (sc->sc_chipset >= XI_CHIPSET_DINGO) {
1.1 gmcgarry 162: struct pcmcia_mem_handle pcmh;
163: int ccr_window;
1.30 martin 164: bus_size_t ccr_offset;
1.1 gmcgarry 165:
1.11 gmcgarry 166: /* get access to the DINGO CCR space */
1.1 gmcgarry 167: if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO,
168: &pcmh)) {
1.2 gmcgarry 169: DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n"));
1.1 gmcgarry 170: goto fail;
171: }
172: if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR,
173: psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO,
174: &pcmh, &ccr_offset, &ccr_window)) {
1.2 gmcgarry 175: DPRINTF(XID_CONFIG, ("xi: bad mem map\n"));
1.1 gmcgarry 176: pcmcia_mem_free(psc->sc_pf, &pcmh);
177: goto fail;
178: }
179:
1.11 gmcgarry 180: /* enable the second function - usually modem */
1.1 gmcgarry 181: bus_space_write_1(pcmh.memt, pcmh.memh,
182: ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT);
183: bus_space_write_1(pcmh.memt, pcmh.memh,
184: ccr_offset + PCMCIA_CCR_DCOR1,
185: PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6);
186: bus_space_write_1(pcmh.memt, pcmh.memh,
187: ccr_offset + PCMCIA_CCR_DCOR2, 0);
188: bus_space_write_1(pcmh.memt, pcmh.memh,
189: ccr_offset + PCMCIA_CCR_DCOR3, 0);
190: bus_space_write_1(pcmh.memt, pcmh.memh,
191: ccr_offset + PCMCIA_CCR_DCOR4, 0);
192:
193: /* We don't need them anymore and can free them (I think). */
194: pcmcia_mem_unmap(psc->sc_pf, ccr_window);
195: pcmcia_mem_free(psc->sc_pf, &pcmh);
196: }
1.39 mycroft 197: #endif
1.11 gmcgarry 198:
1.39 mycroft 199: /* Reset and initialize the card. */
200: xi_full_reset(sc);
1.1 gmcgarry 201:
1.69 dyoung 202: printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea));
1.1 gmcgarry 203:
204: ifp = &sc->sc_ethercom.ec_if;
1.39 mycroft 205: /* Initialize the ifnet structure. */
1.69 dyoung 206: strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
1.1 gmcgarry 207: ifp->if_softc = sc;
208: ifp->if_start = xi_start;
209: ifp->if_ioctl = xi_ioctl;
210: ifp->if_watchdog = xi_watchdog;
211: ifp->if_flags =
212: IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST;
1.7 thorpej 213: IFQ_SET_READY(&ifp->if_snd);
1.1 gmcgarry 214:
1.39 mycroft 215: /* 802.1q capability */
216: sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
217:
218: /* Attach the interface. */
219: if_attach(ifp);
1.79 ozaki-r 220: if_deferred_start_init(ifp, NULL);
1.39 mycroft 221: ether_ifattach(ifp, myea);
1.1 gmcgarry 222:
223: /*
224: * Initialize our media structures and probe the MII.
225: */
226: sc->sc_mii.mii_ifp = ifp;
227: sc->sc_mii.mii_readreg = xi_mdi_read;
228: sc->sc_mii.mii_writereg = xi_mdi_write;
229: sc->sc_mii.mii_statchg = xi_statchg;
1.63 dyoung 230: sc->sc_ethercom.ec_mii = &sc->sc_mii;
1.1 gmcgarry 231: ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange,
1.63 dyoung 232: ether_mediastatus);
1.1 gmcgarry 233: DPRINTF(XID_MII | XID_CONFIG,
1.69 dyoung 234: ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1)));
1.39 mycroft 235:
1.69 dyoung 236: mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1.1 gmcgarry 237: MII_OFFSET_ANY, 0);
238: if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL)
239: ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0,
240: NULL);
241: ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
242:
1.72 tls 243: rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev),
1.74 tls 244: RND_TYPE_NET, RND_FLAG_DEFAULT);
1.1 gmcgarry 245: }
246:
247: int
1.67 cegger 248: xi_detach(device_t self, int flags)
1.1 gmcgarry 249: {
1.68 dyoung 250: struct xi_softc *sc = device_private(self);
1.1 gmcgarry 251: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
252:
1.39 mycroft 253: DPRINTF(XID_CONFIG, ("xi_detach()\n"));
1.1 gmcgarry 254:
1.42 mycroft 255: xi_disable(sc);
1.1 gmcgarry 256:
1.39 mycroft 257: rnd_detach_source(&sc->sc_rnd_source);
1.1 gmcgarry 258:
1.39 mycroft 259: mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
260: ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
261: ether_ifdetach(ifp);
262: if_detach(ifp);
1.1 gmcgarry 263:
264: return 0;
265: }
266:
267: int
1.66 dsl 268: xi_intr(void *arg)
1.1 gmcgarry 269: {
270: struct xi_softc *sc = arg;
271: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1.45 mycroft 272: u_int8_t esr, rsr, isr, rx_status;
1.33 mycroft 273: u_int16_t tx_status, recvcount = 0, tempint;
1.1 gmcgarry 274:
1.2 gmcgarry 275: DPRINTF(XID_CONFIG, ("xi_intr()\n"));
1.1 gmcgarry 276:
1.69 dyoung 277: if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev))
1.1 gmcgarry 278: return (0);
279:
280: ifp->if_timer = 0; /* turn watchdog timer off */
281:
1.45 mycroft 282: PAGE(sc, 0);
1.39 mycroft 283: if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) {
1.1 gmcgarry 284: /* Disable interrupt (Linux does it). */
1.48 mycroft 285: bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0);
1.1 gmcgarry 286: }
287:
1.48 mycroft 288: esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR);
289: isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0);
290: rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR);
1.52 perry 291:
1.1 gmcgarry 292: /* Check to see if card has been ejected. */
293: if (isr == 0xff) {
294: #ifdef DIAGNOSTIC
1.69 dyoung 295: printf("%s: interrupt for dead card\n",
296: device_xname(sc->sc_dev));
1.1 gmcgarry 297: #endif
298: goto end;
299: }
1.39 mycroft 300: DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr));
1.1 gmcgarry 301:
1.39 mycroft 302: PAGE(sc, 0x40);
1.1 gmcgarry 303: rx_status =
1.48 mycroft 304: bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0);
305: bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff);
1.1 gmcgarry 306: tx_status =
1.48 mycroft 307: bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0);
1.23 martin 308: tx_status |=
1.48 mycroft 309: bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8;
310: bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0);
311: bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0);
1.39 mycroft 312: DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status,
313: tx_status));
1.1 gmcgarry 314:
315: PAGE(sc, 0);
316: while (esr & FULL_PKT_RCV) {
317: if (!(rsr & RSR_RX_OK))
318: break;
319:
320: /* Compare bytes read this interrupt to hard maximum. */
321: if (recvcount > MAX_BYTES_INTR) {
322: DPRINTF(XID_INTR,
1.2 gmcgarry 323: ("xi: too many bytes this interrupt\n"));
1.1 gmcgarry 324: ifp->if_iqdrops++;
325: /* Drop packet. */
1.48 mycroft 326: bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0,
327: DO_SKIP_RX_PKT);
1.1 gmcgarry 328: }
329: tempint = xi_get(sc); /* XXX doesn't check the error! */
330: recvcount += tempint;
331: ifp->if_ibytes += tempint;
1.48 mycroft 332: esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR);
333: rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR);
1.1 gmcgarry 334: }
1.52 perry 335:
1.1 gmcgarry 336: /* Packet too long? */
337: if (rsr & RSR_TOO_LONG) {
338: ifp->if_ierrors++;
1.2 gmcgarry 339: DPRINTF(XID_INTR, ("xi: packet too long\n"));
1.1 gmcgarry 340: }
341:
342: /* CRC error? */
343: if (rsr & RSR_CRCERR) {
344: ifp->if_ierrors++;
1.2 gmcgarry 345: DPRINTF(XID_INTR, ("xi: CRC error detected\n"));
1.1 gmcgarry 346: }
347:
348: /* Alignment error? */
349: if (rsr & RSR_ALIGNERR) {
350: ifp->if_ierrors++;
1.2 gmcgarry 351: DPRINTF(XID_INTR, ("xi: alignment error detected\n"));
1.1 gmcgarry 352: }
353:
354: /* Check for rx overrun. */
355: if (rx_status & RX_OVERRUN) {
1.23 martin 356: ifp->if_ierrors++;
1.48 mycroft 357: bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN);
1.2 gmcgarry 358: DPRINTF(XID_INTR, ("xi: overrun cleared\n"));
1.1 gmcgarry 359: }
1.52 perry 360:
1.1 gmcgarry 361: /* Try to start more packets transmitting. */
1.79 ozaki-r 362: if_schedule_deferred_start(ifp);
1.1 gmcgarry 363:
364: /* Detected excessive collisions? */
365: if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) {
1.2 gmcgarry 366: DPRINTF(XID_INTR, ("xi: excessive collisions\n"));
1.48 mycroft 367: bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX);
1.1 gmcgarry 368: ifp->if_oerrors++;
369: }
1.52 perry 370:
1.1 gmcgarry 371: if ((tx_status & TX_ABORT) && ifp->if_opackets > 0)
372: ifp->if_oerrors++;
373:
1.33 mycroft 374: /* have handled the interrupt */
1.52 perry 375: rnd_add_uint32(&sc->sc_rnd_source, tx_status);
1.33 mycroft 376:
1.1 gmcgarry 377: end:
378: /* Reenable interrupts. */
1.45 mycroft 379: PAGE(sc, 0);
1.48 mycroft 380: bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT);
1.11 gmcgarry 381:
1.1 gmcgarry 382: return (1);
383: }
384:
385: /*
386: * Pull a packet from the card into an mbuf chain.
387: */
1.39 mycroft 388: STATIC u_int16_t
1.66 dsl 389: xi_get(struct xi_softc *sc)
1.1 gmcgarry 390: {
391: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
392: struct mbuf *top, **mp, *m;
393: u_int16_t pktlen, len, recvcount = 0;
394: u_int8_t *data;
1.52 perry 395:
1.2 gmcgarry 396: DPRINTF(XID_CONFIG, ("xi_get()\n"));
1.1 gmcgarry 397:
398: PAGE(sc, 0);
399: pktlen =
1.48 mycroft 400: bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK;
1.1 gmcgarry 401:
402: DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen));
403:
404: if (pktlen == 0) {
405: /*
406: * XXX At least one CE2 sets RBC0 == 0 occasionally, and only
407: * when MPE is set. It is not known why.
408: */
409: return (0);
410: }
411:
412: /* XXX should this be incremented now ? */
413: recvcount += pktlen;
414:
415: MGETHDR(m, M_DONTWAIT, MT_DATA);
1.56 christos 416: if (m == NULL)
1.1 gmcgarry 417: return (recvcount);
1.77 ozaki-r 418: m_set_rcvif(m, ifp);
1.1 gmcgarry 419: m->m_pkthdr.len = pktlen;
420: len = MHLEN;
1.56 christos 421: top = NULL;
1.1 gmcgarry 422: mp = ⊤
1.52 perry 423:
1.1 gmcgarry 424: while (pktlen > 0) {
425: if (top) {
426: MGET(m, M_DONTWAIT, MT_DATA);
1.56 christos 427: if (m == NULL) {
1.1 gmcgarry 428: m_freem(top);
429: return (recvcount);
430: }
431: len = MLEN;
432: }
433: if (pktlen >= MINCLSIZE) {
434: MCLGET(m, M_DONTWAIT);
435: if (!(m->m_flags & M_EXT)) {
436: m_freem(m);
437: m_freem(top);
438: return (recvcount);
439: }
440: len = MCLBYTES;
441: }
1.56 christos 442: if (top == NULL) {
1.60 christos 443: char *newdata = (char *)ALIGN(m->m_data +
1.1 gmcgarry 444: sizeof(struct ether_header)) -
445: sizeof(struct ether_header);
446: len -= newdata - m->m_data;
447: m->m_data = newdata;
448: }
449: len = min(pktlen, len);
450: data = mtod(m, u_int8_t *);
451: if (len > 1) {
452: len &= ~1;
1.48 mycroft 453: bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP,
454: (u_int16_t *)data, len>>1);
1.1 gmcgarry 455: } else
1.48 mycroft 456: *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP);
1.1 gmcgarry 457: m->m_len = len;
458: pktlen -= len;
459: *mp = m;
460: mp = &m->m_next;
461: }
462:
463: /* Skip Rx packet. */
1.48 mycroft 464: bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT);
1.50 thorpej 465:
1.56 christos 466: if (top == NULL)
467: return recvcount;
468:
1.50 thorpej 469: /* Trim the CRC off the end of the packet. */
470: m_adj(top, -ETHER_CRC_LEN);
471:
1.76 ozaki-r 472: if_percpuq_enqueue(ifp->if_percpuq, top);
1.1 gmcgarry 473: return (recvcount);
474: }
475:
476: /*
477: * Serial management for the MII.
478: * The DELAY's below stem from the fact that the maximum frequency
479: * acceptable on the MDC pin is 2.5 MHz and fast processors can easily
480: * go much faster than that.
481: */
482:
483: /* Let the MII serial management be idle for one period. */
1.51 perry 484: static INLINE void xi_mdi_idle(struct xi_softc *);
1.1 gmcgarry 485: static INLINE void
1.66 dsl 486: xi_mdi_idle(struct xi_softc *sc)
1.1 gmcgarry 487: {
488: bus_space_tag_t bst = sc->sc_bst;
489: bus_space_handle_t bsh = sc->sc_bsh;
490:
491: /* Drive MDC low... */
1.48 mycroft 492: bus_space_write_1(bst, bsh, GP2, MDC_LOW);
1.1 gmcgarry 493: DELAY(1);
494:
495: /* and high again. */
1.48 mycroft 496: bus_space_write_1(bst, bsh, GP2, MDC_HIGH);
1.1 gmcgarry 497: DELAY(1);
498: }
499:
500: /* Pulse out one bit of data. */
1.51 perry 501: static INLINE void xi_mdi_pulse(struct xi_softc *, int);
1.1 gmcgarry 502: static INLINE void
1.66 dsl 503: xi_mdi_pulse(struct xi_softc *sc, int data)
1.1 gmcgarry 504: {
505: bus_space_tag_t bst = sc->sc_bst;
506: bus_space_handle_t bsh = sc->sc_bsh;
507: u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW;
508:
509: /* First latch the data bit MDIO with clock bit MDC low...*/
1.48 mycroft 510: bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW);
1.1 gmcgarry 511: DELAY(1);
512:
513: /* then raise the clock again, preserving the data bit. */
1.48 mycroft 514: bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH);
1.1 gmcgarry 515: DELAY(1);
516: }
517:
518: /* Probe one bit of data. */
1.51 perry 519: static INLINE int xi_mdi_probe(struct xi_softc *sc);
1.1 gmcgarry 520: static INLINE int
1.66 dsl 521: xi_mdi_probe(struct xi_softc *sc)
1.1 gmcgarry 522: {
523: bus_space_tag_t bst = sc->sc_bst;
524: bus_space_handle_t bsh = sc->sc_bsh;
525: u_int8_t x;
526:
527: /* Pull clock bit MDCK low... */
1.48 mycroft 528: bus_space_write_1(bst, bsh, GP2, MDC_LOW);
1.1 gmcgarry 529: DELAY(1);
530:
531: /* Read data and drive clock high again. */
1.48 mycroft 532: x = bus_space_read_1(bst, bsh, GP2);
533: bus_space_write_1(bst, bsh, GP2, MDC_HIGH);
1.1 gmcgarry 534: DELAY(1);
535:
1.39 mycroft 536: return (x & MDIO);
1.1 gmcgarry 537: }
538:
539: /* Pulse out a sequence of data bits. */
1.51 perry 540: static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int);
1.1 gmcgarry 541: static INLINE void
1.66 dsl 542: xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len)
1.1 gmcgarry 543: {
544: u_int32_t mask;
545:
546: for (mask = 1 << (len - 1); mask; mask >>= 1)
547: xi_mdi_pulse(sc, data & mask);
548: }
549:
550: /* Read a PHY register. */
1.39 mycroft 551: STATIC int
1.67 cegger 552: xi_mdi_read(device_t self, int phy, int reg)
1.1 gmcgarry 553: {
1.68 dyoung 554: struct xi_softc *sc = device_private(self);
1.1 gmcgarry 555: int i;
556: u_int32_t mask;
557: u_int32_t data = 0;
558:
559: PAGE(sc, 2);
560: for (i = 0; i < 32; i++) /* Synchronize. */
561: xi_mdi_pulse(sc, 1);
562: xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */
563: xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */
564: xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */
565: xi_mdi_idle(sc); /* Turn around. */
566: xi_mdi_probe(sc); /* Drop initial zero bit. */
567:
568: for (mask = 1 << 15; mask; mask >>= 1) {
569: if (xi_mdi_probe(sc))
570: data |= mask;
571: }
572: xi_mdi_idle(sc);
573:
574: DPRINTF(XID_MII,
575: ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data));
576:
577: return (data);
578: }
579:
580: /* Write a PHY register. */
1.39 mycroft 581: STATIC void
1.67 cegger 582: xi_mdi_write(device_t self, int phy, int reg, int value)
1.1 gmcgarry 583: {
1.68 dyoung 584: struct xi_softc *sc = device_private(self);
1.1 gmcgarry 585: int i;
586:
587: PAGE(sc, 2);
588: for (i = 0; i < 32; i++) /* Synchronize. */
589: xi_mdi_pulse(sc, 1);
590: xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */
591: xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */
592: xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */
593: xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */
594: xi_mdi_pulse_bits(sc, value, 16); /* Write the data */
595: xi_mdi_idle(sc); /* Idle away. */
596:
597: DPRINTF(XID_MII,
598: ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value));
599: }
600:
1.39 mycroft 601: STATIC void
1.73 matt 602: xi_statchg(struct ifnet *ifp)
1.1 gmcgarry 603: {
604: /* XXX Update ifp->if_baudrate */
605: }
606:
607: /*
608: * Change media according to request.
609: */
1.39 mycroft 610: STATIC int
1.66 dsl 611: xi_mediachange(struct ifnet *ifp)
1.1 gmcgarry 612: {
1.42 mycroft 613: int s;
614:
1.2 gmcgarry 615: DPRINTF(XID_CONFIG, ("xi_mediachange()\n"));
1.1 gmcgarry 616:
1.42 mycroft 617: if (ifp->if_flags & IFF_UP) {
618: s = splnet();
1.1 gmcgarry 619: xi_init(ifp->if_softc);
1.42 mycroft 620: splx(s);
621: }
1.1 gmcgarry 622: return (0);
623: }
624:
1.39 mycroft 625: STATIC void
1.66 dsl 626: xi_reset(struct xi_softc *sc)
1.1 gmcgarry 627: {
628: int s;
629:
1.2 gmcgarry 630: DPRINTF(XID_CONFIG, ("xi_reset()\n"));
1.1 gmcgarry 631:
632: s = splnet();
633: xi_stop(sc);
634: xi_init(sc);
635: splx(s);
636: }
637:
1.39 mycroft 638: STATIC void
1.66 dsl 639: xi_watchdog(struct ifnet *ifp)
1.1 gmcgarry 640: {
641: struct xi_softc *sc = ifp->if_softc;
642:
1.69 dyoung 643: printf("%s: device timeout\n", device_xname(sc->sc_dev));
1.1 gmcgarry 644: ++ifp->if_oerrors;
645:
646: xi_reset(sc);
647: }
648:
1.39 mycroft 649: STATIC void
1.66 dsl 650: xi_stop(register struct xi_softc *sc)
1.1 gmcgarry 651: {
1.39 mycroft 652: bus_space_tag_t bst = sc->sc_bst;
653: bus_space_handle_t bsh = sc->sc_bsh;
654:
1.2 gmcgarry 655: DPRINTF(XID_CONFIG, ("xi_stop()\n"));
1.1 gmcgarry 656:
1.44 mycroft 657: PAGE(sc, 0x40);
1.48 mycroft 658: bus_space_write_1(bst, bsh, CMD0, DISABLE_RX);
1.44 mycroft 659:
1.1 gmcgarry 660: /* Disable interrupts. */
661: PAGE(sc, 0);
1.48 mycroft 662: bus_space_write_1(bst, bsh, CR, 0);
1.1 gmcgarry 663:
664: PAGE(sc, 1);
1.48 mycroft 665: bus_space_write_1(bst, bsh, IMR0, 0);
1.52 perry 666:
1.1 gmcgarry 667: /* Cancel watchdog timer. */
668: sc->sc_ethercom.ec_if.if_timer = 0;
669: }
670:
1.42 mycroft 671: STATIC int
1.66 dsl 672: xi_enable(struct xi_softc *sc)
1.42 mycroft 673: {
674: int error;
675:
676: if (!sc->sc_enabled) {
677: error = (*sc->sc_enable)(sc);
678: if (error)
679: return (error);
680: sc->sc_enabled = 1;
681: xi_full_reset(sc);
682: }
683: return (0);
684: }
685:
686: STATIC void
1.66 dsl 687: xi_disable(struct xi_softc *sc)
1.42 mycroft 688: {
689:
690: if (sc->sc_enabled) {
691: sc->sc_enabled = 0;
692: (*sc->sc_disable)(sc);
693: }
694: }
695:
1.39 mycroft 696: STATIC void
1.66 dsl 697: xi_init(struct xi_softc *sc)
1.1 gmcgarry 698: {
699: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1.39 mycroft 700: bus_space_tag_t bst = sc->sc_bst;
701: bus_space_handle_t bsh = sc->sc_bsh;
1.1 gmcgarry 702:
1.2 gmcgarry 703: DPRINTF(XID_CONFIG, ("xi_init()\n"));
1.1 gmcgarry 704:
1.39 mycroft 705: /* Setup the ethernet interrupt mask. */
706: PAGE(sc, 1);
1.48 mycroft 707: bus_space_write_1(bst, bsh, IMR0,
1.39 mycroft 708: ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */
709: ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT);
710: if (sc->sc_chipset < XI_CHIPSET_DINGO) {
711: /* XXX What is this? Not for Dingo at least. */
712: /* Unmask TX underrun detection */
1.48 mycroft 713: bus_space_write_1(bst, bsh, IMR1, 1);
1.39 mycroft 714: }
715:
716: /* Enable interrupts. */
717: PAGE(sc, 0);
1.48 mycroft 718: bus_space_write_1(bst, bsh, CR, ENABLE_INT);
1.39 mycroft 719:
1.44 mycroft 720: xi_set_address(sc);
721:
722: PAGE(sc, 0x40);
1.48 mycroft 723: bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE);
1.44 mycroft 724:
725: PAGE(sc, 0);
726:
1.1 gmcgarry 727: /* Set current media. */
728: mii_mediachg(&sc->sc_mii);
729:
730: ifp->if_flags |= IFF_RUNNING;
731: ifp->if_flags &= ~IFF_OACTIVE;
1.39 mycroft 732:
1.42 mycroft 733: xi_start(ifp);
1.1 gmcgarry 734: }
735:
736: /*
737: * Start outputting on the interface.
738: * Always called as splnet().
739: */
1.39 mycroft 740: STATIC void
1.66 dsl 741: xi_start(struct ifnet *ifp)
1.1 gmcgarry 742: {
743: struct xi_softc *sc = ifp->if_softc;
744: bus_space_tag_t bst = sc->sc_bst;
745: bus_space_handle_t bsh = sc->sc_bsh;
746: unsigned int s, len, pad = 0;
747: struct mbuf *m0, *m;
748: u_int16_t space;
749:
1.2 gmcgarry 750: DPRINTF(XID_CONFIG, ("xi_start()\n"));
1.1 gmcgarry 751:
752: /* Don't transmit if interface is busy or not running. */
753: if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) {
1.2 gmcgarry 754: DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n"));
1.1 gmcgarry 755: return;
756: }
757:
758: /* Peek at the next packet. */
1.7 thorpej 759: IFQ_POLL(&ifp->if_snd, m0);
1.1 gmcgarry 760: if (m0 == 0)
761: return;
762:
763: /* We need to use m->m_pkthdr.len, so require the header. */
764: if (!(m0->m_flags & M_PKTHDR))
765: panic("xi_start: no header mbuf");
766:
767: len = m0->m_pkthdr.len;
768:
1.39 mycroft 769: #if 1
1.1 gmcgarry 770: /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */
771: if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
772: pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
1.39 mycroft 773: #else
774: pad = 0;
775: #endif
1.1 gmcgarry 776:
777: PAGE(sc, 0);
1.39 mycroft 778:
1.48 mycroft 779: bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2);
780: space = bus_space_read_2(bst, bsh, TSO) & 0x7fff;
1.1 gmcgarry 781: if (len + pad + 2 > space) {
782: DPRINTF(XID_FIFO,
1.2 gmcgarry 783: ("xi: not enough space in output FIFO (%d > %d)\n",
784: len + pad + 2, space));
1.1 gmcgarry 785: return;
786: }
787:
1.7 thorpej 788: IFQ_DEQUEUE(&ifp->if_snd, m0);
1.1 gmcgarry 789:
1.71 joerg 790: bpf_mtap(ifp, m0);
1.1 gmcgarry 791:
792: /*
793: * Do the output at splhigh() so that an interrupt from another device
794: * won't cause a FIFO underrun.
795: */
796: s = splhigh();
797:
1.48 mycroft 798: bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad);
1.1 gmcgarry 799: for (m = m0; m; ) {
800: if (m->m_len > 1)
1.48 mycroft 801: bus_space_write_multi_2(bst, bsh, EDP,
1.21 takemura 802: mtod(m, u_int16_t *), m->m_len>>1);
1.39 mycroft 803: if (m->m_len & 1) {
804: DPRINTF(XID_CONFIG, ("xi: XXX odd!\n"));
1.48 mycroft 805: bus_space_write_1(bst, bsh, EDP,
1.1 gmcgarry 806: *(mtod(m, u_int8_t *) + m->m_len - 1));
1.39 mycroft 807: }
1.78 christos 808: m = m0 = m_free(m);
1.1 gmcgarry 809: }
1.39 mycroft 810: DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4));
811: if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
1.48 mycroft 812: bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT);
1.1 gmcgarry 813: else {
814: for (; pad > 1; pad -= 2)
1.48 mycroft 815: bus_space_write_2(bst, bsh, EDP, 0);
1.1 gmcgarry 816: if (pad == 1)
1.48 mycroft 817: bus_space_write_1(bst, bsh, EDP, 0);
1.1 gmcgarry 818: }
819:
820: splx(s);
821:
822: ifp->if_timer = 5;
823: ++ifp->if_opackets;
824: }
825:
1.39 mycroft 826: STATIC int
1.66 dsl 827: xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1.1 gmcgarry 828: {
829: struct ifaddr *ifa = (struct ifaddr *)data;
830: struct xi_softc *sc = ifp->if_softc;
1.42 mycroft 831: int error;
1.1 gmcgarry 832:
1.2 gmcgarry 833: DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n"));
1.1 gmcgarry 834:
835: switch (cmd) {
1.65 dyoung 836: case SIOCINITIFADDR:
1.42 mycroft 837: if ((error = xi_enable(sc)) != 0)
838: break;
839:
1.1 gmcgarry 840: ifp->if_flags |= IFF_UP;
841:
1.65 dyoung 842: xi_init(sc);
1.1 gmcgarry 843: switch (ifa->ifa_addr->sa_family) {
844: #ifdef INET
845: case AF_INET:
846: arp_ifinit(ifp, ifa);
847: break;
848: #endif /* INET */
849:
850:
851: default:
852: break;
853: }
854: break;
855:
856: default:
857: return (EINVAL);
858: }
859:
860: return (0);
861: }
862:
1.39 mycroft 863: STATIC int
1.65 dyoung 864: xi_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1.1 gmcgarry 865: {
1.39 mycroft 866: struct xi_softc *sc = ifp->if_softc;
1.1 gmcgarry 867: int s, error = 0;
868:
1.2 gmcgarry 869: DPRINTF(XID_CONFIG, ("xi_ioctl()\n"));
1.1 gmcgarry 870:
1.8 thorpej 871: s = splnet();
1.1 gmcgarry 872:
1.39 mycroft 873: switch (cmd) {
1.65 dyoung 874: case SIOCINITIFADDR:
1.39 mycroft 875: error = xi_ether_ioctl(ifp, cmd, data);
1.1 gmcgarry 876: break;
877:
878: case SIOCSIFFLAGS:
1.65 dyoung 879: if ((error = ifioctl_common(ifp, cmd, data)) != 0)
880: break;
881: /* XXX re-use ether_ioctl() */
882: switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
883: case IFF_RUNNING:
1.39 mycroft 884: /*
885: * If interface is marked down and it is running,
886: * stop it.
887: */
888: xi_stop(sc);
889: ifp->if_flags &= ~IFF_RUNNING;
1.42 mycroft 890: xi_disable(sc);
1.65 dyoung 891: break;
892: case IFF_UP:
1.39 mycroft 893: /*
894: * If interface is marked up and it is stopped,
895: * start it.
896: */
1.42 mycroft 897: if ((error = xi_enable(sc)) != 0)
898: break;
1.1 gmcgarry 899: xi_init(sc);
1.65 dyoung 900: break;
901: case IFF_UP|IFF_RUNNING:
1.39 mycroft 902: /*
903: * Reset the interface to pick up changes in any
904: * other flags that affect hardware registers.
905: */
1.42 mycroft 906: xi_set_address(sc);
1.65 dyoung 907: break;
908: case 0:
909: break;
1.1 gmcgarry 910: }
911: break;
912:
913: case SIOCADDMULTI:
914: case SIOCDELMULTI:
1.39 mycroft 915: if (sc->sc_enabled == 0) {
916: error = EIO;
917: break;
918: }
1.63 dyoung 919: /*FALLTHROUGH*/
920: case SIOCSIFMEDIA:
921: case SIOCGIFMEDIA:
1.62 dyoung 922: if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
1.1 gmcgarry 923: /*
924: * Multicast list has changed; set the hardware
925: * filter accordingly.
926: */
1.49 thorpej 927: if (ifp->if_flags & IFF_RUNNING)
928: xi_set_address(sc);
1.1 gmcgarry 929: error = 0;
930: }
931: break;
932:
933: default:
1.65 dyoung 934: error = ether_ioctl(ifp, cmd, data);
1.39 mycroft 935: break;
1.1 gmcgarry 936: }
1.39 mycroft 937:
1.1 gmcgarry 938: splx(s);
939: return (error);
940: }
941:
1.39 mycroft 942: STATIC void
1.66 dsl 943: xi_set_address(struct xi_softc *sc)
1.1 gmcgarry 944: {
945: bus_space_tag_t bst = sc->sc_bst;
946: bus_space_handle_t bsh = sc->sc_bsh;
947: struct ethercom *ether = &sc->sc_ethercom;
1.11 gmcgarry 948: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
949: struct ether_multistep step;
1.1 gmcgarry 950: struct ether_multi *enm;
1.39 mycroft 951: int page, num;
1.11 gmcgarry 952: int i;
1.39 mycroft 953: u_int8_t x;
1.61 dyoung 954: const u_int8_t *enaddr;
1.39 mycroft 955: u_int8_t indaddr[64];
1.1 gmcgarry 956:
1.2 gmcgarry 957: DPRINTF(XID_CONFIG, ("xi_set_address()\n"));
1.1 gmcgarry 958:
1.61 dyoung 959: enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl);
1.39 mycroft 960: if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
961: for (i = 0; i < 6; i++)
962: indaddr[i] = enaddr[5 - i];
963: else
964: for (i = 0; i < 6; i++)
965: indaddr[i] = enaddr[i];
966: num = 1;
967:
968: if (ether->ec_multicnt > 9) {
969: ifp->if_flags |= IFF_ALLMULTI;
970: goto done;
1.1 gmcgarry 971: }
1.11 gmcgarry 972:
1.39 mycroft 973: ETHER_FIRST_MULTI(step, ether, enm);
974: for (; enm; num++) {
975: if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
976: sizeof(enm->enm_addrlo)) != 0) {
977: /*
978: * The multicast address is really a range;
979: * it's easier just to accept all multicasts.
980: * XXX should we be setting IFF_ALLMULTI here?
981: */
982: ifp->if_flags |= IFF_ALLMULTI;
983: goto done;
1.1 gmcgarry 984: }
1.39 mycroft 985: if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
986: for (i = 0; i < 6; i++)
987: indaddr[num * 6 + i] = enm->enm_addrlo[5 - i];
988: else
989: for (i = 0; i < 6; i++)
990: indaddr[num * 6 + i] = enm->enm_addrlo[i];
991: ETHER_NEXT_MULTI(step, enm);
992: }
993: ifp->if_flags &= ~IFF_ALLMULTI;
1.1 gmcgarry 994:
1.39 mycroft 995: done:
996: if (num < 10)
997: memset(&indaddr[num * 6], 0xff, 6 * (10 - num));
1.11 gmcgarry 998:
1.39 mycroft 999: for (page = 0; page < 8; page++) {
1000: #ifdef XIDEBUG
1001: if (xidebug & XID_MCAST) {
1.46 mycroft 1002: printf("page %d before:", page);
1.39 mycroft 1003: for (i = 0; i < 8; i++)
1004: printf(" %02x", indaddr[page * 8 + i]);
1.11 gmcgarry 1005: printf("\n");
1.1 gmcgarry 1006: }
1.11 gmcgarry 1007: #endif
1.39 mycroft 1008:
1009: PAGE(sc, 0x50 + page);
1.48 mycroft 1010: bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8],
1011: page == 7 ? 4 : 8);
1.46 mycroft 1012: /*
1013: * XXX
1014: * Without this delay, the address registers on my CE2 get
1015: * trashed the first and I have to cycle it. I have no idea
1016: * why. - mycroft, 2004/08/09
1017: */
1018: DELAY(50);
1019:
1020: #ifdef XIDEBUG
1021: if (xidebug & XID_MCAST) {
1.48 mycroft 1022: bus_space_read_region_1(bst, bsh, IA,
1.46 mycroft 1023: &indaddr[page * 8], page == 7 ? 4 : 8);
1024: printf("page %d after: ", page);
1025: for (i = 0; i < 8; i++)
1026: printf(" %02x", indaddr[page * 8 + i]);
1027: printf("\n");
1028: }
1029: #endif
1.1 gmcgarry 1030: }
1.39 mycroft 1031:
1032: PAGE(sc, 0x42);
1033: x = SWC1_IND_ADDR;
1034: if (ifp->if_flags & IFF_PROMISC)
1035: x |= SWC1_PROMISC;
1.44 mycroft 1036: if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC))
1.39 mycroft 1037: x |= SWC1_MCAST_PROM;
1038: if (!LIST_FIRST(&sc->sc_mii.mii_phys))
1039: x |= SWC1_AUTO_MEDIA;
1.48 mycroft 1040: bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x);
1.1 gmcgarry 1041: }
1042:
1.39 mycroft 1043: STATIC void
1.66 dsl 1044: xi_cycle_power(struct xi_softc *sc)
1.1 gmcgarry 1045: {
1046: bus_space_tag_t bst = sc->sc_bst;
1047: bus_space_handle_t bsh = sc->sc_bsh;
1048:
1.2 gmcgarry 1049: DPRINTF(XID_CONFIG, ("xi_cycle_power()\n"));
1.1 gmcgarry 1050:
1051: PAGE(sc, 4);
1052: DELAY(1);
1.48 mycroft 1053: bus_space_write_1(bst, bsh, GP1, 0);
1.47 mycroft 1054: tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000);
1.39 mycroft 1055: if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
1.48 mycroft 1056: bus_space_write_1(bst, bsh, GP1, POWER_UP);
1.1 gmcgarry 1057: else
1058: /* XXX What is bit 2 (aka AIC)? */
1.48 mycroft 1059: bus_space_write_1(bst, bsh, GP1, POWER_UP | 4);
1.47 mycroft 1060: tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000);
1.1 gmcgarry 1061: }
1062:
1.39 mycroft 1063: STATIC void
1.66 dsl 1064: xi_full_reset(struct xi_softc *sc)
1.1 gmcgarry 1065: {
1066: bus_space_tag_t bst = sc->sc_bst;
1067: bus_space_handle_t bsh = sc->sc_bsh;
1.39 mycroft 1068: u_int8_t x;
1.1 gmcgarry 1069:
1.2 gmcgarry 1070: DPRINTF(XID_CONFIG, ("xi_full_reset()\n"));
1.1 gmcgarry 1071:
1072: /* Do an as extensive reset as possible on all functions. */
1073: xi_cycle_power(sc);
1.48 mycroft 1074: bus_space_write_1(bst, bsh, CR, SOFT_RESET);
1.47 mycroft 1075: tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000);
1.48 mycroft 1076: bus_space_write_1(bst, bsh, CR, 0);
1.47 mycroft 1077: tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000);
1.39 mycroft 1078: PAGE(sc, 4);
1079: if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) {
1.1 gmcgarry 1080: /*
1081: * Drive GP1 low to power up ML6692 and GP2 high to power up
1.29 tsutsui 1082: * the 10MHz chip. XXX What chip is that? The phy?
1.1 gmcgarry 1083: */
1.48 mycroft 1084: bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR);
1.1 gmcgarry 1085: }
1.47 mycroft 1086: tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000);
1.1 gmcgarry 1087:
1088: /* Get revision information. XXX Symbolic constants. */
1.48 mycroft 1089: sc->sc_rev = bus_space_read_1(bst, bsh, BV) &
1.39 mycroft 1090: ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4;
1091: DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev));
1.1 gmcgarry 1092:
1093: /* Media selection. XXX Maybe manual overriding too? */
1.39 mycroft 1094: if (sc->sc_chipset < XI_CHIPSET_MOHAWK) {
1.1 gmcgarry 1095: /*
1096: * XXX I have no idea what this really does, it is from the
1097: * Linux driver.
1098: */
1.48 mycroft 1099: bus_space_write_1(bst, bsh, GP0, GP1_OUT);
1.1 gmcgarry 1100: }
1.47 mycroft 1101: tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000);
1.1 gmcgarry 1102:
1103: /*
1104: * Disable source insertion.
1105: * XXX Dingo does not have this bit, but Linux does it unconditionally.
1106: */
1.39 mycroft 1107: if (sc->sc_chipset < XI_CHIPSET_DINGO) {
1.1 gmcgarry 1108: PAGE(sc, 0x42);
1.48 mycroft 1109: bus_space_write_1(bst, bsh, SWC0, 0x20);
1.1 gmcgarry 1110: }
1111:
1112: /* Set the local memory dividing line. */
1113: if (sc->sc_rev != 1) {
1114: PAGE(sc, 2);
1115: /* XXX Symbolic constant preferrable. */
1.48 mycroft 1116: bus_space_write_2(bst, bsh, RBS0, 0x2000);
1.1 gmcgarry 1117: }
1118:
1119: /*
1120: * Apparently the receive byte pointer can be bad after a reset, so
1121: * we hardwire it correctly.
1122: */
1123: PAGE(sc, 0);
1.48 mycroft 1124: bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET);
1.1 gmcgarry 1125:
1126: /* Setup ethernet MAC registers. XXX Symbolic constants. */
1127: PAGE(sc, 0x40);
1.48 mycroft 1128: bus_space_write_1(bst, bsh, RX0MSK,
1.1 gmcgarry 1129: PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK);
1.48 mycroft 1130: bus_space_write_1(bst, bsh, TX0MSK,
1.1 gmcgarry 1131: CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION |
1132: SQE | TX_ABORT | TX_OK);
1.39 mycroft 1133: if (sc->sc_chipset < XI_CHIPSET_DINGO)
1.1 gmcgarry 1134: /* XXX From Linux, dunno what 0xb0 means. */
1.48 mycroft 1135: bus_space_write_1(bst, bsh, TX1MSK, 0xb0);
1136: bus_space_write_1(bst, bsh, RXST0, 0);
1137: bus_space_write_1(bst, bsh, TXST0, 0);
1138: bus_space_write_1(bst, bsh, TXST1, 0);
1.1 gmcgarry 1139:
1.39 mycroft 1140: PAGE(sc, 2);
1141:
1.1 gmcgarry 1142: /* Enable MII function if available. */
1.39 mycroft 1143: x = 0;
1144: if (LIST_FIRST(&sc->sc_mii.mii_phys))
1145: x |= SELECT_MII;
1.48 mycroft 1146: bus_space_write_1(bst, bsh, MSR, x);
1.47 mycroft 1147: tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000);
1.1 gmcgarry 1148:
1149: /* Configure the LED registers. */
1150: /* XXX This is not good for 10base2. */
1.48 mycroft 1151: bus_space_write_1(bst, bsh, LED,
1.41 mycroft 1152: (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT));
1153: if (sc->sc_chipset >= XI_CHIPSET_DINGO)
1.48 mycroft 1154: bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT);
1.1 gmcgarry 1155:
1156: /*
1157: * The Linux driver says this:
1158: * We should switch back to page 0 to avoid a bug in revision 0
1159: * where regs with offset below 8 can't be read after an access
1160: * to the MAC registers.
1161: */
1162: PAGE(sc, 0);
1163: }
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