Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. =================================================================== RCS file: /ftp/cvs/cvsroot/src/sys/dev/pci/pcidevs.h,v rcsdiff: /ftp/cvs/cvsroot/src/sys/dev/pci/pcidevs.h,v: warning: Unknown phrases like `commitid ...;' are present. retrieving revision 1.1200 retrieving revision 1.1201 diff -u -p -r1.1200 -r1.1201 --- src/sys/dev/pci/pcidevs.h 2014/12/15 12:51:06 1.1200 +++ src/sys/dev/pci/pcidevs.h 2014/12/15 13:13:36 1.1201 @@ -1,10 +1,10 @@ -/* $NetBSD: pcidevs.h,v 1.1200 2014/12/15 12:51:06 msaitoh Exp $ */ +/* $NetBSD: pcidevs.h,v 1.1201 2014/12/15 13:13:36 msaitoh Exp $ */ /* * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * NetBSD: pcidevs,v 1.1206 2014/12/15 12:48:42 msaitoh Exp + * NetBSD: pcidevs,v 1.1207 2014/12/15 13:13:17 msaitoh Exp */ /* @@ -2592,6 +2592,7 @@ #define PCI_PRODUCT_INTEL_HASWELL_IGD 0x0402 /* Haswell Integrated Graphics Device */ #define PCI_PRODUCT_INTEL_HASWELL_IGD_1 0x0412 /* Haswell Integrated Graphics Device */ #define PCI_PRODUCT_INTEL_DH89XXCC_IQIA 0x0434 /* DH89xxCC PCIe Endpoint and QuickAssist */ +#define PCI_PRODUCT_INTEL_DH89XXCL_IQIA 0x0435 /* DH89xxCL PCIe Endpoint and QuickAssist */ #define PCI_PRODUCT_INTEL_DH89XXCC_SGMII 0x0438 /* DH89XXCC SGMII */ #define PCI_PRODUCT_INTEL_DH89XXCC_SERDES 0x043a /* DH89XXCC SerDes */ #define PCI_PRODUCT_INTEL_DH89XXCC_BPLANE 0x043c /* DH89XXCC backplane */ @@ -3101,19 +3102,42 @@ #define PCI_PRODUCT_INTEL_C2000_SGMII 0x1f41 /* C2000 Ethernet(SGMII) */ #define PCI_PRODUCT_INTEL_C2000_DUMMYGBE 0x1f42 /* C2000 Ethernet(Dummy function) */ #define PCI_PRODUCT_INTEL_C2000_25GBE 0x1f45 /* C2000 Ethernet(2.5Gbe) */ -#define PCI_PRODUCT_INTEL_DH89XX_LPC 0x2310 /* DH89xx LPC Controller */ -#define PCI_PRODUCT_INTEL_DH89XX_SATA_1 0x2323 /* DH89xx SATA Controller */ -#define PCI_PRODUCT_INTEL_DH89XX_SATA_2 0x2326 /* DH89xx SATA Controller */ -#define PCI_PRODUCT_INTEL_DH89XX_SMB 0x2330 /* DH89xx SMBus Host Controller */ -#define PCI_PRODUCT_INTEL_DH89XX_THERMAL 0x2332 /* DH89xx Thermal Subsystem */ -#define PCI_PRODUCT_INTEL_DH89XX_USB 0x2334 /* DH89xx USB EHCI */ -#define PCI_PRODUCT_INTEL_DH89XX_PCIE_1 0x2342 /* DH89xx PCIe Root Port */ -#define PCI_PRODUCT_INTEL_DH89XX_PCIE_2 0x2344 /* DH89xx PCIe Root Port */ -#define PCI_PRODUCT_INTEL_DH89XX_PCIE_3 0x2346 /* DH89xx PCIe Root Port */ -#define PCI_PRODUCT_INTEL_DH89XX_PCIE_4 0x2348 /* DH89xx PCIe Root Port */ -#define PCI_PRODUCT_INTEL_DH89XX_WDT 0x2360 /* DH89xx Watchdog Timer for Core Reset */ -#define PCI_PRODUCT_INTEL_DH89XX_MEI_1 0x2364 /* DH89xx MEI Controller */ -#define PCI_PRODUCT_INTEL_DH89XX_MEI_2 0x2365 /* DH89xx MEI Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCC_LPC 0x2310 /* DH89xxCC LPC Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCC_SATA_1 0x2323 /* DH89xxCC SATA Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCC_SATA_2 0x2326 /* DH89xxCC SATA Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCC_SMB 0x2330 /* DH89xxCC SMBus Host Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCC_THERMAL 0x2332 /* DH89xxCC Thermal Subsystem */ +#define PCI_PRODUCT_INTEL_DH89XXCC_USB_1 0x2334 /* DH89xxCC USB EHCI */ +#define PCI_PRODUCT_INTEL_DH89XXCC_USB_2 0x2335 /* DH89xxCC USB EHCI */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_1_1 0x2342 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_1_2 0x2343 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_2_1 0x2344 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_2_2 0x2345 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_3_1 0x2346 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_3_2 0x2347 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_4_1 0x2348 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_PCIE_4_2 0x2349 /* DH89xxCC PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCC_WDT 0x2360 /* DH89xxCC Watchdog Timer for Core Reset */ +#define PCI_PRODUCT_INTEL_DH89XXCC_MEI_1 0x2364 /* DH89xxCC MEI Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCC_MEI_2 0x2365 /* DH89xxCC MEI Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCL_LPC 0x2390 /* DH89xxCL LPC Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCL_SATA_1 0x23a3 /* DH89xxCL SATA Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCL_SATA_2 0x23a6 /* DH89xxCL SATA Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCL_SMB 0x23b0 /* DH89xxCL SMBus Host Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCL_THERMAL 0x23b2 /* DH89xxCL Thermal Subsystem */ +#define PCI_PRODUCT_INTEL_DH89XXCL_USB_1 0x23b4 /* DH89xxCL USB EHCI */ +#define PCI_PRODUCT_INTEL_DH89XXCL_USB_2 0x23b4 /* DH89xxCL USB EHCI */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_1_1 0x23c2 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_1_2 0x23c3 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_2_1 0x23c4 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_2_2 0x23c5 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_3_1 0x23c6 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_3_2 0x23c7 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_4_1 0x23c8 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_PCIE_4_2 0x23c9 /* DH89xxCL PCIe Root Port */ +#define PCI_PRODUCT_INTEL_DH89XXCL_WDT 0x23e0 /* DH89xxCL Watchdog Timer for Core Reset */ +#define PCI_PRODUCT_INTEL_DH89XXCL_MEI_1 0x23e4 /* DH89xxCL MEI Controller */ +#define PCI_PRODUCT_INTEL_DH89XXCL_MEI_2 0x23e5 /* DH89xxCL MEI Controller */ #define PCI_PRODUCT_INTEL_82801AA_LPC 0x2410 /* 82801AA LPC Interface Bridge */ #define PCI_PRODUCT_INTEL_82801AA_IDE 0x2411 /* 82801AA IDE Controller */ #define PCI_PRODUCT_INTEL_82801AA_USB 0x2412 /* 82801AA USB Controller */