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Annotation of src/sys/dev/pci/pci_subr.c, Revision 1.74.4.2

1.74.4.2! yamt        1: /*     $NetBSD: pci_subr.c,v 1.74.4.1 2008/05/16 02:24:44 yamt Exp $   */
1.3       cgd         2:
1.1       mycroft     3: /*
1.22      thorpej     4:  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
1.40      cgd         5:  * Copyright (c) 1995, 1996, 1998, 2000
1.26      cgd         6:  *     Christopher G. Demetriou.  All rights reserved.
1.30      mycroft     7:  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
1.1       mycroft     8:  *
                      9:  * Redistribution and use in source and binary forms, with or without
                     10:  * modification, are permitted provided that the following conditions
                     11:  * are met:
                     12:  * 1. Redistributions of source code must retain the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer.
                     14:  * 2. Redistributions in binary form must reproduce the above copyright
                     15:  *    notice, this list of conditions and the following disclaimer in the
                     16:  *    documentation and/or other materials provided with the distribution.
                     17:  * 3. All advertising materials mentioning features or use of this software
                     18:  *    must display the following acknowledgement:
1.30      mycroft    19:  *     This product includes software developed by Charles M. Hannum.
1.1       mycroft    20:  * 4. The name of the author may not be used to endorse or promote products
                     21:  *    derived from this software without specific prior written permission.
                     22:  *
                     23:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
                     24:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
                     25:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
                     26:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
                     27:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
                     28:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
                     29:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
                     30:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
                     31:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
                     32:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                     33:  */
                     34:
                     35: /*
1.10      cgd        36:  * PCI autoconfiguration support functions.
1.45      thorpej    37:  *
                     38:  * Note: This file is also built into a userland library (libpci).
                     39:  * Pay attention to this when you make modifications.
1.1       mycroft    40:  */
1.47      lukem      41:
                     42: #include <sys/cdefs.h>
1.74.4.2! yamt       43: __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.74.4.1 2008/05/16 02:24:44 yamt Exp $");
1.21      enami      44:
1.45      thorpej    45: #ifdef _KERNEL_OPT
1.35      cgd        46: #include "opt_pci.h"
1.45      thorpej    47: #endif
1.1       mycroft    48:
                     49: #include <sys/param.h>
                     50:
1.45      thorpej    51: #ifdef _KERNEL
1.62      simonb     52: #include <sys/systm.h>
1.73      ad         53: #include <sys/intr.h>
1.45      thorpej    54: #else
                     55: #include <pci.h>
1.72      joerg      56: #include <stdbool.h>
1.46      enami      57: #include <stdio.h>
1.45      thorpej    58: #endif
1.24      thorpej    59:
1.10      cgd        60: #include <dev/pci/pcireg.h>
1.45      thorpej    61: #ifdef _KERNEL
1.7       cgd        62: #include <dev/pci/pcivar.h>
1.45      thorpej    63: #endif
1.10      cgd        64: #ifdef PCIVERBOSE
                     65: #include <dev/pci/pcidevs.h>
                     66: #endif
                     67:
                     68: /*
                     69:  * Descriptions of known PCI classes and subclasses.
                     70:  *
                     71:  * Subclasses are described in the same way as classes, but have a
                     72:  * NULL subclass pointer.
                     73:  */
                     74: struct pci_class {
1.44      thorpej    75:        const char      *name;
1.10      cgd        76:        int             val;            /* as wide as pci_{,sub}class_t */
1.42      jdolecek   77:        const struct pci_class *subclasses;
1.10      cgd        78: };
                     79:
1.61      thorpej    80: static const struct pci_class pci_subclass_prehistoric[] = {
1.65      christos   81:        { "miscellaneous",      PCI_SUBCLASS_PREHISTORIC_MISC,  NULL,   },
                     82:        { "VGA",                PCI_SUBCLASS_PREHISTORIC_VGA,   NULL,   },
                     83:        { NULL,                 0,                              NULL,   },
1.10      cgd        84: };
                     85:
1.61      thorpej    86: static const struct pci_class pci_subclass_mass_storage[] = {
1.65      christos   87:        { "SCSI",               PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL,   },
                     88:        { "IDE",                PCI_SUBCLASS_MASS_STORAGE_IDE,  NULL,   },
                     89:        { "floppy",             PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, },
                     90:        { "IPI",                PCI_SUBCLASS_MASS_STORAGE_IPI,  NULL,   },
                     91:        { "RAID",               PCI_SUBCLASS_MASS_STORAGE_RAID, NULL,   },
                     92:        { "ATA",                PCI_SUBCLASS_MASS_STORAGE_ATA,  NULL,   },
                     93:        { "SATA",               PCI_SUBCLASS_MASS_STORAGE_SATA, NULL,   },
                     94:        { "SAS",                PCI_SUBCLASS_MASS_STORAGE_SAS,  NULL,   },
                     95:        { "miscellaneous",      PCI_SUBCLASS_MASS_STORAGE_MISC, NULL,   },
                     96:        { NULL,                 0,                              NULL,   },
1.10      cgd        97: };
                     98:
1.61      thorpej    99: static const struct pci_class pci_subclass_network[] = {
1.65      christos  100:        { "ethernet",           PCI_SUBCLASS_NETWORK_ETHERNET,  NULL,   },
                    101:        { "token ring",         PCI_SUBCLASS_NETWORK_TOKENRING, NULL,   },
                    102:        { "FDDI",               PCI_SUBCLASS_NETWORK_FDDI,      NULL,   },
                    103:        { "ATM",                PCI_SUBCLASS_NETWORK_ATM,       NULL,   },
                    104:        { "ISDN",               PCI_SUBCLASS_NETWORK_ISDN,      NULL,   },
                    105:        { "WorldFip",           PCI_SUBCLASS_NETWORK_WORLDFIP,  NULL,   },
                    106:        { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
                    107:        { "miscellaneous",      PCI_SUBCLASS_NETWORK_MISC,      NULL,   },
                    108:        { NULL,                 0,                              NULL,   },
1.10      cgd       109: };
                    110:
1.61      thorpej   111: static const struct pci_class pci_subclass_display[] = {
1.65      christos  112:        { "VGA",                PCI_SUBCLASS_DISPLAY_VGA,       NULL,   },
                    113:        { "XGA",                PCI_SUBCLASS_DISPLAY_XGA,       NULL,   },
                    114:        { "3D",                 PCI_SUBCLASS_DISPLAY_3D,        NULL,   },
                    115:        { "miscellaneous",      PCI_SUBCLASS_DISPLAY_MISC,      NULL,   },
                    116:        { NULL,                 0,                              NULL,   },
1.10      cgd       117: };
                    118:
1.61      thorpej   119: static const struct pci_class pci_subclass_multimedia[] = {
1.65      christos  120:        { "video",              PCI_SUBCLASS_MULTIMEDIA_VIDEO,  NULL,   },
                    121:        { "audio",              PCI_SUBCLASS_MULTIMEDIA_AUDIO,  NULL,   },
                    122:        { "telephony",          PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
                    123:        { "miscellaneous",      PCI_SUBCLASS_MULTIMEDIA_MISC,   NULL,   },
                    124:        { NULL,                 0,                              NULL,   },
1.10      cgd       125: };
                    126:
1.61      thorpej   127: static const struct pci_class pci_subclass_memory[] = {
1.65      christos  128:        { "RAM",                PCI_SUBCLASS_MEMORY_RAM,        NULL,   },
                    129:        { "flash",              PCI_SUBCLASS_MEMORY_FLASH,      NULL,   },
                    130:        { "miscellaneous",      PCI_SUBCLASS_MEMORY_MISC,       NULL,   },
                    131:        { NULL,                 0,                              NULL,   },
1.10      cgd       132: };
                    133:
1.61      thorpej   134: static const struct pci_class pci_subclass_bridge[] = {
1.65      christos  135:        { "host",               PCI_SUBCLASS_BRIDGE_HOST,       NULL,   },
                    136:        { "ISA",                PCI_SUBCLASS_BRIDGE_ISA,        NULL,   },
                    137:        { "EISA",               PCI_SUBCLASS_BRIDGE_EISA,       NULL,   },
                    138:        { "MicroChannel",       PCI_SUBCLASS_BRIDGE_MC,         NULL,   },
                    139:        { "PCI",                PCI_SUBCLASS_BRIDGE_PCI,        NULL,   },
                    140:        { "PCMCIA",             PCI_SUBCLASS_BRIDGE_PCMCIA,     NULL,   },
                    141:        { "NuBus",              PCI_SUBCLASS_BRIDGE_NUBUS,      NULL,   },
                    142:        { "CardBus",            PCI_SUBCLASS_BRIDGE_CARDBUS,    NULL,   },
                    143:        { "RACEway",            PCI_SUBCLASS_BRIDGE_RACEWAY,    NULL,   },
                    144:        { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,    NULL,   },
                    145:        { "InfiniBand",         PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL,   },
                    146:        { "miscellaneous",      PCI_SUBCLASS_BRIDGE_MISC,       NULL,   },
                    147:        { NULL,                 0,                              NULL,   },
1.10      cgd       148: };
                    149:
1.61      thorpej   150: static const struct pci_class pci_subclass_communications[] = {
1.65      christos  151:        { "serial",             PCI_SUBCLASS_COMMUNICATIONS_SERIAL,     NULL, },
                    152:        { "parallel",           PCI_SUBCLASS_COMMUNICATIONS_PARALLEL,   NULL, },
                    153:        { "multi-port serial",  PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL,   NULL, },
                    154:        { "modem",              PCI_SUBCLASS_COMMUNICATIONS_MODEM,      NULL, },
                    155:        { "GPIB",               PCI_SUBCLASS_COMMUNICATIONS_GPIB,       NULL, },
                    156:        { "smartcard",          PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD,  NULL, },
                    157:        { "miscellaneous",      PCI_SUBCLASS_COMMUNICATIONS_MISC,       NULL, },
                    158:        { NULL,                 0,                                      NULL, },
1.20      cgd       159: };
                    160:
1.61      thorpej   161: static const struct pci_class pci_subclass_system[] = {
1.65      christos  162:        { "interrupt",          PCI_SUBCLASS_SYSTEM_PIC,        NULL,   },
                    163:        { "8237 DMA",           PCI_SUBCLASS_SYSTEM_DMA,        NULL,   },
                    164:        { "8254 timer",         PCI_SUBCLASS_SYSTEM_TIMER,      NULL,   },
                    165:        { "RTC",                PCI_SUBCLASS_SYSTEM_RTC,        NULL,   },
                    166:        { "PCI Hot-Plug",       PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL,   },
                    167:        { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC,       NULL,   },
                    168:        { "miscellaneous",      PCI_SUBCLASS_SYSTEM_MISC,       NULL,   },
                    169:        { NULL,                 0,                              NULL,   },
1.20      cgd       170: };
                    171:
1.61      thorpej   172: static const struct pci_class pci_subclass_input[] = {
1.65      christos  173:        { "keyboard",           PCI_SUBCLASS_INPUT_KEYBOARD,    NULL,   },
                    174:        { "digitizer",          PCI_SUBCLASS_INPUT_DIGITIZER,   NULL,   },
                    175:        { "mouse",              PCI_SUBCLASS_INPUT_MOUSE,       NULL,   },
                    176:        { "scanner",            PCI_SUBCLASS_INPUT_SCANNER,     NULL,   },
                    177:        { "game port",          PCI_SUBCLASS_INPUT_GAMEPORT,    NULL,   },
                    178:        { "miscellaneous",      PCI_SUBCLASS_INPUT_MISC,        NULL,   },
                    179:        { NULL,                 0,                              NULL,   },
1.20      cgd       180: };
                    181:
1.61      thorpej   182: static const struct pci_class pci_subclass_dock[] = {
1.65      christos  183:        { "generic",            PCI_SUBCLASS_DOCK_GENERIC,      NULL,   },
                    184:        { "miscellaneous",      PCI_SUBCLASS_DOCK_MISC,         NULL,   },
                    185:        { NULL,                 0,                              NULL,   },
1.20      cgd       186: };
                    187:
1.61      thorpej   188: static const struct pci_class pci_subclass_processor[] = {
1.65      christos  189:        { "386",                PCI_SUBCLASS_PROCESSOR_386,     NULL,   },
                    190:        { "486",                PCI_SUBCLASS_PROCESSOR_486,     NULL,   },
                    191:        { "Pentium",            PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL,   },
                    192:        { "Alpha",              PCI_SUBCLASS_PROCESSOR_ALPHA,   NULL,   },
                    193:        { "PowerPC",            PCI_SUBCLASS_PROCESSOR_POWERPC, NULL,   },
                    194:        { "MIPS",               PCI_SUBCLASS_PROCESSOR_MIPS,    NULL,   },
                    195:        { "Co-processor",       PCI_SUBCLASS_PROCESSOR_COPROC,  NULL,   },
                    196:        { NULL,                 0,                              NULL,   },
1.20      cgd       197: };
                    198:
1.61      thorpej   199: static const struct pci_class pci_subclass_serialbus[] = {
1.65      christos  200:        { "Firewire",           PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL,  },
                    201:        { "ACCESS.bus",         PCI_SUBCLASS_SERIALBUS_ACCESS,  NULL,   },
                    202:        { "SSA",                PCI_SUBCLASS_SERIALBUS_SSA,     NULL,   },
                    203:        { "USB",                PCI_SUBCLASS_SERIALBUS_USB,     NULL,   },
1.32      cgd       204:        /* XXX Fiber Channel/_FIBRECHANNEL */
1.65      christos  205:        { "Fiber Channel",      PCI_SUBCLASS_SERIALBUS_FIBER,   NULL,   },
                    206:        { "SMBus",              PCI_SUBCLASS_SERIALBUS_SMBUS,   NULL,   },
                    207:        { "InfiniBand",         PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,},
                    208:        { "IPMI",               PCI_SUBCLASS_SERIALBUS_IPMI,    NULL,   },
                    209:        { "SERCOS",             PCI_SUBCLASS_SERIALBUS_SERCOS,  NULL,   },
                    210:        { "CANbus",             PCI_SUBCLASS_SERIALBUS_CANBUS,  NULL,   },
                    211:        { NULL,                 0,                              NULL,   },
1.32      cgd       212: };
                    213:
1.61      thorpej   214: static const struct pci_class pci_subclass_wireless[] = {
1.65      christos  215:        { "IrDA",               PCI_SUBCLASS_WIRELESS_IRDA,     NULL,   },
                    216:        { "Consumer IR",        PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
                    217:        { "RF",                 PCI_SUBCLASS_WIRELESS_RF,       NULL,   },
                    218:        { "bluetooth",          PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL,  },
                    219:        { "broadband",          PCI_SUBCLASS_WIRELESS_BROADBAND, NULL,  },
                    220:        { "802.11a (5 GHz)",    PCI_SUBCLASS_WIRELESS_802_11A,  NULL,   },
                    221:        { "802.11b (2.4 GHz)",  PCI_SUBCLASS_WIRELESS_802_11B,  NULL,   },
                    222:        { "miscellaneous",      PCI_SUBCLASS_WIRELESS_MISC,     NULL,   },
                    223:        { NULL,                 0,                              NULL,   },
1.32      cgd       224: };
                    225:
1.61      thorpej   226: static const struct pci_class pci_subclass_i2o[] = {
1.65      christos  227:        { "standard",           PCI_SUBCLASS_I2O_STANDARD,      NULL,   },
                    228:        { NULL,                 0,                              NULL,   },
1.32      cgd       229: };
                    230:
1.61      thorpej   231: static const struct pci_class pci_subclass_satcom[] = {
1.65      christos  232:        { "TV",                 PCI_SUBCLASS_SATCOM_TV,         NULL,   },
                    233:        { "audio",              PCI_SUBCLASS_SATCOM_AUDIO,      NULL,   },
                    234:        { "voice",              PCI_SUBCLASS_SATCOM_VOICE,      NULL,   },
                    235:        { "data",               PCI_SUBCLASS_SATCOM_DATA,       NULL,   },
                    236:        { NULL,                 0,                              NULL,   },
1.32      cgd       237: };
                    238:
1.61      thorpej   239: static const struct pci_class pci_subclass_crypto[] = {
1.65      christos  240:        { "network/computing",  PCI_SUBCLASS_CRYPTO_NETCOMP,    NULL,   },
                    241:        { "entertainment",      PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
                    242:        { "miscellaneous",      PCI_SUBCLASS_CRYPTO_MISC,       NULL,   },
                    243:        { NULL,                 0,                              NULL,   },
1.32      cgd       244: };
                    245:
1.61      thorpej   246: static const struct pci_class pci_subclass_dasp[] = {
1.65      christos  247:        { "DPIO",               PCI_SUBCLASS_DASP_DPIO,         NULL,   },
                    248:        { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ,     NULL,   },
                    249:        { "synchronization",    PCI_SUBCLASS_DASP_SYNC,         NULL,   },
                    250:        { "management",         PCI_SUBCLASS_DASP_MGMT,         NULL,   },
                    251:        { "miscellaneous",      PCI_SUBCLASS_DASP_MISC,         NULL,   },
                    252:        { NULL,                 0,                              NULL,   },
1.20      cgd       253: };
                    254:
1.61      thorpej   255: static const struct pci_class pci_class[] = {
1.10      cgd       256:        { "prehistoric",        PCI_CLASS_PREHISTORIC,
                    257:            pci_subclass_prehistoric,                           },
                    258:        { "mass storage",       PCI_CLASS_MASS_STORAGE,
                    259:            pci_subclass_mass_storage,                          },
                    260:        { "network",            PCI_CLASS_NETWORK,
                    261:            pci_subclass_network,                               },
                    262:        { "display",            PCI_CLASS_DISPLAY,
1.11      cgd       263:            pci_subclass_display,                               },
1.10      cgd       264:        { "multimedia",         PCI_CLASS_MULTIMEDIA,
                    265:            pci_subclass_multimedia,                            },
                    266:        { "memory",             PCI_CLASS_MEMORY,
                    267:            pci_subclass_memory,                                },
                    268:        { "bridge",             PCI_CLASS_BRIDGE,
                    269:            pci_subclass_bridge,                                },
1.20      cgd       270:        { "communications",     PCI_CLASS_COMMUNICATIONS,
                    271:            pci_subclass_communications,                        },
                    272:        { "system",             PCI_CLASS_SYSTEM,
                    273:            pci_subclass_system,                                },
                    274:        { "input",              PCI_CLASS_INPUT,
                    275:            pci_subclass_input,                                 },
                    276:        { "dock",               PCI_CLASS_DOCK,
                    277:            pci_subclass_dock,                                  },
                    278:        { "processor",          PCI_CLASS_PROCESSOR,
                    279:            pci_subclass_processor,                             },
                    280:        { "serial bus",         PCI_CLASS_SERIALBUS,
                    281:            pci_subclass_serialbus,                             },
1.32      cgd       282:        { "wireless",           PCI_CLASS_WIRELESS,
                    283:            pci_subclass_wireless,                              },
                    284:        { "I2O",                PCI_CLASS_I2O,
                    285:            pci_subclass_i2o,                                   },
                    286:        { "satellite comm",     PCI_CLASS_SATCOM,
                    287:            pci_subclass_satcom,                                },
                    288:        { "crypto",             PCI_CLASS_CRYPTO,
                    289:            pci_subclass_crypto,                                },
                    290:        { "DASP",               PCI_CLASS_DASP,
                    291:            pci_subclass_dasp,                                  },
1.10      cgd       292:        { "undefined",          PCI_CLASS_UNDEFINED,
1.65      christos  293:            NULL,                                               },
                    294:        { NULL,                 0,
                    295:            NULL,                                               },
1.10      cgd       296: };
                    297:
                    298: #ifdef PCIVERBOSE
                    299: /*
                    300:  * Descriptions of of known vendors and devices ("products").
                    301:  */
                    302:
                    303: #include <dev/pci/pcidevs_data.h>
                    304: #endif /* PCIVERBOSE */
1.29      augustss  305:
1.74.4.2! yamt      306: #ifdef PCIVERBOSE
        !           307: #ifndef _KERNEL
        !           308: #include <string.h>
        !           309: #endif
        !           310: static const char *
        !           311: pci_untokenstring(const uint16_t *token, char *buf, size_t len)
        !           312: {
        !           313:        char *cp = buf;
        !           314:
        !           315:        buf[0] = '\0';
        !           316:        for (; *token != 0; token++) {
        !           317:                cp = buf + strlcat(buf, pci_words + *token, len - 2);
        !           318:                cp[0] = ' ';
        !           319:                cp[1] = '\0';
        !           320:        }
        !           321:        *cp = '\0';
        !           322:        return cp != buf ? buf : NULL;
        !           323: }
        !           324: #endif /* PCIVERBOSE */
        !           325:
1.59      mycroft   326: const char *
1.71      christos  327: pci_findvendor(pcireg_t id_reg)
1.29      augustss  328: {
                    329: #ifdef PCIVERBOSE
1.74.4.2! yamt      330:        static char buf[256];
1.29      augustss  331:        pci_vendor_id_t vendor = PCI_VENDOR(id_reg);
1.74.4.2! yamt      332:        size_t n;
1.29      augustss  333:
1.74.4.2! yamt      334:        for (n = 0; n < __arraycount(pci_vendors); n++) {
        !           335:                if (pci_vendors[n] == vendor)
        !           336:                        return pci_untokenstring(&pci_vendors[n+1], buf,
        !           337:                            sizeof(buf));
        !           338:
        !           339:                /* Skip Tokens */
        !           340:                n++;
        !           341:                while (pci_vendors[n] != 0 && n < __arraycount(pci_vendors))
        !           342:                        n++;
        !           343:        }
1.59      mycroft   344: #endif
1.29      augustss  345:        return (NULL);
1.59      mycroft   346: }
                    347:
                    348: const char *
1.71      christos  349: pci_findproduct(pcireg_t id_reg)
1.59      mycroft   350: {
                    351: #ifdef PCIVERBOSE
1.74.4.2! yamt      352:        static char buf[256];
1.59      mycroft   353:        pci_vendor_id_t vendor = PCI_VENDOR(id_reg);
                    354:        pci_product_id_t product = PCI_PRODUCT(id_reg);
1.74.4.2! yamt      355:        size_t n;
1.59      mycroft   356:
1.74.4.2! yamt      357:        for (n = 0; n < __arraycount(pci_products); n++) {
        !           358:                if (pci_products[n] == vendor && pci_products[n+1] == product)
        !           359:                        return pci_untokenstring(&pci_products[n+2], buf,
        !           360:                            sizeof(buf));
        !           361:
        !           362:                /* Skip Tokens */
        !           363:                n += 2;
        !           364:                while (pci_products[n] != 0 && n < __arraycount(pci_products))
        !           365:                        n++;
        !           366:        }
1.29      augustss  367: #endif
1.59      mycroft   368:        return (NULL);
1.29      augustss  369: }
1.10      cgd       370:
                    371: void
1.58      itojun    372: pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp,
                    373:     size_t l)
1.10      cgd       374: {
                    375:        pci_vendor_id_t vendor;
                    376:        pci_product_id_t product;
                    377:        pci_class_t class;
                    378:        pci_subclass_t subclass;
                    379:        pci_interface_t interface;
                    380:        pci_revision_t revision;
1.59      mycroft   381:        const char *vendor_namep, *product_namep;
1.42      jdolecek  382:        const struct pci_class *classp, *subclassp;
1.10      cgd       383: #ifdef PCIVERBOSE
1.16      cgd       384:        const char *unmatched = "unknown ";
1.15      cgd       385: #else
1.16      cgd       386:        const char *unmatched = "";
1.10      cgd       387: #endif
1.58      itojun    388:        char *ep;
                    389:
                    390:        ep = cp + l;
1.10      cgd       391:
                    392:        vendor = PCI_VENDOR(id_reg);
                    393:        product = PCI_PRODUCT(id_reg);
                    394:
                    395:        class = PCI_CLASS(class_reg);
                    396:        subclass = PCI_SUBCLASS(class_reg);
                    397:        interface = PCI_INTERFACE(class_reg);
                    398:        revision = PCI_REVISION(class_reg);
                    399:
1.59      mycroft   400:        vendor_namep = pci_findvendor(id_reg);
                    401:        product_namep = pci_findproduct(id_reg);
1.10      cgd       402:
                    403:        classp = pci_class;
                    404:        while (classp->name != NULL) {
                    405:                if (class == classp->val)
                    406:                        break;
                    407:                classp++;
                    408:        }
                    409:
                    410:        subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
                    411:        while (subclassp && subclassp->name != NULL) {
                    412:                if (subclass == subclassp->val)
                    413:                        break;
                    414:                subclassp++;
                    415:        }
                    416:
                    417:        if (vendor_namep == NULL)
1.58      itojun    418:                cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x",
1.15      cgd       419:                    unmatched, vendor, product);
1.10      cgd       420:        else if (product_namep != NULL)
1.58      itojun    421:                cp += snprintf(cp, ep - cp, "%s %s", vendor_namep,
                    422:                    product_namep);
1.10      cgd       423:        else
1.58      itojun    424:                cp += snprintf(cp, ep - cp, "%s product 0x%04x",
1.10      cgd       425:                    vendor_namep, product);
1.13      cgd       426:        if (showclass) {
1.58      itojun    427:                cp += snprintf(cp, ep - cp, " (");
1.13      cgd       428:                if (classp->name == NULL)
1.58      itojun    429:                        cp += snprintf(cp, ep - cp,
                    430:                            "class 0x%02x, subclass 0x%02x", class, subclass);
1.13      cgd       431:                else {
                    432:                        if (subclassp == NULL || subclassp->name == NULL)
1.58      itojun    433:                                cp += snprintf(cp, ep - cp,
1.20      cgd       434:                                    "%s subclass 0x%02x",
                    435:                                    classp->name, subclass);
1.13      cgd       436:                        else
1.58      itojun    437:                                cp += snprintf(cp, ep - cp, "%s %s",
1.20      cgd       438:                                    subclassp->name, classp->name);
1.13      cgd       439:                }
1.20      cgd       440:                if (interface != 0)
1.58      itojun    441:                        cp += snprintf(cp, ep - cp, ", interface 0x%02x",
                    442:                            interface);
1.20      cgd       443:                if (revision != 0)
1.58      itojun    444:                        cp += snprintf(cp, ep - cp, ", revision 0x%02x",
                    445:                            revision);
                    446:                cp += snprintf(cp, ep - cp, ")");
1.13      cgd       447:        }
1.22      thorpej   448: }
                    449:
                    450: /*
                    451:  * Print out most of the PCI configuration registers.  Typically used
                    452:  * in a device attach routine like this:
                    453:  *
                    454:  *     #ifdef MYDEV_DEBUG
1.74      cegger    455:  *             printf("%s: ", device_xname(&sc->sc_dev));
1.43      enami     456:  *             pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
1.22      thorpej   457:  *     #endif
                    458:  */
1.26      cgd       459:
                    460: #define        i2o(i)  ((i) * 4)
                    461: #define        o2i(o)  ((o) / 4)
1.27      cgd       462: #define        onoff(str, bit)                                                 \
                    463:        printf("      %s: %s\n", (str), (rval & (bit)) ? "on" : "off");
1.26      cgd       464:
                    465: static void
1.45      thorpej   466: pci_conf_print_common(
                    467: #ifdef _KERNEL
1.71      christos  468:     pci_chipset_tag_t pc, pcitag_t tag,
1.45      thorpej   469: #endif
                    470:     const pcireg_t *regs)
1.22      thorpej   471: {
1.59      mycroft   472:        const char *name;
1.42      jdolecek  473:        const struct pci_class *classp, *subclassp;
1.26      cgd       474:        pcireg_t rval;
1.22      thorpej   475:
1.26      cgd       476:        rval = regs[o2i(PCI_ID_REG)];
1.59      mycroft   477:        name = pci_findvendor(rval);
                    478:        if (name)
                    479:                printf("    Vendor Name: %s (0x%04x)\n", name,
1.26      cgd       480:                    PCI_VENDOR(rval));
1.22      thorpej   481:        else
1.26      cgd       482:                printf("    Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
1.59      mycroft   483:        name = pci_findproduct(rval);
                    484:        if (name)
                    485:                printf("    Device Name: %s (0x%04x)\n", name,
1.26      cgd       486:                    PCI_PRODUCT(rval));
1.22      thorpej   487:        else
1.26      cgd       488:                printf("    Device ID: 0x%04x\n", PCI_PRODUCT(rval));
1.22      thorpej   489:
1.26      cgd       490:        rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
1.23      drochner  491:
1.26      cgd       492:        printf("    Command register: 0x%04x\n", rval & 0xffff);
                    493:        onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE);
                    494:        onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE);
                    495:        onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE);
                    496:        onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE);
                    497:        onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE);
                    498:        onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE);
                    499:        onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE);
                    500:        onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE);
                    501:        onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE);
                    502:        onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE);
1.70      drochner  503:        onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE);
1.26      cgd       504:
                    505:        printf("    Status register: 0x%04x\n", (rval >> 16) & 0xffff);
1.33      kleink    506:        onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT);
1.26      cgd       507:        onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT);
                    508:        onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT);
                    509:        onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT);
                    510:        onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR);
1.22      thorpej   511:
1.26      cgd       512:        printf("      DEVSEL timing: ");
1.22      thorpej   513:        switch (rval & PCI_STATUS_DEVSEL_MASK) {
                    514:        case PCI_STATUS_DEVSEL_FAST:
                    515:                printf("fast");
                    516:                break;
                    517:        case PCI_STATUS_DEVSEL_MEDIUM:
                    518:                printf("medium");
                    519:                break;
                    520:        case PCI_STATUS_DEVSEL_SLOW:
                    521:                printf("slow");
                    522:                break;
1.26      cgd       523:        default:
                    524:                printf("unknown/reserved");     /* XXX */
                    525:                break;
1.22      thorpej   526:        }
1.26      cgd       527:        printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25);
1.22      thorpej   528:
1.26      cgd       529:        onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT);
                    530:        onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT);
                    531:        onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT);
                    532:        onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR);
                    533:        onoff("Parity error detected", PCI_STATUS_PARITY_DETECT);
1.22      thorpej   534:
1.26      cgd       535:        rval = regs[o2i(PCI_CLASS_REG)];
1.22      thorpej   536:        for (classp = pci_class; classp->name != NULL; classp++) {
                    537:                if (PCI_CLASS(rval) == classp->val)
                    538:                        break;
                    539:        }
                    540:        subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
                    541:        while (subclassp && subclassp->name != NULL) {
                    542:                if (PCI_SUBCLASS(rval) == subclassp->val)
                    543:                        break;
                    544:                subclassp++;
                    545:        }
                    546:        if (classp->name != NULL) {
1.26      cgd       547:                printf("    Class Name: %s (0x%02x)\n", classp->name,
                    548:                    PCI_CLASS(rval));
1.22      thorpej   549:                if (subclassp != NULL && subclassp->name != NULL)
1.26      cgd       550:                        printf("    Subclass Name: %s (0x%02x)\n",
                    551:                            subclassp->name, PCI_SUBCLASS(rval));
1.22      thorpej   552:                else
1.26      cgd       553:                        printf("    Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
1.22      thorpej   554:        } else {
1.26      cgd       555:                printf("    Class ID: 0x%02x\n", PCI_CLASS(rval));
                    556:                printf("    Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
1.22      thorpej   557:        }
1.26      cgd       558:        printf("    Interface: 0x%02x\n", PCI_INTERFACE(rval));
                    559:        printf("    Revision ID: 0x%02x\n", PCI_REVISION(rval));
1.22      thorpej   560:
1.26      cgd       561:        rval = regs[o2i(PCI_BHLC_REG)];
                    562:        printf("    BIST: 0x%02x\n", PCI_BIST(rval));
                    563:        printf("    Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
                    564:            PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
                    565:            PCI_HDRTYPE(rval));
                    566:        printf("    Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
                    567:        printf("    Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval));
                    568: }
1.22      thorpej   569:
1.37      nathanw   570: static int
1.45      thorpej   571: pci_conf_print_bar(
                    572: #ifdef _KERNEL
                    573:     pci_chipset_tag_t pc, pcitag_t tag,
                    574: #endif
                    575:     const pcireg_t *regs, int reg, const char *name
                    576: #ifdef _KERNEL
                    577:     , int sizebar
                    578: #endif
                    579:     )
1.26      cgd       580: {
1.45      thorpej   581:        int width;
                    582:        pcireg_t rval, rval64h;
                    583: #ifdef _KERNEL
                    584:        int s;
                    585:        pcireg_t mask, mask64h;
                    586: #endif
                    587:
1.37      nathanw   588:        width = 4;
1.22      thorpej   589:
1.27      cgd       590:        /*
                    591:         * Section 6.2.5.1, `Address Maps', tells us that:
                    592:         *
                    593:         * 1) The builtin software should have already mapped the
                    594:         * device in a reasonable way.
                    595:         *
                    596:         * 2) A device which wants 2^n bytes of memory will hardwire
                    597:         * the bottom n bits of the address to 0.  As recommended,
                    598:         * we write all 1s and see what we get back.
                    599:         */
1.45      thorpej   600:
1.27      cgd       601:        rval = regs[o2i(reg)];
1.45      thorpej   602:        if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
                    603:            PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
                    604:                rval64h = regs[o2i(reg + 4)];
                    605:                width = 8;
                    606:        } else
                    607:                rval64h = 0;
                    608:
                    609: #ifdef _KERNEL
1.38      cgd       610:        /* XXX don't size unknown memory type? */
                    611:        if (rval != 0 && sizebar) {
1.24      thorpej   612:                /*
1.27      cgd       613:                 * The following sequence seems to make some devices
                    614:                 * (e.g. host bus bridges, which don't normally
                    615:                 * have their space mapped) very unhappy, to
                    616:                 * the point of crashing the system.
1.24      thorpej   617:                 *
1.27      cgd       618:                 * Therefore, if the mapping register is zero to
                    619:                 * start out with, don't bother trying.
1.24      thorpej   620:                 */
1.27      cgd       621:                s = splhigh();
                    622:                pci_conf_write(pc, tag, reg, 0xffffffff);
                    623:                mask = pci_conf_read(pc, tag, reg);
                    624:                pci_conf_write(pc, tag, reg, rval);
1.37      nathanw   625:                if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
                    626:                    PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
                    627:                        pci_conf_write(pc, tag, reg + 4, 0xffffffff);
                    628:                        mask64h = pci_conf_read(pc, tag, reg + 4);
                    629:                        pci_conf_write(pc, tag, reg + 4, rval64h);
1.54      scw       630:                } else
                    631:                        mask64h = 0;
1.27      cgd       632:                splx(s);
                    633:        } else
1.54      scw       634:                mask = mask64h = 0;
1.45      thorpej   635: #endif /* _KERNEL */
1.27      cgd       636:
1.28      cgd       637:        printf("    Base address register at 0x%02x", reg);
                    638:        if (name)
                    639:                printf(" (%s)", name);
                    640:        printf("\n      ");
1.27      cgd       641:        if (rval == 0) {
                    642:                printf("not implemented(?)\n");
1.37      nathanw   643:                return width;
1.60      perry     644:        }
1.28      cgd       645:        printf("type: ");
                    646:        if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
1.34      drochner  647:                const char *type, *prefetch;
1.27      cgd       648:
                    649:                switch (PCI_MAPREG_MEM_TYPE(rval)) {
                    650:                case PCI_MAPREG_MEM_TYPE_32BIT:
                    651:                        type = "32-bit";
                    652:                        break;
                    653:                case PCI_MAPREG_MEM_TYPE_32BIT_1M:
                    654:                        type = "32-bit-1M";
                    655:                        break;
                    656:                case PCI_MAPREG_MEM_TYPE_64BIT:
                    657:                        type = "64-bit";
                    658:                        break;
                    659:                default:
                    660:                        type = "unknown (XXX)";
                    661:                        break;
1.22      thorpej   662:                }
1.34      drochner  663:                if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
                    664:                        prefetch = "";
1.27      cgd       665:                else
1.34      drochner  666:                        prefetch = "non";
                    667:                printf("%s %sprefetchable memory\n", type, prefetch);
1.37      nathanw   668:                switch (PCI_MAPREG_MEM_TYPE(rval)) {
                    669:                case PCI_MAPREG_MEM_TYPE_64BIT:
1.38      cgd       670:                        printf("      base: 0x%016llx, ",
1.37      nathanw   671:                            PCI_MAPREG_MEM64_ADDR(
1.38      cgd       672:                                ((((long long) rval64h) << 32) | rval)));
1.45      thorpej   673: #ifdef _KERNEL
1.38      cgd       674:                        if (sizebar)
                    675:                                printf("size: 0x%016llx",
                    676:                                    PCI_MAPREG_MEM64_SIZE(
                    677:                                      ((((long long) mask64h) << 32) | mask)));
                    678:                        else
1.45      thorpej   679: #endif /* _KERNEL */
1.38      cgd       680:                                printf("not sized");
                    681:                        printf("\n");
1.37      nathanw   682:                        break;
                    683:                case PCI_MAPREG_MEM_TYPE_32BIT:
                    684:                case PCI_MAPREG_MEM_TYPE_32BIT_1M:
                    685:                default:
1.38      cgd       686:                        printf("      base: 0x%08x, ",
                    687:                            PCI_MAPREG_MEM_ADDR(rval));
1.45      thorpej   688: #ifdef _KERNEL
1.38      cgd       689:                        if (sizebar)
                    690:                                printf("size: 0x%08x",
                    691:                                    PCI_MAPREG_MEM_SIZE(mask));
                    692:                        else
1.45      thorpej   693: #endif /* _KERNEL */
1.38      cgd       694:                                printf("not sized");
                    695:                        printf("\n");
1.37      nathanw   696:                        break;
                    697:                }
1.27      cgd       698:        } else {
1.45      thorpej   699: #ifdef _KERNEL
1.38      cgd       700:                if (sizebar)
                    701:                        printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
1.45      thorpej   702: #endif /* _KERNEL */
1.27      cgd       703:                printf("i/o\n");
1.38      cgd       704:                printf("      base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval));
1.45      thorpej   705: #ifdef _KERNEL
1.38      cgd       706:                if (sizebar)
                    707:                        printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask));
                    708:                else
1.45      thorpej   709: #endif /* _KERNEL */
1.38      cgd       710:                        printf("not sized");
                    711:                printf("\n");
1.22      thorpej   712:        }
1.37      nathanw   713:
                    714:        return width;
1.27      cgd       715: }
1.28      cgd       716:
                    717: static void
1.44      thorpej   718: pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
1.28      cgd       719: {
                    720:        int off, needaddr, neednl;
                    721:
                    722:        needaddr = 1;
                    723:        neednl = 0;
                    724:        for (off = first; off < pastlast; off += 4) {
                    725:                if ((off % 16) == 0 || needaddr) {
                    726:                        printf("    0x%02x:", off);
                    727:                        needaddr = 0;
                    728:                }
                    729:                printf(" 0x%08x", regs[o2i(off)]);
                    730:                neednl = 1;
                    731:                if ((off % 16) == 12) {
                    732:                        printf("\n");
                    733:                        neednl = 0;
                    734:                }
                    735:        }
                    736:        if (neednl)
                    737:                printf("\n");
                    738: }
                    739:
1.27      cgd       740: static void
1.45      thorpej   741: pci_conf_print_type0(
                    742: #ifdef _KERNEL
                    743:     pci_chipset_tag_t pc, pcitag_t tag,
                    744: #endif
                    745:     const pcireg_t *regs
                    746: #ifdef _KERNEL
                    747:     , int sizebars
                    748: #endif
                    749:     )
1.27      cgd       750: {
1.37      nathanw   751:        int off, width;
1.27      cgd       752:        pcireg_t rval;
                    753:
1.45      thorpej   754:        for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
                    755: #ifdef _KERNEL
1.38      cgd       756:                width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
1.45      thorpej   757: #else
                    758:                width = pci_conf_print_bar(regs, off, NULL);
                    759: #endif
                    760:        }
1.22      thorpej   761:
1.26      cgd       762:        printf("    Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
1.22      thorpej   763:
1.31      drochner  764:        rval = regs[o2i(PCI_SUBSYS_ID_REG)];
1.26      cgd       765:        printf("    Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
                    766:        printf("    Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
                    767:
                    768:        /* XXX */
                    769:        printf("    Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]);
1.33      kleink    770:
                    771:        if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
                    772:                printf("    Capability list pointer: 0x%02x\n",
                    773:                    PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
                    774:        else
                    775:                printf("    Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
                    776:
1.26      cgd       777:        printf("    Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
                    778:
                    779:        rval = regs[o2i(PCI_INTERRUPT_REG)];
                    780:        printf("    Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
                    781:        printf("    Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
1.27      cgd       782:        printf("    Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
1.22      thorpej   783:        switch (PCI_INTERRUPT_PIN(rval)) {
                    784:        case PCI_INTERRUPT_PIN_NONE:
1.27      cgd       785:                printf("(none)");
1.22      thorpej   786:                break;
                    787:        case PCI_INTERRUPT_PIN_A:
1.27      cgd       788:                printf("(pin A)");
1.22      thorpej   789:                break;
                    790:        case PCI_INTERRUPT_PIN_B:
1.27      cgd       791:                printf("(pin B)");
1.22      thorpej   792:                break;
                    793:        case PCI_INTERRUPT_PIN_C:
1.27      cgd       794:                printf("(pin C)");
1.22      thorpej   795:                break;
                    796:        case PCI_INTERRUPT_PIN_D:
1.27      cgd       797:                printf("(pin D)");
                    798:                break;
                    799:        default:
1.36      mrg       800:                printf("(? ? ?)");
1.22      thorpej   801:                break;
                    802:        }
                    803:        printf("\n");
1.26      cgd       804:        printf("    Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
1.51      drochner  805: }
                    806:
                    807: static void
1.72      joerg     808: pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
                    809: {
                    810:        bool check_slot = false;
                    811:
                    812:        printf("\n  PCI Express Capabilities Register\n");
                    813:        printf("    Capability version: %x\n",
                    814:            (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16));
                    815:        printf("    Device type: ");
                    816:        switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) {
                    817:        case 0x0:
                    818:                printf("PCI Express Endpoint device\n");
                    819:                break;
                    820:        case 0x1:
1.74.4.1  yamt      821:                printf("Legacy PCI Express Endpoint device\n");
1.72      joerg     822:                break;
                    823:        case 0x4:
                    824:                printf("Root Port of PCI Express Root Complex\n");
                    825:                check_slot = true;
                    826:                break;
                    827:        case 0x5:
                    828:                printf("Upstream Port of PCI Express Switch\n");
                    829:                break;
                    830:        case 0x6:
                    831:                printf("Downstream Port of PCI Express Switch\n");
                    832:                check_slot = true;
                    833:                break;
                    834:        case 0x7:
                    835:                printf("PCI Express to PCI/PCI-X Bridge\n");
                    836:                break;
                    837:        case 0x8:
                    838:                printf("PCI/PCI-X to PCI Express Bridge\n");
                    839:                break;
                    840:        default:
                    841:                printf("unknown\n");
                    842:                break;
                    843:        }
                    844:        if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0)
                    845:                printf("    Slot implemented\n");
                    846:        printf("    Interrupt Message Number: %x\n",
                    847:            (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27));
                    848:        if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) {
                    849:                printf("    Slot Control Register:\n");
                    850:                if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0)
                    851:                        printf("      Attention Button Pressed Enabled\n");
                    852:                if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0)
                    853:                        printf("      Power Fault Detected Enabled\n");
                    854:                if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0)
                    855:                        printf("      MRL Sensor Changed Enabled\n");
                    856:                if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0)
                    857:                        printf("      Presense Detected Changed Enabled\n");
                    858:                if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0)
                    859:                        printf("      Command Completed Interrupt Enabled\n");
                    860:                if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0)
                    861:                        printf("      Hot-Plug Interrupt Enabled\n");
                    862:                printf("      Attention Indictor Control: ");
                    863:                switch ((regs[o2i(capoff + 0x18)] & 0x00a0) >> 6) {
                    864:                case 0x0:
                    865:                        printf("reserved\n");
                    866:                        break;
                    867:                case 0x1:
                    868:                        printf("on\n");
                    869:                        break;
                    870:                case 0x2:
                    871:                        printf("blink\n");
                    872:                        break;
                    873:                case 0x3:
                    874:                        printf("off\n");
                    875:                        break;
                    876:                }
                    877:                printf("      Power Indictor Control: ");
                    878:                switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) {
                    879:                case 0x0:
                    880:                        printf("reserved\n");
                    881:                        break;
                    882:                case 0x1:
                    883:                        printf("on\n");
                    884:                        break;
                    885:                case 0x2:
                    886:                        printf("blink\n");
                    887:                        break;
                    888:                case 0x3:
                    889:                        printf("off\n");
                    890:                        break;
                    891:                }
                    892:                printf("      Power Controller Control: ");
                    893:                if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0)
                    894:                        printf("off\n");
                    895:                else
                    896:                        printf("on\n");
                    897:        }
                    898: }
                    899:
1.74.4.2! yamt      900: static const char *
        !           901: pci_conf_print_pcipm_cap_aux(uint16_t caps)
        !           902: {
        !           903:        switch ((caps >> 6) & 7) {
        !           904:        case 0: return "self-powered";
        !           905:        case 1: return "55 mA";
        !           906:        case 2: return "100 mA";
        !           907:        case 3: return "160 mA";
        !           908:        case 4: return "220 mA";
        !           909:        case 5: return "270 mA";
        !           910:        case 6: return "320 mA";
        !           911:        case 7:
        !           912:        default: return "375 mA";
        !           913:        }
        !           914: }
        !           915:
        !           916: static const char *
        !           917: pci_conf_print_pcipm_cap_pmrev(uint8_t val)
        !           918: {
        !           919:        static const char unk[] = "unknown";
        !           920:        static const char *pmrev[8] = {
        !           921:                unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
        !           922:        };
        !           923:        if (val > 7)
        !           924:                return unk;
        !           925:        return pmrev[val];
        !           926: }
        !           927:
        !           928: static void
        !           929: pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
        !           930: {
        !           931:        uint16_t caps, pmcsr;
        !           932:
        !           933:        caps = regs[o2i(capoff)] >> 16;
        !           934:        pmcsr = regs[o2i(capoff + 0x04)] & 0xffff;
        !           935:
        !           936:        printf("\n  PCI Power Management Capabilities Register\n");
        !           937:
        !           938:        printf("    Capabilities register: 0x%04x\n", caps);
        !           939:        printf("      Version: %s\n",
        !           940:            pci_conf_print_pcipm_cap_pmrev(caps & 0x3));
        !           941:        printf("      PME# clock: %s\n", caps & 0x4 ? "on" : "off");
        !           942:        printf("      Device specific initialization: %s\n",
        !           943:            caps & 0x20 ? "on" : "off");
        !           944:        printf("      3.3V auxiliary current: %s\n",
        !           945:            pci_conf_print_pcipm_cap_aux(caps));
        !           946:        printf("      D1 power management state support: %s\n",
        !           947:            (caps >> 9) & 1 ? "on" : "off");
        !           948:        printf("      D2 power management state support: %s\n",
        !           949:            (caps >> 10) & 1 ? "on" : "off");
        !           950:        printf("      PME# support: 0x%02x\n", caps >> 11);
        !           951:
        !           952:        printf("    Control/status register: 0x%04x\n", pmcsr);
        !           953:        printf("      Power state: D%d\n", pmcsr & 3);
        !           954:        printf("      PCI Express reserved: %s\n",
        !           955:            (pmcsr >> 2) & 1 ? "on" : "off");
        !           956:        printf("      No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off");
        !           957:        printf("      PME# assertion %sabled\n",
        !           958:            (pmcsr >> 8) & 1 ? "en" : "dis");
        !           959:        printf("      PME# status: %s\n", (pmcsr >> 15) ? "on" : "off");
        !           960: }
        !           961:
1.72      joerg     962: static void
1.51      drochner  963: pci_conf_print_caplist(
                    964: #ifdef _KERNEL
1.71      christos  965:     pci_chipset_tag_t pc, pcitag_t tag,
1.51      drochner  966: #endif
1.52      drochner  967:     const pcireg_t *regs, int capoff)
1.51      drochner  968: {
                    969:        int off;
                    970:        pcireg_t rval;
1.74.4.2! yamt      971:        int pcie_off = -1, pcipm_off = -1;
1.33      kleink    972:
1.52      drochner  973:        for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
1.51      drochner  974:             off != 0;
                    975:             off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
                    976:                rval = regs[o2i(off)];
                    977:                printf("  Capability register at 0x%02x\n", off);
                    978:
                    979:                printf("    type: 0x%02x (", PCI_CAPLIST_CAP(rval));
                    980:                switch (PCI_CAPLIST_CAP(rval)) {
                    981:                case PCI_CAP_RESERVED0:
                    982:                        printf("reserved");
                    983:                        break;
                    984:                case PCI_CAP_PWRMGMT:
1.64      drochner  985:                        printf("Power Management, rev. %s",
1.74.4.2! yamt      986:                            pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07));
        !           987:                        pcipm_off = off;
1.51      drochner  988:                        break;
                    989:                case PCI_CAP_AGP:
                    990:                        printf("AGP, rev. %d.%d",
1.57      soren     991:                                PCI_CAP_AGP_MAJOR(rval),
                    992:                                PCI_CAP_AGP_MINOR(rval));
1.51      drochner  993:                        break;
                    994:                case PCI_CAP_VPD:
                    995:                        printf("VPD");
                    996:                        break;
                    997:                case PCI_CAP_SLOTID:
                    998:                        printf("SlotID");
                    999:                        break;
                   1000:                case PCI_CAP_MSI:
                   1001:                        printf("MSI");
                   1002:                        break;
                   1003:                case PCI_CAP_CPCI_HOTSWAP:
                   1004:                        printf("CompactPCI Hot-swapping");
                   1005:                        break;
                   1006:                case PCI_CAP_PCIX:
                   1007:                        printf("PCI-X");
                   1008:                        break;
                   1009:                case PCI_CAP_LDT:
                   1010:                        printf("LDT");
                   1011:                        break;
                   1012:                case PCI_CAP_VENDSPEC:
                   1013:                        printf("Vendor-specific");
                   1014:                        break;
                   1015:                case PCI_CAP_DEBUGPORT:
                   1016:                        printf("Debug Port");
                   1017:                        break;
                   1018:                case PCI_CAP_CPCI_RSRCCTL:
                   1019:                        printf("CompactPCI Resource Control");
                   1020:                        break;
                   1021:                case PCI_CAP_HOTPLUG:
                   1022:                        printf("Hot-Plug");
                   1023:                        break;
                   1024:                case PCI_CAP_AGP8:
                   1025:                        printf("AGP 8x");
                   1026:                        break;
                   1027:                case PCI_CAP_SECURE:
                   1028:                        printf("Secure Device");
                   1029:                        break;
                   1030:                case PCI_CAP_PCIEXPRESS:
                   1031:                        printf("PCI Express");
1.72      joerg    1032:                        pcie_off = off;
1.51      drochner 1033:                        break;
                   1034:                case PCI_CAP_MSIX:
                   1035:                        printf("MSI-X");
                   1036:                        break;
                   1037:                default:
                   1038:                        printf("unknown");
1.33      kleink   1039:                }
1.51      drochner 1040:                printf(")\n");
1.33      kleink   1041:        }
1.74.4.2! yamt     1042:        if (pcipm_off != -1)
        !          1043:                pci_conf_print_pcipm_cap(regs, pcipm_off);
1.72      joerg    1044:        if (pcie_off != -1)
                   1045:                pci_conf_print_pcie_cap(regs, pcie_off);
1.26      cgd      1046: }
                   1047:
1.27      cgd      1048: static void
1.45      thorpej  1049: pci_conf_print_type1(
                   1050: #ifdef _KERNEL
                   1051:     pci_chipset_tag_t pc, pcitag_t tag,
                   1052: #endif
                   1053:     const pcireg_t *regs
                   1054: #ifdef _KERNEL
                   1055:     , int sizebars
                   1056: #endif
                   1057:     )
1.27      cgd      1058: {
1.37      nathanw  1059:        int off, width;
1.27      cgd      1060:        pcireg_t rval;
                   1061:
                   1062:        /*
                   1063:         * XXX these need to be printed in more detail, need to be
                   1064:         * XXX checked against specs/docs, etc.
                   1065:         *
                   1066:         * This layout was cribbed from the TI PCI2030 PCI-to-PCI
                   1067:         * Bridge chip documentation, and may not be correct with
                   1068:         * respect to various standards. (XXX)
                   1069:         */
                   1070:
1.45      thorpej  1071:        for (off = 0x10; off < 0x18; off += width) {
                   1072: #ifdef _KERNEL
1.38      cgd      1073:                width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
1.45      thorpej  1074: #else
                   1075:                width = pci_conf_print_bar(regs, off, NULL);
                   1076: #endif
                   1077:        }
1.27      cgd      1078:
                   1079:        printf("    Primary bus number: 0x%02x\n",
                   1080:            (regs[o2i(0x18)] >> 0) & 0xff);
                   1081:        printf("    Secondary bus number: 0x%02x\n",
                   1082:            (regs[o2i(0x18)] >> 8) & 0xff);
                   1083:        printf("    Subordinate bus number: 0x%02x\n",
                   1084:            (regs[o2i(0x18)] >> 16) & 0xff);
                   1085:        printf("    Secondary bus latency timer: 0x%02x\n",
                   1086:            (regs[o2i(0x18)] >> 24) & 0xff);
                   1087:
                   1088:        rval = (regs[o2i(0x1c)] >> 16) & 0xffff;
                   1089:        printf("    Secondary status register: 0x%04x\n", rval); /* XXX bits */
                   1090:        onoff("66 MHz capable", 0x0020);
                   1091:        onoff("User Definable Features (UDF) support", 0x0040);
                   1092:        onoff("Fast back-to-back capable", 0x0080);
                   1093:        onoff("Data parity error detected", 0x0100);
                   1094:
                   1095:        printf("      DEVSEL timing: ");
                   1096:        switch (rval & 0x0600) {
                   1097:        case 0x0000:
                   1098:                printf("fast");
                   1099:                break;
                   1100:        case 0x0200:
                   1101:                printf("medium");
                   1102:                break;
                   1103:        case 0x0400:
                   1104:                printf("slow");
                   1105:                break;
                   1106:        default:
                   1107:                printf("unknown/reserved");     /* XXX */
                   1108:                break;
                   1109:        }
                   1110:        printf(" (0x%x)\n", (rval & 0x0600) >> 9);
                   1111:
                   1112:        onoff("Signaled Target Abort", 0x0800);
                   1113:        onoff("Received Target Abort", 0x1000);
                   1114:        onoff("Received Master Abort", 0x2000);
                   1115:        onoff("System Error", 0x4000);
                   1116:        onoff("Parity Error", 0x8000);
                   1117:
                   1118:        /* XXX Print more prettily */
                   1119:        printf("    I/O region:\n");
                   1120:        printf("      base register:  0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff);
                   1121:        printf("      limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff);
                   1122:        printf("      base upper 16 bits register:  0x%04x\n",
                   1123:            (regs[o2i(0x30)] >> 0) & 0xffff);
                   1124:        printf("      limit upper 16 bits register: 0x%04x\n",
                   1125:            (regs[o2i(0x30)] >> 16) & 0xffff);
                   1126:
                   1127:        /* XXX Print more prettily */
                   1128:        printf("    Memory region:\n");
                   1129:        printf("      base register:  0x%04x\n",
                   1130:            (regs[o2i(0x20)] >> 0) & 0xffff);
                   1131:        printf("      limit register: 0x%04x\n",
                   1132:            (regs[o2i(0x20)] >> 16) & 0xffff);
                   1133:
                   1134:        /* XXX Print more prettily */
                   1135:        printf("    Prefetchable memory region:\n");
                   1136:        printf("      base register:  0x%04x\n",
                   1137:            (regs[o2i(0x24)] >> 0) & 0xffff);
                   1138:        printf("      limit register: 0x%04x\n",
                   1139:            (regs[o2i(0x24)] >> 16) & 0xffff);
                   1140:        printf("      base upper 32 bits register:  0x%08x\n", regs[o2i(0x28)]);
                   1141:        printf("      limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]);
                   1142:
1.53      drochner 1143:        if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
                   1144:                printf("    Capability list pointer: 0x%02x\n",
                   1145:                    PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
                   1146:        else
                   1147:                printf("    Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
                   1148:
1.27      cgd      1149:        /* XXX */
                   1150:        printf("    Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
                   1151:
                   1152:        printf("    Interrupt line: 0x%02x\n",
                   1153:            (regs[o2i(0x3c)] >> 0) & 0xff);
                   1154:        printf("    Interrupt pin: 0x%02x ",
                   1155:            (regs[o2i(0x3c)] >> 8) & 0xff);
                   1156:        switch ((regs[o2i(0x3c)] >> 8) & 0xff) {
                   1157:        case PCI_INTERRUPT_PIN_NONE:
                   1158:                printf("(none)");
                   1159:                break;
                   1160:        case PCI_INTERRUPT_PIN_A:
                   1161:                printf("(pin A)");
                   1162:                break;
                   1163:        case PCI_INTERRUPT_PIN_B:
                   1164:                printf("(pin B)");
                   1165:                break;
                   1166:        case PCI_INTERRUPT_PIN_C:
                   1167:                printf("(pin C)");
                   1168:                break;
                   1169:        case PCI_INTERRUPT_PIN_D:
                   1170:                printf("(pin D)");
                   1171:                break;
                   1172:        default:
1.36      mrg      1173:                printf("(? ? ?)");
1.27      cgd      1174:                break;
                   1175:        }
                   1176:        printf("\n");
                   1177:        rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
                   1178:        printf("    Bridge control register: 0x%04x\n", rval); /* XXX bits */
                   1179:        onoff("Parity error response", 0x0001);
                   1180:        onoff("Secondary SERR forwarding", 0x0002);
                   1181:        onoff("ISA enable", 0x0004);
                   1182:        onoff("VGA enable", 0x0008);
                   1183:        onoff("Master abort reporting", 0x0020);
                   1184:        onoff("Secondary bus reset", 0x0040);
                   1185:        onoff("Fast back-to-back capable", 0x0080);
                   1186: }
                   1187:
                   1188: static void
1.45      thorpej  1189: pci_conf_print_type2(
                   1190: #ifdef _KERNEL
                   1191:     pci_chipset_tag_t pc, pcitag_t tag,
                   1192: #endif
                   1193:     const pcireg_t *regs
                   1194: #ifdef _KERNEL
                   1195:     , int sizebars
                   1196: #endif
                   1197:     )
1.27      cgd      1198: {
                   1199:        pcireg_t rval;
                   1200:
                   1201:        /*
                   1202:         * XXX these need to be printed in more detail, need to be
                   1203:         * XXX checked against specs/docs, etc.
                   1204:         *
                   1205:         * This layout was cribbed from the TI PCI1130 PCI-to-CardBus
                   1206:         * controller chip documentation, and may not be correct with
                   1207:         * respect to various standards. (XXX)
                   1208:         */
                   1209:
1.45      thorpej  1210: #ifdef _KERNEL
1.28      cgd      1211:        pci_conf_print_bar(pc, tag, regs, 0x10,
1.38      cgd      1212:            "CardBus socket/ExCA registers", sizebars);
1.45      thorpej  1213: #else
                   1214:        pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers");
                   1215: #endif
1.27      cgd      1216:
1.53      drochner 1217:        if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
                   1218:                printf("    Capability list pointer: 0x%02x\n",
                   1219:                    PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]));
                   1220:        else
                   1221:                printf("    Reserved @ 0x14: 0x%04x\n",
                   1222:                       (regs[o2i(0x14)] >> 0) & 0xffff);
1.27      cgd      1223:        rval = (regs[o2i(0x14)] >> 16) & 0xffff;
                   1224:        printf("    Secondary status register: 0x%04x\n", rval);
                   1225:        onoff("66 MHz capable", 0x0020);
                   1226:        onoff("User Definable Features (UDF) support", 0x0040);
                   1227:        onoff("Fast back-to-back capable", 0x0080);
                   1228:        onoff("Data parity error detection", 0x0100);
                   1229:
                   1230:        printf("      DEVSEL timing: ");
                   1231:        switch (rval & 0x0600) {
                   1232:        case 0x0000:
                   1233:                printf("fast");
                   1234:                break;
                   1235:        case 0x0200:
                   1236:                printf("medium");
                   1237:                break;
                   1238:        case 0x0400:
                   1239:                printf("slow");
                   1240:                break;
                   1241:        default:
                   1242:                printf("unknown/reserved");     /* XXX */
                   1243:                break;
                   1244:        }
                   1245:        printf(" (0x%x)\n", (rval & 0x0600) >> 9);
                   1246:        onoff("PCI target aborts terminate CardBus bus master transactions",
                   1247:            0x0800);
                   1248:        onoff("CardBus target aborts terminate PCI bus master transactions",
                   1249:            0x1000);
                   1250:        onoff("Bus initiator aborts terminate initiator transactions",
                   1251:            0x2000);
                   1252:        onoff("System error", 0x4000);
                   1253:        onoff("Parity error", 0x8000);
                   1254:
                   1255:        printf("    PCI bus number: 0x%02x\n",
                   1256:            (regs[o2i(0x18)] >> 0) & 0xff);
                   1257:        printf("    CardBus bus number: 0x%02x\n",
                   1258:            (regs[o2i(0x18)] >> 8) & 0xff);
                   1259:        printf("    Subordinate bus number: 0x%02x\n",
                   1260:            (regs[o2i(0x18)] >> 16) & 0xff);
                   1261:        printf("    CardBus latency timer: 0x%02x\n",
                   1262:            (regs[o2i(0x18)] >> 24) & 0xff);
                   1263:
                   1264:        /* XXX Print more prettily */
                   1265:        printf("    CardBus memory region 0:\n");
                   1266:        printf("      base register:  0x%08x\n", regs[o2i(0x1c)]);
                   1267:        printf("      limit register: 0x%08x\n", regs[o2i(0x20)]);
                   1268:        printf("    CardBus memory region 1:\n");
                   1269:        printf("      base register:  0x%08x\n", regs[o2i(0x24)]);
                   1270:        printf("      limit register: 0x%08x\n", regs[o2i(0x28)]);
                   1271:        printf("    CardBus I/O region 0:\n");
                   1272:        printf("      base register:  0x%08x\n", regs[o2i(0x2c)]);
                   1273:        printf("      limit register: 0x%08x\n", regs[o2i(0x30)]);
                   1274:        printf("    CardBus I/O region 1:\n");
                   1275:        printf("      base register:  0x%08x\n", regs[o2i(0x34)]);
                   1276:        printf("      limit register: 0x%08x\n", regs[o2i(0x38)]);
                   1277:
                   1278:        printf("    Interrupt line: 0x%02x\n",
                   1279:            (regs[o2i(0x3c)] >> 0) & 0xff);
                   1280:        printf("    Interrupt pin: 0x%02x ",
                   1281:            (regs[o2i(0x3c)] >> 8) & 0xff);
                   1282:        switch ((regs[o2i(0x3c)] >> 8) & 0xff) {
                   1283:        case PCI_INTERRUPT_PIN_NONE:
                   1284:                printf("(none)");
                   1285:                break;
                   1286:        case PCI_INTERRUPT_PIN_A:
                   1287:                printf("(pin A)");
                   1288:                break;
                   1289:        case PCI_INTERRUPT_PIN_B:
                   1290:                printf("(pin B)");
                   1291:                break;
                   1292:        case PCI_INTERRUPT_PIN_C:
                   1293:                printf("(pin C)");
                   1294:                break;
                   1295:        case PCI_INTERRUPT_PIN_D:
                   1296:                printf("(pin D)");
                   1297:                break;
                   1298:        default:
1.36      mrg      1299:                printf("(? ? ?)");
1.27      cgd      1300:                break;
                   1301:        }
                   1302:        printf("\n");
                   1303:        rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
                   1304:        printf("    Bridge control register: 0x%04x\n", rval);
                   1305:        onoff("Parity error response", 0x0001);
                   1306:        onoff("CardBus SERR forwarding", 0x0002);
                   1307:        onoff("ISA enable", 0x0004);
                   1308:        onoff("VGA enable", 0x0008);
                   1309:        onoff("CardBus master abort reporting", 0x0020);
                   1310:        onoff("CardBus reset", 0x0040);
                   1311:        onoff("Functional interrupts routed by ExCA registers", 0x0080);
                   1312:        onoff("Memory window 0 prefetchable", 0x0100);
                   1313:        onoff("Memory window 1 prefetchable", 0x0200);
                   1314:        onoff("Write posting enable", 0x0400);
1.28      cgd      1315:
                   1316:        rval = regs[o2i(0x40)];
                   1317:        printf("    Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
                   1318:        printf("    Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
                   1319:
1.45      thorpej  1320: #ifdef _KERNEL
1.38      cgd      1321:        pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers",
                   1322:            sizebars);
1.45      thorpej  1323: #else
                   1324:        pci_conf_print_bar(regs, 0x44, "legacy-mode registers");
                   1325: #endif
1.27      cgd      1326: }
                   1327:
1.26      cgd      1328: void
1.45      thorpej  1329: pci_conf_print(
                   1330: #ifdef _KERNEL
                   1331:     pci_chipset_tag_t pc, pcitag_t tag,
                   1332:     void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)
                   1333: #else
                   1334:     int pcifd, u_int bus, u_int dev, u_int func
                   1335: #endif
                   1336:     )
1.26      cgd      1337: {
                   1338:        pcireg_t regs[o2i(256)];
1.52      drochner 1339:        int off, capoff, endoff, hdrtype;
1.27      cgd      1340:        const char *typename;
1.45      thorpej  1341: #ifdef _KERNEL
1.38      cgd      1342:        void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int);
                   1343:        int sizebars;
1.45      thorpej  1344: #else
                   1345:        void (*typeprintfn)(const pcireg_t *);
                   1346: #endif
1.26      cgd      1347:
                   1348:        printf("PCI configuration registers:\n");
                   1349:
1.45      thorpej  1350:        for (off = 0; off < 256; off += 4) {
                   1351: #ifdef _KERNEL
1.26      cgd      1352:                regs[o2i(off)] = pci_conf_read(pc, tag, off);
1.45      thorpej  1353: #else
                   1354:                if (pcibus_conf_read(pcifd, bus, dev, func, off,
                   1355:                    &regs[o2i(off)]) == -1)
                   1356:                        regs[o2i(off)] = 0;
                   1357: #endif
                   1358:        }
1.26      cgd      1359:
1.45      thorpej  1360: #ifdef _KERNEL
1.38      cgd      1361:        sizebars = 1;
                   1362:        if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE &&
                   1363:            PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST)
                   1364:                sizebars = 0;
1.45      thorpej  1365: #endif
1.38      cgd      1366:
1.26      cgd      1367:        /* common header */
                   1368:        printf("  Common header:\n");
1.28      cgd      1369:        pci_conf_print_regs(regs, 0, 16);
                   1370:
1.26      cgd      1371:        printf("\n");
1.45      thorpej  1372: #ifdef _KERNEL
1.26      cgd      1373:        pci_conf_print_common(pc, tag, regs);
1.45      thorpej  1374: #else
                   1375:        pci_conf_print_common(regs);
                   1376: #endif
1.26      cgd      1377:        printf("\n");
                   1378:
                   1379:        /* type-dependent header */
                   1380:        hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
                   1381:        switch (hdrtype) {              /* XXX make a table, eventually */
                   1382:        case 0:
1.27      cgd      1383:                /* Standard device header */
                   1384:                typename = "\"normal\" device";
                   1385:                typeprintfn = &pci_conf_print_type0;
1.52      drochner 1386:                capoff = PCI_CAPLISTPTR_REG;
1.28      cgd      1387:                endoff = 64;
1.27      cgd      1388:                break;
                   1389:        case 1:
                   1390:                /* PCI-PCI bridge header */
                   1391:                typename = "PCI-PCI bridge";
1.26      cgd      1392:                typeprintfn = &pci_conf_print_type1;
1.52      drochner 1393:                capoff = PCI_CAPLISTPTR_REG;
1.28      cgd      1394:                endoff = 64;
1.26      cgd      1395:                break;
1.27      cgd      1396:        case 2:
                   1397:                /* PCI-CardBus bridge header */
                   1398:                typename = "PCI-CardBus bridge";
                   1399:                typeprintfn = &pci_conf_print_type2;
1.52      drochner 1400:                capoff = PCI_CARDBUS_CAPLISTPTR_REG;
1.28      cgd      1401:                endoff = 72;
1.27      cgd      1402:                break;
1.26      cgd      1403:        default:
1.27      cgd      1404:                typename = NULL;
1.26      cgd      1405:                typeprintfn = 0;
1.52      drochner 1406:                capoff = -1;
1.28      cgd      1407:                endoff = 64;
                   1408:                break;
1.26      cgd      1409:        }
1.27      cgd      1410:        printf("  Type %d ", hdrtype);
                   1411:        if (typename != NULL)
                   1412:                printf("(%s) ", typename);
                   1413:        printf("header:\n");
1.28      cgd      1414:        pci_conf_print_regs(regs, 16, endoff);
1.27      cgd      1415:        printf("\n");
1.45      thorpej  1416:        if (typeprintfn) {
                   1417: #ifdef _KERNEL
1.38      cgd      1418:                (*typeprintfn)(pc, tag, regs, sizebars);
1.45      thorpej  1419: #else
                   1420:                (*typeprintfn)(regs);
                   1421: #endif
                   1422:        } else
1.26      cgd      1423:                printf("    Don't know how to pretty-print type %d header.\n",
                   1424:                    hdrtype);
                   1425:        printf("\n");
1.51      drochner 1426:
1.55      jdolecek 1427:        /* capability list, if present */
1.52      drochner 1428:        if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
                   1429:                && (capoff > 0)) {
1.51      drochner 1430: #ifdef _KERNEL
1.52      drochner 1431:                pci_conf_print_caplist(pc, tag, regs, capoff);
1.51      drochner 1432: #else
1.52      drochner 1433:                pci_conf_print_caplist(regs, capoff);
1.51      drochner 1434: #endif
                   1435:                printf("\n");
                   1436:        }
1.26      cgd      1437:
                   1438:        /* device-dependent header */
                   1439:        printf("  Device-dependent header:\n");
1.28      cgd      1440:        pci_conf_print_regs(regs, endoff, 256);
1.26      cgd      1441:        printf("\n");
1.49      nathanw  1442: #ifdef _KERNEL
1.26      cgd      1443:        if (printfn)
                   1444:                (*printfn)(pc, tag, regs);
                   1445:        else
                   1446:                printf("    Don't know how to pretty-print device-dependent header.\n");
                   1447:        printf("\n");
1.45      thorpej  1448: #endif /* _KERNEL */
1.1       mycroft  1449: }

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