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Annotation of src/sys/dev/pci/pci_subr.c, Revision 1.183.2.8

1.183.2.8! sborrill    1: /*     $NetBSD: pci_subr.c,v 1.183.2.7 2018/09/23 17:40:37 martin Exp $        */
1.3       cgd         2:
1.1       mycroft     3: /*
1.22      thorpej     4:  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
1.40      cgd         5:  * Copyright (c) 1995, 1996, 1998, 2000
1.26      cgd         6:  *     Christopher G. Demetriou.  All rights reserved.
1.30      mycroft     7:  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
1.1       mycroft     8:  *
                      9:  * Redistribution and use in source and binary forms, with or without
                     10:  * modification, are permitted provided that the following conditions
                     11:  * are met:
                     12:  * 1. Redistributions of source code must retain the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer.
                     14:  * 2. Redistributions in binary form must reproduce the above copyright
                     15:  *    notice, this list of conditions and the following disclaimer in the
                     16:  *    documentation and/or other materials provided with the distribution.
                     17:  * 3. All advertising materials mentioning features or use of this software
                     18:  *    must display the following acknowledgement:
1.30      mycroft    19:  *     This product includes software developed by Charles M. Hannum.
1.1       mycroft    20:  * 4. The name of the author may not be used to endorse or promote products
                     21:  *    derived from this software without specific prior written permission.
                     22:  *
                     23:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
                     24:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
                     25:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
                     26:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
                     27:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
                     28:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
                     29:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
                     30:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
                     31:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
                     32:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                     33:  */
                     34:
                     35: /*
1.10      cgd        36:  * PCI autoconfiguration support functions.
1.45      thorpej    37:  *
                     38:  * Note: This file is also built into a userland library (libpci).
                     39:  * Pay attention to this when you make modifications.
1.1       mycroft    40:  */
1.47      lukem      41:
                     42: #include <sys/cdefs.h>
1.183.2.8! sborrill   43: __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.7 2018/09/23 17:40:37 martin Exp $");
1.21      enami      44:
1.45      thorpej    45: #ifdef _KERNEL_OPT
1.35      cgd        46: #include "opt_pci.h"
1.45      thorpej    47: #endif
1.1       mycroft    48:
                     49: #include <sys/param.h>
                     50:
1.45      thorpej    51: #ifdef _KERNEL
1.62      simonb     52: #include <sys/systm.h>
1.73      ad         53: #include <sys/intr.h>
1.80      pgoyette   54: #include <sys/module.h>
1.45      thorpej    55: #else
                     56: #include <pci.h>
1.155     pgoyette   57: #include <stdarg.h>
1.72      joerg      58: #include <stdbool.h>
1.46      enami      59: #include <stdio.h>
1.135     msaitoh    60: #include <stdlib.h>
1.117     msaitoh    61: #include <string.h>
1.45      thorpej    62: #endif
1.24      thorpej    63:
1.10      cgd        64: #include <dev/pci/pcireg.h>
1.45      thorpej    65: #ifdef _KERNEL
1.7       cgd        66: #include <dev/pci/pcivar.h>
1.126     christos   67: #else
                     68: #include <dev/pci/pci_verbose.h>
                     69: #include <dev/pci/pcidevs.h>
                     70: #include <dev/pci/pcidevs_data.h>
1.10      cgd        71: #endif
                     72:
1.183.2.4  snj        73: static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *);
                     74: static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *);
1.181     msaitoh    75: static void pci_conf_print_pcie_power(uint8_t, unsigned int);
1.165     msaitoh    76:
1.10      cgd        77: /*
                     78:  * Descriptions of known PCI classes and subclasses.
                     79:  *
                     80:  * Subclasses are described in the same way as classes, but have a
                     81:  * NULL subclass pointer.
                     82:  */
                     83: struct pci_class {
1.44      thorpej    84:        const char      *name;
1.91      matt       85:        u_int           val;            /* as wide as pci_{,sub}class_t */
1.42      jdolecek   86:        const struct pci_class *subclasses;
1.10      cgd        87: };
                     88:
1.117     msaitoh    89: /*
                     90:  * Class 0x00.
                     91:  * Before rev. 2.0.
                     92:  */
1.61      thorpej    93: static const struct pci_class pci_subclass_prehistoric[] = {
1.65      christos   94:        { "miscellaneous",      PCI_SUBCLASS_PREHISTORIC_MISC,  NULL,   },
                     95:        { "VGA",                PCI_SUBCLASS_PREHISTORIC_VGA,   NULL,   },
                     96:        { NULL,                 0,                              NULL,   },
1.10      cgd        97: };
                     98:
1.117     msaitoh    99: /*
                    100:  * Class 0x01.
1.130     msaitoh   101:  * Mass storage controller
1.117     msaitoh   102:  */
                    103:
                    104: /* ATA programming interface */
                    105: static const struct pci_class pci_interface_ata[] = {
                    106:        { "with single DMA",    PCI_INTERFACE_ATA_SINGLEDMA,    NULL,   },
                    107:        { "with chained DMA",   PCI_INTERFACE_ATA_CHAINEDDMA,   NULL,   },
                    108:        { NULL,                 0,                              NULL,   },
                    109: };
                    110:
                    111: /* SATA programming interface */
                    112: static const struct pci_class pci_interface_sata[] = {
1.128     msaitoh   113:        { "vendor specific",    PCI_INTERFACE_SATA_VND,         NULL,   },
1.117     msaitoh   114:        { "AHCI 1.0",           PCI_INTERFACE_SATA_AHCI10,      NULL,   },
1.128     msaitoh   115:        { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, },
                    116:        { NULL,                 0,                              NULL,   },
                    117: };
                    118:
                    119: /* Flash programming interface */
                    120: static const struct pci_class pci_interface_nvm[] = {
                    121:        { "vendor specific",    PCI_INTERFACE_NVM_VND,          NULL,   },
                    122:        { "NVMHCI 1.0",         PCI_INTERFACE_NVM_NVMHCI10,     NULL,   },
1.134     msaitoh   123:        { "NVMe",               PCI_INTERFACE_NVM_NVME,         NULL,   },
1.117     msaitoh   124:        { NULL,                 0,                              NULL,   },
                    125: };
                    126:
                    127: /* Subclasses */
1.61      thorpej   128: static const struct pci_class pci_subclass_mass_storage[] = {
1.65      christos  129:        { "SCSI",               PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL,   },
                    130:        { "IDE",                PCI_SUBCLASS_MASS_STORAGE_IDE,  NULL,   },
                    131:        { "floppy",             PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, },
                    132:        { "IPI",                PCI_SUBCLASS_MASS_STORAGE_IPI,  NULL,   },
                    133:        { "RAID",               PCI_SUBCLASS_MASS_STORAGE_RAID, NULL,   },
1.117     msaitoh   134:        { "ATA",                PCI_SUBCLASS_MASS_STORAGE_ATA,
                    135:          pci_interface_ata, },
                    136:        { "SATA",               PCI_SUBCLASS_MASS_STORAGE_SATA,
                    137:          pci_interface_sata, },
1.65      christos  138:        { "SAS",                PCI_SUBCLASS_MASS_STORAGE_SAS,  NULL,   },
1.128     msaitoh   139:        { "Flash",              PCI_SUBCLASS_MASS_STORAGE_NVM,
                    140:          pci_interface_nvm,    },
1.65      christos  141:        { "miscellaneous",      PCI_SUBCLASS_MASS_STORAGE_MISC, NULL,   },
                    142:        { NULL,                 0,                              NULL,   },
1.10      cgd       143: };
                    144:
1.117     msaitoh   145: /*
                    146:  * Class 0x02.
                    147:  * Network controller.
                    148:  */
1.61      thorpej   149: static const struct pci_class pci_subclass_network[] = {
1.65      christos  150:        { "ethernet",           PCI_SUBCLASS_NETWORK_ETHERNET,  NULL,   },
                    151:        { "token ring",         PCI_SUBCLASS_NETWORK_TOKENRING, NULL,   },
                    152:        { "FDDI",               PCI_SUBCLASS_NETWORK_FDDI,      NULL,   },
                    153:        { "ATM",                PCI_SUBCLASS_NETWORK_ATM,       NULL,   },
                    154:        { "ISDN",               PCI_SUBCLASS_NETWORK_ISDN,      NULL,   },
                    155:        { "WorldFip",           PCI_SUBCLASS_NETWORK_WORLDFIP,  NULL,   },
                    156:        { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
                    157:        { "miscellaneous",      PCI_SUBCLASS_NETWORK_MISC,      NULL,   },
                    158:        { NULL,                 0,                              NULL,   },
1.10      cgd       159: };
                    160:
1.117     msaitoh   161: /*
                    162:  * Class 0x03.
                    163:  * Display controller.
                    164:  */
                    165:
                    166: /* VGA programming interface */
                    167: static const struct pci_class pci_interface_vga[] = {
                    168:        { "",                   PCI_INTERFACE_VGA_VGA,          NULL,   },
                    169:        { "8514-compat",        PCI_INTERFACE_VGA_8514,         NULL,   },
                    170:        { NULL,                 0,                              NULL,   },
                    171: };
                    172: /* Subclasses */
1.61      thorpej   173: static const struct pci_class pci_subclass_display[] = {
1.117     msaitoh   174:        { "VGA",                PCI_SUBCLASS_DISPLAY_VGA,  pci_interface_vga,},
1.65      christos  175:        { "XGA",                PCI_SUBCLASS_DISPLAY_XGA,       NULL,   },
                    176:        { "3D",                 PCI_SUBCLASS_DISPLAY_3D,        NULL,   },
                    177:        { "miscellaneous",      PCI_SUBCLASS_DISPLAY_MISC,      NULL,   },
                    178:        { NULL,                 0,                              NULL,   },
1.10      cgd       179: };
                    180:
1.117     msaitoh   181: /*
                    182:  * Class 0x04.
                    183:  * Multimedia device.
                    184:  */
1.61      thorpej   185: static const struct pci_class pci_subclass_multimedia[] = {
1.65      christos  186:        { "video",              PCI_SUBCLASS_MULTIMEDIA_VIDEO,  NULL,   },
                    187:        { "audio",              PCI_SUBCLASS_MULTIMEDIA_AUDIO,  NULL,   },
                    188:        { "telephony",          PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
1.128     msaitoh   189:        { "mixed mode",         PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
1.65      christos  190:        { "miscellaneous",      PCI_SUBCLASS_MULTIMEDIA_MISC,   NULL,   },
                    191:        { NULL,                 0,                              NULL,   },
1.10      cgd       192: };
                    193:
1.117     msaitoh   194: /*
                    195:  * Class 0x05.
                    196:  * Memory controller.
                    197:  */
1.61      thorpej   198: static const struct pci_class pci_subclass_memory[] = {
1.65      christos  199:        { "RAM",                PCI_SUBCLASS_MEMORY_RAM,        NULL,   },
                    200:        { "flash",              PCI_SUBCLASS_MEMORY_FLASH,      NULL,   },
                    201:        { "miscellaneous",      PCI_SUBCLASS_MEMORY_MISC,       NULL,   },
                    202:        { NULL,                 0,                              NULL,   },
1.10      cgd       203: };
                    204:
1.117     msaitoh   205: /*
                    206:  * Class 0x06.
                    207:  * Bridge device.
                    208:  */
                    209:
                    210: /* PCI bridge programming interface */
                    211: static const struct pci_class pci_interface_pcibridge[] = {
                    212:        { "",                   PCI_INTERFACE_BRIDGE_PCI_PCI, NULL,     },
                    213:        { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL,  },
                    214:        { NULL,                 0,                              NULL,   },
                    215: };
                    216:
1.128     msaitoh   217: /* Semi-transparent PCI-to-PCI bridge programming interface */
1.117     msaitoh   218: static const struct pci_class pci_interface_stpci[] = {
                    219:        { "primary side facing host",   PCI_INTERFACE_STPCI_PRIMARY, NULL, },
                    220:        { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, },
                    221:        { NULL,                 0,                              NULL,   },
                    222: };
                    223:
1.128     msaitoh   224: /* Advanced Switching programming interface */
                    225: static const struct pci_class pci_interface_advsw[] = {
                    226:        { "custom interface",   PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
                    227:        { "ASI-SIG",            PCI_INTERFACE_ADVSW_ASISIG, NULL, },
                    228:        { NULL,                 0,                              NULL,   },
                    229: };
                    230:
1.117     msaitoh   231: /* Subclasses */
1.61      thorpej   232: static const struct pci_class pci_subclass_bridge[] = {
1.65      christos  233:        { "host",               PCI_SUBCLASS_BRIDGE_HOST,       NULL,   },
                    234:        { "ISA",                PCI_SUBCLASS_BRIDGE_ISA,        NULL,   },
                    235:        { "EISA",               PCI_SUBCLASS_BRIDGE_EISA,       NULL,   },
                    236:        { "MicroChannel",       PCI_SUBCLASS_BRIDGE_MC,         NULL,   },
1.117     msaitoh   237:        { "PCI",                PCI_SUBCLASS_BRIDGE_PCI,
                    238:          pci_interface_pcibridge,      },
1.65      christos  239:        { "PCMCIA",             PCI_SUBCLASS_BRIDGE_PCMCIA,     NULL,   },
                    240:        { "NuBus",              PCI_SUBCLASS_BRIDGE_NUBUS,      NULL,   },
                    241:        { "CardBus",            PCI_SUBCLASS_BRIDGE_CARDBUS,    NULL,   },
                    242:        { "RACEway",            PCI_SUBCLASS_BRIDGE_RACEWAY,    NULL,   },
1.117     msaitoh   243:        { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,
                    244:          pci_interface_stpci,  },
1.65      christos  245:        { "InfiniBand",         PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL,   },
1.128     msaitoh   246:        { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW,
                    247:          pci_interface_advsw,  },
1.65      christos  248:        { "miscellaneous",      PCI_SUBCLASS_BRIDGE_MISC,       NULL,   },
                    249:        { NULL,                 0,                              NULL,   },
1.10      cgd       250: };
                    251:
1.117     msaitoh   252: /*
                    253:  * Class 0x07.
                    254:  * Simple communications controller.
                    255:  */
                    256:
                    257: /* Serial controller programming interface */
                    258: static const struct pci_class pci_interface_serial[] = {
1.129     msaitoh   259:        { "generic XT-compat",  PCI_INTERFACE_SERIAL_XT,        NULL,   },
1.117     msaitoh   260:        { "16450-compat",       PCI_INTERFACE_SERIAL_16450,     NULL,   },
                    261:        { "16550-compat",       PCI_INTERFACE_SERIAL_16550,     NULL,   },
                    262:        { "16650-compat",       PCI_INTERFACE_SERIAL_16650,     NULL,   },
                    263:        { "16750-compat",       PCI_INTERFACE_SERIAL_16750,     NULL,   },
                    264:        { "16850-compat",       PCI_INTERFACE_SERIAL_16850,     NULL,   },
                    265:        { "16950-compat",       PCI_INTERFACE_SERIAL_16950,     NULL,   },
                    266:        { NULL,                 0,                              NULL,   },
                    267: };
                    268:
                    269: /* Parallel controller programming interface */
                    270: static const struct pci_class pci_interface_parallel[] = {
                    271:        { "",                   PCI_INTERFACE_PARALLEL,                 NULL,},
                    272:        { "bi-directional",     PCI_INTERFACE_PARALLEL_BIDIRECTIONAL,   NULL,},
                    273:        { "ECP 1.X-compat",     PCI_INTERFACE_PARALLEL_ECP1X,           NULL,},
1.128     msaitoh   274:        { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,},
                    275:        { "IEEE1284 target",    PCI_INTERFACE_PARALLEL_IEEE1284_TGT,    NULL,},
1.117     msaitoh   276:        { NULL,                 0,                                      NULL,},
                    277: };
                    278:
                    279: /* Modem programming interface */
                    280: static const struct pci_class pci_interface_modem[] = {
                    281:        { "",                   PCI_INTERFACE_MODEM,                    NULL,},
                    282:        { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450,         NULL,},
                    283:        { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550,         NULL,},
                    284:        { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650,         NULL,},
                    285:        { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750,         NULL,},
                    286:        { NULL,                 0,                                      NULL,},
                    287: };
                    288:
                    289: /* Subclasses */
1.61      thorpej   290: static const struct pci_class pci_subclass_communications[] = {
1.117     msaitoh   291:        { "serial",             PCI_SUBCLASS_COMMUNICATIONS_SERIAL,
                    292:          pci_interface_serial, },
                    293:        { "parallel",           PCI_SUBCLASS_COMMUNICATIONS_PARALLEL,
                    294:          pci_interface_parallel, },
1.115     msaitoh   295:        { "multi-port serial",  PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL,   NULL,},
1.117     msaitoh   296:        { "modem",              PCI_SUBCLASS_COMMUNICATIONS_MODEM,
                    297:          pci_interface_modem, },
1.115     msaitoh   298:        { "GPIB",               PCI_SUBCLASS_COMMUNICATIONS_GPIB,       NULL,},
                    299:        { "smartcard",          PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD,  NULL,},
                    300:        { "miscellaneous",      PCI_SUBCLASS_COMMUNICATIONS_MISC,       NULL,},
                    301:        { NULL,                 0,                                      NULL,},
1.20      cgd       302: };
                    303:
1.117     msaitoh   304: /*
                    305:  * Class 0x08.
                    306:  * Base system peripheral.
                    307:  */
                    308:
                    309: /* PIC programming interface */
                    310: static const struct pci_class pci_interface_pic[] = {
1.129     msaitoh   311:        { "generic 8259",       PCI_INTERFACE_PIC_8259,         NULL,   },
1.117     msaitoh   312:        { "ISA PIC",            PCI_INTERFACE_PIC_ISA,          NULL,   },
                    313:        { "EISA PIC",           PCI_INTERFACE_PIC_EISA,         NULL,   },
                    314:        { "IO APIC",            PCI_INTERFACE_PIC_IOAPIC,       NULL,   },
                    315:        { "IO(x) APIC",         PCI_INTERFACE_PIC_IOXAPIC,      NULL,   },
                    316:        { NULL,                 0,                              NULL,   },
                    317: };
                    318:
                    319: /* DMA programming interface */
                    320: static const struct pci_class pci_interface_dma[] = {
1.129     msaitoh   321:        { "generic 8237",       PCI_INTERFACE_DMA_8237,         NULL,   },
1.117     msaitoh   322:        { "ISA",                PCI_INTERFACE_DMA_ISA,          NULL,   },
                    323:        { "EISA",               PCI_INTERFACE_DMA_EISA,         NULL,   },
                    324:        { NULL,                 0,                              NULL,   },
                    325: };
                    326:
                    327: /* Timer programming interface */
                    328: static const struct pci_class pci_interface_tmr[] = {
1.129     msaitoh   329:        { "generic 8254",       PCI_INTERFACE_TIMER_8254,       NULL,   },
1.117     msaitoh   330:        { "ISA",                PCI_INTERFACE_TIMER_ISA,        NULL,   },
                    331:        { "EISA",               PCI_INTERFACE_TIMER_EISA,       NULL,   },
1.128     msaitoh   332:        { "HPET",               PCI_INTERFACE_TIMER_HPET,       NULL,   },
1.117     msaitoh   333:        { NULL,                 0,                              NULL,   },
                    334: };
                    335:
                    336: /* RTC programming interface */
                    337: static const struct pci_class pci_interface_rtc[] = {
                    338:        { "generic",            PCI_INTERFACE_RTC_GENERIC,      NULL,   },
                    339:        { "ISA",                PCI_INTERFACE_RTC_ISA,          NULL,   },
                    340:        { NULL,                 0,                              NULL,   },
                    341: };
                    342:
                    343: /* Subclasses */
1.61      thorpej   344: static const struct pci_class pci_subclass_system[] = {
1.117     msaitoh   345:        { "interrupt",          PCI_SUBCLASS_SYSTEM_PIC,   pci_interface_pic,},
                    346:        { "DMA",                PCI_SUBCLASS_SYSTEM_DMA,   pci_interface_dma,},
                    347:        { "timer",              PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,},
                    348:        { "RTC",                PCI_SUBCLASS_SYSTEM_RTC,   pci_interface_rtc,},
1.65      christos  349:        { "PCI Hot-Plug",       PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL,   },
                    350:        { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC,       NULL,   },
1.124     msaitoh   351:        { "IOMMU",              PCI_SUBCLASS_SYSTEM_IOMMU,      NULL,   },
                    352:        { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, },
1.65      christos  353:        { "miscellaneous",      PCI_SUBCLASS_SYSTEM_MISC,       NULL,   },
                    354:        { NULL,                 0,                              NULL,   },
1.20      cgd       355: };
                    356:
1.117     msaitoh   357: /*
                    358:  * Class 0x09.
                    359:  * Input device.
                    360:  */
                    361:
                    362: /* Gameport programming interface */
                    363: static const struct pci_class pci_interface_game[] = {
                    364:        { "generic",            PCI_INTERFACE_GAMEPORT_GENERIC, NULL,   },
                    365:        { "legacy",             PCI_INTERFACE_GAMEPORT_LEGACY,  NULL,   },
                    366:        { NULL,                 0,                              NULL,   },
                    367: };
                    368:
                    369: /* Subclasses */
1.61      thorpej   370: static const struct pci_class pci_subclass_input[] = {
1.65      christos  371:        { "keyboard",           PCI_SUBCLASS_INPUT_KEYBOARD,    NULL,   },
                    372:        { "digitizer",          PCI_SUBCLASS_INPUT_DIGITIZER,   NULL,   },
                    373:        { "mouse",              PCI_SUBCLASS_INPUT_MOUSE,       NULL,   },
                    374:        { "scanner",            PCI_SUBCLASS_INPUT_SCANNER,     NULL,   },
1.117     msaitoh   375:        { "game port",          PCI_SUBCLASS_INPUT_GAMEPORT,
                    376:          pci_interface_game, },
1.65      christos  377:        { "miscellaneous",      PCI_SUBCLASS_INPUT_MISC,        NULL,   },
                    378:        { NULL,                 0,                              NULL,   },
1.20      cgd       379: };
                    380:
1.117     msaitoh   381: /*
                    382:  * Class 0x0a.
                    383:  * Docking station.
                    384:  */
1.61      thorpej   385: static const struct pci_class pci_subclass_dock[] = {
1.65      christos  386:        { "generic",            PCI_SUBCLASS_DOCK_GENERIC,      NULL,   },
                    387:        { "miscellaneous",      PCI_SUBCLASS_DOCK_MISC,         NULL,   },
                    388:        { NULL,                 0,                              NULL,   },
1.20      cgd       389: };
                    390:
1.117     msaitoh   391: /*
                    392:  * Class 0x0b.
                    393:  * Processor.
                    394:  */
1.61      thorpej   395: static const struct pci_class pci_subclass_processor[] = {
1.65      christos  396:        { "386",                PCI_SUBCLASS_PROCESSOR_386,     NULL,   },
                    397:        { "486",                PCI_SUBCLASS_PROCESSOR_486,     NULL,   },
                    398:        { "Pentium",            PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL,   },
                    399:        { "Alpha",              PCI_SUBCLASS_PROCESSOR_ALPHA,   NULL,   },
                    400:        { "PowerPC",            PCI_SUBCLASS_PROCESSOR_POWERPC, NULL,   },
                    401:        { "MIPS",               PCI_SUBCLASS_PROCESSOR_MIPS,    NULL,   },
                    402:        { "Co-processor",       PCI_SUBCLASS_PROCESSOR_COPROC,  NULL,   },
1.128     msaitoh   403:        { "miscellaneous",      PCI_SUBCLASS_PROCESSOR_MISC,    NULL,   },
1.65      christos  404:        { NULL,                 0,                              NULL,   },
1.20      cgd       405: };
                    406:
1.117     msaitoh   407: /*
                    408:  * Class 0x0c.
                    409:  * Serial bus controller.
                    410:  */
                    411:
                    412: /* IEEE1394 programming interface */
                    413: static const struct pci_class pci_interface_ieee1394[] = {
                    414:        { "Firewire",           PCI_INTERFACE_IEEE1394_FIREWIRE,        NULL,},
                    415:        { "OpenHCI",            PCI_INTERFACE_IEEE1394_OPENHCI,         NULL,},
                    416:        { NULL,                 0,                                      NULL,},
                    417: };
                    418:
                    419: /* USB programming interface */
                    420: static const struct pci_class pci_interface_usb[] = {
                    421:        { "UHCI",               PCI_INTERFACE_USB_UHCI,         NULL,   },
                    422:        { "OHCI",               PCI_INTERFACE_USB_OHCI,         NULL,   },
                    423:        { "EHCI",               PCI_INTERFACE_USB_EHCI,         NULL,   },
                    424:        { "xHCI",               PCI_INTERFACE_USB_XHCI,         NULL,   },
                    425:        { "other HC",           PCI_INTERFACE_USB_OTHERHC,      NULL,   },
                    426:        { "device",             PCI_INTERFACE_USB_DEVICE,       NULL,   },
                    427:        { NULL,                 0,                              NULL,   },
                    428: };
                    429:
                    430: /* IPMI programming interface */
                    431: static const struct pci_class pci_interface_ipmi[] = {
                    432:        { "SMIC",               PCI_INTERFACE_IPMI_SMIC,                NULL,},
                    433:        { "keyboard",           PCI_INTERFACE_IPMI_KBD,                 NULL,},
                    434:        { "block transfer",     PCI_INTERFACE_IPMI_BLOCKXFER,           NULL,},
                    435:        { NULL,                 0,                                      NULL,},
                    436: };
                    437:
                    438: /* Subclasses */
1.61      thorpej   439: static const struct pci_class pci_subclass_serialbus[] = {
1.117     msaitoh   440:        { "IEEE1394",           PCI_SUBCLASS_SERIALBUS_FIREWIRE,
                    441:          pci_interface_ieee1394, },
1.65      christos  442:        { "ACCESS.bus",         PCI_SUBCLASS_SERIALBUS_ACCESS,  NULL,   },
                    443:        { "SSA",                PCI_SUBCLASS_SERIALBUS_SSA,     NULL,   },
1.117     msaitoh   444:        { "USB",                PCI_SUBCLASS_SERIALBUS_USB,
                    445:          pci_interface_usb, },
1.32      cgd       446:        /* XXX Fiber Channel/_FIBRECHANNEL */
1.65      christos  447:        { "Fiber Channel",      PCI_SUBCLASS_SERIALBUS_FIBER,   NULL,   },
                    448:        { "SMBus",              PCI_SUBCLASS_SERIALBUS_SMBUS,   NULL,   },
                    449:        { "InfiniBand",         PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,},
1.117     msaitoh   450:        { "IPMI",               PCI_SUBCLASS_SERIALBUS_IPMI,
                    451:          pci_interface_ipmi, },
1.65      christos  452:        { "SERCOS",             PCI_SUBCLASS_SERIALBUS_SERCOS,  NULL,   },
                    453:        { "CANbus",             PCI_SUBCLASS_SERIALBUS_CANBUS,  NULL,   },
1.114     msaitoh   454:        { "miscellaneous",      PCI_SUBCLASS_SERIALBUS_MISC,    NULL,   },
1.65      christos  455:        { NULL,                 0,                              NULL,   },
1.32      cgd       456: };
                    457:
1.117     msaitoh   458: /*
                    459:  * Class 0x0d.
                    460:  * Wireless Controller.
                    461:  */
1.61      thorpej   462: static const struct pci_class pci_subclass_wireless[] = {
1.65      christos  463:        { "IrDA",               PCI_SUBCLASS_WIRELESS_IRDA,     NULL,   },
1.128     msaitoh   464:        { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
1.65      christos  465:        { "RF",                 PCI_SUBCLASS_WIRELESS_RF,       NULL,   },
                    466:        { "bluetooth",          PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL,  },
                    467:        { "broadband",          PCI_SUBCLASS_WIRELESS_BROADBAND, NULL,  },
                    468:        { "802.11a (5 GHz)",    PCI_SUBCLASS_WIRELESS_802_11A,  NULL,   },
                    469:        { "802.11b (2.4 GHz)",  PCI_SUBCLASS_WIRELESS_802_11B,  NULL,   },
                    470:        { "miscellaneous",      PCI_SUBCLASS_WIRELESS_MISC,     NULL,   },
                    471:        { NULL,                 0,                              NULL,   },
1.32      cgd       472: };
                    473:
1.117     msaitoh   474: /*
                    475:  * Class 0x0e.
                    476:  * Intelligent IO controller.
                    477:  */
                    478:
                    479: /* Intelligent IO programming interface */
                    480: static const struct pci_class pci_interface_i2o[] = {
                    481:        { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40,            NULL,},
                    482:        { NULL,                 0,                                      NULL,},
                    483: };
                    484:
                    485: /* Subclasses */
1.61      thorpej   486: static const struct pci_class pci_subclass_i2o[] = {
1.117     msaitoh   487:        { "standard",           PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,},
1.114     msaitoh   488:        { "miscellaneous",      PCI_SUBCLASS_I2O_MISC,          NULL,   },
1.65      christos  489:        { NULL,                 0,                              NULL,   },
1.32      cgd       490: };
                    491:
1.117     msaitoh   492: /*
                    493:  * Class 0x0f.
                    494:  * Satellite communication controller.
                    495:  */
1.61      thorpej   496: static const struct pci_class pci_subclass_satcom[] = {
1.65      christos  497:        { "TV",                 PCI_SUBCLASS_SATCOM_TV,         NULL,   },
                    498:        { "audio",              PCI_SUBCLASS_SATCOM_AUDIO,      NULL,   },
                    499:        { "voice",              PCI_SUBCLASS_SATCOM_VOICE,      NULL,   },
                    500:        { "data",               PCI_SUBCLASS_SATCOM_DATA,       NULL,   },
1.114     msaitoh   501:        { "miscellaneous",      PCI_SUBCLASS_SATCOM_MISC,       NULL,   },
1.65      christos  502:        { NULL,                 0,                              NULL,   },
1.32      cgd       503: };
                    504:
1.117     msaitoh   505: /*
                    506:  * Class 0x10.
                    507:  * Encryption/Decryption controller.
                    508:  */
1.61      thorpej   509: static const struct pci_class pci_subclass_crypto[] = {
1.65      christos  510:        { "network/computing",  PCI_SUBCLASS_CRYPTO_NETCOMP,    NULL,   },
                    511:        { "entertainment",      PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
                    512:        { "miscellaneous",      PCI_SUBCLASS_CRYPTO_MISC,       NULL,   },
                    513:        { NULL,                 0,                              NULL,   },
1.32      cgd       514: };
                    515:
1.117     msaitoh   516: /*
                    517:  * Class 0x11.
                    518:  * Data aquuisition and signal processing controller.
                    519:  */
1.61      thorpej   520: static const struct pci_class pci_subclass_dasp[] = {
1.65      christos  521:        { "DPIO",               PCI_SUBCLASS_DASP_DPIO,         NULL,   },
1.128     msaitoh   522:        { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ,   NULL,   },
1.65      christos  523:        { "synchronization",    PCI_SUBCLASS_DASP_SYNC,         NULL,   },
                    524:        { "management",         PCI_SUBCLASS_DASP_MGMT,         NULL,   },
                    525:        { "miscellaneous",      PCI_SUBCLASS_DASP_MISC,         NULL,   },
                    526:        { NULL,                 0,                              NULL,   },
1.20      cgd       527: };
                    528:
1.117     msaitoh   529: /* List of classes */
1.163     msaitoh   530: static const struct pci_class pci_classes[] = {
1.10      cgd       531:        { "prehistoric",        PCI_CLASS_PREHISTORIC,
                    532:            pci_subclass_prehistoric,                           },
                    533:        { "mass storage",       PCI_CLASS_MASS_STORAGE,
                    534:            pci_subclass_mass_storage,                          },
                    535:        { "network",            PCI_CLASS_NETWORK,
                    536:            pci_subclass_network,                               },
                    537:        { "display",            PCI_CLASS_DISPLAY,
1.11      cgd       538:            pci_subclass_display,                               },
1.10      cgd       539:        { "multimedia",         PCI_CLASS_MULTIMEDIA,
                    540:            pci_subclass_multimedia,                            },
                    541:        { "memory",             PCI_CLASS_MEMORY,
                    542:            pci_subclass_memory,                                },
                    543:        { "bridge",             PCI_CLASS_BRIDGE,
                    544:            pci_subclass_bridge,                                },
1.20      cgd       545:        { "communications",     PCI_CLASS_COMMUNICATIONS,
                    546:            pci_subclass_communications,                        },
                    547:        { "system",             PCI_CLASS_SYSTEM,
                    548:            pci_subclass_system,                                },
                    549:        { "input",              PCI_CLASS_INPUT,
                    550:            pci_subclass_input,                                 },
                    551:        { "dock",               PCI_CLASS_DOCK,
                    552:            pci_subclass_dock,                                  },
                    553:        { "processor",          PCI_CLASS_PROCESSOR,
                    554:            pci_subclass_processor,                             },
                    555:        { "serial bus",         PCI_CLASS_SERIALBUS,
                    556:            pci_subclass_serialbus,                             },
1.32      cgd       557:        { "wireless",           PCI_CLASS_WIRELESS,
                    558:            pci_subclass_wireless,                              },
                    559:        { "I2O",                PCI_CLASS_I2O,
                    560:            pci_subclass_i2o,                                   },
                    561:        { "satellite comm",     PCI_CLASS_SATCOM,
                    562:            pci_subclass_satcom,                                },
                    563:        { "crypto",             PCI_CLASS_CRYPTO,
                    564:            pci_subclass_crypto,                                },
                    565:        { "DASP",               PCI_CLASS_DASP,
                    566:            pci_subclass_dasp,                                  },
1.164     msaitoh   567:        { "processing accelerators", PCI_CLASS_ACCEL,
                    568:            NULL,                                               },
                    569:        { "non-essential instrumentation", PCI_CLASS_INSTRUMENT,
                    570:            NULL,                                               },
1.10      cgd       571:        { "undefined",          PCI_CLASS_UNDEFINED,
1.65      christos  572:            NULL,                                               },
                    573:        { NULL,                 0,
                    574:            NULL,                                               },
1.10      cgd       575: };
                    576:
1.126     christos  577: DEV_VERBOSE_DEFINE(pci);
1.10      cgd       578:
1.155     pgoyette  579: /*
                    580:  * Append a formatted string to dest without writing more than len
                    581:  * characters (including the trailing NUL character).  dest and len
                    582:  * are updated for use in subsequent calls to snappendf().
                    583:  *
                    584:  * Returns 0 on success, a negative value if vnsprintf() fails, or
                    585:  * a positive value if the dest buffer would have overflowed.
                    586:  */
                    587:
                    588: static int __printflike(3,4)
                    589: snappendf(char **dest, size_t *len, const char * restrict fmt, ...)
                    590: {
                    591:        va_list ap;
                    592:        int count;
                    593:
                    594:        va_start(ap, fmt);
                    595:        count = vsnprintf(*dest, *len, fmt, ap);
                    596:        va_end(ap);
                    597:
                    598:        /* Let vsnprintf() errors bubble up to caller */
                    599:        if (count < 0 || *len == 0)
                    600:                return count;
                    601:
                    602:        /* Handle overflow */
                    603:        if ((size_t)count >= *len) {
                    604:                *dest += *len - 1;
                    605:                *len = 1;
                    606:                return 1;
                    607:        }
                    608:
                    609:        /* Update dest & len to point at trailing NUL */
                    610:        *dest += count;
                    611:        *len -= count;
                    612:
                    613:        return 0;
                    614: }
                    615:
1.10      cgd       616: void
1.58      itojun    617: pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp,
                    618:     size_t l)
1.10      cgd       619: {
1.163     msaitoh   620:        pci_class_t class;
1.10      cgd       621:        pci_subclass_t subclass;
                    622:        pci_interface_t interface;
                    623:        pci_revision_t revision;
1.126     christos  624:        char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
1.117     msaitoh   625:        const struct pci_class *classp, *subclassp, *interfacep;
1.10      cgd       626:
1.163     msaitoh   627:        class = PCI_CLASS(class_reg);
1.10      cgd       628:        subclass = PCI_SUBCLASS(class_reg);
                    629:        interface = PCI_INTERFACE(class_reg);
                    630:        revision = PCI_REVISION(class_reg);
                    631:
1.126     christos  632:        pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg));
                    633:        pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg),
                    634:            PCI_PRODUCT(id_reg));
1.10      cgd       635:
1.163     msaitoh   636:        classp = pci_classes;
1.10      cgd       637:        while (classp->name != NULL) {
1.163     msaitoh   638:                if (class == classp->val)
1.10      cgd       639:                        break;
                    640:                classp++;
                    641:        }
                    642:
                    643:        subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
                    644:        while (subclassp && subclassp->name != NULL) {
                    645:                if (subclass == subclassp->val)
                    646:                        break;
                    647:                subclassp++;
                    648:        }
                    649:
1.119     njoly     650:        interfacep = (subclassp && subclassp->name != NULL) ?
                    651:            subclassp->subclasses : NULL;
1.117     msaitoh   652:        while (interfacep && interfacep->name != NULL) {
                    653:                if (interface == interfacep->val)
                    654:                        break;
                    655:                interfacep++;
                    656:        }
                    657:
1.155     pgoyette  658:        (void)snappendf(&cp, &l, "%s %s", vendor, product);
1.13      cgd       659:        if (showclass) {
1.155     pgoyette  660:                (void)snappendf(&cp, &l, " (");
1.13      cgd       661:                if (classp->name == NULL)
1.155     pgoyette  662:                        (void)snappendf(&cp, &l,
                    663:                            "class 0x%02x, subclass 0x%02x",
1.163     msaitoh   664:                            class, subclass);
1.13      cgd       665:                else {
                    666:                        if (subclassp == NULL || subclassp->name == NULL)
1.155     pgoyette  667:                                (void)snappendf(&cp, &l,
1.78      drochner  668:                                    "%s, subclass 0x%02x",
1.20      cgd       669:                                    classp->name, subclass);
1.13      cgd       670:                        else
1.155     pgoyette  671:                                (void)snappendf(&cp, &l, "%s %s",
1.20      cgd       672:                                    subclassp->name, classp->name);
1.13      cgd       673:                }
1.117     msaitoh   674:                if ((interfacep == NULL) || (interfacep->name == NULL)) {
                    675:                        if (interface != 0)
1.155     pgoyette  676:                                (void)snappendf(&cp, &l, ", interface 0x%02x",
                    677:                                    interface);
1.117     msaitoh   678:                } else if (strncmp(interfacep->name, "", 1) != 0)
1.155     pgoyette  679:                        (void)snappendf(&cp, &l, ", %s", interfacep->name);
1.20      cgd       680:                if (revision != 0)
1.155     pgoyette  681:                        (void)snappendf(&cp, &l, ", revision 0x%02x", revision);
                    682:                (void)snappendf(&cp, &l, ")");
1.13      cgd       683:        }
1.22      thorpej   684: }
                    685:
1.89      drochner  686: #ifdef _KERNEL
                    687: void
1.90      drochner  688: pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive,
                    689:                         const char *known, int addrev)
1.89      drochner  690: {
                    691:        char devinfo[256];
                    692:
1.90      drochner  693:        if (known) {
                    694:                aprint_normal(": %s", known);
                    695:                if (addrev)
                    696:                        aprint_normal(" (rev. 0x%02x)",
                    697:                                      PCI_REVISION(pa->pa_class));
                    698:                aprint_normal("\n");
                    699:        } else {
                    700:                pci_devinfo(pa->pa_id, pa->pa_class, 0,
                    701:                            devinfo, sizeof(devinfo));
                    702:                aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
                    703:                              PCI_REVISION(pa->pa_class));
                    704:        }
                    705:        if (naive)
                    706:                aprint_naive(": %s\n", naive);
                    707:        else
                    708:                aprint_naive("\n");
1.89      drochner  709: }
                    710: #endif
                    711:
1.22      thorpej   712: /*
                    713:  * Print out most of the PCI configuration registers.  Typically used
                    714:  * in a device attach routine like this:
                    715:  *
                    716:  *     #ifdef MYDEV_DEBUG
1.95      chs       717:  *             printf("%s: ", device_xname(sc->sc_dev));
1.43      enami     718:  *             pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
1.22      thorpej   719:  *     #endif
                    720:  */
1.26      cgd       721:
                    722: #define        i2o(i)  ((i) * 4)
                    723: #define        o2i(o)  ((o) / 4)
1.112     msaitoh   724: #define        onoff2(str, rval, bit, onstr, offstr)                                 \
                    725:        printf("      %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr);
                    726: #define        onoff(str, rval, bit)   onoff2(str, rval, bit, "on", "off")
1.26      cgd       727:
                    728: static void
1.45      thorpej   729: pci_conf_print_common(
                    730: #ifdef _KERNEL
1.71      christos  731:     pci_chipset_tag_t pc, pcitag_t tag,
1.45      thorpej   732: #endif
                    733:     const pcireg_t *regs)
1.22      thorpej   734: {
1.163     msaitoh   735:        pci_class_t class;
                    736:        pci_subclass_t subclass;
                    737:        pci_interface_t interface;
                    738:        pci_revision_t revision;
                    739:        char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
1.165     msaitoh   740:        const struct pci_class *classp, *subclassp, *interfacep;
1.59      mycroft   741:        const char *name;
1.26      cgd       742:        pcireg_t rval;
1.117     msaitoh   743:        unsigned int num;
1.22      thorpej   744:
1.163     msaitoh   745:        rval = regs[o2i(PCI_CLASS_REG)];
                    746:        class = PCI_CLASS(rval);
                    747:        subclass = PCI_SUBCLASS(rval);
                    748:        interface = PCI_INTERFACE(rval);
                    749:        revision = PCI_REVISION(rval);
                    750:
1.26      cgd       751:        rval = regs[o2i(PCI_ID_REG)];
1.126     christos  752:        name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval));
1.59      mycroft   753:        if (name)
                    754:                printf("    Vendor Name: %s (0x%04x)\n", name,
1.26      cgd       755:                    PCI_VENDOR(rval));
1.22      thorpej   756:        else
1.26      cgd       757:                printf("    Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
1.126     christos  758:        name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval),
                    759:            PCI_PRODUCT(rval));
1.59      mycroft   760:        if (name)
                    761:                printf("    Device Name: %s (0x%04x)\n", name,
1.26      cgd       762:                    PCI_PRODUCT(rval));
1.22      thorpej   763:        else
1.26      cgd       764:                printf("    Device ID: 0x%04x\n", PCI_PRODUCT(rval));
1.22      thorpej   765:
1.26      cgd       766:        rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
1.23      drochner  767:
1.26      cgd       768:        printf("    Command register: 0x%04x\n", rval & 0xffff);
1.112     msaitoh   769:        onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
                    770:        onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE);
                    771:        onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
                    772:        onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE);
                    773:        onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE);
                    774:        onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE);
                    775:        onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
                    776:        onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
                    777:        onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
1.115     msaitoh   778:        onoff("Fast back-to-back transactions", rval,
                    779:            PCI_COMMAND_BACKTOBACK_ENABLE);
1.112     msaitoh   780:        onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
1.26      cgd       781:
                    782:        printf("    Status register: 0x%04x\n", (rval >> 16) & 0xffff);
1.172     msaitoh   783:        onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS);
1.115     msaitoh   784:        onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
                    785:            "inactive");
1.112     msaitoh   786:        onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
                    787:        onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
1.115     msaitoh   788:        onoff("User Definable Features (UDF) support", rval,
                    789:            PCI_STATUS_UDF_SUPPORT);
                    790:        onoff("Fast back-to-back capable", rval,
                    791:            PCI_STATUS_BACKTOBACK_SUPPORT);
1.112     msaitoh   792:        onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
1.22      thorpej   793:
1.26      cgd       794:        printf("      DEVSEL timing: ");
1.22      thorpej   795:        switch (rval & PCI_STATUS_DEVSEL_MASK) {
                    796:        case PCI_STATUS_DEVSEL_FAST:
                    797:                printf("fast");
                    798:                break;
                    799:        case PCI_STATUS_DEVSEL_MEDIUM:
                    800:                printf("medium");
                    801:                break;
                    802:        case PCI_STATUS_DEVSEL_SLOW:
                    803:                printf("slow");
                    804:                break;
1.26      cgd       805:        default:
                    806:                printf("unknown/reserved");     /* XXX */
                    807:                break;
1.22      thorpej   808:        }
1.159     msaitoh   809:        printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK));
1.22      thorpej   810:
1.115     msaitoh   811:        onoff("Slave signaled Target Abort", rval,
                    812:            PCI_STATUS_TARGET_TARGET_ABORT);
                    813:        onoff("Master received Target Abort", rval,
                    814:            PCI_STATUS_MASTER_TARGET_ABORT);
1.112     msaitoh   815:        onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
                    816:        onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
                    817:        onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
1.22      thorpej   818:
1.26      cgd       819:        rval = regs[o2i(PCI_CLASS_REG)];
1.163     msaitoh   820:        for (classp = pci_classes; classp->name != NULL; classp++) {
                    821:                if (class == classp->val)
1.22      thorpej   822:                        break;
                    823:        }
1.166     msaitoh   824:
                    825:        /*
                    826:         * ECN: Change Root Complex Event Collector Class Code
                    827:         * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type
                    828:         * in PCIe extend capability to know whether it's RCEC or IOMMU.
                    829:         */
                    830:        if ((class == PCI_CLASS_SYSTEM)
                    831:            && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) {
                    832:                int pcie_capoff;
                    833:                pcireg_t reg;
                    834:
1.183.2.4  snj       835:                if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
1.166     msaitoh   836:                        reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
                    837:                        if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
                    838:                                subclass = PCI_SUBCLASS_SYSTEM_RCEC;
                    839:                }
                    840:        }
1.22      thorpej   841:        subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
                    842:        while (subclassp && subclassp->name != NULL) {
1.163     msaitoh   843:                if (subclass == subclassp->val)
1.22      thorpej   844:                        break;
                    845:                subclassp++;
                    846:        }
1.166     msaitoh   847:
1.165     msaitoh   848:        interfacep = (subclassp && subclassp->name != NULL) ?
                    849:            subclassp->subclasses : NULL;
                    850:        while (interfacep && interfacep->name != NULL) {
                    851:                if (interface == interfacep->val)
                    852:                        break;
                    853:                interfacep++;
                    854:        }
                    855:
                    856:        if (classp->name != NULL)
1.163     msaitoh   857:                printf("    Class Name: %s (0x%02x)\n", classp->name, class);
1.165     msaitoh   858:        else
1.163     msaitoh   859:                printf("    Class ID: 0x%02x\n", class);
1.165     msaitoh   860:        if (subclassp != NULL && subclassp->name != NULL)
                    861:                printf("    Subclass Name: %s (0x%02x)\n",
                    862:                    subclassp->name, PCI_SUBCLASS(rval));
                    863:        else
                    864:                printf("    Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
                    865:        if ((interfacep != NULL) && (interfacep->name != NULL)
                    866:            && (strncmp(interfacep->name, "", 1) != 0))
                    867:                printf("    Interface Name: %s (0x%02x)\n",
                    868:                    interfacep->name, interface);
                    869:        else
                    870:                printf("    Interface: 0x%02x\n", interface);
1.163     msaitoh   871:        printf("    Revision ID: 0x%02x\n", revision);
1.22      thorpej   872:
1.26      cgd       873:        rval = regs[o2i(PCI_BHLC_REG)];
                    874:        printf("    BIST: 0x%02x\n", PCI_BIST(rval));
                    875:        printf("    Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
                    876:            PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
                    877:            PCI_HDRTYPE(rval));
                    878:        printf("    Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
1.117     msaitoh   879:        num = PCI_CACHELINE(rval);
                    880:        printf("    Cache Line Size: %ubytes (0x%02x)\n", num * 4, num);
1.26      cgd       881: }
1.22      thorpej   882:
1.37      nathanw   883: static int
1.45      thorpej   884: pci_conf_print_bar(
                    885: #ifdef _KERNEL
                    886:     pci_chipset_tag_t pc, pcitag_t tag,
                    887: #endif
1.167     msaitoh   888:     const pcireg_t *regs, int reg, const char *name)
1.26      cgd       889: {
1.45      thorpej   890:        int width;
                    891:        pcireg_t rval, rval64h;
1.167     msaitoh   892:        bool ioen, memen;
1.168     msaitoh   893: #ifdef _KERNEL
1.167     msaitoh   894:        pcireg_t mask, mask64h = 0;
1.168     msaitoh   895: #endif
1.167     msaitoh   896:
                    897:        rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
                    898:        ioen = rval & PCI_COMMAND_IO_ENABLE;
                    899:        memen = rval & PCI_COMMAND_MEM_ENABLE;
1.45      thorpej   900:
1.37      nathanw   901:        width = 4;
1.27      cgd       902:        /*
                    903:         * Section 6.2.5.1, `Address Maps', tells us that:
                    904:         *
                    905:         * 1) The builtin software should have already mapped the
                    906:         * device in a reasonable way.
                    907:         *
                    908:         * 2) A device which wants 2^n bytes of memory will hardwire
                    909:         * the bottom n bits of the address to 0.  As recommended,
                    910:         * we write all 1s and see what we get back.
                    911:         */
1.45      thorpej   912:
1.27      cgd       913:        rval = regs[o2i(reg)];
1.45      thorpej   914:        if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
                    915:            PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
                    916:                rval64h = regs[o2i(reg + 4)];
                    917:                width = 8;
                    918:        } else
                    919:                rval64h = 0;
                    920:
                    921: #ifdef _KERNEL
1.167     msaitoh   922:        if (rval != 0 && memen) {
                    923:                int s;
                    924:
1.24      thorpej   925:                /*
1.27      cgd       926:                 * The following sequence seems to make some devices
                    927:                 * (e.g. host bus bridges, which don't normally
                    928:                 * have their space mapped) very unhappy, to
                    929:                 * the point of crashing the system.
1.24      thorpej   930:                 *
1.27      cgd       931:                 * Therefore, if the mapping register is zero to
                    932:                 * start out with, don't bother trying.
1.24      thorpej   933:                 */
1.27      cgd       934:                s = splhigh();
                    935:                pci_conf_write(pc, tag, reg, 0xffffffff);
                    936:                mask = pci_conf_read(pc, tag, reg);
                    937:                pci_conf_write(pc, tag, reg, rval);
1.37      nathanw   938:                if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
                    939:                    PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
                    940:                        pci_conf_write(pc, tag, reg + 4, 0xffffffff);
                    941:                        mask64h = pci_conf_read(pc, tag, reg + 4);
                    942:                        pci_conf_write(pc, tag, reg + 4, rval64h);
1.167     msaitoh   943:                }
1.27      cgd       944:                splx(s);
                    945:        } else
1.168     msaitoh   946:                mask = mask64h = 0;
1.45      thorpej   947: #endif /* _KERNEL */
1.27      cgd       948:
1.28      cgd       949:        printf("    Base address register at 0x%02x", reg);
                    950:        if (name)
                    951:                printf(" (%s)", name);
                    952:        printf("\n      ");
1.27      cgd       953:        if (rval == 0) {
1.167     msaitoh   954:                printf("not implemented\n");
1.37      nathanw   955:                return width;
1.60      perry     956:        }
1.28      cgd       957:        printf("type: ");
                    958:        if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
1.34      drochner  959:                const char *type, *prefetch;
1.27      cgd       960:
                    961:                switch (PCI_MAPREG_MEM_TYPE(rval)) {
                    962:                case PCI_MAPREG_MEM_TYPE_32BIT:
                    963:                        type = "32-bit";
                    964:                        break;
                    965:                case PCI_MAPREG_MEM_TYPE_32BIT_1M:
                    966:                        type = "32-bit-1M";
                    967:                        break;
                    968:                case PCI_MAPREG_MEM_TYPE_64BIT:
                    969:                        type = "64-bit";
                    970:                        break;
                    971:                default:
                    972:                        type = "unknown (XXX)";
                    973:                        break;
1.22      thorpej   974:                }
1.34      drochner  975:                if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
                    976:                        prefetch = "";
1.27      cgd       977:                else
1.34      drochner  978:                        prefetch = "non";
                    979:                printf("%s %sprefetchable memory\n", type, prefetch);
1.37      nathanw   980:                switch (PCI_MAPREG_MEM_TYPE(rval)) {
                    981:                case PCI_MAPREG_MEM_TYPE_64BIT:
1.168     msaitoh   982:                        printf("      base: 0x%016llx",
1.37      nathanw   983:                            PCI_MAPREG_MEM64_ADDR(
1.38      cgd       984:                                ((((long long) rval64h) << 32) | rval)));
1.167     msaitoh   985:                        if (!memen)
                    986:                                printf(", disabled");
1.38      cgd       987:                        printf("\n");
1.168     msaitoh   988: #ifdef _KERNEL
                    989:                        printf("      size: 0x%016llx\n",
                    990:                            PCI_MAPREG_MEM64_SIZE(
                    991:                                    ((((long long) mask64h) << 32) | mask)));
                    992: #endif
1.37      nathanw   993:                        break;
                    994:                case PCI_MAPREG_MEM_TYPE_32BIT:
                    995:                case PCI_MAPREG_MEM_TYPE_32BIT_1M:
                    996:                default:
1.168     msaitoh   997:                        printf("      base: 0x%08x",
                    998:                            PCI_MAPREG_MEM_ADDR(rval));
1.167     msaitoh   999:                        if (!memen)
                   1000:                                printf(", disabled");
1.38      cgd      1001:                        printf("\n");
1.168     msaitoh  1002: #ifdef _KERNEL
                   1003:                        printf("      size: 0x%08x\n",
                   1004:                            PCI_MAPREG_MEM_SIZE(mask));
                   1005: #endif
1.37      nathanw  1006:                        break;
                   1007:                }
1.27      cgd      1008:        } else {
1.168     msaitoh  1009: #ifdef _KERNEL
                   1010:                if (ioen)
                   1011:                        printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
                   1012: #endif
                   1013:                printf("I/O\n");
                   1014:                printf("      base: 0x%08x", PCI_MAPREG_IO_ADDR(rval));
1.167     msaitoh  1015:                if (!ioen)
                   1016:                        printf(", disabled");
1.38      cgd      1017:                printf("\n");
1.168     msaitoh  1018: #ifdef _KERNEL
                   1019:                printf("      size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask));
                   1020: #endif
1.22      thorpej  1021:        }
1.37      nathanw  1022:
                   1023:        return width;
1.27      cgd      1024: }
1.28      cgd      1025:
                   1026: static void
1.44      thorpej  1027: pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
1.28      cgd      1028: {
                   1029:        int off, needaddr, neednl;
                   1030:
                   1031:        needaddr = 1;
                   1032:        neednl = 0;
                   1033:        for (off = first; off < pastlast; off += 4) {
                   1034:                if ((off % 16) == 0 || needaddr) {
                   1035:                        printf("    0x%02x:", off);
                   1036:                        needaddr = 0;
                   1037:                }
                   1038:                printf(" 0x%08x", regs[o2i(off)]);
                   1039:                neednl = 1;
                   1040:                if ((off % 16) == 12) {
                   1041:                        printf("\n");
                   1042:                        neednl = 0;
                   1043:                }
                   1044:        }
                   1045:        if (neednl)
                   1046:                printf("\n");
                   1047: }
                   1048:
1.161     msaitoh  1049: static const char *
                   1050: pci_conf_print_agp_calcycle(uint8_t cal)
                   1051: {
                   1052:
                   1053:        switch (cal) {
                   1054:        case 0x0:
                   1055:                return "4ms";
                   1056:        case 0x1:
                   1057:                return "16ms";
                   1058:        case 0x2:
                   1059:                return "64ms";
                   1060:        case 0x3:
                   1061:                return "256ms";
                   1062:        case 0x7:
                   1063:                return "Calibration Cycle Not Needed";
                   1064:        default:
                   1065:                return "(reserved)";
                   1066:        }
                   1067: }
                   1068:
                   1069: static void
                   1070: pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3)
                   1071: {
                   1072:        if (isagp3) {
                   1073:                /* AGP 3.0 */
                   1074:                if (reg & AGP_MODE_V3_RATE_4x)
                   1075:                        printf("x4");
                   1076:                if (reg & AGP_MODE_V3_RATE_8x)
                   1077:                        printf("x8");
                   1078:        } else {
                   1079:                /* AGP 2.0 */
                   1080:                if (reg & AGP_MODE_V2_RATE_1x)
                   1081:                        printf("x1");
                   1082:                if (reg & AGP_MODE_V2_RATE_2x)
                   1083:                        printf("x2");
                   1084:                if (reg & AGP_MODE_V2_RATE_4x)
                   1085:                        printf("x4");
                   1086:        }
                   1087:        printf("\n");
                   1088: }
                   1089:
1.132     msaitoh  1090: static void
                   1091: pci_conf_print_agp_cap(const pcireg_t *regs, int capoff)
                   1092: {
                   1093:        pcireg_t rval;
1.161     msaitoh  1094:        bool isagp3;
1.132     msaitoh  1095:
                   1096:        printf("\n  AGP Capabilities Register\n");
                   1097:
                   1098:        rval = regs[o2i(capoff)];
                   1099:        printf("    Revision: %d.%d\n",
                   1100:            PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval));
                   1101:
1.161     msaitoh  1102:        rval = regs[o2i(capoff + PCI_AGP_STATUS)];
                   1103:        printf("    Status register: 0x%04x\n", rval);
                   1104:        printf("      RQ: %d\n",
                   1105:            (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1);
                   1106:        printf("      ARQSZ: %d\n",
                   1107:            (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ));
                   1108:        printf("      CAL cycle: %s\n",
                   1109:               pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL)));
                   1110:        onoff("SBA", rval, AGP_MODE_SBA);
                   1111:        onoff("htrans#", rval, AGP_MODE_HTRANS);
                   1112:        onoff("Over 4G", rval, AGP_MODE_4G);
                   1113:        onoff("Fast Write", rval, AGP_MODE_FW);
                   1114:        onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3);
                   1115:        isagp3 = rval & AGP_MODE_MODE_3;
                   1116:        printf("      Data Rate Support: ");
                   1117:        pci_conf_print_agp_datarate(rval, isagp3);
                   1118:
                   1119:        rval = regs[o2i(capoff + PCI_AGP_COMMAND)];
                   1120:        printf("    Command register: 0x%08x\n", rval);
                   1121:        printf("      PRQ: %d\n",
                   1122:            (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1);
                   1123:        printf("      PARQSZ: %d\n",
                   1124:            (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ));
                   1125:        printf("      PCAL cycle: %s\n",
                   1126:               pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL)));
                   1127:        onoff("SBA", rval, AGP_MODE_SBA);
                   1128:        onoff("AGP", rval, AGP_MODE_AGP);
                   1129:        onoff("Over 4G", rval, AGP_MODE_4G);
                   1130:        onoff("Fast Write", rval, AGP_MODE_FW);
                   1131:        if (isagp3) {
                   1132:                printf("      Data Rate Enable: ");
                   1133:                /*
                   1134:                 * The Data Rate Enable bits are used only on 3.0 and the
                   1135:                 * Command register has no AGP_MODE_MODE_3 bit, so pass the
                   1136:                 * flag to print correctly.
                   1137:                 */
                   1138:                pci_conf_print_agp_datarate(rval, isagp3);
                   1139:        }
1.132     msaitoh  1140: }
                   1141:
1.115     msaitoh  1142: static const char *
                   1143: pci_conf_print_pcipm_cap_aux(uint16_t caps)
                   1144: {
                   1145:
                   1146:        switch ((caps >> 6) & 7) {
                   1147:        case 0: return "self-powered";
                   1148:        case 1: return "55 mA";
                   1149:        case 2: return "100 mA";
                   1150:        case 3: return "160 mA";
                   1151:        case 4: return "220 mA";
                   1152:        case 5: return "270 mA";
                   1153:        case 6: return "320 mA";
                   1154:        case 7:
                   1155:        default: return "375 mA";
                   1156:        }
                   1157: }
                   1158:
                   1159: static const char *
                   1160: pci_conf_print_pcipm_cap_pmrev(uint8_t val)
                   1161: {
                   1162:        static const char unk[] = "unknown";
                   1163:        static const char *pmrev[8] = {
                   1164:                unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
                   1165:        };
                   1166:        if (val > 7)
                   1167:                return unk;
                   1168:        return pmrev[val];
                   1169: }
                   1170:
1.27      cgd      1171: static void
1.115     msaitoh  1172: pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
1.27      cgd      1173: {
1.115     msaitoh  1174:        uint16_t caps, pmcsr;
                   1175:
                   1176:        caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
1.183.2.6  snj      1177:        pmcsr = regs[o2i(capoff + PCI_PMCSR)];
1.115     msaitoh  1178:
                   1179:        printf("\n  PCI Power Management Capabilities Register\n");
1.27      cgd      1180:
1.115     msaitoh  1181:        printf("    Capabilities register: 0x%04x\n", caps);
                   1182:        printf("      Version: %s\n",
                   1183:            pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK));
                   1184:        onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
                   1185:        onoff("Device specific initialization", caps, PCI_PMCR_DSI);
                   1186:        printf("      3.3V auxiliary current: %s\n",
                   1187:            pci_conf_print_pcipm_cap_aux(caps));
                   1188:        onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
                   1189:        onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
1.117     msaitoh  1190:        onoff("PME# support D0", caps, PCI_PMCR_PME_D0);
                   1191:        onoff("PME# support D1", caps, PCI_PMCR_PME_D1);
                   1192:        onoff("PME# support D2", caps, PCI_PMCR_PME_D2);
                   1193:        onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT);
                   1194:        onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD);
1.22      thorpej  1195:
1.183.2.6  snj      1196:        printf("    Control/status register: 0x%08x\n", pmcsr);
1.115     msaitoh  1197:        printf("      Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
                   1198:        onoff("PCI Express reserved", (pmcsr >> 2), 1);
1.117     msaitoh  1199:        onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST);
1.115     msaitoh  1200:        printf("      PME# assertion: %sabled\n",
                   1201:            (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
1.157     msaitoh  1202:        printf("      Data Select: %d\n",
                   1203:            __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK));
                   1204:        printf("      Data Scale: %d\n",
                   1205:            __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK));
1.115     msaitoh  1206:        onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
                   1207:        printf("    Bridge Support Extensions register: 0x%02x\n",
1.183.2.6  snj      1208:            (pmcsr >> 16) & 0xff);
                   1209:        onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT);
                   1210:        onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN);
                   1211:        printf("    Data register: 0x%02x\n",
                   1212:               __SHIFTOUT(pmcsr, PCI_PMCSR_DATA));
1.115     msaitoh  1213: }
1.22      thorpej  1214:
1.115     msaitoh  1215: /* XXX pci_conf_print_vpd_cap */
                   1216: /* XXX pci_conf_print_slotid_cap */
1.26      cgd      1217:
1.115     msaitoh  1218: static void
                   1219: pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
                   1220: {
                   1221:        uint32_t ctl, mmc, mme;
1.33      kleink   1222:
1.115     msaitoh  1223:        regs += o2i(capoff);
                   1224:        ctl = *regs++;
                   1225:        mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
                   1226:        mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
1.33      kleink   1227:
1.115     msaitoh  1228:        printf("\n  PCI Message Signaled Interrupt\n");
1.26      cgd      1229:
1.115     msaitoh  1230:        printf("    Message Control register: 0x%04x\n", ctl >> 16);
                   1231:        onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
                   1232:        printf("      Multiple Message Capable: %s (%d vector%s)\n",
                   1233:            mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : "");
                   1234:        printf("      Multiple Message Enabled: %s (%d vector%s)\n",
                   1235:            mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
                   1236:        onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
                   1237:        onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
1.152     msaitoh  1238:        onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP);
                   1239:        onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN);
1.115     msaitoh  1240:        printf("    Message Address %sregister: 0x%08x\n",
                   1241:            ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
                   1242:        if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
                   1243:                printf("    Message Address %sregister: 0x%08x\n",
                   1244:                    "(upper) ", *regs++);
                   1245:        }
1.183     msaitoh  1246:        printf("    Message Data register: ");
                   1247:        if (ctl & PCI_MSI_CTL_EXTMDATA_CAP)
                   1248:                printf("0x%08x\n", *regs);
                   1249:        else
                   1250:                printf("0x%04x\n", *regs & 0xffff);
1.157     msaitoh  1251:        regs++;
1.115     msaitoh  1252:        if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
                   1253:                printf("    Vector Mask register: 0x%08x\n", *regs++);
                   1254:                printf("    Vector Pending register: 0x%08x\n", *regs++);
1.22      thorpej  1255:        }
1.51      drochner 1256: }
                   1257:
1.115     msaitoh  1258: /* XXX pci_conf_print_cpci_hostwap_cap */
1.122     msaitoh  1259:
                   1260: /*
                   1261:  * For both command register and status register.
                   1262:  * The argument "idx" is index number (0 to 7).
                   1263:  */
                   1264: static int
                   1265: pcix_split_trans(unsigned int idx)
                   1266: {
                   1267:        static int table[8] = {
                   1268:                1, 2, 3, 4, 8, 12, 16, 32
                   1269:        };
                   1270:
                   1271:        if (idx >= __arraycount(table))
                   1272:                return -1;
                   1273:        return table[idx];
                   1274: }
                   1275:
                   1276: static void
1.140     msaitoh  1277: pci_conf_print_pcix_cap_2ndbusmode(int num)
                   1278: {
                   1279:        const char *maxfreq, *maxperiod;
                   1280:
                   1281:        printf("      Mode: ");
                   1282:        if (num <= 0x07)
                   1283:                printf("PCI-X Mode 1\n");
                   1284:        else if (num <= 0x0b)
                   1285:                printf("PCI-X 266 (Mode 2)\n");
                   1286:        else
                   1287:                printf("PCI-X 533 (Mode 2)\n");
                   1288:
                   1289:        printf("      Error protection: %s\n", (num <= 3) ? "parity" : "ECC");
                   1290:        switch (num & 0x03) {
                   1291:        default:
                   1292:        case 0:
                   1293:                maxfreq = "N/A";
                   1294:                maxperiod = "N/A";
                   1295:                break;
                   1296:        case 1:
                   1297:                maxfreq = "66MHz";
                   1298:                maxperiod = "15ns";
                   1299:                break;
                   1300:        case 2:
                   1301:                maxfreq = "100MHz";
                   1302:                maxperiod = "10ns";
                   1303:                break;
                   1304:        case 3:
                   1305:                maxfreq = "133MHz";
                   1306:                maxperiod = "7.5ns";
                   1307:                break;
                   1308:        }
                   1309:        printf("      Max Clock Freq: %s\n", maxfreq);
                   1310:        printf("      Min Clock Period: %s\n", maxperiod);
                   1311: }
                   1312:
                   1313: static void
1.122     msaitoh  1314: pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff)
                   1315: {
                   1316:        pcireg_t reg;
                   1317:        int isbridge;
                   1318:        int i;
                   1319:
                   1320:        isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])
                   1321:            & PCI_HDRTYPE_PPB) != 0 ? 1 : 0;
                   1322:        printf("\n  PCI-X %s Capabilities Register\n",
                   1323:            isbridge ? "Bridge" : "Non-bridge");
                   1324:
                   1325:        reg = regs[o2i(capoff)];
                   1326:        if (isbridge != 0) {
                   1327:                printf("    Secondary status register: 0x%04x\n",
                   1328:                    (reg & 0xffff0000) >> 16);
                   1329:                onoff("64bit device", reg, PCIX_STATUS_64BIT);
                   1330:                onoff("133MHz capable", reg, PCIX_STATUS_133);
                   1331:                onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
                   1332:                onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
                   1333:                onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
                   1334:                onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
1.140     msaitoh  1335:                pci_conf_print_pcix_cap_2ndbusmode(
                   1336:                        __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF));
1.122     msaitoh  1337:                printf("      Version: 0x%x\n",
                   1338:                    (reg & PCIX_BRIDGE_2NDST_VER_MASK)
                   1339:                    >> PCIX_BRIDGE_2NDST_VER_SHIFT);
                   1340:                onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266);
                   1341:                onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533);
                   1342:        } else {
                   1343:                printf("    Command register: 0x%04x\n",
                   1344:                    (reg & 0xffff0000) >> 16);
                   1345:                onoff("Data Parity Error Recovery", reg,
                   1346:                    PCIX_CMD_PERR_RECOVER);
                   1347:                onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER);
                   1348:                printf("      Maximum Burst Read Count: %u\n",
                   1349:                    PCIX_CMD_BYTECNT(reg));
                   1350:                printf("      Maximum Split Transactions: %d\n",
                   1351:                    pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK)
                   1352:                        >> PCIX_CMD_SPLTRANS_SHIFT));
                   1353:        }
                   1354:        reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */
                   1355:        printf("    %sStatus register: 0x%08x\n",
                   1356:            isbridge ? "Bridge " : "", reg);
                   1357:        printf("      Function: %d\n", PCIX_STATUS_FN(reg));
                   1358:        printf("      Device: %d\n", PCIX_STATUS_DEV(reg));
                   1359:        printf("      Bus: %d\n", PCIX_STATUS_BUS(reg));
                   1360:        onoff("64bit device", reg, PCIX_STATUS_64BIT);
                   1361:        onoff("133MHz capable", reg, PCIX_STATUS_133);
                   1362:        onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
                   1363:        onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
                   1364:        if (isbridge != 0) {
                   1365:                onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
                   1366:                onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
                   1367:        } else {
                   1368:                onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX,
                   1369:                    "bridge device", "simple device");
                   1370:                printf("      Designed max memory read byte count: %d\n",
                   1371:                    512 << ((reg & PCIX_STATUS_MAXB_MASK)
                   1372:                        >> PCIX_STATUS_MAXB_SHIFT));
                   1373:                printf("      Designed max outstanding split transaction: %d\n",
                   1374:                    pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK)
                   1375:                        >> PCIX_STATUS_MAXST_SHIFT));
                   1376:                printf("      MAX cumulative Read Size: %u\n",
                   1377:                    8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT));
                   1378:                onoff("Received split completion error", reg,
                   1379:                    PCIX_STATUS_SCERR);
                   1380:        }
                   1381:        onoff("266MHz capable", reg, PCIX_STATUS_266);
                   1382:        onoff("533MHz capable", reg, PCIX_STATUS_533);
                   1383:
                   1384:        if (isbridge == 0)
                   1385:                return;
                   1386:
                   1387:        /* Only for bridge */
                   1388:        for (i = 0; i < 2; i++) {
1.163     msaitoh  1389:                reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))];
1.122     msaitoh  1390:                printf("    %s split transaction control register: 0x%08x\n",
                   1391:                    (i == 0) ? "Upstream" : "Downstream", reg);
                   1392:                printf("      Capacity: %d\n", reg & PCIX_BRIDGE_STCAP);
                   1393:                printf("      Commitment Limit: %d\n",
                   1394:                    (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT);
                   1395:        }
                   1396: }
                   1397:
1.141     msaitoh  1398: /* pci_conf_print_ht_slave_cap */
                   1399: /* pci_conf_print_ht_host_cap */
                   1400: /* pci_conf_print_ht_switch_cap */
                   1401: /* pci_conf_print_ht_intr_cap */
                   1402: /* pci_conf_print_ht_revid_cap */
                   1403: /* pci_conf_print_ht_unitid_cap */
                   1404: /* pci_conf_print_ht_extcnf_cap */
                   1405: /* pci_conf_print_ht_addrmap_cap */
                   1406: /* pci_conf_print_ht_msimap_cap */
                   1407:
                   1408: static void
                   1409: pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff)
                   1410: {
                   1411:        pcireg_t val;
                   1412:        uint32_t lo, hi;
                   1413:
                   1414:        /*
                   1415:         * Print the rest of the command register bits. Others are
                   1416:         * printed in pci_conf_print_ht_cap().
                   1417:         */
                   1418:        val = regs[o2i(capoff + PCI_HT_CMD)];
                   1419:        onoff("Enable", val, PCI_HT_MSI_ENABLED);
                   1420:        onoff("Fixed", val, PCI_HT_MSI_FIXED);
                   1421:
                   1422:        lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)];
                   1423:        hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)];
                   1424:        printf("    Address Low register: 0x%08x\n", lo);
                   1425:        printf("    Address high register: 0x%08x\n", hi);
                   1426:        printf("      Address: 0x%016" PRIx64 "\n",
                   1427:            (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK));
                   1428: }
                   1429:
                   1430: /* pci_conf_print_ht_droute_cap */
                   1431: /* pci_conf_print_ht_vcset_cap */
                   1432: /* pci_conf_print_ht_retry_cap */
                   1433: /* pci_conf_print_ht_x86enc_cap */
                   1434: /* pci_conf_print_ht_gen3_cap */
                   1435: /* pci_conf_print_ht_fle_cap */
                   1436: /* pci_conf_print_ht_pm_cap */
                   1437: /* pci_conf_print_ht_hnc_cap */
                   1438:
                   1439: static const struct ht_types {
                   1440:        pcireg_t cap;
                   1441:        const char *name;
                   1442:        void (*printfunc)(const pcireg_t *, int);
                   1443: } ht_captab[] = {
                   1444:        {PCI_HT_CAP_SLAVE,      "Slave or Primary Interface", NULL },
                   1445:        {PCI_HT_CAP_HOST,       "Host or Secondary Interface", NULL },
                   1446:        {PCI_HT_CAP_SWITCH,     "Switch", NULL },
                   1447:        {PCI_HT_CAP_INTERRUPT,  "Interrupt Discovery and Configuration", NULL},
                   1448:        {PCI_HT_CAP_REVID,      "Revision ID",  NULL },
                   1449:        {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping",    NULL },
                   1450:        {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL },
                   1451:        {PCI_HT_CAP_ADDRMAP,    "Address Mapping",      NULL },
                   1452:        {PCI_HT_CAP_MSIMAP,     "MSI Mapping",  pci_conf_print_ht_msimap_cap },
                   1453:        {PCI_HT_CAP_DIRECTROUTE, "Direct Route",        NULL },
                   1454:        {PCI_HT_CAP_VCSET,      "VCSet",        NULL },
                   1455:        {PCI_HT_CAP_RETRYMODE,  "Retry Mode",   NULL },
                   1456:        {PCI_HT_CAP_X86ENCODE,  "X86 Encoding", NULL },
                   1457:        {PCI_HT_CAP_GEN3,       "Gen3", NULL },
                   1458:        {PCI_HT_CAP_FLE,        "Function-Level Extension",     NULL },
                   1459:        {PCI_HT_CAP_PM,         "Power Management",     NULL },
                   1460:        {PCI_HT_CAP_HIGHNODECNT, "High Node Count",     NULL },
                   1461: };
                   1462:
                   1463: static void
                   1464: pci_conf_print_ht_cap(const pcireg_t *regs, int capoff)
                   1465: {
                   1466:        pcireg_t val, foundcap;
                   1467:        unsigned int off;
                   1468:
                   1469:        val = regs[o2i(capoff + PCI_HT_CMD)];
                   1470:
                   1471:        printf("\n  HyperTransport Capability Register at 0x%02x\n", capoff);
                   1472:
                   1473:        printf("    Command register: 0x%04x\n", val >> 16);
                   1474:        foundcap = PCI_HT_CAP(val);
                   1475:        for (off = 0; off < __arraycount(ht_captab); off++) {
                   1476:                if (ht_captab[off].cap == foundcap)
                   1477:                        break;
                   1478:        }
                   1479:        printf("      Capability Type: 0x%02x ", foundcap);
                   1480:        if (off >= __arraycount(ht_captab)) {
                   1481:                printf("(unknown)\n");
                   1482:                return;
                   1483:        }
                   1484:        printf("(%s)\n", ht_captab[off].name);
                   1485:        if (ht_captab[off].printfunc != NULL)
1.142     msaitoh  1486:                ht_captab[off].printfunc(regs, capoff);
1.141     msaitoh  1487: }
1.118     msaitoh  1488:
                   1489: static void
                   1490: pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff)
                   1491: {
                   1492:        uint16_t caps;
                   1493:
                   1494:        caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT;
                   1495:
                   1496:        printf("\n  PCI Vendor Specific Capabilities Register\n");
                   1497:        printf("    Capabilities length: 0x%02x\n", caps & 0xff);
                   1498: }
                   1499:
                   1500: static void
                   1501: pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff)
                   1502: {
                   1503:        pcireg_t val;
                   1504:
                   1505:        val = regs[o2i(capoff + PCI_DEBUG_BASER)];
                   1506:
                   1507:        printf("\n  Debugport Capability Register\n");
                   1508:        printf("    Debug base Register: 0x%04x\n",
                   1509:            val >> PCI_DEBUG_BASER_SHIFT);
                   1510:        printf("      port offset: 0x%04x\n",
                   1511:            (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT);
                   1512:        printf("      BAR number: %u\n",
                   1513:            (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT);
                   1514: }
                   1515:
1.115     msaitoh  1516: /* XXX pci_conf_print_cpci_rsrcctl_cap */
                   1517: /* XXX pci_conf_print_hotplug_cap */
1.118     msaitoh  1518:
                   1519: static void
                   1520: pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff)
                   1521: {
                   1522:        pcireg_t reg;
                   1523:
                   1524:        reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)];
                   1525:
                   1526:        printf("\n  Subsystem ID Capability Register\n");
                   1527:        printf("    Subsystem ID : 0x%08x\n", reg);
                   1528: }
                   1529:
1.115     msaitoh  1530: /* XXX pci_conf_print_agp8_cap */
1.183.2.2  martin   1531: static void
                   1532: pci_conf_print_secure_cap(const pcireg_t *regs, int capoff)
                   1533: {
                   1534:        pcireg_t reg, reg2, val;
                   1535:        bool havemisc1;
                   1536:
                   1537:        printf("\n  Secure Capability Register\n");
                   1538:        reg = regs[o2i(capoff + PCI_SECURE_CAP)];
                   1539:        printf("    Capability Register: 0x%04x\n", reg >> 16);
                   1540:        val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE);
                   1541:        printf("      Capability block type: ");
                   1542:        /* I know IOMMU Only */
                   1543:        if (val == PCI_SECURE_CAP_TYPE_IOMMU)
                   1544:                printf("IOMMU\n");
                   1545:        else {
                   1546:                printf("0x%x(unknown)\n", val);
                   1547:                return;
                   1548:        }
                   1549:
                   1550:        val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV);
                   1551:        printf("      Capability revision: 0x%02x ", val);
                   1552:        if (val == PCI_SECURE_CAP_REV_IOMMU)
                   1553:                printf("(IOMMU)\n");
                   1554:        else {
                   1555:                printf("(unknown)\n");
                   1556:                return;
                   1557:        }
                   1558:        onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP);
                   1559:        onoff("HyperTransport tunnel translation support", reg,
                   1560:            PCI_SECURE_CAP_HTTUNNEL);
                   1561:        onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE);
                   1562:        onoff("IOMMU Extended Feature Register support", reg,
                   1563:            PCI_SECURE_CAP_EFRSUP);
                   1564:        onoff("IOMMU Miscellaneous Information Register 1", reg,
                   1565:            PCI_SECURE_CAP_EXT);
                   1566:        havemisc1 = reg & PCI_SECURE_CAP_EXT;
                   1567:
                   1568:        reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)];
                   1569:        printf("    Base Address Low Register: 0x%08x\n", reg);
                   1570:        onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN);
                   1571:        reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)];
                   1572:        printf("    Base Address High Register: 0x%08x\n", reg2);
                   1573:        printf("      Base Address : 0x%016" PRIx64 "\n",
                   1574:            ((uint64_t)reg2 << 32)
                   1575:            | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L)));
                   1576:
                   1577:        reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];
                   1578:        printf("    IOMMU Range Register: 0x%08x\n", reg);
                   1579:        printf("      HyperTransport UnitID: 0x%02x\n",
                   1580:            (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID));
                   1581:        onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID);
                   1582:        printf("      Device range bus number: 0x%02x\n",
                   1583:            (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM));
                   1584:        printf("      First device: 0x%04x\n",
                   1585:            (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV));
                   1586:        printf("      Last device: 0x%04x\n",
                   1587:            (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV));
                   1588:
                   1589:        reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)];
                   1590:        printf("    Miscellaneous Information Register 0: 0x%08x\n", reg);
                   1591:        printf("      MSI Message number: 0x%02x\n",
                   1592:            (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM));
                   1593:        val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE);
                   1594:        printf("      Guest Virtual Address size: ");
                   1595:        if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B)
                   1596:                printf("48bits\n");
                   1597:        else
                   1598:                printf("0x%x(unknown)\n", val);
                   1599:        val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE);
                   1600:        printf("      Physical Address size: %dbits\n", val);
                   1601:        val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE);
                   1602:        printf("      Virtual Address size: %dbits\n", val);
                   1603:        onoff("ATS response address range reserved", reg,
                   1604:            PCI_SECURE_IOMMU_MISC0_ATSRESV);
                   1605:        printf("      Peripheral Page Request MSI Message number: 0x%02x\n",
                   1606:            (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR));
                   1607:
                   1608:        if (!havemisc1)
                   1609:                return;
                   1610:
                   1611:        reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];
                   1612:        printf("    Miscellaneous Information Register 1: 0x%08x\n", reg);
                   1613:        printf("      MSI Message number (GA): 0x%02x\n",
                   1614:            (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM));
                   1615: }
1.115     msaitoh  1616:
1.51      drochner 1617: static void
1.99      msaitoh  1618: pci_print_pcie_L0s_latency(uint32_t val)
                   1619: {
                   1620:
                   1621:        switch (val) {
                   1622:        case 0x0:
                   1623:                printf("Less than 64ns\n");
                   1624:                break;
                   1625:        case 0x1:
                   1626:        case 0x2:
                   1627:        case 0x3:
                   1628:                printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1));
                   1629:                break;
                   1630:        case 0x4:
                   1631:                printf("512ns to less than 1us\n");
                   1632:                break;
                   1633:        case 0x5:
                   1634:                printf("1us to less than 2us\n");
                   1635:                break;
                   1636:        case 0x6:
                   1637:                printf("2us - 4us\n");
                   1638:                break;
                   1639:        case 0x7:
                   1640:                printf("More than 4us\n");
                   1641:                break;
                   1642:        }
                   1643: }
                   1644:
                   1645: static void
                   1646: pci_print_pcie_L1_latency(uint32_t val)
                   1647: {
                   1648:
                   1649:        switch (val) {
                   1650:        case 0x0:
                   1651:                printf("Less than 1us\n");
                   1652:                break;
                   1653:        case 0x6:
                   1654:                printf("32us - 64us\n");
                   1655:                break;
                   1656:        case 0x7:
                   1657:                printf("More than 64us\n");
                   1658:                break;
                   1659:        default:
                   1660:                printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val);
                   1661:                break;
                   1662:        }
                   1663: }
                   1664:
                   1665: static void
1.105     msaitoh  1666: pci_print_pcie_compl_timeout(uint32_t val)
                   1667: {
                   1668:
                   1669:        switch (val) {
                   1670:        case 0x0:
                   1671:                printf("50us to 50ms\n");
                   1672:                break;
                   1673:        case 0x5:
                   1674:                printf("16ms to 55ms\n");
                   1675:                break;
                   1676:        case 0x6:
                   1677:                printf("65ms to 210ms\n");
                   1678:                break;
                   1679:        case 0x9:
                   1680:                printf("260ms to 900ms\n");
                   1681:                break;
                   1682:        case 0xa:
                   1683:                printf("1s to 3.5s\n");
                   1684:                break;
                   1685:        default:
                   1686:                printf("unknown %u value\n", val);
                   1687:                break;
                   1688:        }
                   1689: }
                   1690:
1.183.2.1  martin   1691: static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"};
1.146     msaitoh  1692:
1.183.2.1  martin   1693: /*
                   1694:  * Print link speed. This function is used for the following register bits:
                   1695:  *   Maximum Link Speed in LCAP
                   1696:  *   Current Link Speed in LCSR
                   1697:  *   Target Link Speed in LCSR2
                   1698:  * All of above bitfield's values start from 1.
                   1699:  * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and
                   1700:  * this check also works for devices which compliant to versions of the base
                   1701:  * specification prior to 3.0.
                   1702:  */
1.146     msaitoh  1703: static void
1.183.2.1  martin   1704: pci_print_pcie_linkspeed(int regnum, pcireg_t val)
1.146     msaitoh  1705: {
                   1706:
1.183.2.1  martin   1707:        if ((regnum == PCIE_LCSR2) && (val == 0))
                   1708:                printf("2.5GT/s\n");
                   1709:        else if ((val < 1) || (val > __arraycount(pcie_linkspeeds)))
1.146     msaitoh  1710:                printf("unknown value (%u)\n", val);
                   1711:        else
1.183.2.1  martin   1712:                printf("%sGT/s\n", pcie_linkspeeds[val - 1]);
1.146     msaitoh  1713: }
                   1714:
1.183.2.1  martin   1715: /*
                   1716:  * Print link speed "vector".
                   1717:  * This function is used for the following register bits:
                   1718:  *   Supported Link Speeds Vector in LCAP2
                   1719:  *   Lower SKP OS Generation Supported Speed Vector  in LCAP2
                   1720:  *   Lower SKP OS Reception Supported Speed Vector in LCAP2
                   1721:  *   Enable Lower SKP OS Generation Vector in LCTL3
                   1722:  * All of above bitfield's values start from 0.
                   1723:  */
1.146     msaitoh  1724: static void
                   1725: pci_print_pcie_linkspeedvector(pcireg_t val)
                   1726: {
                   1727:        unsigned int i;
                   1728:
                   1729:        /* Start from 0 */
                   1730:        for (i = 0; i < 16; i++)
                   1731:                if (((val >> i) & 0x01) != 0) {
                   1732:                        if (i >= __arraycount(pcie_linkspeeds))
1.157     msaitoh  1733:                                printf(" unknown vector (0x%x)", 1 << i);
1.146     msaitoh  1734:                        else
                   1735:                                printf(" %sGT/s", pcie_linkspeeds[i]);
                   1736:                }
                   1737: }
                   1738:
1.105     msaitoh  1739: static void
1.157     msaitoh  1740: pci_print_pcie_link_deemphasis(pcireg_t val)
                   1741: {
                   1742:        switch (val) {
                   1743:        case 0:
                   1744:                printf("-6dB");
                   1745:                break;
                   1746:        case 1:
                   1747:                printf("-3.5dB");
                   1748:                break;
                   1749:        default:
                   1750:                printf("(reserved value)");
                   1751:        }
                   1752: }
                   1753:
                   1754: static void
1.72      joerg    1755: pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
                   1756: {
1.101     msaitoh  1757:        pcireg_t reg; /* for each register */
                   1758:        pcireg_t val; /* for each bitfield */
1.180     msaitoh  1759:        bool check_link = true;
1.72      joerg    1760:        bool check_slot = false;
1.101     msaitoh  1761:        bool check_rootport = false;
1.181     msaitoh  1762:        bool check_upstreamport = false;
1.105     msaitoh  1763:        unsigned int pciever;
1.157     msaitoh  1764:        unsigned int i;
1.72      joerg    1765:
                   1766:        printf("\n  PCI Express Capabilities Register\n");
1.99      msaitoh  1767:        /* Capability Register */
1.101     msaitoh  1768:        reg = regs[o2i(capoff)];
1.157     msaitoh  1769:        printf("    Capability register: 0x%04x\n", reg >> 16);
1.183.2.4  snj      1770:        pciever = (unsigned int)(PCIE_XCAP_VER(reg));
1.105     msaitoh  1771:        printf("      Capability version: %u\n", pciever);
1.99      msaitoh  1772:        printf("      Device type: ");
1.183.2.4  snj      1773:        switch (PCIE_XCAP_TYPE(reg)) {
1.159     msaitoh  1774:        case PCIE_XCAP_TYPE_PCIE_DEV:   /* 0x0 */
1.72      joerg    1775:                printf("PCI Express Endpoint device\n");
1.181     msaitoh  1776:                check_upstreamport = true;
1.72      joerg    1777:                break;
1.159     msaitoh  1778:        case PCIE_XCAP_TYPE_PCI_DEV:    /* 0x1 */
1.75      jmcneill 1779:                printf("Legacy PCI Express Endpoint device\n");
1.181     msaitoh  1780:                check_upstreamport = true;
1.72      joerg    1781:                break;
1.159     msaitoh  1782:        case PCIE_XCAP_TYPE_ROOT:       /* 0x4 */
1.72      joerg    1783:                printf("Root Port of PCI Express Root Complex\n");
                   1784:                check_slot = true;
1.105     msaitoh  1785:                check_rootport = true;
1.72      joerg    1786:                break;
1.159     msaitoh  1787:        case PCIE_XCAP_TYPE_UP:         /* 0x5 */
1.72      joerg    1788:                printf("Upstream Port of PCI Express Switch\n");
1.181     msaitoh  1789:                check_upstreamport = true;
1.72      joerg    1790:                break;
1.159     msaitoh  1791:        case PCIE_XCAP_TYPE_DOWN:       /* 0x6 */
1.72      joerg    1792:                printf("Downstream Port of PCI Express Switch\n");
                   1793:                check_slot = true;
1.105     msaitoh  1794:                check_rootport = true;
1.72      joerg    1795:                break;
1.159     msaitoh  1796:        case PCIE_XCAP_TYPE_PCIE2PCI:   /* 0x7 */
1.72      joerg    1797:                printf("PCI Express to PCI/PCI-X Bridge\n");
1.181     msaitoh  1798:                check_upstreamport = true;
1.72      joerg    1799:                break;
1.159     msaitoh  1800:        case PCIE_XCAP_TYPE_PCI2PCIE:   /* 0x8 */
1.72      joerg    1801:                printf("PCI/PCI-X to PCI Express Bridge\n");
1.181     msaitoh  1802:                /* Upstream port is not PCIe */
1.179     msaitoh  1803:                check_slot = true;
1.72      joerg    1804:                break;
1.159     msaitoh  1805:        case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
1.96      msaitoh  1806:                printf("Root Complex Integrated Endpoint\n");
1.180     msaitoh  1807:                check_link = false;
1.96      msaitoh  1808:                break;
1.159     msaitoh  1809:        case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
1.180     msaitoh  1810:                printf("Root Complex Event Collector\n");
                   1811:                check_link = false;
1.105     msaitoh  1812:                check_rootport = true;
1.96      msaitoh  1813:                break;
1.72      joerg    1814:        default:
                   1815:                printf("unknown\n");
                   1816:                break;
                   1817:        }
1.127     msaitoh  1818:        onoff("Slot implemented", reg, PCIE_XCAP_SI);
1.157     msaitoh  1819:        printf("      Interrupt Message Number: 0x%02x\n",
1.159     msaitoh  1820:            (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ));
1.99      msaitoh  1821:
                   1822:        /* Device Capability Register */
1.103     msaitoh  1823:        reg = regs[o2i(capoff + PCIE_DCAP)];
1.101     msaitoh  1824:        printf("    Device Capabilities Register: 0x%08x\n", reg);
1.99      msaitoh  1825:        printf("      Max Payload Size Supported: %u bytes max\n",
1.116     msaitoh  1826:            128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD));
1.99      msaitoh  1827:        printf("      Phantom Functions Supported: ");
1.159     msaitoh  1828:        switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) {
1.99      msaitoh  1829:        case 0x0:
                   1830:                printf("not available\n");
                   1831:                break;
                   1832:        case 0x1:
                   1833:                printf("MSB\n");
                   1834:                break;
                   1835:        case 0x2:
                   1836:                printf("two MSB\n");
                   1837:                break;
                   1838:        case 0x3:
                   1839:                printf("All three bits\n");
                   1840:                break;
                   1841:        }
                   1842:        printf("      Extended Tag Field Supported: %dbit\n",
1.103     msaitoh  1843:            (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);
1.99      msaitoh  1844:        printf("      Endpoint L0 Acceptable Latency: ");
1.159     msaitoh  1845:        pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY));
1.99      msaitoh  1846:        printf("      Endpoint L1 Acceptable Latency: ");
1.159     msaitoh  1847:        pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY));
1.122     msaitoh  1848:        onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);
                   1849:        onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
1.112     msaitoh  1850:        onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
                   1851:        onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);
1.181     msaitoh  1852:        if (check_upstreamport) {
                   1853:                printf("      Captured Slot Power Limit: ");
                   1854:                pci_conf_print_pcie_power(
                   1855:                        __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL),
                   1856:                        __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE));
                   1857:        }
1.112     msaitoh  1858:        onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);
1.99      msaitoh  1859:
                   1860:        /* Device Control Register */
1.103     msaitoh  1861:        reg = regs[o2i(capoff + PCIE_DCSR)];
1.101     msaitoh  1862:        printf("    Device Control Register: 0x%04x\n", reg & 0xffff);
1.112     msaitoh  1863:        onoff("Correctable Error Reporting Enable", reg,
                   1864:            PCIE_DCSR_ENA_COR_ERR);
                   1865:        onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER);
                   1866:        onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER);
                   1867:        onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR);
                   1868:        onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD);
1.99      msaitoh  1869:        printf("      Max Payload Size: %d byte\n",
1.159     msaitoh  1870:            128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD));
1.112     msaitoh  1871:        onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD);
                   1872:        onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS);
                   1873:        onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM);
                   1874:        onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
1.99      msaitoh  1875:        printf("      Max Read Request Size: %d byte\n",
1.159     msaitoh  1876:            128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));
1.99      msaitoh  1877:
                   1878:        /* Device Status Register */
1.103     msaitoh  1879:        reg = regs[o2i(capoff + PCIE_DCSR)];
1.101     msaitoh  1880:        printf("    Device Status Register: 0x%04x\n", reg >> 16);
1.112     msaitoh  1881:        onoff("Correctable Error Detected", reg, PCIE_DCSR_CED);
                   1882:        onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED);
                   1883:        onoff("Fatal Error Detected", reg, PCIE_DCSR_FED);
                   1884:        onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD);
                   1885:        onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR);
                   1886:        onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);
1.159     msaitoh  1887:        onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD);
1.99      msaitoh  1888:
1.105     msaitoh  1889:        if (check_link) {
                   1890:                /* Link Capability Register */
                   1891:                reg = regs[o2i(capoff + PCIE_LCAP)];
                   1892:                printf("    Link Capabilities Register: 0x%08x\n", reg);
                   1893:                printf("      Maximum Link Speed: ");
1.183.2.1  martin   1894:                pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED);
1.105     msaitoh  1895:                printf("      Maximum Link Width: x%u lanes\n",
1.159     msaitoh  1896:                    (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH));
1.105     msaitoh  1897:                printf("      Active State PM Support: ");
1.159     msaitoh  1898:                switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) {
1.145     msaitoh  1899:                case 0x0:
                   1900:                        printf("No ASPM support\n");
                   1901:                        break;
1.105     msaitoh  1902:                case 0x1:
1.145     msaitoh  1903:                        printf("L0s supported\n");
                   1904:                        break;
                   1905:                case 0x2:
                   1906:                        printf("L1 supported\n");
1.105     msaitoh  1907:                        break;
                   1908:                case 0x3:
                   1909:                        printf("L0s and L1 supported\n");
                   1910:                        break;
                   1911:                }
                   1912:                printf("      L0 Exit Latency: ");
1.159     msaitoh  1913:                pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT));
1.105     msaitoh  1914:                printf("      L1 Exit Latency: ");
1.159     msaitoh  1915:                pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT));
                   1916:                printf("      Port Number: %u\n",
                   1917:                    (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT));
1.117     msaitoh  1918:                onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM);
                   1919:                onoff("Surprise Down Error Report", reg,
                   1920:                    PCIE_LCAP_SURPRISE_DOWN);
                   1921:                onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE);
                   1922:                onoff("Link BW Notification Capable", reg,
                   1923:                        PCIE_LCAP_LINK_BW_NOTIFY);
                   1924:                onoff("ASPM Optionally Compliance", reg,
                   1925:                    PCIE_LCAP_ASPM_COMPLIANCE);
1.105     msaitoh  1926:
                   1927:                /* Link Control Register */
                   1928:                reg = regs[o2i(capoff + PCIE_LCSR)];
                   1929:                printf("    Link Control Register: 0x%04x\n", reg & 0xffff);
                   1930:                printf("      Active State PM Control: ");
1.159     msaitoh  1931:                switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) {
1.105     msaitoh  1932:                case 0:
                   1933:                        printf("disabled\n");
                   1934:                        break;
                   1935:                case 1:
                   1936:                        printf("L0s Entry Enabled\n");
                   1937:                        break;
                   1938:                case 2:
                   1939:                        printf("L1 Entry Enabled\n");
                   1940:                        break;
                   1941:                case 3:
                   1942:                        printf("L0s and L1 Entry Enabled\n");
                   1943:                        break;
                   1944:                }
1.112     msaitoh  1945:                onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB,
                   1946:                    "128bytes", "64bytes");
                   1947:                onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS);
                   1948:                onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN);
                   1949:                onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG);
                   1950:                onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC);
                   1951:                onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM);
1.159     msaitoh  1952:                onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD);
1.112     msaitoh  1953:                onoff("Link Bandwidth Management Interrupt Enable", reg,
                   1954:                    PCIE_LCSR_LBMIE);
                   1955:                onoff("Link Autonomous Bandwidth Interrupt Enable", reg,
                   1956:                    PCIE_LCSR_LABIE);
1.146     msaitoh  1957:                printf("      DRS Signaling Control: ");
1.159     msaitoh  1958:                switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) {
1.146     msaitoh  1959:                case 0:
                   1960:                        printf("not reported\n");
                   1961:                        break;
                   1962:                case 1:
                   1963:                        printf("Interrupt Enabled\n");
                   1964:                        break;
                   1965:                case 2:
                   1966:                        printf("DRS to FRS Signaling Enabled\n");
                   1967:                        break;
                   1968:                default:
                   1969:                        printf("reserved\n");
                   1970:                        break;
                   1971:                }
1.105     msaitoh  1972:
                   1973:                /* Link Status Register */
                   1974:                reg = regs[o2i(capoff + PCIE_LCSR)];
                   1975:                printf("    Link Status Register: 0x%04x\n", reg >> 16);
                   1976:                printf("      Negotiated Link Speed: ");
1.183.2.1  martin   1977:                pci_print_pcie_linkspeed(PCIE_LCSR,
                   1978:                    __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED));
1.105     msaitoh  1979:                printf("      Negotiated Link Width: x%u lanes\n",
1.159     msaitoh  1980:                    (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW));
1.112     msaitoh  1981:                onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
                   1982:                onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);
                   1983:                onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);
                   1984:                onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE);
                   1985:                onoff("Link Bandwidth Management Status", reg,
                   1986:                    PCIE_LCSR_LINK_BW_MGMT);
                   1987:                onoff("Link Autonomous Bandwidth Status", reg,
                   1988:                    PCIE_LCSR_LINK_AUTO_BW);
1.86      matt     1989:        }
1.99      msaitoh  1990:
1.102     msaitoh  1991:        if (check_slot == true) {
1.183.2.1  martin   1992:                pcireg_t slcap;
                   1993:
1.101     msaitoh  1994:                /* Slot Capability Register */
1.183.2.1  martin   1995:                slcap = reg = regs[o2i(capoff + PCIE_SLCAP)];
1.157     msaitoh  1996:                printf("    Slot Capability Register: 0x%08x\n", reg);
1.117     msaitoh  1997:                onoff("Attention Button Present", reg, PCIE_SLCAP_ABP);
                   1998:                onoff("Power Controller Present", reg, PCIE_SLCAP_PCP);
                   1999:                onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP);
                   2000:                onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP);
                   2001:                onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);
                   2002:                onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
                   2003:                onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
1.181     msaitoh  2004:                printf("      Slot Power Limit Value: ");
                   2005:                pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV),
                   2006:                    __SHIFTOUT(reg, PCIE_SLCAP_SPLS));
1.117     msaitoh  2007:                onoff("Electromechanical Interlock Present", reg,
                   2008:                    PCIE_SLCAP_EIP);
                   2009:                onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS);
1.101     msaitoh  2010:                printf("      Physical Slot Number: %d\n",
1.103     msaitoh  2011:                    (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19);
1.101     msaitoh  2012:
                   2013:                /* Slot Control Register */
1.103     msaitoh  2014:                reg = regs[o2i(capoff + PCIE_SLCSR)];
1.175     msaitoh  2015:                printf("    Slot Control Register: 0x%04x\n", reg & 0xffff);
1.117     msaitoh  2016:                onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE);
                   2017:                onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE);
                   2018:                onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE);
1.172     msaitoh  2019:                onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE);
1.117     msaitoh  2020:                onoff("Command Completed Interrupt Enabled", reg,
                   2021:                    PCIE_SLCSR_CCE);
                   2022:                onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE);
1.183.2.1  martin   2023:                /*
                   2024:                 * For Attention Indicator Control and Power Indicator Control,
                   2025:                 * it's allowed to be a read only value 0 if corresponding
                   2026:                 * capability register bit is 0.
                   2027:                 */
                   2028:                if (slcap & PCIE_SLCAP_AIP) {
                   2029:                        printf("      Attention Indicator Control: ");
                   2030:                        switch ((reg & PCIE_SLCSR_AIC) >> 6) {
                   2031:                        case 0x0:
                   2032:                                printf("reserved\n");
                   2033:                                break;
                   2034:                        case PCIE_SLCSR_IND_ON:
                   2035:                                printf("on\n");
                   2036:                                break;
                   2037:                        case PCIE_SLCSR_IND_BLINK:
                   2038:                                printf("blink\n");
                   2039:                                break;
                   2040:                        case PCIE_SLCSR_IND_OFF:
                   2041:                                printf("off\n");
                   2042:                                break;
                   2043:                        }
1.72      joerg    2044:                }
1.183.2.1  martin   2045:                if (slcap & PCIE_SLCAP_PIP) {
                   2046:                        printf("      Power Indicator Control: ");
                   2047:                        switch ((reg & PCIE_SLCSR_PIC) >> 8) {
                   2048:                        case 0x0:
                   2049:                                printf("reserved\n");
                   2050:                                break;
                   2051:                        case PCIE_SLCSR_IND_ON:
                   2052:                                printf("on\n");
                   2053:                                break;
                   2054:                        case PCIE_SLCSR_IND_BLINK:
                   2055:                                printf("blink\n");
                   2056:                                break;
                   2057:                        case PCIE_SLCSR_IND_OFF:
                   2058:                                printf("off\n");
                   2059:                                break;
                   2060:                        }
1.72      joerg    2061:                }
1.156     msaitoh  2062:                printf("      Power Controller Control: Power %s\n",
                   2063:                    reg & PCIE_SLCSR_PCC ? "off" : "on");
1.117     msaitoh  2064:                onoff("Electromechanical Interlock Control",
                   2065:                    reg, PCIE_SLCSR_EIC);
1.116     msaitoh  2066:                onoff("Data Link Layer State Changed Enable", reg,
                   2067:                    PCIE_SLCSR_DLLSCE);
1.146     msaitoh  2068:                onoff("Auto Slot Power Limit Disable", reg,
                   2069:                    PCIE_SLCSR_AUTOSPLDIS);
1.101     msaitoh  2070:
                   2071:                /* Slot Status Register */
1.157     msaitoh  2072:                printf("    Slot Status Register: 0x%04x\n", reg >> 16);
1.117     msaitoh  2073:                onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP);
                   2074:                onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD);
                   2075:                onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC);
1.172     msaitoh  2076:                onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC);
1.117     msaitoh  2077:                onoff("Command Completed", reg, PCIE_SLCSR_CC);
                   2078:                onoff("MRL Open", reg, PCIE_SLCSR_MS);
                   2079:                onoff("Card Present in slot", reg, PCIE_SLCSR_PDS);
                   2080:                onoff("Electromechanical Interlock engaged", reg,
                   2081:                    PCIE_SLCSR_EIS);
                   2082:                onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS);
1.101     msaitoh  2083:        }
                   2084:
                   2085:        if (check_rootport == true) {
                   2086:                /* Root Control Register */
1.103     msaitoh  2087:                reg = regs[o2i(capoff + PCIE_RCR)];
1.175     msaitoh  2088:                printf("    Root Control Register: 0x%04x\n", reg & 0xffff);
1.117     msaitoh  2089:                onoff("SERR on Correctable Error Enable", reg,
                   2090:                    PCIE_RCR_SERR_CER);
                   2091:                onoff("SERR on Non-Fatal Error Enable", reg,
                   2092:                    PCIE_RCR_SERR_NFER);
                   2093:                onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER);
                   2094:                onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE);
                   2095:                onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE);
1.101     msaitoh  2096:
                   2097:                /* Root Capability Register */
1.157     msaitoh  2098:                printf("    Root Capability Register: 0x%04x\n",
1.101     msaitoh  2099:                    reg >> 16);
1.133     msaitoh  2100:                onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV);
1.101     msaitoh  2101:
                   2102:                /* Root Status Register */
1.103     msaitoh  2103:                reg = regs[o2i(capoff + PCIE_RSR)];
1.157     msaitoh  2104:                printf("    Root Status Register: 0x%08x\n", reg);
                   2105:                printf("      PME Requester ID: 0x%04x\n",
1.104     msaitoh  2106:                    (unsigned int)(reg & PCIE_RSR_PME_REQESTER));
1.117     msaitoh  2107:                onoff("PME was asserted", reg, PCIE_RSR_PME_STAT);
                   2108:                onoff("another PME is pending", reg, PCIE_RSR_PME_PEND);
1.72      joerg    2109:        }
1.105     msaitoh  2110:
                   2111:        /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
                   2112:        if (pciever < 2)
                   2113:                return;
                   2114:
                   2115:        /* Device Capabilities 2 */
                   2116:        reg = regs[o2i(capoff + PCIE_DCAP2)];
                   2117:        printf("    Device Capabilities 2: 0x%08x\n", reg);
1.157     msaitoh  2118:        printf("      Completion Timeout Ranges Supported: ");
                   2119:        val = reg & PCIE_DCAP2_COMPT_RANGE;
                   2120:        switch (val) {
                   2121:        case 0:
                   2122:                printf("not supported\n");
                   2123:                break;
                   2124:        default:
                   2125:                for (i = 0; i <= 3; i++) {
                   2126:                        if (((val >> i) & 0x01) != 0)
                   2127:                                printf("%c", 'A' + i);
                   2128:                }
                   2129:                printf("\n");
                   2130:        }
1.112     msaitoh  2131:        onoff("Completion Timeout Disable Supported", reg,
                   2132:            PCIE_DCAP2_COMPT_DIS);
                   2133:        onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD);
                   2134:        onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT);
                   2135:        onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM);
                   2136:        onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM);
                   2137:        onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS);
                   2138:        onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS);
                   2139:        onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC);
1.157     msaitoh  2140:        printf("      TPH Completer Supported: ");
                   2141:        switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) {
                   2142:        case 0:
1.172     msaitoh  2143:                printf("Not supported\n");
1.157     msaitoh  2144:                break;
                   2145:        case 1:
                   2146:                printf("TPH\n");
                   2147:                break;
                   2148:        case 3:
                   2149:                printf("TPH and Extended TPH\n");
                   2150:                break;
                   2151:        default:
                   2152:                printf("(reserved value)\n");
                   2153:                break;
                   2154:
                   2155:        }
1.145     msaitoh  2156:        printf("      LN System CLS: ");
                   2157:        switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) {
                   2158:        case 0x0:
                   2159:                printf("Not supported or not in effect\n");
                   2160:                break;
                   2161:        case 0x1:
                   2162:                printf("64byte cachelines in effect\n");
                   2163:                break;
                   2164:        case 0x2:
                   2165:                printf("128byte cachelines in effect\n");
                   2166:                break;
                   2167:        case 0x3:
                   2168:                printf("Reserved\n");
                   2169:                break;
                   2170:        }
1.105     msaitoh  2171:        printf("      OBFF Supported: ");
1.183.2.2  martin   2172:        switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {
1.105     msaitoh  2173:        case 0x0:
                   2174:                printf("Not supported\n");
                   2175:                break;
                   2176:        case 0x1:
                   2177:                printf("Message only\n");
                   2178:                break;
                   2179:        case 0x2:
                   2180:                printf("WAKE# only\n");
                   2181:                break;
                   2182:        case 0x3:
                   2183:                printf("Both\n");
                   2184:                break;
                   2185:        }
1.112     msaitoh  2186:        onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD);
                   2187:        onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);
1.157     msaitoh  2188:        val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP);
                   2189:        printf("      Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val);
1.152     msaitoh  2190:        printf("      Emergency Power Reduction Supported: ");
                   2191:        switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) {
                   2192:        case 0x0:
                   2193:                printf("Not supported\n");
                   2194:                break;
                   2195:        case 0x1:
                   2196:                printf("Device Specific mechanism\n");
                   2197:                break;
                   2198:        case 0x2:
                   2199:                printf("Form Factor spec or Device Specific mechanism\n");
                   2200:                break;
                   2201:        case 0x3:
                   2202:                printf("Reserved\n");
                   2203:                break;
                   2204:        }
                   2205:        onoff("Emergency Power Reduction Initialization Required", reg,
                   2206:            PCIE_DCAP2_EMGPWRRED_INI);
1.146     msaitoh  2207:        onoff("FRS Supported", reg, PCIE_DCAP2_FRS);
1.105     msaitoh  2208:
                   2209:        /* Device Control 2 */
                   2210:        reg = regs[o2i(capoff + PCIE_DCSR2)];
                   2211:        printf("    Device Control 2: 0x%04x\n", reg & 0xffff);
                   2212:        printf("      Completion Timeout Value: ");
                   2213:        pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL);
1.117     msaitoh  2214:        onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS);
                   2215:        onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD);
1.172     msaitoh  2216:        onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ);
1.117     msaitoh  2217:        onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK);
                   2218:        onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ);
                   2219:        onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP);
                   2220:        onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
1.152     msaitoh  2221:        onoff("Emergency Power Reduction Request", reg,
                   2222:            PCIE_DCSR2_EMGPWRRED_REQ);
1.105     msaitoh  2223:        printf("      OBFF: ");
1.183.2.2  martin   2224:        switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {
1.105     msaitoh  2225:        case 0x0:
                   2226:                printf("Disabled\n");
                   2227:                break;
                   2228:        case 0x1:
                   2229:                printf("Enabled with Message Signaling Variation A\n");
                   2230:                break;
                   2231:        case 0x2:
                   2232:                printf("Enabled with Message Signaling Variation B\n");
                   2233:                break;
                   2234:        case 0x3:
                   2235:                printf("Enabled using WAKE# signaling\n");
                   2236:                break;
                   2237:        }
1.117     msaitoh  2238:        onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);
1.105     msaitoh  2239:
                   2240:        if (check_link) {
1.157     msaitoh  2241:                bool drs_supported = false;
1.146     msaitoh  2242:
1.105     msaitoh  2243:                /* Link Capability 2 */
                   2244:                reg = regs[o2i(capoff + PCIE_LCAP2)];
1.157     msaitoh  2245:                /* If the vector is 0, LCAP2 is not implemented */
                   2246:                if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) {
                   2247:                        printf("    Link Capabilities 2: 0x%08x\n", reg);
                   2248:                        printf("      Supported Link Speeds Vector:");
                   2249:                        pci_print_pcie_linkspeedvector(
                   2250:                                __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV));
                   2251:                        printf("\n");
                   2252:                        onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK);
                   2253:                        printf("      "
                   2254:                            "Lower SKP OS Generation Supported Speed Vector:");
                   2255:                        pci_print_pcie_linkspeedvector(
                   2256:                                __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV));
                   2257:                        printf("\n");
                   2258:                        printf("      "
                   2259:                            "Lower SKP OS Reception Supported Speed Vector:");
                   2260:                        pci_print_pcie_linkspeedvector(
                   2261:                                __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV));
                   2262:                        printf("\n");
                   2263:                        onoff("DRS Supported", reg, PCIE_LCAP2_DRS);
                   2264:                        drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false;
                   2265:                }
1.105     msaitoh  2266:
                   2267:                /* Link Control 2 */
                   2268:                reg = regs[o2i(capoff + PCIE_LCSR2)];
1.183.2.1  martin   2269:                /* If the vector is 0, LCAP2 is not implemented */
1.105     msaitoh  2270:                printf("    Link Control 2: 0x%04x\n", reg & 0xffff);
                   2271:                printf("      Target Link Speed: ");
1.183.2.1  martin   2272:                pci_print_pcie_linkspeed(PCIE_LCSR2,
                   2273:                    __SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED));
1.117     msaitoh  2274:                onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL);
                   2275:                onoff("HW Autonomous Speed Disabled", reg,
                   2276:                    PCIE_LCSR2_HW_AS_DIS);
1.157     msaitoh  2277:                printf("      Selectable De-emphasis: ");
                   2278:                pci_print_pcie_link_deemphasis(
                   2279:                        __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP));
                   2280:                printf("\n");
1.105     msaitoh  2281:                printf("      Transmit Margin: %u\n",
                   2282:                    (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
1.117     msaitoh  2283:                onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
                   2284:                onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
1.157     msaitoh  2285:                printf("      Compliance Present/De-emphasis: ");
                   2286:                pci_print_pcie_link_deemphasis(
                   2287:                        __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP));
                   2288:                printf("\n");
1.105     msaitoh  2289:
                   2290:                /* Link Status 2 */
1.117     msaitoh  2291:                printf("    Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff);
1.157     msaitoh  2292:                printf("      Current De-emphasis Level: ");
                   2293:                pci_print_pcie_link_deemphasis(
                   2294:                        __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL));
                   2295:                printf("\n");
1.117     msaitoh  2296:                onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL);
                   2297:                onoff("Equalization Phase 1 Successful", reg,
                   2298:                    PCIE_LCSR2_EQP1_SUC);
                   2299:                onoff("Equalization Phase 2 Successful", reg,
                   2300:                    PCIE_LCSR2_EQP2_SUC);
                   2301:                onoff("Equalization Phase 3 Successful", reg,
                   2302:                    PCIE_LCSR2_EQP3_SUC);
                   2303:                onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ);
1.146     msaitoh  2304:                onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD);
                   2305:                if (drs_supported) {
                   2306:                        printf("      Downstream Component Presence: ");
                   2307:                        switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) {
                   2308:                        case PCIE_DSCOMPN_DOWN_NOTDETERM:
                   2309:                                printf("Link Down - Presence Not"
                   2310:                                    " Determined\n");
                   2311:                                break;
                   2312:                        case PCIE_DSCOMPN_DOWN_NOTPRES:
                   2313:                                printf("Link Down - Component Not Present\n");
                   2314:                                break;
                   2315:                        case PCIE_DSCOMPN_DOWN_PRES:
                   2316:                                printf("Link Down - Component Present\n");
                   2317:                                break;
                   2318:                        case PCIE_DSCOMPN_UP_PRES:
                   2319:                                printf("Link Up - Component Present\n");
                   2320:                                break;
                   2321:                        case PCIE_DSCOMPN_UP_PRES_DRS:
                   2322:                                printf("Link Up - Component Present and DRS"
                   2323:                                    " received\n");
                   2324:                                break;
                   2325:                        default:
                   2326:                                printf("reserved\n");
                   2327:                                break;
                   2328:                        }
                   2329:                        onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV);
                   2330:                }
1.105     msaitoh  2331:        }
                   2332:
                   2333:        /* Slot Capability 2 */
                   2334:        /* Slot Control 2 */
                   2335:        /* Slot Status 2 */
1.72      joerg    2336: }
                   2337:
1.120     msaitoh  2338: static void
                   2339: pci_conf_print_msix_cap(const pcireg_t *regs, int capoff)
                   2340: {
                   2341:        pcireg_t reg;
                   2342:
                   2343:        printf("\n  MSI-X Capability Register\n");
                   2344:
                   2345:        reg = regs[o2i(capoff + PCI_MSIX_CTL)];
                   2346:        printf("    Message Control register: 0x%04x\n",
                   2347:            (reg >> 16) & 0xff);
                   2348:        printf("      Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg));
                   2349:        onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK);
                   2350:        onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);
                   2351:        reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];
                   2352:        printf("    Table offset register: 0x%08x\n", reg);
1.157     msaitoh  2353:        printf("      Table offset: 0x%08x\n",
1.145     msaitoh  2354:            (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK));
                   2355:        printf("      BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK));
1.120     msaitoh  2356:        reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)];
                   2357:        printf("    Pending bit array register: 0x%08x\n", reg);
1.157     msaitoh  2358:        printf("      Pending bit array offset: 0x%08x\n",
1.145     msaitoh  2359:            (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK));
                   2360:        printf("      BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK));
1.120     msaitoh  2361: }
                   2362:
1.138     msaitoh  2363: static void
                   2364: pci_conf_print_sata_cap(const pcireg_t *regs, int capoff)
                   2365: {
                   2366:        pcireg_t reg;
                   2367:
                   2368:        printf("\n  Serial ATA Capability Register\n");
                   2369:
1.169     msaitoh  2370:        reg = regs[o2i(capoff + PCI_SATA_REV)];
1.138     msaitoh  2371:        printf("    Revision register: 0x%04x\n", (reg >> 16) & 0xff);
1.139     msaitoh  2372:        printf("      Revision: %u.%u\n",
                   2373:            (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR),
                   2374:            (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR));
1.138     msaitoh  2375:
                   2376:        reg = regs[o2i(capoff + PCI_SATA_BAR)];
                   2377:
                   2378:        printf("    BAR Register: 0x%08x\n", reg);
1.140     msaitoh  2379:        printf("      Register location: ");
                   2380:        if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF)
                   2381:                printf("in config space\n");
                   2382:        else {
                   2383:                printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg));
                   2384:                printf("      BAR offset: 0x%08x\n",
                   2385:                    (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4);
                   2386:        }
1.138     msaitoh  2387: }
                   2388:
1.118     msaitoh  2389: static void
                   2390: pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff)
                   2391: {
                   2392:        pcireg_t reg;
                   2393:
                   2394:        printf("\n  Advanced Features Capability Register\n");
                   2395:
                   2396:        reg = regs[o2i(capoff + PCI_AFCAPR)];
                   2397:        printf("    AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff);
1.145     msaitoh  2398:        printf("    AF Structure Length: 0x%02x\n",
                   2399:            (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH));
1.118     msaitoh  2400:        onoff("Transaction Pending", reg, PCI_AF_TP_CAP);
                   2401:        onoff("Function Level Reset", reg, PCI_AF_FLR_CAP);
                   2402:        reg = regs[o2i(capoff + PCI_AFCSR)];
                   2403:        printf("    AF Control register: 0x%02x\n", reg & 0xff);
                   2404:        /*
                   2405:         * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register
                   2406:         * and it's always 0 on read
                   2407:         */
                   2408:        printf("    AF Status register: 0x%02x\n", (reg >> 8) & 0xff);
                   2409:        onoff("Transaction Pending", reg, PCI_AFSR_TP);
                   2410: }
1.77      jmcneill 2411:
1.177     msaitoh  2412: /* XXX pci_conf_print_ea_cap */
                   2413: /* XXX pci_conf_print_fpb_cap */
                   2414:
1.132     msaitoh  2415: static struct {
                   2416:        pcireg_t cap;
                   2417:        const char *name;
                   2418:        void (*printfunc)(const pcireg_t *, int);
                   2419: } pci_captab[] = {
                   2420:        { PCI_CAP_RESERVED0,    "reserved",     NULL },
                   2421:        { PCI_CAP_PWRMGMT,      "Power Management", pci_conf_print_pcipm_cap },
                   2422:        { PCI_CAP_AGP,          "AGP",          pci_conf_print_agp_cap },
                   2423:        { PCI_CAP_VPD,          "VPD",          NULL },
                   2424:        { PCI_CAP_SLOTID,       "SlotID",       NULL },
                   2425:        { PCI_CAP_MSI,          "MSI",          pci_conf_print_msi_cap },
                   2426:        { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL },
                   2427:        { PCI_CAP_PCIX,         "PCI-X",        pci_conf_print_pcix_cap },
1.141     msaitoh  2428:        { PCI_CAP_LDT,          "HyperTransport", pci_conf_print_ht_cap },
1.132     msaitoh  2429:        { PCI_CAP_VENDSPEC,     "Vendor-specific",
                   2430:          pci_conf_print_vendspec_cap },
                   2431:        { PCI_CAP_DEBUGPORT,    "Debug Port",   pci_conf_print_debugport_cap },
                   2432:        { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL },
                   2433:        { PCI_CAP_HOTPLUG,      "Hot-Plug",     NULL },
                   2434:        { PCI_CAP_SUBVENDOR,    "Subsystem vendor ID",
                   2435:          pci_conf_print_subsystem_cap },
                   2436:        { PCI_CAP_AGP8,         "AGP 8x",       NULL },
1.183.2.2  martin   2437:        { PCI_CAP_SECURE,       "Secure Device", pci_conf_print_secure_cap },
1.132     msaitoh  2438:        { PCI_CAP_PCIEXPRESS,   "PCI Express",  pci_conf_print_pcie_cap },
                   2439:        { PCI_CAP_MSIX,         "MSI-X",        pci_conf_print_msix_cap },
1.138     msaitoh  2440:        { PCI_CAP_SATA,         "SATA",         pci_conf_print_sata_cap },
1.145     msaitoh  2441:        { PCI_CAP_PCIAF,        "Advanced Features", pci_conf_print_pciaf_cap},
1.178     kre      2442:        { PCI_CAP_EA,           "Enhanced Allocation", NULL },
1.177     msaitoh  2443:        { PCI_CAP_FPB,          "Flattening Portal Bridge", NULL }
1.132     msaitoh  2444: };
                   2445:
1.135     msaitoh  2446: static int
1.183.2.4  snj      2447: pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp)
1.135     msaitoh  2448: {
                   2449:        pcireg_t rval;
1.183.2.4  snj      2450:        unsigned int capptr;
1.135     msaitoh  2451:        int off;
                   2452:
1.183.2.4  snj      2453:        if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT))
                   2454:                return 0;
                   2455:
                   2456:        /* Determine the Capability List Pointer register to start with. */
                   2457:        switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) {
                   2458:        case 0: /* standard device header */
                   2459:        case 1: /* PCI-PCI bridge header */
                   2460:                capptr = PCI_CAPLISTPTR_REG;
                   2461:                break;
                   2462:        case 2: /* PCI-CardBus Bridge header */
                   2463:                capptr = PCI_CARDBUS_CAPLISTPTR_REG;
                   2464:                break;
                   2465:        default:
                   2466:                return 0;
                   2467:        }
                   2468:
                   2469:        for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]);
1.141     msaitoh  2470:             off != 0; off = PCI_CAPLIST_NEXT(rval)) {
1.135     msaitoh  2471:                rval = regs[o2i(off)];
                   2472:                if (capid == PCI_CAPLIST_CAP(rval)) {
                   2473:                        if (offsetp != NULL)
                   2474:                                *offsetp = off;
                   2475:                        return 1;
                   2476:                }
                   2477:        }
                   2478:        return 0;
                   2479: }
                   2480:
1.86      matt     2481: static void
1.51      drochner 2482: pci_conf_print_caplist(
                   2483: #ifdef _KERNEL
1.71      christos 2484:     pci_chipset_tag_t pc, pcitag_t tag,
1.51      drochner 2485: #endif
1.52      drochner 2486:     const pcireg_t *regs, int capoff)
1.51      drochner 2487: {
                   2488:        int off;
1.132     msaitoh  2489:        pcireg_t foundcap;
1.51      drochner 2490:        pcireg_t rval;
1.132     msaitoh  2491:        bool foundtable[__arraycount(pci_captab)];
                   2492:        unsigned int i;
1.33      kleink   2493:
1.132     msaitoh  2494:        /* Clear table */
                   2495:        for (i = 0; i < __arraycount(pci_captab); i++)
                   2496:                foundtable[i] = false;
                   2497:
                   2498:        /* Print capability register's offset and the type first */
1.52      drochner 2499:        for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
1.141     msaitoh  2500:             off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
1.51      drochner 2501:                rval = regs[o2i(off)];
                   2502:                printf("  Capability register at 0x%02x\n", off);
                   2503:
                   2504:                printf("    type: 0x%02x (", PCI_CAPLIST_CAP(rval));
1.132     msaitoh  2505:                foundcap = PCI_CAPLIST_CAP(rval);
                   2506:                if (foundcap < __arraycount(pci_captab)) {
                   2507:                        printf("%s)\n", pci_captab[foundcap].name);
                   2508:                        /* Mark as found */
                   2509:                        foundtable[foundcap] = true;
                   2510:                } else
                   2511:                        printf("unknown)\n");
                   2512:        }
                   2513:
                   2514:        /*
                   2515:         * And then, print the detail of each capability registers
                   2516:         * in capability value's order.
                   2517:         */
                   2518:        for (i = 0; i < __arraycount(pci_captab); i++) {
                   2519:                if (foundtable[i] == false)
                   2520:                        continue;
                   2521:
                   2522:                /*
                   2523:                 * The type was found. Search capability list again and
                   2524:                 * print all capabilities that the capabiliy type is
                   2525:                 * the same. This is required because some capabilities
                   2526:                 * appear multiple times (e.g. HyperTransport capability).
                   2527:                 */
1.141     msaitoh  2528:                for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
                   2529:                     off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
                   2530:                        rval = regs[o2i(off)];
                   2531:                        if ((PCI_CAPLIST_CAP(rval) == i)
                   2532:                            && (pci_captab[i].printfunc != NULL))
                   2533:                                pci_captab[i].printfunc(regs, off);
                   2534:                }
1.135     msaitoh  2535:        }
                   2536: }
                   2537:
                   2538: /* Extended Capability */
                   2539:
                   2540: static void
                   2541: pci_conf_print_aer_cap_uc(pcireg_t reg)
                   2542: {
                   2543:
                   2544:        onoff("Undefined", reg, PCI_AER_UC_UNDEFINED);
                   2545:        onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR);
                   2546:        onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR);
1.146     msaitoh  2547:        onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP);
1.135     msaitoh  2548:        onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR);
                   2549:        onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT);
                   2550:        onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT);
                   2551:        onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION);
                   2552:        onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW);
                   2553:        onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP);
                   2554:        onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR);
                   2555:        onoff("Unsupported Request Error", reg,
                   2556:            PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR);
                   2557:        onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION);
                   2558:        onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR);
                   2559:        onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP);
                   2560:        onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED);
                   2561:        onoff("TLP Prefix Blocked Error", reg,
1.146     msaitoh  2562:            PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR);
                   2563:        onoff("Poisoned TLP Egress Blocked", reg,
                   2564:            PCI_AER_UC_POISONTLP_EGRESS_BLOCKED);
1.135     msaitoh  2565: }
                   2566:
                   2567: static void
                   2568: pci_conf_print_aer_cap_cor(pcireg_t reg)
                   2569: {
                   2570:
                   2571:        onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR);
                   2572:        onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP);
                   2573:        onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP);
                   2574:        onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER);
                   2575:        onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT);
                   2576:        onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR);
                   2577:        onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR);
                   2578:        onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW);
                   2579: }
                   2580:
                   2581: static void
                   2582: pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log)
                   2583: {
                   2584:
                   2585:        printf("      First Error Pointer: 0x%04x\n",
                   2586:            (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR));
                   2587:        onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE);
                   2588:        onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE);
                   2589:        onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE);
1.172     msaitoh  2590:        onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE);
1.135     msaitoh  2591:        onoff("Multiple Header Recording Capable", reg,
                   2592:            PCI_AER_MULT_HDR_CAPABLE);
1.146     msaitoh  2593:        onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE);
                   2594:        onoff("Completion Timeout Prefix/Header Log Capable", reg,
                   2595:            PCI_AER_COMPTOUTPRFXHDRLOG_CAP);
1.135     msaitoh  2596:
                   2597:        /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */
                   2598:        if (!tlp_prefix_log)
                   2599:                return;
                   2600:        onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT);
                   2601:        *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false;
                   2602: }
                   2603:
                   2604: static void
                   2605: pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg)
                   2606: {
                   2607:
                   2608:        onoff("Correctable Error Reporting Enable", reg,
                   2609:            PCI_AER_ROOTERR_COR_ENABLE);
                   2610:        onoff("Non-Fatal Error Reporting Enable", reg,
                   2611:            PCI_AER_ROOTERR_NF_ENABLE);
                   2612:        onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE);
                   2613: }
                   2614:
                   2615: static void
                   2616: pci_conf_print_aer_cap_rooterr_status(pcireg_t reg)
                   2617: {
                   2618:
                   2619:        onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR);
                   2620:        onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR);
                   2621:        onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR);
                   2622:        onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg,
                   2623:            PCI_AER_ROOTERR_MULTI_UC_ERR);
1.159     msaitoh  2624:        onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL);
                   2625:        onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR);
1.135     msaitoh  2626:        onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR);
1.158     msaitoh  2627:        printf("      Advanced Error Interrupt Message Number: 0x%02x\n",
1.159     msaitoh  2628:            (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE));
1.135     msaitoh  2629: }
                   2630:
                   2631: static void
                   2632: pci_conf_print_aer_cap_errsrc_id(pcireg_t reg)
                   2633: {
                   2634:
                   2635:        printf("      Correctable Source ID: 0x%04x\n",
                   2636:            (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR));
                   2637:        printf("      ERR_FATAL/NONFATAL Source ID: 0x%04x\n",
                   2638:            (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC));
                   2639: }
                   2640:
                   2641: static void
1.183.2.4  snj      2642: pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  2643: {
                   2644:        pcireg_t reg;
                   2645:        int pcie_capoff;
                   2646:        int pcie_devtype = -1;
                   2647:        bool tlp_prefix_log = false;
                   2648:
1.183.2.4  snj      2649:        if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
1.135     msaitoh  2650:                reg = regs[o2i(pcie_capoff)];
1.143     msaitoh  2651:                pcie_devtype = PCIE_XCAP_TYPE(reg);
1.135     msaitoh  2652:                /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
                   2653:                if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) {
                   2654:                        reg = regs[o2i(pcie_capoff + PCIE_DCAP2)];
                   2655:                        /* End-End TLP Prefix Supported */
                   2656:                        if (reg & PCIE_DCAP2_EETLP_PREF) {
                   2657:                                tlp_prefix_log = true;
                   2658:                        }
                   2659:                }
                   2660:        }
                   2661:
                   2662:        printf("\n  Advanced Error Reporting Register\n");
                   2663:
                   2664:        reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)];
                   2665:        printf("    Uncorrectable Error Status register: 0x%08x\n", reg);
                   2666:        pci_conf_print_aer_cap_uc(reg);
                   2667:        reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)];
                   2668:        printf("    Uncorrectable Error Mask register: 0x%08x\n", reg);
                   2669:        pci_conf_print_aer_cap_uc(reg);
                   2670:        reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)];
                   2671:        printf("    Uncorrectable Error Severity register: 0x%08x\n", reg);
                   2672:        pci_conf_print_aer_cap_uc(reg);
                   2673:
                   2674:        reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)];
                   2675:        printf("    Correctable Error Status register: 0x%08x\n", reg);
                   2676:        pci_conf_print_aer_cap_cor(reg);
                   2677:        reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)];
                   2678:        printf("    Correctable Error Mask register: 0x%08x\n", reg);
                   2679:        pci_conf_print_aer_cap_cor(reg);
                   2680:
                   2681:        reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)];
                   2682:        printf("    Advanced Error Capabilities and Control register: 0x%08x\n",
                   2683:            reg);
                   2684:        pci_conf_print_aer_cap_control(reg, &tlp_prefix_log);
                   2685:        reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)];
                   2686:        printf("    Header Log register:\n");
                   2687:        pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG,
                   2688:            extcapoff + PCI_AER_ROOTERR_CMD);
                   2689:
                   2690:        switch (pcie_devtype) {
                   2691:        case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
                   2692:        case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
                   2693:                reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
                   2694:                printf("    Root Error Command register: 0x%08x\n", reg);
                   2695:                pci_conf_print_aer_cap_rooterr_cmd(reg);
                   2696:                reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)];
                   2697:                printf("    Root Error Status register: 0x%08x\n", reg);
                   2698:                pci_conf_print_aer_cap_rooterr_status(reg);
                   2699:
                   2700:                reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)];
1.183.2.3  martin   2701:                printf("    Error Source Identification register: 0x%08x\n",
                   2702:                    reg);
1.135     msaitoh  2703:                pci_conf_print_aer_cap_errsrc_id(reg);
                   2704:                break;
                   2705:        }
                   2706:
                   2707:        if (tlp_prefix_log) {
                   2708:                reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)];
                   2709:                printf("    TLP Prefix Log register: 0x%08x\n", reg);
                   2710:        }
                   2711: }
                   2712:
                   2713: static void
                   2714: pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
                   2715:     pcireg_t parbsel, int parbsize)
                   2716: {
                   2717:        pcireg_t reg;
                   2718:        int num = 16 << parbsel;
                   2719:        int num_per_reg = sizeof(pcireg_t) / parbsize;
                   2720:        int i, j;
                   2721:
                   2722:        /* First, dump the table */
                   2723:        for (i = 0; i < num; i += num_per_reg) {
                   2724:                reg = regs[o2i(off + i / num_per_reg)];
                   2725:                printf("    %s Arbitration Table: 0x%08x\n", name, reg);
                   2726:        }
                   2727:        /* And then, decode each entry */
                   2728:        for (i = 0; i < num; i += num_per_reg) {
                   2729:                reg = regs[o2i(off + i / num_per_reg)];
                   2730:                for (j = 0; j < num_per_reg; j++)
                   2731:                        printf("      Phase[%d]: %d\n", j, reg);
                   2732:        }
                   2733: }
                   2734:
                   2735: static void
1.183.2.4  snj      2736: pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  2737: {
                   2738:        pcireg_t reg, n;
                   2739:        int parbtab, parbsize;
                   2740:        pcireg_t parbsel;
                   2741:        int varbtab, varbsize;
                   2742:        pcireg_t varbsel;
                   2743:        int i, count;
                   2744:
                   2745:        printf("\n  Virtual Channel Register\n");
                   2746:        reg = regs[o2i(extcapoff + PCI_VC_CAP1)];
                   2747:        printf("    Port VC Capability register 1: 0x%08x\n", reg);
                   2748:        count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT);
                   2749:        printf("      Extended VC Count: %d\n", count);
                   2750:        n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT);
                   2751:        printf("      Low Priority Extended VC Count: %u\n", n);
                   2752:        n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK);
                   2753:        printf("      Reference Clock: %s\n",
1.140     msaitoh  2754:            (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown");
1.135     msaitoh  2755:        parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE);
                   2756:        printf("      Port Arbitration Table Entry Size: %dbit\n", parbsize);
                   2757:
                   2758:        reg = regs[o2i(extcapoff + PCI_VC_CAP2)];
                   2759:        printf("    Port VC Capability register 2: 0x%08x\n", reg);
                   2760:        onoff("Hardware fixed arbitration scheme",
                   2761:            reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME);
                   2762:        onoff("WRR arbitration with 32 phases",
                   2763:            reg, PCI_VC_CAP2_ARB_CAP_WRR_32);
                   2764:        onoff("WRR arbitration with 64 phases",
                   2765:            reg, PCI_VC_CAP2_ARB_CAP_WRR_64);
                   2766:        onoff("WRR arbitration with 128 phases",
                   2767:            reg, PCI_VC_CAP2_ARB_CAP_WRR_128);
                   2768:        varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
                   2769:        printf("      VC Arbitration Table Offset: 0x%x\n", varbtab);
                   2770:
                   2771:        reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;
                   2772:        printf("    Port VC Control register: 0x%04x\n", reg);
                   2773:        varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
                   2774:        printf("      VC Arbitration Select: 0x%x\n", varbsel);
                   2775:
                   2776:        reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;
                   2777:        printf("    Port VC Status register: 0x%04x\n", reg);
                   2778:        onoff("VC Arbitration Table Status",
                   2779:            reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);
                   2780:
                   2781:        for (i = 0; i < count + 1; i++) {
                   2782:                reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];
                   2783:                printf("    VC number %d\n", i);
                   2784:                printf("      VC Resource Capability Register: 0x%08x\n", reg);
                   2785:                onoff("  Non-configurable Hardware fixed arbitration scheme",
                   2786:                    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME);
                   2787:                onoff("  WRR arbitration with 32 phases",
                   2788:                    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32);
                   2789:                onoff("  WRR arbitration with 64 phases",
                   2790:                    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64);
                   2791:                onoff("  WRR arbitration with 128 phases",
                   2792:                    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128);
                   2793:                onoff("  Time-based WRR arbitration with 128 phases",
                   2794:                    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128);
                   2795:                onoff("  WRR arbitration with 256 phases",
                   2796:                    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256);
                   2797:                onoff("  Advanced Packet Switching",
                   2798:                    reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH);
                   2799:                onoff("  Reject Snoop Transaction",
                   2800:                    reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);
                   2801:                n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;
                   2802:                printf("        Maximum Time Slots: %d\n", n);
                   2803:                parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S;
                   2804:                printf("        Port Arbitration Table offset: 0x%02x\n",
                   2805:                    parbtab);
                   2806:
                   2807:                reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];
                   2808:                printf("      VC Resource Control Register: 0x%08x\n", reg);
1.157     msaitoh  2809:                printf("        TC/VC Map: 0x%02x\n",
1.135     msaitoh  2810:                    (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP));
                   2811:                /*
                   2812:                 * The load Port Arbitration Table bit is used to update
                   2813:                 * the Port Arbitration logic and it's always 0 on read, so
                   2814:                 * we don't print it.
                   2815:                 */
                   2816:                parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
1.157     msaitoh  2817:                printf("        Port Arbitration Select: 0x%x\n", parbsel);
1.135     msaitoh  2818:                n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);
1.174     msaitoh  2819:                printf("        VC ID: %d\n", n);
1.135     msaitoh  2820:                onoff("  VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
                   2821:
                   2822:                reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16;
                   2823:                printf("      VC Resource Status Register: 0x%08x\n", reg);
                   2824:                onoff("  Port Arbitration Table Status",
                   2825:                    reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE);
                   2826:                onoff("  VC Negotiation Pending",
                   2827:                    reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);
                   2828:
                   2829:                if ((parbtab != 0) && (parbsel != 0))
                   2830:                        pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab,
                   2831:                            "Port", parbsel, parbsize);
                   2832:        }
                   2833:
                   2834:        varbsize = 8;
                   2835:        if ((varbtab != 0) && (varbsel != 0))
                   2836:                pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab,
                   2837:                    "  VC", varbsel, varbsize);
                   2838: }
                   2839:
1.181     msaitoh  2840: /*
                   2841:  * Print Power limit. This encoding is the same among the following registers:
                   2842:  *  - The Captured Slot Power Limit in the PCIe Device Capability Register.
                   2843:  *  - The Slot Power Limit in the PCIe Slot Capability Register.
                   2844:  *  - The Base Power in the Data register of Power Budgeting capability.
                   2845:  */
1.160     msaitoh  2846: static void
1.181     msaitoh  2847: pci_conf_print_pcie_power(uint8_t base, unsigned int scale)
1.135     msaitoh  2848: {
1.181     msaitoh  2849:        unsigned int sdiv = 1;
1.162     christos 2850:
1.181     msaitoh  2851:        if ((scale == 0) && (base > 0xef)) {
                   2852:                const char *s;
1.162     christos 2853:
1.181     msaitoh  2854:                switch (base) {
                   2855:                case 0xf0:
                   2856:                        s = "239W < x <= 250W";
                   2857:                        break;
                   2858:                case 0xf1:
                   2859:                        s = "250W < x <= 275W";
                   2860:                        break;
                   2861:                case 0xf2:
                   2862:                        s = "275W < x <= 300W";
                   2863:                        break;
                   2864:                default:
1.183.2.4  snj      2865:                        s = "reserved for greater than 300W";
1.181     msaitoh  2866:                        break;
1.160     msaitoh  2867:                }
1.181     msaitoh  2868:                printf("%s\n", s);
1.183.2.1  martin   2869:                return;
1.160     msaitoh  2870:        }
1.162     christos 2871:
1.181     msaitoh  2872:        for (unsigned int i = scale; i > 0; i--)
                   2873:                sdiv *= 10;
                   2874:
                   2875:        printf("%u", base / sdiv);
1.162     christos 2876:
1.181     msaitoh  2877:        if (scale != 0) {
                   2878:                printf(".%u", base % sdiv);
1.135     msaitoh  2879:        }
1.181     msaitoh  2880:        printf ("W\n");
                   2881:        return;
1.135     msaitoh  2882: }
                   2883:
                   2884: static const char *
                   2885: pci_conf_print_pwrbdgt_type(uint8_t reg)
                   2886: {
                   2887:
                   2888:        switch (reg) {
                   2889:        case 0x00:
                   2890:                return "PME Aux";
                   2891:        case 0x01:
                   2892:                return "Auxilary";
                   2893:        case 0x02:
                   2894:                return "Idle";
                   2895:        case 0x03:
                   2896:                return "Sustained";
1.152     msaitoh  2897:        case 0x04:
                   2898:                return "Sustained (Emergency Power Reduction)";
                   2899:        case 0x05:
                   2900:                return "Maximum (Emergency Power Reduction)";
1.135     msaitoh  2901:        case 0x07:
1.160     msaitoh  2902:                return "Maximum";
1.135     msaitoh  2903:        default:
                   2904:                return "Unknown";
                   2905:        }
                   2906: }
                   2907:
                   2908: static const char *
                   2909: pci_conf_print_pwrbdgt_pwrrail(uint8_t reg)
                   2910: {
                   2911:
                   2912:        switch (reg) {
                   2913:        case 0x00:
                   2914:                return "Power(12V)";
                   2915:        case 0x01:
                   2916:                return "Power(3.3V)";
                   2917:        case 0x02:
                   2918:                return "Power(1.5V or 1.8V)";
                   2919:        case 0x07:
                   2920:                return "Thermal";
                   2921:        default:
                   2922:                return "Unknown";
                   2923:        }
                   2924: }
                   2925:
                   2926: static void
1.183.2.4  snj      2927: pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  2928: {
                   2929:        pcireg_t reg;
                   2930:
1.160     msaitoh  2931:        printf("\n  Power Budgeting\n");
1.135     msaitoh  2932:
                   2933:        reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)];
                   2934:        printf("    Data Select register: 0x%08x\n", reg);
                   2935:
                   2936:        reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)];
                   2937:        printf("    Data register: 0x%08x\n", reg);
1.160     msaitoh  2938:        printf("      Base Power: ");
1.181     msaitoh  2939:        pci_conf_print_pcie_power(
                   2940:            __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR),
                   2941:            __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE));
1.135     msaitoh  2942:        printf("      PM Sub State: 0x%hhx\n",
                   2943:            (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT));
                   2944:        printf("      PM State: D%u\n",
                   2945:            (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT));
                   2946:        printf("      Type: %s\n",
                   2947:            pci_conf_print_pwrbdgt_type(
                   2948:                    (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE))));
                   2949:        printf("      Power Rail: %s\n",
                   2950:            pci_conf_print_pwrbdgt_pwrrail(
                   2951:                    (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL))));
                   2952:
                   2953:        reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)];
                   2954:        printf("    Power Budget Capability register: 0x%08x\n", reg);
                   2955:        onoff("System Allocated",
                   2956:            reg, PCI_PWRBDGT_CAP_SYSALLOC);
                   2957: }
                   2958:
                   2959: static const char *
                   2960: pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type)
                   2961: {
                   2962:
                   2963:        switch (type) {
                   2964:        case 0x00:
                   2965:                return "Configuration Space Element";
                   2966:        case 0x01:
                   2967:                return "System Egress Port or internal sink (memory)";
                   2968:        case 0x02:
                   2969:                return "Internal Root Complex Link";
                   2970:        default:
                   2971:                return "Unknown";
                   2972:        }
                   2973: }
                   2974:
                   2975: static void
1.183.2.4  snj      2976: pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  2977: {
                   2978:        pcireg_t reg;
                   2979:        unsigned char nent, linktype;
                   2980:        int i;
                   2981:
                   2982:        printf("\n  Root Complex Link Declaration\n");
                   2983:
                   2984:        reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)];
                   2985:        printf("    Element Self Description Register: 0x%08x\n", reg);
                   2986:        printf("      Element Type: %s\n",
                   2987:            pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg));
                   2988:        nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT);
                   2989:        printf("      Number of Link Entries: %hhu\n", nent);
                   2990:        printf("      Component ID: %hhu\n",
                   2991:            (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID));
                   2992:        printf("      Port Number: %hhu\n",
                   2993:            (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM));
                   2994:        for (i = 0; i < nent; i++) {
                   2995:                reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))];
1.140     msaitoh  2996:                printf("    Link Entry %d:\n", i + 1);
                   2997:                printf("      Link Description Register: 0x%08x\n", reg);
                   2998:                onoff("  Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID);
1.135     msaitoh  2999:                linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE;
1.140     msaitoh  3000:                onoff2("  Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE,
1.135     msaitoh  3001:                    "Configuration Space", "Memory-Mapped Space");
1.140     msaitoh  3002:                onoff("  Associated RCRB Header", reg,
1.135     msaitoh  3003:                    PCI_RCLINK_DCL_LINKDESC_ARCRBH);
1.140     msaitoh  3004:                printf("        Target Component ID: %hhu\n",
1.135     msaitoh  3005:                    (unsigned char)__SHIFTOUT(reg,
                   3006:                        PCI_RCLINK_DCL_LINKDESC_TCOMPID));
1.140     msaitoh  3007:                printf("        Target Port Number: %hhu\n",
1.135     msaitoh  3008:                    (unsigned char)__SHIFTOUT(reg,
                   3009:                        PCI_RCLINK_DCL_LINKDESC_TPNUM));
                   3010:
                   3011:                if (linktype == 0) {
                   3012:                        /* Memory-Mapped Space */
                   3013:                        reg = regs[o2i(extcapoff
                   3014:                                    + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))];
1.140     msaitoh  3015:                        printf("      Link Address Low Register: 0x%08x\n",
                   3016:                            reg);
1.135     msaitoh  3017:                        reg = regs[o2i(extcapoff
                   3018:                                    + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))];
1.140     msaitoh  3019:                        printf("      Link Address High Register: 0x%08x\n",
                   3020:                            reg);
1.135     msaitoh  3021:                } else {
                   3022:                        unsigned int nb;
                   3023:                        pcireg_t lo, hi;
                   3024:
                   3025:                        /* Configuration Space */
                   3026:                        lo = regs[o2i(extcapoff
                   3027:                                    + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))];
1.140     msaitoh  3028:                        printf("      Configuration Space Low Register: "
                   3029:                            "0x%08x\n", lo);
1.135     msaitoh  3030:                        hi = regs[o2i(extcapoff
                   3031:                                    + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))];
1.140     msaitoh  3032:                        printf("      Configuration Space High Register: "
                   3033:                            "0x%08x\n", hi);
1.135     msaitoh  3034:                        nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N);
1.140     msaitoh  3035:                        printf("        N: %u\n", nb);
                   3036:                        printf("        Func: %hhu\n",
1.135     msaitoh  3037:                            (unsigned char)__SHIFTOUT(lo,
                   3038:                                PCI_RCLINK_DCL_LINKADDR_LT1_FUNC));
1.140     msaitoh  3039:                        printf("        Dev: %hhu\n",
1.135     msaitoh  3040:                            (unsigned char)__SHIFTOUT(lo,
                   3041:                                PCI_RCLINK_DCL_LINKADDR_LT1_DEV));
1.140     msaitoh  3042:                        printf("        Bus: %hhu\n",
1.135     msaitoh  3043:                            (unsigned char)__SHIFTOUT(lo,
                   3044:                                PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb)));
                   3045:                        lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i);
1.140     msaitoh  3046:                        printf("        Configuration Space Base Address: "
                   3047:                            "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo);
1.135     msaitoh  3048:                }
                   3049:        }
                   3050: }
                   3051:
                   3052: /* XXX pci_conf_print_rclink_ctl_cap */
                   3053:
                   3054: static void
1.183.2.4  snj      3055: pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3056: {
                   3057:        pcireg_t reg;
                   3058:
                   3059:        printf("\n  Root Complex Event Collector Association\n");
                   3060:
                   3061:        reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)];
                   3062:        printf("    Association Bitmap for Root Complex Integrated Devices:"
                   3063:            " 0x%08x\n", reg);
1.183.2.8! sborrill 3064:
        !          3065:        if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) {
        !          3066:                reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)];
        !          3067:                printf("    RCEC Associated Bus Numbers register: 0x%08x\n",
        !          3068:                    reg);
        !          3069:                printf("      RCEC Next Bus: %u\n",
        !          3070:                    (unsigned int)__SHIFTOUT(reg,
        !          3071:                        PCI_RCEC_ASSOCBUSNUM_RCECNEXT));
        !          3072:                printf("      RCEC Last Bus: %u\n",
        !          3073:                    (unsigned int)__SHIFTOUT(reg,
        !          3074:                        PCI_RCEC_ASSOCBUSNUM_RCECLAST));
        !          3075:        }
1.135     msaitoh  3076: }
                   3077:
                   3078: /* XXX pci_conf_print_mfvc_cap */
                   3079: /* XXX pci_conf_print_vc2_cap */
                   3080: /* XXX pci_conf_print_rcrb_cap */
                   3081: /* XXX pci_conf_print_vendor_cap */
                   3082: /* XXX pci_conf_print_cac_cap */
                   3083:
                   3084: static void
1.183.2.4  snj      3085: pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3086: {
                   3087:        pcireg_t reg, cap, ctl;
                   3088:        unsigned int size, i;
                   3089:
                   3090:        printf("\n  Access Control Services\n");
                   3091:
                   3092:        reg = regs[o2i(extcapoff + PCI_ACS_CAP)];
                   3093:        cap = reg & 0xffff;
                   3094:        ctl = reg >> 16;
                   3095:        printf("    ACS Capability register: 0x%08x\n", cap);
                   3096:        onoff("ACS Source Validation", cap, PCI_ACS_CAP_V);
                   3097:        onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B);
                   3098:        onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R);
                   3099:        onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C);
                   3100:        onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U);
                   3101:        onoff("ACS Egress Control", cap, PCI_ACS_CAP_E);
                   3102:        onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T);
                   3103:        size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE);
                   3104:        if (size == 0)
                   3105:                size = 256;
                   3106:        printf("      Egress Control Vector Size: %u\n", size);
                   3107:        printf("    ACS Control register: 0x%08x\n", ctl);
                   3108:        onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V);
                   3109:        onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B);
                   3110:        onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R);
                   3111:        onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C);
                   3112:        onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U);
                   3113:        onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E);
                   3114:        onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T);
                   3115:
                   3116:        /*
                   3117:         * If the P2P Egress Control Capability bit is 0, ignore the Egress
                   3118:         * Control vector.
                   3119:         */
                   3120:        if ((cap & PCI_ACS_CAP_E) == 0)
                   3121:                return;
                   3122:        for (i = 0; i < size; i += 32)
1.157     msaitoh  3123:                printf("    Egress Control Vector [%u..%u]: 0x%08x\n", i + 31,
1.135     msaitoh  3124:                    i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]);
                   3125: }
                   3126:
                   3127: static void
1.183.2.4  snj      3128: pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3129: {
                   3130:        pcireg_t reg, cap, ctl;
                   3131:
                   3132:        printf("\n  Alternative Routing-ID Interpretation Register\n");
                   3133:
                   3134:        reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
                   3135:        cap = reg & 0xffff;
                   3136:        ctl = reg >> 16;
                   3137:        printf("    Capability register: 0x%08x\n", cap);
                   3138:        onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M);
                   3139:        onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A);
                   3140:        printf("      Next Function Number: %u\n",
                   3141:            (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN));
                   3142:        printf("    Control register: 0x%08x\n", ctl);
                   3143:        onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M);
                   3144:        onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A);
                   3145:        printf("      Function Group: %u\n",
                   3146:            (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP));
                   3147: }
                   3148:
                   3149: static void
1.183.2.4  snj      3150: pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3151: {
                   3152:        pcireg_t reg, cap, ctl;
                   3153:        unsigned int num;
                   3154:
                   3155:        printf("\n  Address Translation Services\n");
                   3156:
                   3157:        reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
                   3158:        cap = reg & 0xffff;
                   3159:        ctl = reg >> 16;
                   3160:        printf("    Capability register: 0x%04x\n", cap);
                   3161:        num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH);
                   3162:        if (num == 0)
                   3163:                num = 32;
                   3164:        printf("      Invalidate Queue Depth: %u\n", num);
                   3165:        onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ);
1.145     msaitoh  3166:        onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL);
1.183.2.7  martin   3167:        onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD);
1.135     msaitoh  3168:
                   3169:        printf("    Control register: 0x%04x\n", ctl);
                   3170:        printf("      Smallest Translation Unit: %u\n",
                   3171:            (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU));
                   3172:        onoff("Enable", reg, PCI_ATS_CTL_EN);
                   3173: }
                   3174:
                   3175: static void
1.183.2.4  snj      3176: pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3177: {
                   3178:        pcireg_t lo, hi;
                   3179:
                   3180:        printf("\n  Device Serial Number Register\n");
                   3181:
                   3182:        lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)];
                   3183:        hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)];
                   3184:        printf("    Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
                   3185:            hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff,
                   3186:            lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff);
                   3187: }
                   3188:
                   3189: static void
1.183.2.4  snj      3190: pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3191: {
                   3192:        char buf[sizeof("99999 MB")];
                   3193:        pcireg_t reg;
                   3194:        pcireg_t total_vfs;
                   3195:        int i;
                   3196:        bool first;
                   3197:
                   3198:        printf("\n  Single Root IO Virtualization Register\n");
                   3199:
                   3200:        reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)];
                   3201:        printf("    Capabilities register: 0x%08x\n", reg);
                   3202:        onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION);
                   3203:        onoff("ARI Capable Hierarchy Preserved", reg,
                   3204:            PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED);
                   3205:        if (reg & PCI_SRIOV_CAP_VF_MIGRATION) {
1.158     msaitoh  3206:                printf("      VF Migration Interrupt Message Number: 0x%03x\n",
1.135     msaitoh  3207:                    (pcireg_t)__SHIFTOUT(reg,
                   3208:                      PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N));
                   3209:        }
                   3210:
                   3211:        reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff;
                   3212:        printf("    Control register: 0x%04x\n", reg);
                   3213:        onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE);
                   3214:        onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT);
                   3215:        onoff("VF Migration Interrupt Enable", reg,
                   3216:            PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE);
                   3217:        onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE);
                   3218:        onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER);
                   3219:
                   3220:        reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16;
                   3221:        printf("    Status register: 0x%04x\n", reg);
                   3222:        onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION);
                   3223:
                   3224:        reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff;
                   3225:        printf("    InitialVFs register: 0x%04x\n", reg);
                   3226:        total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16;
                   3227:        printf("    TotalVFs register: 0x%04x\n", reg);
                   3228:        reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff;
                   3229:        printf("    NumVFs register: 0x%04x\n", reg);
                   3230:
                   3231:        reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16;
                   3232:        printf("    Function Dependency Link register: 0x%04x\n", reg);
                   3233:
                   3234:        reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff;
                   3235:        printf("    First VF Offset register: 0x%04x\n", reg);
                   3236:        reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16;
                   3237:        printf("    VF Stride register: 0x%04x\n", reg);
1.157     msaitoh  3238:        reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16;
                   3239:        printf("    Device ID: 0x%04x\n", reg);
1.135     msaitoh  3240:
                   3241:        reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)];
                   3242:        printf("    Supported Page Sizes register: 0x%08x\n", reg);
                   3243:        printf("      Supported Page Size:");
                   3244:        for (i = 0, first = true; i < 32; i++) {
                   3245:                if (reg & __BIT(i)) {
                   3246: #ifdef _KERNEL
                   3247:                        format_bytes(buf, sizeof(buf), 1LL << (i + 12));
                   3248: #else
                   3249:                        humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B",
                   3250:                            HN_AUTOSCALE, 0);
                   3251: #endif
                   3252:                        printf("%s %s", first ? "" : ",", buf);
                   3253:                        first = false;
                   3254:                }
                   3255:        }
                   3256:        printf("\n");
                   3257:
                   3258:        reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)];
                   3259:        printf("    System Page Sizes register: 0x%08x\n", reg);
                   3260:        printf("      Page Size: ");
                   3261:        if (reg != 0) {
1.171     msaitoh  3262:                int bitpos = ffs(reg) -1;
                   3263:
                   3264:                /* Assume only one bit is set. */
1.135     msaitoh  3265: #ifdef _KERNEL
1.171     msaitoh  3266:                format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12));
1.135     msaitoh  3267: #else
1.171     msaitoh  3268:                humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12),
                   3269:                    "B", HN_AUTOSCALE, 0);
1.135     msaitoh  3270: #endif
                   3271:                printf("%s", buf);
                   3272:        } else {
                   3273:                printf("unknown");
                   3274:        }
                   3275:        printf("\n");
                   3276:
                   3277:        for (i = 0; i < 6; i++) {
                   3278:                reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))];
                   3279:                printf("    VF BAR%d register: 0x%08x\n", i, reg);
                   3280:        }
                   3281:
                   3282:        if (total_vfs > 0) {
                   3283:                reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)];
                   3284:                printf("    VF Migration State Array Offset register: 0x%08x\n",
                   3285:                    reg);
                   3286:                printf("      VF Migration State Offset: 0x%08x\n",
                   3287:                    (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET));
                   3288:                i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR);
                   3289:                printf("      VF Migration State BIR: ");
                   3290:                if (i >= 0 && i <= 5) {
                   3291:                        printf("BAR%d", i);
                   3292:                } else {
                   3293:                        printf("unknown BAR (%d)", i);
                   3294:                }
                   3295:                printf("\n");
                   3296:        }
                   3297: }
                   3298:
                   3299: /* XXX pci_conf_print_mriov_cap */
1.138     msaitoh  3300:
                   3301: static void
1.183.2.4  snj      3302: pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff)
1.138     msaitoh  3303: {
                   3304:        pcireg_t reg, cap, ctl;
                   3305:        pcireg_t regl, regh;
                   3306:        uint64_t addr;
                   3307:        int n;
                   3308:
                   3309:        printf("\n  Multicast\n");
                   3310:
                   3311:        reg = regs[o2i(extcapoff + PCI_MCAST_CTL)];
                   3312:        cap = reg & 0xffff;
                   3313:        ctl = reg >> 16;
                   3314:        printf("    Capability Register: 0x%04x\n", cap);
1.139     msaitoh  3315:        printf("      Max Group: %u\n",
                   3316:            (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1);
1.138     msaitoh  3317:
                   3318:        /* Endpoint Only */
                   3319:        n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ);
                   3320:        if (n > 0)
                   3321:                printf("      Windw Size Requested: %d\n", 1 << (n - 1));
                   3322:
                   3323:        onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN);
                   3324:
                   3325:        printf("    Control Register: 0x%04x\n", ctl);
1.139     msaitoh  3326:        printf("      Num Group: %u\n",
                   3327:            (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1);
1.138     msaitoh  3328:        onoff("Enable", reg, PCI_MCAST_CTL_ENA);
                   3329:
                   3330:        regl = regs[o2i(extcapoff + PCI_MCAST_BARL)];
                   3331:        regh = regs[o2i(extcapoff + PCI_MCAST_BARH)];
                   3332:        printf("    Base Address Register 0: 0x%08x\n", regl);
                   3333:        printf("    Base Address Register 1: 0x%08x\n", regh);
1.139     msaitoh  3334:        printf("      Index Position: %u\n",
                   3335:            (unsigned int)(regl & PCI_MCAST_BARL_INDPOS));
1.138     msaitoh  3336:        addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR);
                   3337:        printf("      Base Address: 0x%016" PRIx64 "\n", addr);
                   3338:
                   3339:        regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)];
                   3340:        regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)];
                   3341:        printf("    Receive Register 0: 0x%08x\n", regl);
                   3342:        printf("    Receive Register 1: 0x%08x\n", regh);
                   3343:
                   3344:        regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)];
                   3345:        regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)];
                   3346:        printf("    Block All Register 0: 0x%08x\n", regl);
                   3347:        printf("    Block All Register 1: 0x%08x\n", regh);
                   3348:
                   3349:        regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)];
                   3350:        regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)];
                   3351:        printf("    Block Untranslated Register 0: 0x%08x\n", regl);
                   3352:        printf("    Block Untranslated Register 1: 0x%08x\n", regh);
                   3353:
                   3354:        regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)];
                   3355:        regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)];
                   3356:        printf("    Overlay BAR 0: 0x%08x\n", regl);
                   3357:        printf("    Overlay BAR 1: 0x%08x\n", regh);
                   3358:
                   3359:        n = regl & PCI_MCAST_OVERLAYL_SIZE;
                   3360:        printf("      Overlay Size: ");
                   3361:        if (n >= 6)
                   3362:                printf("%d\n", n);
                   3363:        else
                   3364:                printf("off\n");
                   3365:        addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR);
                   3366:        printf("      Overlay BAR: 0x%016" PRIx64 "\n", addr);
                   3367: }
1.135     msaitoh  3368:
                   3369: static void
1.183.2.4  snj      3370: pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3371: {
                   3372:        pcireg_t reg, ctl, sta;
                   3373:
                   3374:        printf("\n  Page Request\n");
                   3375:
                   3376:        reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)];
                   3377:        ctl = reg & 0xffff;
                   3378:        sta = reg >> 16;
                   3379:        printf("    Control Register: 0x%04x\n", ctl);
                   3380:        onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E);
                   3381:        onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);
                   3382:
                   3383:        printf("    Status Register: 0x%04x\n", sta);
                   3384:        onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF);
                   3385:        onoff("Unexpected Page Request Group Index", reg,
                   3386:            PCI_PAGE_REQ_STA_UPRGI);
                   3387:        onoff("Stopped", reg, PCI_PAGE_REQ_STA_S);
1.145     msaitoh  3388:        onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR);
1.135     msaitoh  3389:
                   3390:        reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)];
                   3391:        printf("    Outstanding Page Request Capacity: %u\n", reg);
                   3392:        reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)];
                   3393:        printf("    Outstanding Page Request Allocation: %u\n", reg);
                   3394: }
                   3395:
                   3396: /* XXX pci_conf_print_amd_cap */
1.153     msaitoh  3397:
                   3398: #define MEM_PBUFSIZE   sizeof("999GB")
                   3399:
                   3400: static void
1.183.2.4  snj      3401: pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff)
1.153     msaitoh  3402: {
                   3403:        pcireg_t cap, ctl;
                   3404:        unsigned int bars, i, n;
                   3405:        char pbuf[MEM_PBUFSIZE];
                   3406:
                   3407:        printf("\n  Resizable BAR\n");
                   3408:
                   3409:        /* Get Number of Resizable BARs */
                   3410:        ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))];
                   3411:        bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR);
                   3412:        printf("    Number of Resizable BARs: ");
                   3413:        if (bars <= 6)
                   3414:                printf("%u\n", bars);
                   3415:        else {
                   3416:                printf("incorrect (%u)\n", bars);
                   3417:                return;
                   3418:        }
                   3419:
                   3420:        for (n = 0; n < 6; n++) {
                   3421:                cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))];
                   3422:                printf("    Capability register(%u): 0x%08x\n", n, cap);
                   3423:                if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0)
                   3424:                        continue; /* Not Used */
                   3425:                printf("      Acceptable BAR sizes:");
                   3426:                for (i = 4; i <= 23; i++) {
                   3427:                        if ((cap & (1 << i)) != 0) {
                   3428:                                humanize_number(pbuf, MEM_PBUFSIZE,
                   3429:                                    (int64_t)1024 * 1024 << (i - 4), "B",
1.154     martin   3430: #ifdef _KERNEL
                   3431:                                    1);
                   3432: #else
1.153     msaitoh  3433:                                    HN_AUTOSCALE, HN_NOSPACE);
1.154     martin   3434: #endif
1.153     msaitoh  3435:                                printf(" %s", pbuf);
                   3436:                        }
                   3437:                }
                   3438:                printf("\n");
                   3439:
                   3440:                ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))];
                   3441:                printf("    Control register(%u): 0x%08x\n", n, ctl);
                   3442:                printf("      BAR Index: %u\n",
                   3443:                    (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX));
                   3444:                humanize_number(pbuf, MEM_PBUFSIZE,
                   3445:                    (int64_t)1024 * 1024
                   3446:                    << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ),
1.154     martin   3447:                    "B",
                   3448: #ifdef _KERNEL
                   3449:                    1);
                   3450: #else
                   3451:                    HN_AUTOSCALE, HN_NOSPACE);
                   3452: #endif
1.153     msaitoh  3453:                printf("      BAR Size: %s\n", pbuf);
                   3454:        }
                   3455: }
1.149     msaitoh  3456:
                   3457: static void
1.183.2.4  snj      3458: pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff)
1.149     msaitoh  3459: {
                   3460:        pcireg_t reg;
                   3461:        unsigned int substmax, i;
                   3462:
                   3463:        printf("\n  Dynamic Power Allocation\n");
                   3464:
                   3465:        reg = regs[o2i(extcapoff + PCI_DPA_CAP)];
                   3466:        printf("    Capability register: 0x%08x\n", reg);
                   3467:        substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX);
                   3468:        printf("      Substate Max: %u\n", substmax);
                   3469:        printf("      Transition Latency Unit: ");
                   3470:        switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) {
                   3471:        case 0:
                   3472:                printf("1ms\n");
                   3473:                break;
                   3474:        case 1:
                   3475:                printf("10ms\n");
                   3476:                break;
                   3477:        case 2:
                   3478:                printf("100ms\n");
                   3479:                break;
                   3480:        default:
                   3481:                printf("reserved\n");
                   3482:                break;
                   3483:        }
                   3484:        printf("      Power Allocation Scale: ");
                   3485:        switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) {
                   3486:        case 0:
                   3487:                printf("10.0x\n");
                   3488:                break;
                   3489:        case 1:
                   3490:                printf("1.0x\n");
                   3491:                break;
                   3492:        case 2:
                   3493:                printf("0.1x\n");
                   3494:                break;
                   3495:        case 3:
                   3496:                printf("0.01x\n");
                   3497:                break;
                   3498:        }
                   3499:        printf("      Transition Latency Value 0: %u\n",
                   3500:            (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0));
                   3501:        printf("      Transition Latency Value 1: %u\n",
                   3502:            (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1));
                   3503:
                   3504:        reg = regs[o2i(extcapoff + PCI_DPA_LATIND)];
                   3505:        printf("    Latency Indicatior register: 0x%08x\n", reg);
                   3506:
                   3507:        reg = regs[o2i(extcapoff + PCI_DPA_CS)];
                   3508:        printf("    Status register: 0x%04x\n", reg & 0xffff);
1.157     msaitoh  3509:        printf("      Substate Status: 0x%02x\n",
1.149     msaitoh  3510:            (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT));
                   3511:        onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN);
                   3512:        printf("    Control register: 0x%04x\n", reg >> 16);
1.157     msaitoh  3513:        printf("      Substate Control: 0x%02x\n",
1.149     msaitoh  3514:            (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL));
                   3515:
                   3516:        for (i = 0; i <= substmax; i++)
                   3517:                printf("    Substate Power Allocation register %d: 0x%02x\n",
                   3518:                    i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff));
                   3519: }
1.135     msaitoh  3520:
                   3521: static const char *
1.183.2.2  martin   3522: pci_conf_print_tph_req_cap_sttabloc(uint8_t val)
1.135     msaitoh  3523: {
                   3524:
                   3525:        switch (val) {
1.183.2.2  martin   3526:        case PCI_TPH_REQ_STTBLLOC_NONE:
1.135     msaitoh  3527:                return "Not Present";
1.183.2.2  martin   3528:        case PCI_TPH_REQ_STTBLLOC_TPHREQ:
1.135     msaitoh  3529:                return "in the TPH Requester Capability Structure";
1.183.2.2  martin   3530:        case PCI_TPH_REQ_STTBLLOC_MSIX:
1.135     msaitoh  3531:                return "in the MSI-X Table";
                   3532:        default:
                   3533:                return "Unknown";
                   3534:        }
                   3535: }
                   3536:
                   3537: static void
1.183.2.4  snj      3538: pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3539: {
                   3540:        pcireg_t reg;
1.183.2.8! sborrill 3541:        int size = 0, i, j;
1.183.2.2  martin   3542:        uint8_t sttbloc;
1.135     msaitoh  3543:
                   3544:        printf("\n  TPH Requester Extended Capability\n");
                   3545:
                   3546:        reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)];
                   3547:        printf("    TPH Requester Capabililty register: 0x%08x\n", reg);
                   3548:        onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);
                   3549:        onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
                   3550:        onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
                   3551:        onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
1.183.2.2  martin   3552:        sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC);
1.135     msaitoh  3553:        printf("      ST Table Location: %s\n",
1.183.2.2  martin   3554:            pci_conf_print_tph_req_cap_sttabloc(sttbloc));
1.183.2.8! sborrill 3555:        if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) {
        !          3556:                size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1;
        !          3557:                printf("      ST Table Size: %d\n", size);
        !          3558:        }
1.182     msaitoh  3559:
                   3560:        reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)];
                   3561:        printf("    TPH Requester Control register: 0x%08x\n", reg);
                   3562:        printf("      ST Mode Select: ");
                   3563:        switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) {
                   3564:        case PCI_TPH_REQ_CTL_STSEL_NO:
                   3565:                printf("No ST Mode\n");
                   3566:                break;
                   3567:        case PCI_TPH_REQ_CTL_STSEL_IV:
                   3568:                printf("Interrupt Vector Mode\n");
                   3569:                break;
                   3570:        case PCI_TPH_REQ_CTL_STSEL_DS:
                   3571:                printf("Device Specific Mode\n");
                   3572:                break;
                   3573:        default:
                   3574:                printf("(reserved vaule)\n");
                   3575:                break;
                   3576:        }
                   3577:        printf("      TPH Requester Enable: ");
                   3578:        switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) {
                   3579:        case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */
                   3580:                printf("Not permitted\n");
                   3581:                break;
                   3582:        case PCI_TPH_REQ_CTL_TPHREQEN_TPH:
                   3583:                printf("TPH and not Extended TPH\n");
                   3584:                break;
                   3585:        case PCI_TPH_REQ_CTL_TPHREQEN_ETPH:
                   3586:                printf("TPH and Extended TPH");
                   3587:                break;
                   3588:        default:
                   3589:                printf("(reserved vaule)\n");
                   3590:                break;
                   3591:        }
1.183.2.2  martin   3592:
                   3593:        if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ)
                   3594:                return;
                   3595:
1.135     msaitoh  3596:        for (i = 0; i < size ; i += 2) {
                   3597:                reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)];
                   3598:                for (j = 0; j < 2 ; j++) {
1.136     msaitoh  3599:                        uint32_t entry = reg;
1.135     msaitoh  3600:
                   3601:                        if (j != 0)
                   3602:                                entry >>= 16;
                   3603:                        entry &= 0xffff;
1.137     joerg    3604:                        printf("    TPH ST Table Entry (%d): 0x%04"PRIx32"\n",
1.135     msaitoh  3605:                            i + j, entry);
                   3606:                }
                   3607:        }
                   3608: }
                   3609:
                   3610: static void
1.183.2.4  snj      3611: pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3612: {
                   3613:        pcireg_t reg;
                   3614:
                   3615:        printf("\n  Latency Tolerance Reporting\n");
1.183.2.1  martin   3616:        reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)];
                   3617:        printf("    Max Snoop Latency Register: 0x%04x\n", reg & 0xffff);
                   3618:        printf("      Max Snoop Latency: %juns\n",
                   3619:            (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)
                   3620:            * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))));
                   3621:        printf("    Max No-Snoop Latency Register: 0x%04x\n", reg >> 16);
                   3622:        printf("      Max No-Snoop Latency: %juns\n",
                   3623:            (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)
                   3624:            * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))));
1.135     msaitoh  3625: }
                   3626:
                   3627: static void
1.183.2.4  snj      3628: pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3629: {
                   3630:        int pcie_capoff;
                   3631:        pcireg_t reg;
                   3632:        int i, maxlinkwidth;
                   3633:
                   3634:        printf("\n  Secondary PCI Express Register\n");
                   3635:
                   3636:        reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)];
                   3637:        printf("    Link Control 3 register: 0x%08x\n", reg);
                   3638:        onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ);
                   3639:        onoff("Link Equalization Request Interrupt Enable",
                   3640:            reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE);
1.146     msaitoh  3641:        printf("      Enable Lower SKP OS Generation Vector:");
                   3642:        pci_print_pcie_linkspeedvector(
                   3643:                __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV));
                   3644:        printf("\n");
1.135     msaitoh  3645:
                   3646:        reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)];
                   3647:        printf("    Lane Error Status register: 0x%08x\n", reg);
                   3648:
                   3649:        /* Get Max Link Width */
1.183.2.4  snj      3650:        if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
1.135     msaitoh  3651:                reg = regs[o2i(pcie_capoff + PCIE_LCAP)];
                   3652:                maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
                   3653:        } else {
                   3654:                printf("error: falied to get PCIe capablity\n");
                   3655:                return;
                   3656:        }
                   3657:        for (i = 0; i < maxlinkwidth; i++) {
                   3658:                reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))];
                   3659:                if (i % 2 != 0)
                   3660:                        reg >>= 16;
                   3661:                else
                   3662:                        reg &= 0xffff;
1.157     msaitoh  3663:                printf("    Equalization Control Register (Link %d): 0x%04x\n",
1.135     msaitoh  3664:                    i, reg);
                   3665:                printf("      Downstream Port Transmit Preset: 0x%x\n",
                   3666:                    (pcireg_t)__SHIFTOUT(reg,
                   3667:                        PCI_SECPCIE_EQCTL_DP_XMIT_PRESET));
                   3668:                printf("      Downstream Port Receive Hint: 0x%x\n",
                   3669:                    (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT));
                   3670:                printf("      Upstream Port Transmit Preset: 0x%x\n",
                   3671:                    (pcireg_t)__SHIFTOUT(reg,
                   3672:                        PCI_SECPCIE_EQCTL_UP_XMIT_PRESET));
                   3673:                printf("      Upstream Port Receive Hint: 0x%x\n",
                   3674:                    (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT));
                   3675:        }
                   3676: }
                   3677:
                   3678: /* XXX pci_conf_print_pmux_cap */
                   3679:
                   3680: static void
1.183.2.4  snj      3681: pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3682: {
                   3683:        pcireg_t reg, cap, ctl;
                   3684:        unsigned int num;
                   3685:
                   3686:        printf("\n  Process Address Space ID\n");
                   3687:
                   3688:        reg = regs[o2i(extcapoff + PCI_PASID_CAP)];
                   3689:        cap = reg & 0xffff;
                   3690:        ctl = reg >> 16;
                   3691:        printf("    PASID Capability Register: 0x%04x\n", cap);
                   3692:        onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM);
                   3693:        onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE);
                   3694:        num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1;
                   3695:        printf("      Max PASID Width: %u\n", num);
                   3696:
                   3697:        printf("    PASID Control Register: 0x%04x\n", ctl);
                   3698:        onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN);
                   3699:        onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN);
                   3700:        onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN);
                   3701: }
                   3702:
                   3703: static void
1.183.2.4  snj      3704: pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3705: {
                   3706:        pcireg_t reg, cap, ctl;
                   3707:        unsigned int num;
                   3708:
                   3709:        printf("\n  LN Requester\n");
                   3710:
                   3711:        reg = regs[o2i(extcapoff + PCI_LNR_CAP)];
                   3712:        cap = reg & 0xffff;
                   3713:        ctl = reg >> 16;
                   3714:        printf("    LNR Capability register: 0x%04x\n", cap);
                   3715:        onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64);
                   3716:        onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128);
                   3717:        num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX);
                   3718:        printf("      LNR Registration MAX: %u\n", num);
                   3719:
                   3720:        printf("    LNR Control register: 0x%04x\n", ctl);
                   3721:        onoff("LNR Enable", reg, PCI_LNR_CTL_EN);
                   3722:        onoff("LNR CLS", reg, PCI_LNR_CTL_CLS);
                   3723:        num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM);
                   3724:        printf("      LNR Registration Limit: %u\n", num);
                   3725: }
                   3726:
1.176     msaitoh  3727: static void
                   3728: pci_conf_print_dpc_pio(pcireg_t r)
                   3729: {
                   3730:        onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL);
                   3731:        onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL);
                   3732:        onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO);
                   3733:        onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL);
                   3734:        onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL);
                   3735:        onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO);
                   3736:        onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL);
                   3737:        onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL);
                   3738:        onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO);
                   3739: }
                   3740:
                   3741: static void
1.183.2.4  snj      3742: pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff)
1.176     msaitoh  3743: {
                   3744:        pcireg_t reg, cap, ctl, stat, errsrc;
                   3745:        const char *trigstr;
                   3746:        bool rpext;
                   3747:
                   3748:        printf("\n  Downstream Port Containment\n");
                   3749:
                   3750:        reg = regs[o2i(extcapoff + PCI_DPC_CCR)];
                   3751:        cap = reg & 0xffff;
                   3752:        ctl = reg >> 16;
                   3753:        rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false;
                   3754:        printf("    DPC Capability register: 0x%04x\n", cap);
                   3755:        printf("      DPC Interrupt Message Number: %02x\n",
                   3756:            (unsigned int)(cap & PCI_DPCCAP_IMSGN));
                   3757:        onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT);
                   3758:        onoff("Poisoned TLP Egress Blocking Supported", reg,
                   3759:            PCI_DPCCAP_POISONTLPEB);
                   3760:        onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG);
                   3761:        printf("      RP PIO Log Size: %u\n",
                   3762:            (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ));
                   3763:        onoff("DL_Active ERR_COR Signaling Supported", reg,
                   3764:            PCI_DPCCAP_DLACTECORS);
                   3765:        printf("    DPC Control register: 0x%04x\n", ctl);
                   3766:        switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) {
                   3767:        case 0:
                   3768:                trigstr = "disabled";
                   3769:                break;
                   3770:        case 1:
                   3771:                trigstr = "enabled(ERR_FATAL)";
                   3772:                break;
                   3773:        case 2:
                   3774:                trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)";
                   3775:                break;
                   3776:        default:
                   3777:                trigstr = "(reserverd)";
                   3778:                break;
                   3779:        }
                   3780:        printf("      DPC Trigger Enable: %s\n", trigstr);
                   3781:        printf("      DPC Completion Control: %s Completion Status\n",
                   3782:            (reg & PCI_DPCCTL_COMPCTL)
                   3783:            ? "Unsupported Request(UR)" : "Completer Abort(CA)");
                   3784:        onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE);
                   3785:        onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN);
                   3786:        onoff("Poisoned TLP Egress Blocking Enable", reg,
                   3787:            PCI_DPCCTL_POISONTLPEB);
                   3788:        onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG);
                   3789:        onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR);
                   3790:
                   3791:        reg = regs[o2i(extcapoff + PCI_DPC_STATESID)];
                   3792:        stat = reg & 0xffff;
                   3793:        errsrc = reg >> 16;
                   3794:        printf("    DPC Status register: 0x%04x\n", stat);
                   3795:        onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT);
                   3796:        switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {
                   3797:        case 0:
                   3798:                trigstr = "an unmasked uncorrectable error";
                   3799:                break;
                   3800:        case 1:
                   3801:                trigstr = "receiving an ERR_NONFATAL";
                   3802:                break;
                   3803:        case 2:
                   3804:                trigstr = "receiving an ERR_FATAL";
                   3805:                break;
                   3806:        case 3:
                   3807:                trigstr = "DPC Trigger Reason Extension field";
                   3808:                break;
                   3809:        }
                   3810:        printf("      DPC Trigger Reason: Due to %s\n", trigstr);
                   3811:        onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT);
                   3812:        if (rpext)
                   3813:                onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY);
                   3814:        switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {
                   3815:        case 0:
                   3816:                trigstr = "Due to RP PIO error";
                   3817:                break;
                   3818:        case 1:
                   3819:                trigstr = "Due to the DPC Software trigger bit";
                   3820:                break;
                   3821:        default:
                   3822:                trigstr = "(reserved)";
                   3823:                break;
                   3824:        }
                   3825:        printf("      DPC Trigger Reason Extension: %s\n", trigstr);
                   3826:        if (rpext)
                   3827:                printf("      RP PIO First Error Pointer: %02x\n",
                   3828:                    (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP));
                   3829:        printf("    DPC Error Source ID register: 0x%04x\n", errsrc);
                   3830:
                   3831:        if (!rpext)
                   3832:                return;
                   3833:        /*
                   3834:         * All of the following registers are implemented by a device which has
                   3835:         * RP Extensions for DPC
                   3836:         */
                   3837:
                   3838:        reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)];
                   3839:        printf("    RP PIO Status Register: 0x%04x\n", reg);
                   3840:        pci_conf_print_dpc_pio(reg);
                   3841:
                   3842:        reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)];
                   3843:        printf("    RP PIO Mask Register: 0x%04x\n", reg);
                   3844:        pci_conf_print_dpc_pio(reg);
                   3845:
                   3846:        reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)];
                   3847:        printf("    RP PIO Severity Register: 0x%04x\n", reg);
                   3848:        pci_conf_print_dpc_pio(reg);
                   3849:
                   3850:        reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)];
                   3851:        printf("    RP PIO SysError Register: 0x%04x\n", reg);
                   3852:        pci_conf_print_dpc_pio(reg);
                   3853:
                   3854:        reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)];
                   3855:        printf("    RP PIO Exception Register: 0x%04x\n", reg);
                   3856:        pci_conf_print_dpc_pio(reg);
                   3857:
                   3858:        printf("    RP PIO Header Log Register: start from 0x%03x\n",
                   3859:            extcapoff + PCI_DPC_RPPIO_HLOG);
                   3860:        printf("    RP PIO ImpSpec Log Register: start from 0x%03x\n",
                   3861:            extcapoff + PCI_DPC_RPPIO_IMPSLOG);
1.183.2.5  snj      3862:        printf("    RP PIO TLP Prefix Log Register: start from 0x%03x\n",
1.176     msaitoh  3863:            extcapoff + PCI_DPC_RPPIO_TLPPLOG);
                   3864: }
                   3865:
1.135     msaitoh  3866:
                   3867: static int
                   3868: pci_conf_l1pm_cap_tposcale(unsigned char scale)
                   3869: {
                   3870:
                   3871:        /* Return scale in us */
                   3872:        switch (scale) {
                   3873:        case 0x0:
                   3874:                return 2;
                   3875:        case 0x1:
                   3876:                return 10;
                   3877:        case 0x2:
                   3878:                return 100;
                   3879:        default:
                   3880:                return -1;
                   3881:        }
                   3882: }
                   3883:
                   3884: static void
1.183.2.4  snj      3885: pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff)
1.135     msaitoh  3886: {
                   3887:        pcireg_t reg;
                   3888:        int scale, val;
1.183.2.4  snj      3889:        int pcie_capoff;
1.135     msaitoh  3890:
                   3891:        printf("\n  L1 PM Substates\n");
                   3892:
                   3893:        reg = regs[o2i(extcapoff + PCI_L1PM_CAP)];
                   3894:        printf("    L1 PM Substates Capability register: 0x%08x\n", reg);
                   3895:        onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12);
                   3896:        onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11);
                   3897:        onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12);
                   3898:        onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11);
                   3899:        onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM);
1.183.2.4  snj      3900:        /* The Link Activation Supported bit is only for Downstream Port */
                   3901:        if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
                   3902:                uint32_t t = regs[o2i(pcie_capoff)];
                   3903:
                   3904:                if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN))
                   3905:                        onoff("Link Activation Supported", reg,
                   3906:                            PCI_L1PM_CAP_LA);
                   3907:        }
1.135     msaitoh  3908:        printf("      Port Common Mode Restore Time: %uus\n",
                   3909:            (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT));
                   3910:        scale = pci_conf_l1pm_cap_tposcale(
                   3911:                __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE));
                   3912:        val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL);
                   3913:        printf("      Port T_POWER_ON: ");
                   3914:        if (scale == -1)
                   3915:                printf("unknown\n");
                   3916:        else
                   3917:                printf("%dus\n", val * scale);
                   3918:
                   3919:        reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)];
                   3920:        printf("    L1 PM Substates Control register 1: 0x%08x\n", reg);
                   3921:        onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN);
                   3922:        onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN);
                   3923:        onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN);
                   3924:        onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN);
1.183.2.4  snj      3925:        onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE);
                   3926:        onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA);
1.135     msaitoh  3927:        printf("      Common Mode Restore Time: %uus\n",
                   3928:            (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT));
                   3929:        scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE));
                   3930:        val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL);
                   3931:        printf("      LTR L1.2 THRESHOLD: %dus\n", val * scale);
                   3932:
                   3933:        reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];
                   3934:        printf("    L1 PM Substates Control register 2: 0x%08x\n", reg);
                   3935:        scale = pci_conf_l1pm_cap_tposcale(
                   3936:                __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE));
                   3937:        val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL);
                   3938:        printf("      T_POWER_ON: ");
                   3939:        if (scale == -1)
                   3940:                printf("unknown\n");
                   3941:        else
                   3942:                printf("%dus\n", val * scale);
1.183.2.4  snj      3943:
                   3944:        if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) {
                   3945:                reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];
                   3946:                printf("    L1 PM Substates Status register: 0x%08x\n", reg);
                   3947:                onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA);
                   3948:        }
1.135     msaitoh  3949: }
                   3950:
1.147     msaitoh  3951: static void
1.183.2.4  snj      3952: pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff)
1.147     msaitoh  3953: {
                   3954:        pcireg_t reg;
                   3955:        uint32_t val;
                   3956:
                   3957:        printf("\n  Precision Time Management\n");
                   3958:
                   3959:        reg = regs[o2i(extcapoff + PCI_PTM_CAP)];
                   3960:        printf("    PTM Capability register: 0x%08x\n", reg);
                   3961:        onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ);
                   3962:        onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP);
                   3963:        onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT);
                   3964:        printf("      Local Clock Granularity: ");
                   3965:        val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL);
                   3966:        switch (val) {
                   3967:        case 0:
                   3968:                printf("Not implemented\n");
                   3969:                break;
                   3970:        case 0xffff:
                   3971:                printf("> 254ns\n");
                   3972:                break;
                   3973:        default:
                   3974:                printf("%uns\n", val);
                   3975:                break;
                   3976:        }
                   3977:
                   3978:        reg = regs[o2i(extcapoff + PCI_PTM_CTL)];
                   3979:        printf("    PTM Control register: 0x%08x\n", reg);
                   3980:        onoff("PTM Enable", reg, PCI_PTM_CTL_EN);
                   3981:        onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL);
                   3982:        printf("      Effective Granularity: ");
                   3983:        val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL);
                   3984:        switch (val) {
                   3985:        case 0:
                   3986:                printf("Unknown\n");
                   3987:                break;
                   3988:        case 0xffff:
                   3989:                printf("> 254ns\n");
                   3990:                break;
                   3991:        default:
                   3992:                printf("%uns\n", val);
                   3993:                break;
                   3994:        }
                   3995: }
                   3996:
1.135     msaitoh  3997: /* XXX pci_conf_print_mpcie_cap */
                   3998: /* XXX pci_conf_print_frsq_cap */
                   3999: /* XXX pci_conf_print_rtr_cap */
                   4000: /* XXX pci_conf_print_desigvndsp_cap */
1.153     msaitoh  4001: /* XXX pci_conf_print_vf_resizbar_cap */
1.177     msaitoh  4002: /* XXX pci_conf_print_hierarchyid_cap */
1.183.2.2  martin   4003: /* XXX pci_conf_print_npem_cap */
1.135     msaitoh  4004:
                   4005: #undef MS
                   4006: #undef SM
                   4007: #undef RW
                   4008:
                   4009: static struct {
                   4010:        pcireg_t cap;
                   4011:        const char *name;
1.183.2.4  snj      4012:        void (*printfunc)(const pcireg_t *, int);
1.135     msaitoh  4013: } pci_extcaptab[] = {
                   4014:        { 0,                    "reserved",
                   4015:          NULL },
                   4016:        { PCI_EXTCAP_AER,       "Advanced Error Reporting",
                   4017:          pci_conf_print_aer_cap },
                   4018:        { PCI_EXTCAP_VC,        "Virtual Channel",
                   4019:          pci_conf_print_vc_cap },
                   4020:        { PCI_EXTCAP_SERNUM,    "Device Serial Number",
                   4021:          pci_conf_print_sernum_cap },
                   4022:        { PCI_EXTCAP_PWRBDGT,   "Power Budgeting",
                   4023:          pci_conf_print_pwrbdgt_cap },
                   4024:        { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration",
                   4025:          pci_conf_print_rclink_dcl_cap },
                   4026:        { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control",
                   4027:          NULL },
                   4028:        { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association",
                   4029:          pci_conf_print_rcec_assoc_cap },
                   4030:        { PCI_EXTCAP_MFVC,      "Multi-Function Virtual Channel",
                   4031:          NULL },
                   4032:        { PCI_EXTCAP_VC2,       "Virtual Channel",
                   4033:          NULL },
                   4034:        { PCI_EXTCAP_RCRB,      "RCRB Header",
                   4035:          NULL },
                   4036:        { PCI_EXTCAP_VENDOR,    "Vendor Unique",
                   4037:          NULL },
                   4038:        { PCI_EXTCAP_CAC,       "Configuration Access Correction",
                   4039:          NULL },
                   4040:        { PCI_EXTCAP_ACS,       "Access Control Services",
                   4041:          pci_conf_print_acs_cap },
                   4042:        { PCI_EXTCAP_ARI,       "Alternative Routing-ID Interpretation",
                   4043:          pci_conf_print_ari_cap },
                   4044:        { PCI_EXTCAP_ATS,       "Address Translation Services",
                   4045:          pci_conf_print_ats_cap },
                   4046:        { PCI_EXTCAP_SRIOV,     "Single Root IO Virtualization",
                   4047:          pci_conf_print_sriov_cap },
                   4048:        { PCI_EXTCAP_MRIOV,     "Multiple Root IO Virtualization",
                   4049:          NULL },
1.138     msaitoh  4050:        { PCI_EXTCAP_MCAST,     "Multicast",
                   4051:          pci_conf_print_multicast_cap },
1.135     msaitoh  4052:        { PCI_EXTCAP_PAGE_REQ,  "Page Request",
                   4053:          pci_conf_print_page_req_cap },
                   4054:        { PCI_EXTCAP_AMD,       "Reserved for AMD",
                   4055:          NULL },
1.153     msaitoh  4056:        { PCI_EXTCAP_RESIZBAR,  "Resizable BAR",
                   4057:          pci_conf_print_resizbar_cap },
1.135     msaitoh  4058:        { PCI_EXTCAP_DPA,       "Dynamic Power Allocation",
1.149     msaitoh  4059:          pci_conf_print_dpa_cap },
1.135     msaitoh  4060:        { PCI_EXTCAP_TPH_REQ,   "TPH Requester",
                   4061:          pci_conf_print_tph_req_cap },
                   4062:        { PCI_EXTCAP_LTR,       "Latency Tolerance Reporting",
                   4063:          pci_conf_print_ltr_cap },
                   4064:        { PCI_EXTCAP_SEC_PCIE,  "Secondary PCI Express",
                   4065:          pci_conf_print_sec_pcie_cap },
                   4066:        { PCI_EXTCAP_PMUX,      "Protocol Multiplexing",
                   4067:          NULL },
                   4068:        { PCI_EXTCAP_PASID,     "Process Address Space ID",
                   4069:          pci_conf_print_pasid_cap },
1.183.2.2  martin   4070:        { PCI_EXTCAP_LNR,       "LN Requester",
1.135     msaitoh  4071:          pci_conf_print_lnr_cap },
                   4072:        { PCI_EXTCAP_DPC,       "Downstream Port Containment",
1.176     msaitoh  4073:          pci_conf_print_dpc_cap },
1.135     msaitoh  4074:        { PCI_EXTCAP_L1PM,      "L1 PM Substates",
                   4075:          pci_conf_print_l1pm_cap },
                   4076:        { PCI_EXTCAP_PTM,       "Precision Time Management",
1.147     msaitoh  4077:          pci_conf_print_ptm_cap },
1.135     msaitoh  4078:        { PCI_EXTCAP_MPCIE,     "M-PCIe",
                   4079:          NULL },
                   4080:        { PCI_EXTCAP_FRSQ,      "Function Reading Status Queueing",
                   4081:          NULL },
                   4082:        { PCI_EXTCAP_RTR,       "Readiness Time Reporting",
                   4083:          NULL },
                   4084:        { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific",
                   4085:          NULL },
1.153     msaitoh  4086:        { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs",
1.151     msaitoh  4087:          NULL },
1.177     msaitoh  4088:        { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
                   4089:          NULL },
1.183.2.2  martin   4090:        { PCI_EXTCAP_NPEM,      "Native PCIe Enclosure Management",
                   4091:          NULL },
1.135     msaitoh  4092: };
                   4093:
                   4094: static int
1.183.2.4  snj      4095: pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp)
1.135     msaitoh  4096: {
                   4097:        int off;
                   4098:        pcireg_t rval;
                   4099:
                   4100:        for (off = PCI_EXTCAPLIST_BASE;
                   4101:             off != 0;
                   4102:             off = PCI_EXTCAPLIST_NEXT(rval)) {
                   4103:                rval = regs[o2i(off)];
                   4104:                if (capid == PCI_EXTCAPLIST_CAP(rval)) {
                   4105:                        if (offsetp != NULL)
                   4106:                                *offsetp = off;
                   4107:                        return 1;
1.33      kleink   4108:                }
                   4109:        }
1.135     msaitoh  4110:        return 0;
                   4111: }
                   4112:
                   4113: static void
                   4114: pci_conf_print_extcaplist(
                   4115: #ifdef _KERNEL
                   4116:     pci_chipset_tag_t pc, pcitag_t tag,
                   4117: #endif
1.183.2.4  snj      4118:     const pcireg_t *regs)
1.135     msaitoh  4119: {
                   4120:        int off;
                   4121:        pcireg_t foundcap;
                   4122:        pcireg_t rval;
                   4123:        bool foundtable[__arraycount(pci_extcaptab)];
                   4124:        unsigned int i;
                   4125:
                   4126:        /* Check Extended capability structure */
                   4127:        off = PCI_EXTCAPLIST_BASE;
                   4128:        rval = regs[o2i(off)];
                   4129:        if (rval == 0xffffffff || rval == 0)
                   4130:                return;
                   4131:
                   4132:        /* Clear table */
                   4133:        for (i = 0; i < __arraycount(pci_extcaptab); i++)
                   4134:                foundtable[i] = false;
                   4135:
                   4136:        /* Print extended capability register's offset and the type first */
                   4137:        for (;;) {
                   4138:                printf("  Extended Capability Register at 0x%02x\n", off);
                   4139:
                   4140:                foundcap = PCI_EXTCAPLIST_CAP(rval);
                   4141:                printf("    type: 0x%04x (", foundcap);
                   4142:                if (foundcap < __arraycount(pci_extcaptab)) {
                   4143:                        printf("%s)\n", pci_extcaptab[foundcap].name);
                   4144:                        /* Mark as found */
                   4145:                        foundtable[foundcap] = true;
                   4146:                } else
                   4147:                        printf("unknown)\n");
                   4148:                printf("    version: %d\n", PCI_EXTCAPLIST_VERSION(rval));
                   4149:
                   4150:                off = PCI_EXTCAPLIST_NEXT(rval);
                   4151:                if (off == 0)
                   4152:                        break;
1.150     msaitoh  4153:                else if (off <= PCI_CONF_SIZE) {
                   4154:                        printf("    next pointer: 0x%03x (incorrect)\n", off);
                   4155:                        return;
                   4156:                }
1.135     msaitoh  4157:                rval = regs[o2i(off)];
                   4158:        }
                   4159:
                   4160:        /*
                   4161:         * And then, print the detail of each capability registers
                   4162:         * in capability value's order.
                   4163:         */
                   4164:        for (i = 0; i < __arraycount(pci_extcaptab); i++) {
                   4165:                if (foundtable[i] == false)
                   4166:                        continue;
                   4167:
                   4168:                /*
                   4169:                 * The type was found. Search capability list again and
                   4170:                 * print all capabilities that the capabiliy type is
                   4171:                 * the same.
                   4172:                 */
1.183.2.4  snj      4173:                if (pci_conf_find_extcap(regs, i, &off) == 0)
1.135     msaitoh  4174:                        continue;
                   4175:                rval = regs[o2i(off)];
                   4176:                if ((PCI_EXTCAPLIST_VERSION(rval) <= 0)
                   4177:                    || (pci_extcaptab[i].printfunc == NULL))
                   4178:                        continue;
                   4179:
1.183.2.4  snj      4180:                pci_extcaptab[i].printfunc(regs, off);
1.135     msaitoh  4181:
                   4182:        }
1.26      cgd      4183: }
                   4184:
1.79      dyoung   4185: /* Print the Secondary Status Register. */
                   4186: static void
                   4187: pci_conf_print_ssr(pcireg_t rval)
                   4188: {
                   4189:        pcireg_t devsel;
                   4190:
                   4191:        printf("    Secondary status register: 0x%04x\n", rval); /* XXX bits */
1.112     msaitoh  4192:        onoff("66 MHz capable", rval, __BIT(5));
                   4193:        onoff("User Definable Features (UDF) support", rval, __BIT(6));
                   4194:        onoff("Fast back-to-back capable", rval, __BIT(7));
                   4195:        onoff("Data parity error detected", rval, __BIT(8));
1.79      dyoung   4196:
                   4197:        printf("      DEVSEL timing: ");
                   4198:        devsel = __SHIFTOUT(rval, __BITS(10, 9));
                   4199:        switch (devsel) {
                   4200:        case 0:
                   4201:                printf("fast");
                   4202:                break;
                   4203:        case 1:
                   4204:                printf("medium");
                   4205:                break;
                   4206:        case 2:
                   4207:                printf("slow");
                   4208:                break;
                   4209:        default:
                   4210:                printf("unknown/reserved");     /* XXX */
                   4211:                break;
                   4212:        }
                   4213:        printf(" (0x%x)\n", devsel);
                   4214:
1.112     msaitoh  4215:        onoff("Signalled target abort", rval, __BIT(11));
                   4216:        onoff("Received target abort", rval, __BIT(12));
                   4217:        onoff("Received master abort", rval, __BIT(13));
                   4218:        onoff("Received system error", rval, __BIT(14));
                   4219:        onoff("Detected parity error", rval, __BIT(15));
1.79      dyoung   4220: }
                   4221:
1.27      cgd      4222: static void
1.115     msaitoh  4223: pci_conf_print_type0(
                   4224: #ifdef _KERNEL
                   4225:     pci_chipset_tag_t pc, pcitag_t tag,
                   4226: #endif
1.167     msaitoh  4227:     const pcireg_t *regs)
1.115     msaitoh  4228: {
                   4229:        int off, width;
                   4230:        pcireg_t rval;
1.183.2.2  martin   4231:        const char *str;
1.115     msaitoh  4232:
                   4233:        for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
                   4234: #ifdef _KERNEL
1.167     msaitoh  4235:                width = pci_conf_print_bar(pc, tag, regs, off, NULL);
1.115     msaitoh  4236: #else
                   4237:                width = pci_conf_print_bar(regs, off, NULL);
                   4238: #endif
                   4239:        }
                   4240:
1.170     msaitoh  4241:        printf("    Cardbus CIS Pointer: 0x%08x\n",
                   4242:            regs[o2i(PCI_CARDBUS_CIS_REG)]);
1.115     msaitoh  4243:
                   4244:        rval = regs[o2i(PCI_SUBSYS_ID_REG)];
                   4245:        printf("    Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
                   4246:        printf("    Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
                   4247:
1.183.2.2  martin   4248:        rval = regs[o2i(PCI_MAPREG_ROM)];
                   4249:        printf("    Expansion ROM Base Address Register: 0x%08x\n", rval);
                   4250:        printf("      base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval));
                   4251:        onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE);
                   4252:        printf("      Validation Status: ");
                   4253:        switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) {
                   4254:        case PCI_MAPREG_ROM_VSTAT_NOTSUPP:
                   4255:                str = "Validation not supported";
                   4256:                break;
                   4257:        case PCI_MAPREG_ROM_VSTAT_INPROG:
                   4258:                str = "Validation in Progress";
                   4259:                break;
                   4260:        case PCI_MAPREG_ROM_VSTAT_VPASS:
                   4261:                str = "Validation Pass. "
                   4262:                    "Valid contents, trust test was not performed";
                   4263:                break;
                   4264:        case PCI_MAPREG_ROM_VSTAT_VPASSTRUST:
                   4265:                str = "Validation Pass. Valid and trusted contents";
                   4266:                break;
                   4267:        case PCI_MAPREG_ROM_VSTAT_VFAIL:
                   4268:                str = "Validation Fail. Invalid contents";
                   4269:                break;
                   4270:        case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST:
                   4271:                str = "Validation Fail. Valid but untrusted contents";
                   4272:                break;
                   4273:        case PCI_MAPREG_ROM_VSTAT_WPASS:
                   4274:                str = "Warning Pass. Validation passed with warning. "
                   4275:                    "Valid contents, trust test was not performed";
                   4276:                break;
                   4277:        case PCI_MAPREG_ROM_VSTAT_WPASSTRUST:
                   4278:                str = "Warning Pass. Validation passed with warning. "
                   4279:                    "Valid and trusted contents";
                   4280:                break;
                   4281:        }
                   4282:        printf("%s\n", str);
                   4283:        printf("      Validation Details: 0x%x\n",
                   4284:            (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL));
1.115     msaitoh  4285:
                   4286:        if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
                   4287:                printf("    Capability list pointer: 0x%02x\n",
                   4288:                    PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
                   4289:        else
                   4290:                printf("    Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
                   4291:
                   4292:        printf("    Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
                   4293:
                   4294:        rval = regs[o2i(PCI_INTERRUPT_REG)];
1.170     msaitoh  4295:        printf("    Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval));
                   4296:        printf("    Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval));
1.115     msaitoh  4297:        printf("    Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
                   4298:        switch (PCI_INTERRUPT_PIN(rval)) {
                   4299:        case PCI_INTERRUPT_PIN_NONE:
                   4300:                printf("(none)");
                   4301:                break;
                   4302:        case PCI_INTERRUPT_PIN_A:
                   4303:                printf("(pin A)");
                   4304:                break;
                   4305:        case PCI_INTERRUPT_PIN_B:
                   4306:                printf("(pin B)");
                   4307:                break;
                   4308:        case PCI_INTERRUPT_PIN_C:
                   4309:                printf("(pin C)");
                   4310:                break;
                   4311:        case PCI_INTERRUPT_PIN_D:
                   4312:                printf("(pin D)");
                   4313:                break;
                   4314:        default:
                   4315:                printf("(? ? ?)");
                   4316:                break;
                   4317:        }
                   4318:        printf("\n");
                   4319:        printf("    Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
                   4320: }
                   4321:
                   4322: static void
1.45      thorpej  4323: pci_conf_print_type1(
                   4324: #ifdef _KERNEL
                   4325:     pci_chipset_tag_t pc, pcitag_t tag,
                   4326: #endif
1.167     msaitoh  4327:     const pcireg_t *regs)
1.27      cgd      4328: {
1.37      nathanw  4329:        int off, width;
1.183.2.4  snj      4330:        pcireg_t rval, csreg;
1.110     msaitoh  4331:        uint32_t base, limit;
                   4332:        uint32_t base_h, limit_h;
                   4333:        uint64_t pbase, plimit;
                   4334:        int use_upper;
1.27      cgd      4335:
                   4336:        /*
                   4337:         * This layout was cribbed from the TI PCI2030 PCI-to-PCI
                   4338:         * Bridge chip documentation, and may not be correct with
                   4339:         * respect to various standards. (XXX)
                   4340:         */
                   4341:
1.45      thorpej  4342:        for (off = 0x10; off < 0x18; off += width) {
                   4343: #ifdef _KERNEL
1.167     msaitoh  4344:                width = pci_conf_print_bar(pc, tag, regs, off, NULL);
1.45      thorpej  4345: #else
                   4346:                width = pci_conf_print_bar(regs, off, NULL);
                   4347: #endif
                   4348:        }
1.27      cgd      4349:
1.109     msaitoh  4350:        rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
1.27      cgd      4351:        printf("    Primary bus number: 0x%02x\n",
1.114     msaitoh  4352:            PCI_BRIDGE_BUS_PRIMARY(rval));
1.27      cgd      4353:        printf("    Secondary bus number: 0x%02x\n",
1.114     msaitoh  4354:            PCI_BRIDGE_BUS_SECONDARY(rval));
1.27      cgd      4355:        printf("    Subordinate bus number: 0x%02x\n",
1.114     msaitoh  4356:            PCI_BRIDGE_BUS_SUBORDINATE(rval));
1.27      cgd      4357:        printf("    Secondary bus latency timer: 0x%02x\n",
1.114     msaitoh  4358:            PCI_BRIDGE_BUS_SEC_LATTIMER(rval));
1.27      cgd      4359:
1.109     msaitoh  4360:        rval = regs[o2i(PCI_BRIDGE_STATIO_REG)];
                   4361:        pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
1.27      cgd      4362:
1.110     msaitoh  4363:        /* I/O region */
1.27      cgd      4364:        printf("    I/O region:\n");
1.109     msaitoh  4365:        printf("      base register:  0x%02x\n", (rval >> 0) & 0xff);
                   4366:        printf("      limit register: 0x%02x\n", (rval >> 8) & 0xff);
1.110     msaitoh  4367:        if (PCI_BRIDGE_IO_32BITS(rval))
                   4368:                use_upper = 1;
                   4369:        else
                   4370:                use_upper = 0;
1.112     msaitoh  4371:        onoff("32bit I/O", rval, use_upper);
1.110     msaitoh  4372:        base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8;
                   4373:        limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT)
                   4374:            & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8;
                   4375:        limit |= 0x00000fff;
                   4376:
1.109     msaitoh  4377:        rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)];
1.110     msaitoh  4378:        base_h = (rval >> 0) & 0xffff;
                   4379:        limit_h = (rval >> 16) & 0xffff;
                   4380:        printf("      base upper 16 bits register:  0x%04x\n", base_h);
                   4381:        printf("      limit upper 16 bits register: 0x%04x\n", limit_h);
                   4382:
                   4383:        if (use_upper == 1) {
                   4384:                base |= base_h << 16;
                   4385:                limit |= limit_h << 16;
                   4386:        }
                   4387:        if (base < limit) {
                   4388:                if (use_upper == 1)
1.183.2.3  martin   4389:                        printf("      range: 0x%08x-0x%08x\n", base, limit);
1.110     msaitoh  4390:                else
1.183.2.3  martin   4391:                        printf("      range: 0x%04x-0x%04x\n", base, limit);
1.121     msaitoh  4392:        } else
                   4393:                printf("      range:  not set\n");
1.27      cgd      4394:
1.110     msaitoh  4395:        /* Non-prefetchable memory region */
1.109     msaitoh  4396:        rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)];
1.27      cgd      4397:        printf("    Memory region:\n");
                   4398:        printf("      base register:  0x%04x\n",
1.109     msaitoh  4399:            (rval >> 0) & 0xffff);
1.27      cgd      4400:        printf("      limit register: 0x%04x\n",
1.109     msaitoh  4401:            (rval >> 16) & 0xffff);
1.110     msaitoh  4402:        base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT)
                   4403:            & PCI_BRIDGE_MEMORY_BASE_MASK) << 20;
                   4404:        limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT)
                   4405:                & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff;
                   4406:        if (base < limit)
1.183.2.3  martin   4407:                printf("      range: 0x%08x-0x%08x\n", base, limit);
1.121     msaitoh  4408:        else
1.183.2.3  martin   4409:                printf("      range: not set\n");
1.27      cgd      4410:
1.110     msaitoh  4411:        /* Prefetchable memory region */
1.109     msaitoh  4412:        rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)];
1.27      cgd      4413:        printf("    Prefetchable memory region:\n");
                   4414:        printf("      base register:  0x%04x\n",
1.109     msaitoh  4415:            (rval >> 0) & 0xffff);
1.27      cgd      4416:        printf("      limit register: 0x%04x\n",
1.109     msaitoh  4417:            (rval >> 16) & 0xffff);
1.110     msaitoh  4418:        base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)];
                   4419:        limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)];
1.109     msaitoh  4420:        printf("      base upper 32 bits register:  0x%08x\n",
1.110     msaitoh  4421:            base_h);
1.109     msaitoh  4422:        printf("      limit upper 32 bits register: 0x%08x\n",
1.110     msaitoh  4423:            limit_h);
                   4424:        if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval))
                   4425:                use_upper = 1;
                   4426:        else
                   4427:                use_upper = 0;
1.112     msaitoh  4428:        onoff("64bit memory address", rval, use_upper);
1.110     msaitoh  4429:        pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT)
                   4430:            & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20;
                   4431:        plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT)
                   4432:                & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff;
                   4433:        if (use_upper == 1) {
                   4434:                pbase |= (uint64_t)base_h << 32;
                   4435:                plimit |= (uint64_t)limit_h << 32;
                   4436:        }
                   4437:        if (pbase < plimit) {
                   4438:                if (use_upper == 1)
1.183.2.3  martin   4439:                        printf("      range: 0x%016" PRIx64 "-0x%016" PRIx64
1.115     msaitoh  4440:                            "\n", pbase, plimit);
1.110     msaitoh  4441:                else
1.183.2.3  martin   4442:                        printf("      range: 0x%08x-0x%08x\n",
1.110     msaitoh  4443:                            (uint32_t)pbase, (uint32_t)plimit);
1.121     msaitoh  4444:        } else
1.183.2.3  martin   4445:                printf("      range: not set\n");
1.27      cgd      4446:
1.183.2.4  snj      4447:        csreg = regs[o2i(PCI_COMMAND_STATUS_REG)];
                   4448:        if (csreg & PCI_STATUS_CAPLIST_SUPPORT)
1.53      drochner 4449:                printf("    Capability list pointer: 0x%02x\n",
                   4450:                    PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
                   4451:        else
                   4452:                printf("    Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
                   4453:
1.27      cgd      4454:        /* XXX */
                   4455:        printf("    Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
                   4456:
1.109     msaitoh  4457:        rval = regs[o2i(PCI_INTERRUPT_REG)];
1.27      cgd      4458:        printf("    Interrupt line: 0x%02x\n",
1.109     msaitoh  4459:            (rval >> 0) & 0xff);
1.27      cgd      4460:        printf("    Interrupt pin: 0x%02x ",
1.109     msaitoh  4461:            (rval >> 8) & 0xff);
                   4462:        switch ((rval >> 8) & 0xff) {
1.27      cgd      4463:        case PCI_INTERRUPT_PIN_NONE:
                   4464:                printf("(none)");
                   4465:                break;
                   4466:        case PCI_INTERRUPT_PIN_A:
                   4467:                printf("(pin A)");
                   4468:                break;
                   4469:        case PCI_INTERRUPT_PIN_B:
                   4470:                printf("(pin B)");
                   4471:                break;
                   4472:        case PCI_INTERRUPT_PIN_C:
                   4473:                printf("(pin C)");
                   4474:                break;
                   4475:        case PCI_INTERRUPT_PIN_D:
                   4476:                printf("(pin D)");
                   4477:                break;
                   4478:        default:
1.36      mrg      4479:                printf("(? ? ?)");
1.27      cgd      4480:                break;
                   4481:        }
                   4482:        printf("\n");
1.109     msaitoh  4483:        rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT)
                   4484:            & PCI_BRIDGE_CONTROL_MASK;
1.27      cgd      4485:        printf("    Bridge control register: 0x%04x\n", rval); /* XXX bits */
1.159     msaitoh  4486:        onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE);
                   4487:        onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR);
                   4488:        onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA);
                   4489:        onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA);
1.183.2.4  snj      4490:        /*
                   4491:         * VGA 16bit decode bit has meaning if the VGA enable bit or the
                   4492:         * VGA Palette Snoop Enable bit is set.
                   4493:         */
                   4494:        if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0)
                   4495:            || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0))
                   4496:                onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16);
1.159     msaitoh  4497:        onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT);
                   4498:        onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR);
                   4499:        onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B);
1.27      cgd      4500: }
                   4501:
                   4502: static void
1.45      thorpej  4503: pci_conf_print_type2(
                   4504: #ifdef _KERNEL
                   4505:     pci_chipset_tag_t pc, pcitag_t tag,
                   4506: #endif
1.167     msaitoh  4507:     const pcireg_t *regs)
1.27      cgd      4508: {
                   4509:        pcireg_t rval;
                   4510:
                   4511:        /*
                   4512:         * XXX these need to be printed in more detail, need to be
                   4513:         * XXX checked against specs/docs, etc.
                   4514:         *
1.79      dyoung   4515:         * This layout was cribbed from the TI PCI1420 PCI-to-CardBus
1.27      cgd      4516:         * controller chip documentation, and may not be correct with
                   4517:         * respect to various standards. (XXX)
                   4518:         */
                   4519:
1.45      thorpej  4520: #ifdef _KERNEL
1.28      cgd      4521:        pci_conf_print_bar(pc, tag, regs, 0x10,
1.167     msaitoh  4522:            "CardBus socket/ExCA registers");
1.45      thorpej  4523: #else
                   4524:        pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers");
                   4525: #endif
1.27      cgd      4526:
1.109     msaitoh  4527:        /* Capability list pointer and secondary status register */
                   4528:        rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)];
1.53      drochner 4529:        if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
                   4530:                printf("    Capability list pointer: 0x%02x\n",
1.109     msaitoh  4531:                    PCI_CAPLIST_PTR(rval));
1.53      drochner 4532:        else
1.135     msaitoh  4533:                printf("    Reserved @ 0x14: 0x%04x\n",
                   4534:                       (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0)));
1.109     msaitoh  4535:        pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
1.27      cgd      4536:
1.109     msaitoh  4537:        rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
1.27      cgd      4538:        printf("    PCI bus number: 0x%02x\n",
1.109     msaitoh  4539:            (rval >> 0) & 0xff);
1.27      cgd      4540:        printf("    CardBus bus number: 0x%02x\n",
1.109     msaitoh  4541:            (rval >> 8) & 0xff);
1.27      cgd      4542:        printf("    Subordinate bus number: 0x%02x\n",
1.109     msaitoh  4543:            (rval >> 16) & 0xff);
1.27      cgd      4544:        printf("    CardBus latency timer: 0x%02x\n",
1.109     msaitoh  4545:            (rval >> 24) & 0xff);
1.27      cgd      4546:
                   4547:        /* XXX Print more prettily */
                   4548:        printf("    CardBus memory region 0:\n");
                   4549:        printf("      base register:  0x%08x\n", regs[o2i(0x1c)]);
                   4550:        printf("      limit register: 0x%08x\n", regs[o2i(0x20)]);
                   4551:        printf("    CardBus memory region 1:\n");
                   4552:        printf("      base register:  0x%08x\n", regs[o2i(0x24)]);
                   4553:        printf("      limit register: 0x%08x\n", regs[o2i(0x28)]);
                   4554:        printf("    CardBus I/O region 0:\n");
                   4555:        printf("      base register:  0x%08x\n", regs[o2i(0x2c)]);
                   4556:        printf("      limit register: 0x%08x\n", regs[o2i(0x30)]);
                   4557:        printf("    CardBus I/O region 1:\n");
                   4558:        printf("      base register:  0x%08x\n", regs[o2i(0x34)]);
                   4559:        printf("      limit register: 0x%08x\n", regs[o2i(0x38)]);
                   4560:
1.109     msaitoh  4561:        rval = regs[o2i(PCI_INTERRUPT_REG)];
1.27      cgd      4562:        printf("    Interrupt line: 0x%02x\n",
1.109     msaitoh  4563:            (rval >> 0) & 0xff);
1.27      cgd      4564:        printf("    Interrupt pin: 0x%02x ",
1.109     msaitoh  4565:            (rval >> 8) & 0xff);
                   4566:        switch ((rval >> 8) & 0xff) {
1.27      cgd      4567:        case PCI_INTERRUPT_PIN_NONE:
                   4568:                printf("(none)");
                   4569:                break;
                   4570:        case PCI_INTERRUPT_PIN_A:
                   4571:                printf("(pin A)");
                   4572:                break;
                   4573:        case PCI_INTERRUPT_PIN_B:
                   4574:                printf("(pin B)");
                   4575:                break;
                   4576:        case PCI_INTERRUPT_PIN_C:
                   4577:                printf("(pin C)");
                   4578:                break;
                   4579:        case PCI_INTERRUPT_PIN_D:
                   4580:                printf("(pin D)");
                   4581:                break;
                   4582:        default:
1.36      mrg      4583:                printf("(? ? ?)");
1.27      cgd      4584:                break;
                   4585:        }
                   4586:        printf("\n");
1.170     msaitoh  4587:        rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff;
1.27      cgd      4588:        printf("    Bridge control register: 0x%04x\n", rval);
1.112     msaitoh  4589:        onoff("Parity error response", rval, __BIT(0));
                   4590:        onoff("SERR# enable", rval, __BIT(1));
                   4591:        onoff("ISA enable", rval, __BIT(2));
                   4592:        onoff("VGA enable", rval, __BIT(3));
                   4593:        onoff("Master abort mode", rval, __BIT(5));
                   4594:        onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
1.115     msaitoh  4595:        onoff("Functional interrupts routed by ExCA registers", rval,
                   4596:            __BIT(7));
1.112     msaitoh  4597:        onoff("Memory window 0 prefetchable", rval, __BIT(8));
                   4598:        onoff("Memory window 1 prefetchable", rval, __BIT(9));
                   4599:        onoff("Write posting enable", rval, __BIT(10));
1.28      cgd      4600:
                   4601:        rval = regs[o2i(0x40)];
                   4602:        printf("    Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
                   4603:        printf("    Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
                   4604:
1.45      thorpej  4605: #ifdef _KERNEL
1.167     msaitoh  4606:        pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers");
1.45      thorpej  4607: #else
                   4608:        pci_conf_print_bar(regs, 0x44, "legacy-mode registers");
                   4609: #endif
1.27      cgd      4610: }
                   4611:
1.26      cgd      4612: void
1.45      thorpej  4613: pci_conf_print(
                   4614: #ifdef _KERNEL
                   4615:     pci_chipset_tag_t pc, pcitag_t tag,
                   4616:     void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)
                   4617: #else
                   4618:     int pcifd, u_int bus, u_int dev, u_int func
                   4619: #endif
                   4620:     )
1.26      cgd      4621: {
1.135     msaitoh  4622:        pcireg_t regs[o2i(PCI_EXTCONF_SIZE)];
1.52      drochner 4623:        int off, capoff, endoff, hdrtype;
1.125     matt     4624:        const char *type_name;
1.45      thorpej  4625: #ifdef _KERNEL
1.167     msaitoh  4626:        void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *);
1.45      thorpej  4627: #else
1.125     matt     4628:        void (*type_printfn)(const pcireg_t *);
1.45      thorpej  4629: #endif
1.26      cgd      4630:
                   4631:        printf("PCI configuration registers:\n");
                   4632:
1.135     msaitoh  4633:        for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) {
1.45      thorpej  4634: #ifdef _KERNEL
1.26      cgd      4635:                regs[o2i(off)] = pci_conf_read(pc, tag, off);
1.45      thorpej  4636: #else
                   4637:                if (pcibus_conf_read(pcifd, bus, dev, func, off,
                   4638:                    &regs[o2i(off)]) == -1)
                   4639:                        regs[o2i(off)] = 0;
                   4640: #endif
                   4641:        }
1.26      cgd      4642:
                   4643:        /* common header */
                   4644:        printf("  Common header:\n");
1.28      cgd      4645:        pci_conf_print_regs(regs, 0, 16);
                   4646:
1.26      cgd      4647:        printf("\n");
1.45      thorpej  4648: #ifdef _KERNEL
1.26      cgd      4649:        pci_conf_print_common(pc, tag, regs);
1.45      thorpej  4650: #else
                   4651:        pci_conf_print_common(regs);
                   4652: #endif
1.26      cgd      4653:        printf("\n");
                   4654:
                   4655:        /* type-dependent header */
                   4656:        hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
                   4657:        switch (hdrtype) {              /* XXX make a table, eventually */
                   4658:        case 0:
1.27      cgd      4659:                /* Standard device header */
1.125     matt     4660:                type_name = "\"normal\" device";
                   4661:                type_printfn = &pci_conf_print_type0;
1.52      drochner 4662:                capoff = PCI_CAPLISTPTR_REG;
1.28      cgd      4663:                endoff = 64;
1.27      cgd      4664:                break;
                   4665:        case 1:
                   4666:                /* PCI-PCI bridge header */
1.125     matt     4667:                type_name = "PCI-PCI bridge";
                   4668:                type_printfn = &pci_conf_print_type1;
1.52      drochner 4669:                capoff = PCI_CAPLISTPTR_REG;
1.28      cgd      4670:                endoff = 64;
1.26      cgd      4671:                break;
1.27      cgd      4672:        case 2:
                   4673:                /* PCI-CardBus bridge header */
1.125     matt     4674:                type_name = "PCI-CardBus bridge";
                   4675:                type_printfn = &pci_conf_print_type2;
1.52      drochner 4676:                capoff = PCI_CARDBUS_CAPLISTPTR_REG;
1.28      cgd      4677:                endoff = 72;
1.27      cgd      4678:                break;
1.26      cgd      4679:        default:
1.125     matt     4680:                type_name = NULL;
                   4681:                type_printfn = 0;
1.52      drochner 4682:                capoff = -1;
1.28      cgd      4683:                endoff = 64;
                   4684:                break;
1.26      cgd      4685:        }
1.27      cgd      4686:        printf("  Type %d ", hdrtype);
1.125     matt     4687:        if (type_name != NULL)
                   4688:                printf("(%s) ", type_name);
1.27      cgd      4689:        printf("header:\n");
1.28      cgd      4690:        pci_conf_print_regs(regs, 16, endoff);
1.27      cgd      4691:        printf("\n");
1.125     matt     4692:        if (type_printfn) {
1.45      thorpej  4693: #ifdef _KERNEL
1.167     msaitoh  4694:                (*type_printfn)(pc, tag, regs);
1.45      thorpej  4695: #else
1.125     matt     4696:                (*type_printfn)(regs);
1.45      thorpej  4697: #endif
                   4698:        } else
1.26      cgd      4699:                printf("    Don't know how to pretty-print type %d header.\n",
                   4700:                    hdrtype);
                   4701:        printf("\n");
1.51      drochner 4702:
1.55      jdolecek 4703:        /* capability list, if present */
1.52      drochner 4704:        if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
                   4705:                && (capoff > 0)) {
1.51      drochner 4706: #ifdef _KERNEL
1.52      drochner 4707:                pci_conf_print_caplist(pc, tag, regs, capoff);
1.51      drochner 4708: #else
1.52      drochner 4709:                pci_conf_print_caplist(regs, capoff);
1.51      drochner 4710: #endif
                   4711:                printf("\n");
                   4712:        }
1.26      cgd      4713:
                   4714:        /* device-dependent header */
                   4715:        printf("  Device-dependent header:\n");
1.135     msaitoh  4716:        pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE);
1.49      nathanw  4717: #ifdef _KERNEL
1.183.2.8! sborrill 4718:        printf("\n");
1.26      cgd      4719:        if (printfn)
                   4720:                (*printfn)(pc, tag, regs);
                   4721:        else
                   4722:                printf("    Don't know how to pretty-print device-dependent header.\n");
1.45      thorpej  4723: #endif /* _KERNEL */
1.135     msaitoh  4724:
                   4725:        if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff ||
                   4726:            regs[o2i(PCI_EXTCAPLIST_BASE)] == 0)
                   4727:                return;
                   4728:
1.183.2.8! sborrill 4729:        printf("\n");
1.135     msaitoh  4730: #ifdef _KERNEL
1.183.2.4  snj      4731:        pci_conf_print_extcaplist(pc, tag, regs);
1.135     msaitoh  4732: #else
1.183.2.4  snj      4733:        pci_conf_print_extcaplist(regs);
1.135     msaitoh  4734: #endif
                   4735:        printf("\n");
                   4736:
                   4737:        /* Extended Configuration Space, if present */
                   4738:        printf("  Extended Configuration Space:\n");
                   4739:        pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE);
1.1       mycroft  4740: }

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