Annotation of src/sys/dev/pci/pci_subr.c, Revision 1.183.2.11
1.183.2.11! martin 1: /* $NetBSD: pci_subr.c,v 1.183.2.10 2019/07/17 15:34:31 martin Exp $ */
1.3 cgd 2:
1.1 mycroft 3: /*
1.22 thorpej 4: * Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
1.40 cgd 5: * Copyright (c) 1995, 1996, 1998, 2000
1.26 cgd 6: * Christopher G. Demetriou. All rights reserved.
1.30 mycroft 7: * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
1.1 mycroft 8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
1.30 mycroft 19: * This product includes software developed by Charles M. Hannum.
1.1 mycroft 20: * 4. The name of the author may not be used to endorse or promote products
21: * derived from this software without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33: */
34:
35: /*
1.10 cgd 36: * PCI autoconfiguration support functions.
1.45 thorpej 37: *
38: * Note: This file is also built into a userland library (libpci).
39: * Pay attention to this when you make modifications.
1.1 mycroft 40: */
1.47 lukem 41:
42: #include <sys/cdefs.h>
1.183.2.11! martin 43: __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.10 2019/07/17 15:34:31 martin Exp $");
1.21 enami 44:
1.45 thorpej 45: #ifdef _KERNEL_OPT
1.35 cgd 46: #include "opt_pci.h"
1.45 thorpej 47: #endif
1.1 mycroft 48:
49: #include <sys/param.h>
50:
1.45 thorpej 51: #ifdef _KERNEL
1.62 simonb 52: #include <sys/systm.h>
1.73 ad 53: #include <sys/intr.h>
1.80 pgoyette 54: #include <sys/module.h>
1.45 thorpej 55: #else
56: #include <pci.h>
1.155 pgoyette 57: #include <stdarg.h>
1.72 joerg 58: #include <stdbool.h>
1.46 enami 59: #include <stdio.h>
1.135 msaitoh 60: #include <stdlib.h>
1.117 msaitoh 61: #include <string.h>
1.45 thorpej 62: #endif
1.24 thorpej 63:
1.10 cgd 64: #include <dev/pci/pcireg.h>
1.45 thorpej 65: #ifdef _KERNEL
1.7 cgd 66: #include <dev/pci/pcivar.h>
1.126 christos 67: #else
68: #include <dev/pci/pci_verbose.h>
69: #include <dev/pci/pcidevs.h>
70: #include <dev/pci/pcidevs_data.h>
1.10 cgd 71: #endif
72:
1.183.2.4 snj 73: static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *);
74: static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *);
1.181 msaitoh 75: static void pci_conf_print_pcie_power(uint8_t, unsigned int);
1.165 msaitoh 76:
1.10 cgd 77: /*
78: * Descriptions of known PCI classes and subclasses.
79: *
80: * Subclasses are described in the same way as classes, but have a
81: * NULL subclass pointer.
82: */
83: struct pci_class {
1.44 thorpej 84: const char *name;
1.91 matt 85: u_int val; /* as wide as pci_{,sub}class_t */
1.42 jdolecek 86: const struct pci_class *subclasses;
1.10 cgd 87: };
88:
1.117 msaitoh 89: /*
90: * Class 0x00.
91: * Before rev. 2.0.
92: */
1.61 thorpej 93: static const struct pci_class pci_subclass_prehistoric[] = {
1.65 christos 94: { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, },
95: { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, },
96: { NULL, 0, NULL, },
1.10 cgd 97: };
98:
1.117 msaitoh 99: /*
100: * Class 0x01.
1.130 msaitoh 101: * Mass storage controller
1.117 msaitoh 102: */
103:
104: /* ATA programming interface */
105: static const struct pci_class pci_interface_ata[] = {
106: { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, },
107: { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, },
108: { NULL, 0, NULL, },
109: };
110:
111: /* SATA programming interface */
112: static const struct pci_class pci_interface_sata[] = {
1.128 msaitoh 113: { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, },
1.117 msaitoh 114: { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, },
1.128 msaitoh 115: { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, },
116: { NULL, 0, NULL, },
117: };
118:
119: /* Flash programming interface */
120: static const struct pci_class pci_interface_nvm[] = {
121: { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, },
122: { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, },
1.134 msaitoh 123: { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, },
1.117 msaitoh 124: { NULL, 0, NULL, },
125: };
126:
127: /* Subclasses */
1.61 thorpej 128: static const struct pci_class pci_subclass_mass_storage[] = {
1.65 christos 129: { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, },
130: { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, },
131: { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, },
132: { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, },
133: { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, },
1.117 msaitoh 134: { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA,
135: pci_interface_ata, },
136: { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA,
137: pci_interface_sata, },
1.65 christos 138: { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
1.128 msaitoh 139: { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM,
140: pci_interface_nvm, },
1.65 christos 141: { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
142: { NULL, 0, NULL, },
1.10 cgd 143: };
144:
1.117 msaitoh 145: /*
146: * Class 0x02.
147: * Network controller.
148: */
1.61 thorpej 149: static const struct pci_class pci_subclass_network[] = {
1.65 christos 150: { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, },
151: { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, },
152: { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, },
153: { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, },
154: { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, },
155: { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, },
156: { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
157: { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, },
158: { NULL, 0, NULL, },
1.10 cgd 159: };
160:
1.117 msaitoh 161: /*
162: * Class 0x03.
163: * Display controller.
164: */
165:
166: /* VGA programming interface */
167: static const struct pci_class pci_interface_vga[] = {
168: { "", PCI_INTERFACE_VGA_VGA, NULL, },
169: { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, },
170: { NULL, 0, NULL, },
171: };
172: /* Subclasses */
1.61 thorpej 173: static const struct pci_class pci_subclass_display[] = {
1.117 msaitoh 174: { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,},
1.65 christos 175: { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, },
176: { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, },
177: { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, },
178: { NULL, 0, NULL, },
1.10 cgd 179: };
180:
1.117 msaitoh 181: /*
182: * Class 0x04.
183: * Multimedia device.
184: */
1.61 thorpej 185: static const struct pci_class pci_subclass_multimedia[] = {
1.65 christos 186: { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
187: { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
188: { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
1.128 msaitoh 189: { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
1.65 christos 190: { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
191: { NULL, 0, NULL, },
1.10 cgd 192: };
193:
1.117 msaitoh 194: /*
195: * Class 0x05.
196: * Memory controller.
197: */
1.61 thorpej 198: static const struct pci_class pci_subclass_memory[] = {
1.65 christos 199: { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, },
200: { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, },
201: { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, },
202: { NULL, 0, NULL, },
1.10 cgd 203: };
204:
1.117 msaitoh 205: /*
206: * Class 0x06.
207: * Bridge device.
208: */
209:
210: /* PCI bridge programming interface */
211: static const struct pci_class pci_interface_pcibridge[] = {
212: { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, },
213: { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, },
214: { NULL, 0, NULL, },
215: };
216:
1.128 msaitoh 217: /* Semi-transparent PCI-to-PCI bridge programming interface */
1.117 msaitoh 218: static const struct pci_class pci_interface_stpci[] = {
219: { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, },
220: { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, },
221: { NULL, 0, NULL, },
222: };
223:
1.128 msaitoh 224: /* Advanced Switching programming interface */
225: static const struct pci_class pci_interface_advsw[] = {
226: { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
227: { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, },
228: { NULL, 0, NULL, },
229: };
230:
1.117 msaitoh 231: /* Subclasses */
1.61 thorpej 232: static const struct pci_class pci_subclass_bridge[] = {
1.65 christos 233: { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, },
234: { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, },
235: { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, },
236: { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, },
1.117 msaitoh 237: { "PCI", PCI_SUBCLASS_BRIDGE_PCI,
238: pci_interface_pcibridge, },
1.65 christos 239: { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, },
240: { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, },
241: { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, },
242: { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, },
1.117 msaitoh 243: { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,
244: pci_interface_stpci, },
1.65 christos 245: { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, },
1.128 msaitoh 246: { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW,
247: pci_interface_advsw, },
1.65 christos 248: { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, },
249: { NULL, 0, NULL, },
1.10 cgd 250: };
251:
1.117 msaitoh 252: /*
253: * Class 0x07.
254: * Simple communications controller.
255: */
256:
257: /* Serial controller programming interface */
258: static const struct pci_class pci_interface_serial[] = {
1.129 msaitoh 259: { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, },
1.117 msaitoh 260: { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, },
261: { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, },
262: { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, },
263: { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, },
264: { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, },
265: { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, },
266: { NULL, 0, NULL, },
267: };
268:
269: /* Parallel controller programming interface */
270: static const struct pci_class pci_interface_parallel[] = {
271: { "", PCI_INTERFACE_PARALLEL, NULL,},
272: { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,},
273: { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,},
1.128 msaitoh 274: { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,},
275: { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,},
1.117 msaitoh 276: { NULL, 0, NULL,},
277: };
278:
279: /* Modem programming interface */
280: static const struct pci_class pci_interface_modem[] = {
281: { "", PCI_INTERFACE_MODEM, NULL,},
282: { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,},
283: { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,},
284: { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,},
285: { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,},
286: { NULL, 0, NULL,},
287: };
288:
289: /* Subclasses */
1.61 thorpej 290: static const struct pci_class pci_subclass_communications[] = {
1.117 msaitoh 291: { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL,
292: pci_interface_serial, },
293: { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL,
294: pci_interface_parallel, },
1.115 msaitoh 295: { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,},
1.117 msaitoh 296: { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM,
297: pci_interface_modem, },
1.115 msaitoh 298: { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,},
299: { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,},
300: { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,},
301: { NULL, 0, NULL,},
1.20 cgd 302: };
303:
1.117 msaitoh 304: /*
305: * Class 0x08.
306: * Base system peripheral.
307: */
308:
309: /* PIC programming interface */
310: static const struct pci_class pci_interface_pic[] = {
1.129 msaitoh 311: { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, },
1.117 msaitoh 312: { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, },
313: { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, },
314: { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, },
315: { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, },
316: { NULL, 0, NULL, },
317: };
318:
319: /* DMA programming interface */
320: static const struct pci_class pci_interface_dma[] = {
1.129 msaitoh 321: { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, },
1.117 msaitoh 322: { "ISA", PCI_INTERFACE_DMA_ISA, NULL, },
323: { "EISA", PCI_INTERFACE_DMA_EISA, NULL, },
324: { NULL, 0, NULL, },
325: };
326:
327: /* Timer programming interface */
328: static const struct pci_class pci_interface_tmr[] = {
1.129 msaitoh 329: { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, },
1.117 msaitoh 330: { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, },
331: { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, },
1.128 msaitoh 332: { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, },
1.117 msaitoh 333: { NULL, 0, NULL, },
334: };
335:
336: /* RTC programming interface */
337: static const struct pci_class pci_interface_rtc[] = {
338: { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, },
339: { "ISA", PCI_INTERFACE_RTC_ISA, NULL, },
340: { NULL, 0, NULL, },
341: };
342:
343: /* Subclasses */
1.61 thorpej 344: static const struct pci_class pci_subclass_system[] = {
1.117 msaitoh 345: { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,},
346: { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,},
347: { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,},
348: { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,},
1.65 christos 349: { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, },
350: { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, },
1.124 msaitoh 351: { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, },
352: { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, },
1.65 christos 353: { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, },
354: { NULL, 0, NULL, },
1.20 cgd 355: };
356:
1.117 msaitoh 357: /*
358: * Class 0x09.
359: * Input device.
360: */
361:
362: /* Gameport programming interface */
363: static const struct pci_class pci_interface_game[] = {
364: { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, },
365: { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, },
366: { NULL, 0, NULL, },
367: };
368:
369: /* Subclasses */
1.61 thorpej 370: static const struct pci_class pci_subclass_input[] = {
1.65 christos 371: { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, },
372: { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, },
373: { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, },
374: { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, },
1.117 msaitoh 375: { "game port", PCI_SUBCLASS_INPUT_GAMEPORT,
376: pci_interface_game, },
1.65 christos 377: { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, },
378: { NULL, 0, NULL, },
1.20 cgd 379: };
380:
1.117 msaitoh 381: /*
382: * Class 0x0a.
383: * Docking station.
384: */
1.61 thorpej 385: static const struct pci_class pci_subclass_dock[] = {
1.65 christos 386: { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, },
387: { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, },
388: { NULL, 0, NULL, },
1.20 cgd 389: };
390:
1.117 msaitoh 391: /*
392: * Class 0x0b.
393: * Processor.
394: */
1.61 thorpej 395: static const struct pci_class pci_subclass_processor[] = {
1.65 christos 396: { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, },
397: { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, },
398: { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, },
399: { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, },
400: { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, },
401: { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, },
402: { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, },
1.128 msaitoh 403: { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, },
1.65 christos 404: { NULL, 0, NULL, },
1.20 cgd 405: };
406:
1.117 msaitoh 407: /*
408: * Class 0x0c.
409: * Serial bus controller.
410: */
411:
412: /* IEEE1394 programming interface */
413: static const struct pci_class pci_interface_ieee1394[] = {
414: { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,},
415: { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,},
416: { NULL, 0, NULL,},
417: };
418:
419: /* USB programming interface */
420: static const struct pci_class pci_interface_usb[] = {
421: { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, },
422: { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, },
423: { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, },
424: { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, },
425: { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, },
426: { "device", PCI_INTERFACE_USB_DEVICE, NULL, },
427: { NULL, 0, NULL, },
428: };
429:
430: /* IPMI programming interface */
431: static const struct pci_class pci_interface_ipmi[] = {
432: { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,},
433: { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,},
434: { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,},
435: { NULL, 0, NULL,},
436: };
437:
438: /* Subclasses */
1.61 thorpej 439: static const struct pci_class pci_subclass_serialbus[] = {
1.117 msaitoh 440: { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE,
441: pci_interface_ieee1394, },
1.65 christos 442: { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, },
443: { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, },
1.117 msaitoh 444: { "USB", PCI_SUBCLASS_SERIALBUS_USB,
445: pci_interface_usb, },
1.32 cgd 446: /* XXX Fiber Channel/_FIBRECHANNEL */
1.65 christos 447: { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, },
448: { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, },
449: { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,},
1.117 msaitoh 450: { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI,
451: pci_interface_ipmi, },
1.65 christos 452: { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, },
453: { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, },
1.114 msaitoh 454: { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, },
1.65 christos 455: { NULL, 0, NULL, },
1.32 cgd 456: };
457:
1.117 msaitoh 458: /*
459: * Class 0x0d.
460: * Wireless Controller.
461: */
1.61 thorpej 462: static const struct pci_class pci_subclass_wireless[] = {
1.65 christos 463: { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, },
1.128 msaitoh 464: { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
1.65 christos 465: { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, },
466: { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, },
467: { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
468: { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, },
469: { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, },
470: { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, },
471: { NULL, 0, NULL, },
1.32 cgd 472: };
473:
1.117 msaitoh 474: /*
475: * Class 0x0e.
476: * Intelligent IO controller.
477: */
478:
479: /* Intelligent IO programming interface */
480: static const struct pci_class pci_interface_i2o[] = {
481: { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,},
482: { NULL, 0, NULL,},
483: };
484:
485: /* Subclasses */
1.61 thorpej 486: static const struct pci_class pci_subclass_i2o[] = {
1.117 msaitoh 487: { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,},
1.114 msaitoh 488: { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, },
1.65 christos 489: { NULL, 0, NULL, },
1.32 cgd 490: };
491:
1.117 msaitoh 492: /*
493: * Class 0x0f.
494: * Satellite communication controller.
495: */
1.61 thorpej 496: static const struct pci_class pci_subclass_satcom[] = {
1.65 christos 497: { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, },
498: { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, },
499: { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, },
500: { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, },
1.114 msaitoh 501: { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, },
1.65 christos 502: { NULL, 0, NULL, },
1.32 cgd 503: };
504:
1.117 msaitoh 505: /*
506: * Class 0x10.
507: * Encryption/Decryption controller.
508: */
1.61 thorpej 509: static const struct pci_class pci_subclass_crypto[] = {
1.65 christos 510: { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, },
511: { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
512: { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, },
513: { NULL, 0, NULL, },
1.32 cgd 514: };
515:
1.117 msaitoh 516: /*
517: * Class 0x11.
518: * Data aquuisition and signal processing controller.
519: */
1.61 thorpej 520: static const struct pci_class pci_subclass_dasp[] = {
1.65 christos 521: { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, },
1.128 msaitoh 522: { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, },
1.65 christos 523: { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, },
524: { "management", PCI_SUBCLASS_DASP_MGMT, NULL, },
525: { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, },
526: { NULL, 0, NULL, },
1.20 cgd 527: };
528:
1.117 msaitoh 529: /* List of classes */
1.163 msaitoh 530: static const struct pci_class pci_classes[] = {
1.10 cgd 531: { "prehistoric", PCI_CLASS_PREHISTORIC,
532: pci_subclass_prehistoric, },
533: { "mass storage", PCI_CLASS_MASS_STORAGE,
534: pci_subclass_mass_storage, },
535: { "network", PCI_CLASS_NETWORK,
536: pci_subclass_network, },
537: { "display", PCI_CLASS_DISPLAY,
1.11 cgd 538: pci_subclass_display, },
1.10 cgd 539: { "multimedia", PCI_CLASS_MULTIMEDIA,
540: pci_subclass_multimedia, },
541: { "memory", PCI_CLASS_MEMORY,
542: pci_subclass_memory, },
543: { "bridge", PCI_CLASS_BRIDGE,
544: pci_subclass_bridge, },
1.20 cgd 545: { "communications", PCI_CLASS_COMMUNICATIONS,
546: pci_subclass_communications, },
547: { "system", PCI_CLASS_SYSTEM,
548: pci_subclass_system, },
549: { "input", PCI_CLASS_INPUT,
550: pci_subclass_input, },
551: { "dock", PCI_CLASS_DOCK,
552: pci_subclass_dock, },
553: { "processor", PCI_CLASS_PROCESSOR,
554: pci_subclass_processor, },
555: { "serial bus", PCI_CLASS_SERIALBUS,
556: pci_subclass_serialbus, },
1.32 cgd 557: { "wireless", PCI_CLASS_WIRELESS,
558: pci_subclass_wireless, },
559: { "I2O", PCI_CLASS_I2O,
560: pci_subclass_i2o, },
561: { "satellite comm", PCI_CLASS_SATCOM,
562: pci_subclass_satcom, },
563: { "crypto", PCI_CLASS_CRYPTO,
564: pci_subclass_crypto, },
565: { "DASP", PCI_CLASS_DASP,
566: pci_subclass_dasp, },
1.164 msaitoh 567: { "processing accelerators", PCI_CLASS_ACCEL,
568: NULL, },
569: { "non-essential instrumentation", PCI_CLASS_INSTRUMENT,
570: NULL, },
1.10 cgd 571: { "undefined", PCI_CLASS_UNDEFINED,
1.65 christos 572: NULL, },
573: { NULL, 0,
574: NULL, },
1.10 cgd 575: };
576:
1.126 christos 577: DEV_VERBOSE_DEFINE(pci);
1.10 cgd 578:
1.155 pgoyette 579: /*
580: * Append a formatted string to dest without writing more than len
581: * characters (including the trailing NUL character). dest and len
582: * are updated for use in subsequent calls to snappendf().
583: *
584: * Returns 0 on success, a negative value if vnsprintf() fails, or
585: * a positive value if the dest buffer would have overflowed.
586: */
587:
588: static int __printflike(3,4)
589: snappendf(char **dest, size_t *len, const char * restrict fmt, ...)
590: {
591: va_list ap;
592: int count;
593:
594: va_start(ap, fmt);
595: count = vsnprintf(*dest, *len, fmt, ap);
596: va_end(ap);
597:
598: /* Let vsnprintf() errors bubble up to caller */
599: if (count < 0 || *len == 0)
600: return count;
601:
602: /* Handle overflow */
603: if ((size_t)count >= *len) {
604: *dest += *len - 1;
605: *len = 1;
606: return 1;
607: }
608:
609: /* Update dest & len to point at trailing NUL */
610: *dest += count;
611: *len -= count;
612:
613: return 0;
614: }
615:
1.10 cgd 616: void
1.58 itojun 617: pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp,
618: size_t l)
1.10 cgd 619: {
1.163 msaitoh 620: pci_class_t class;
1.10 cgd 621: pci_subclass_t subclass;
622: pci_interface_t interface;
623: pci_revision_t revision;
1.126 christos 624: char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
1.117 msaitoh 625: const struct pci_class *classp, *subclassp, *interfacep;
1.10 cgd 626:
1.163 msaitoh 627: class = PCI_CLASS(class_reg);
1.10 cgd 628: subclass = PCI_SUBCLASS(class_reg);
629: interface = PCI_INTERFACE(class_reg);
630: revision = PCI_REVISION(class_reg);
631:
1.126 christos 632: pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg));
633: pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg),
634: PCI_PRODUCT(id_reg));
1.10 cgd 635:
1.163 msaitoh 636: classp = pci_classes;
1.10 cgd 637: while (classp->name != NULL) {
1.163 msaitoh 638: if (class == classp->val)
1.10 cgd 639: break;
640: classp++;
641: }
642:
643: subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
644: while (subclassp && subclassp->name != NULL) {
645: if (subclass == subclassp->val)
646: break;
647: subclassp++;
648: }
649:
1.119 njoly 650: interfacep = (subclassp && subclassp->name != NULL) ?
651: subclassp->subclasses : NULL;
1.117 msaitoh 652: while (interfacep && interfacep->name != NULL) {
653: if (interface == interfacep->val)
654: break;
655: interfacep++;
656: }
657:
1.155 pgoyette 658: (void)snappendf(&cp, &l, "%s %s", vendor, product);
1.13 cgd 659: if (showclass) {
1.155 pgoyette 660: (void)snappendf(&cp, &l, " (");
1.13 cgd 661: if (classp->name == NULL)
1.155 pgoyette 662: (void)snappendf(&cp, &l,
663: "class 0x%02x, subclass 0x%02x",
1.163 msaitoh 664: class, subclass);
1.13 cgd 665: else {
666: if (subclassp == NULL || subclassp->name == NULL)
1.155 pgoyette 667: (void)snappendf(&cp, &l,
1.78 drochner 668: "%s, subclass 0x%02x",
1.20 cgd 669: classp->name, subclass);
1.13 cgd 670: else
1.155 pgoyette 671: (void)snappendf(&cp, &l, "%s %s",
1.20 cgd 672: subclassp->name, classp->name);
1.13 cgd 673: }
1.117 msaitoh 674: if ((interfacep == NULL) || (interfacep->name == NULL)) {
675: if (interface != 0)
1.155 pgoyette 676: (void)snappendf(&cp, &l, ", interface 0x%02x",
677: interface);
1.117 msaitoh 678: } else if (strncmp(interfacep->name, "", 1) != 0)
1.155 pgoyette 679: (void)snappendf(&cp, &l, ", %s", interfacep->name);
1.20 cgd 680: if (revision != 0)
1.155 pgoyette 681: (void)snappendf(&cp, &l, ", revision 0x%02x", revision);
682: (void)snappendf(&cp, &l, ")");
1.13 cgd 683: }
1.22 thorpej 684: }
685:
1.89 drochner 686: #ifdef _KERNEL
687: void
1.90 drochner 688: pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive,
689: const char *known, int addrev)
1.89 drochner 690: {
691: char devinfo[256];
692:
1.90 drochner 693: if (known) {
694: aprint_normal(": %s", known);
695: if (addrev)
696: aprint_normal(" (rev. 0x%02x)",
697: PCI_REVISION(pa->pa_class));
698: aprint_normal("\n");
699: } else {
700: pci_devinfo(pa->pa_id, pa->pa_class, 0,
701: devinfo, sizeof(devinfo));
702: aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
703: PCI_REVISION(pa->pa_class));
704: }
705: if (naive)
706: aprint_naive(": %s\n", naive);
707: else
708: aprint_naive("\n");
1.89 drochner 709: }
710: #endif
711:
1.22 thorpej 712: /*
713: * Print out most of the PCI configuration registers. Typically used
714: * in a device attach routine like this:
715: *
716: * #ifdef MYDEV_DEBUG
1.95 chs 717: * printf("%s: ", device_xname(sc->sc_dev));
1.43 enami 718: * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
1.22 thorpej 719: * #endif
720: */
1.26 cgd 721:
722: #define i2o(i) ((i) * 4)
723: #define o2i(o) ((o) / 4)
1.112 msaitoh 724: #define onoff2(str, rval, bit, onstr, offstr) \
725: printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr);
726: #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off")
1.26 cgd 727:
728: static void
1.45 thorpej 729: pci_conf_print_common(
730: #ifdef _KERNEL
1.71 christos 731: pci_chipset_tag_t pc, pcitag_t tag,
1.45 thorpej 732: #endif
733: const pcireg_t *regs)
1.22 thorpej 734: {
1.163 msaitoh 735: pci_class_t class;
736: pci_subclass_t subclass;
737: pci_interface_t interface;
738: pci_revision_t revision;
739: char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
1.165 msaitoh 740: const struct pci_class *classp, *subclassp, *interfacep;
1.59 mycroft 741: const char *name;
1.26 cgd 742: pcireg_t rval;
1.117 msaitoh 743: unsigned int num;
1.22 thorpej 744:
1.163 msaitoh 745: rval = regs[o2i(PCI_CLASS_REG)];
746: class = PCI_CLASS(rval);
747: subclass = PCI_SUBCLASS(rval);
748: interface = PCI_INTERFACE(rval);
749: revision = PCI_REVISION(rval);
750:
1.26 cgd 751: rval = regs[o2i(PCI_ID_REG)];
1.126 christos 752: name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval));
1.59 mycroft 753: if (name)
754: printf(" Vendor Name: %s (0x%04x)\n", name,
1.26 cgd 755: PCI_VENDOR(rval));
1.22 thorpej 756: else
1.26 cgd 757: printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
1.126 christos 758: name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval),
759: PCI_PRODUCT(rval));
1.59 mycroft 760: if (name)
761: printf(" Device Name: %s (0x%04x)\n", name,
1.26 cgd 762: PCI_PRODUCT(rval));
1.22 thorpej 763: else
1.26 cgd 764: printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
1.22 thorpej 765:
1.26 cgd 766: rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
1.23 drochner 767:
1.26 cgd 768: printf(" Command register: 0x%04x\n", rval & 0xffff);
1.112 msaitoh 769: onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
770: onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE);
771: onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
772: onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE);
773: onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE);
774: onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE);
775: onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
776: onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
777: onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
1.115 msaitoh 778: onoff("Fast back-to-back transactions", rval,
779: PCI_COMMAND_BACKTOBACK_ENABLE);
1.112 msaitoh 780: onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
1.26 cgd 781:
782: printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff);
1.172 msaitoh 783: onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS);
1.115 msaitoh 784: onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
785: "inactive");
1.112 msaitoh 786: onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
787: onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
1.115 msaitoh 788: onoff("User Definable Features (UDF) support", rval,
789: PCI_STATUS_UDF_SUPPORT);
790: onoff("Fast back-to-back capable", rval,
791: PCI_STATUS_BACKTOBACK_SUPPORT);
1.112 msaitoh 792: onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
1.22 thorpej 793:
1.26 cgd 794: printf(" DEVSEL timing: ");
1.22 thorpej 795: switch (rval & PCI_STATUS_DEVSEL_MASK) {
796: case PCI_STATUS_DEVSEL_FAST:
797: printf("fast");
798: break;
799: case PCI_STATUS_DEVSEL_MEDIUM:
800: printf("medium");
801: break;
802: case PCI_STATUS_DEVSEL_SLOW:
803: printf("slow");
804: break;
1.26 cgd 805: default:
806: printf("unknown/reserved"); /* XXX */
807: break;
1.22 thorpej 808: }
1.159 msaitoh 809: printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK));
1.22 thorpej 810:
1.115 msaitoh 811: onoff("Slave signaled Target Abort", rval,
812: PCI_STATUS_TARGET_TARGET_ABORT);
813: onoff("Master received Target Abort", rval,
814: PCI_STATUS_MASTER_TARGET_ABORT);
1.112 msaitoh 815: onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
816: onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
817: onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
1.22 thorpej 818:
1.26 cgd 819: rval = regs[o2i(PCI_CLASS_REG)];
1.163 msaitoh 820: for (classp = pci_classes; classp->name != NULL; classp++) {
821: if (class == classp->val)
1.22 thorpej 822: break;
823: }
1.166 msaitoh 824:
825: /*
826: * ECN: Change Root Complex Event Collector Class Code
827: * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type
828: * in PCIe extend capability to know whether it's RCEC or IOMMU.
829: */
830: if ((class == PCI_CLASS_SYSTEM)
831: && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) {
832: int pcie_capoff;
833: pcireg_t reg;
834:
1.183.2.4 snj 835: if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
1.166 msaitoh 836: reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
837: if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
838: subclass = PCI_SUBCLASS_SYSTEM_RCEC;
839: }
840: }
1.22 thorpej 841: subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
842: while (subclassp && subclassp->name != NULL) {
1.163 msaitoh 843: if (subclass == subclassp->val)
1.22 thorpej 844: break;
845: subclassp++;
846: }
1.166 msaitoh 847:
1.165 msaitoh 848: interfacep = (subclassp && subclassp->name != NULL) ?
849: subclassp->subclasses : NULL;
850: while (interfacep && interfacep->name != NULL) {
851: if (interface == interfacep->val)
852: break;
853: interfacep++;
854: }
855:
856: if (classp->name != NULL)
1.163 msaitoh 857: printf(" Class Name: %s (0x%02x)\n", classp->name, class);
1.165 msaitoh 858: else
1.163 msaitoh 859: printf(" Class ID: 0x%02x\n", class);
1.165 msaitoh 860: if (subclassp != NULL && subclassp->name != NULL)
861: printf(" Subclass Name: %s (0x%02x)\n",
862: subclassp->name, PCI_SUBCLASS(rval));
863: else
864: printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
865: if ((interfacep != NULL) && (interfacep->name != NULL)
866: && (strncmp(interfacep->name, "", 1) != 0))
867: printf(" Interface Name: %s (0x%02x)\n",
868: interfacep->name, interface);
869: else
870: printf(" Interface: 0x%02x\n", interface);
1.163 msaitoh 871: printf(" Revision ID: 0x%02x\n", revision);
1.22 thorpej 872:
1.26 cgd 873: rval = regs[o2i(PCI_BHLC_REG)];
874: printf(" BIST: 0x%02x\n", PCI_BIST(rval));
875: printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
876: PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
877: PCI_HDRTYPE(rval));
878: printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
1.117 msaitoh 879: num = PCI_CACHELINE(rval);
880: printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num);
1.26 cgd 881: }
1.22 thorpej 882:
1.37 nathanw 883: static int
1.45 thorpej 884: pci_conf_print_bar(
885: #ifdef _KERNEL
886: pci_chipset_tag_t pc, pcitag_t tag,
887: #endif
1.167 msaitoh 888: const pcireg_t *regs, int reg, const char *name)
1.26 cgd 889: {
1.45 thorpej 890: int width;
891: pcireg_t rval, rval64h;
1.167 msaitoh 892: bool ioen, memen;
1.168 msaitoh 893: #ifdef _KERNEL
1.167 msaitoh 894: pcireg_t mask, mask64h = 0;
1.168 msaitoh 895: #endif
1.167 msaitoh 896:
897: rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
898: ioen = rval & PCI_COMMAND_IO_ENABLE;
899: memen = rval & PCI_COMMAND_MEM_ENABLE;
1.45 thorpej 900:
1.37 nathanw 901: width = 4;
1.27 cgd 902: /*
903: * Section 6.2.5.1, `Address Maps', tells us that:
904: *
905: * 1) The builtin software should have already mapped the
906: * device in a reasonable way.
907: *
908: * 2) A device which wants 2^n bytes of memory will hardwire
909: * the bottom n bits of the address to 0. As recommended,
910: * we write all 1s and see what we get back.
911: */
1.45 thorpej 912:
1.27 cgd 913: rval = regs[o2i(reg)];
1.45 thorpej 914: if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
915: PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
916: rval64h = regs[o2i(reg + 4)];
917: width = 8;
918: } else
919: rval64h = 0;
920:
921: #ifdef _KERNEL
1.167 msaitoh 922: if (rval != 0 && memen) {
923: int s;
924:
1.24 thorpej 925: /*
1.27 cgd 926: * The following sequence seems to make some devices
927: * (e.g. host bus bridges, which don't normally
928: * have their space mapped) very unhappy, to
929: * the point of crashing the system.
1.24 thorpej 930: *
1.27 cgd 931: * Therefore, if the mapping register is zero to
932: * start out with, don't bother trying.
1.24 thorpej 933: */
1.27 cgd 934: s = splhigh();
935: pci_conf_write(pc, tag, reg, 0xffffffff);
936: mask = pci_conf_read(pc, tag, reg);
937: pci_conf_write(pc, tag, reg, rval);
1.37 nathanw 938: if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
939: PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
940: pci_conf_write(pc, tag, reg + 4, 0xffffffff);
941: mask64h = pci_conf_read(pc, tag, reg + 4);
942: pci_conf_write(pc, tag, reg + 4, rval64h);
1.167 msaitoh 943: }
1.27 cgd 944: splx(s);
945: } else
1.168 msaitoh 946: mask = mask64h = 0;
1.45 thorpej 947: #endif /* _KERNEL */
1.27 cgd 948:
1.28 cgd 949: printf(" Base address register at 0x%02x", reg);
950: if (name)
951: printf(" (%s)", name);
952: printf("\n ");
1.27 cgd 953: if (rval == 0) {
1.167 msaitoh 954: printf("not implemented\n");
1.37 nathanw 955: return width;
1.60 perry 956: }
1.28 cgd 957: printf("type: ");
958: if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
1.34 drochner 959: const char *type, *prefetch;
1.27 cgd 960:
961: switch (PCI_MAPREG_MEM_TYPE(rval)) {
962: case PCI_MAPREG_MEM_TYPE_32BIT:
963: type = "32-bit";
964: break;
965: case PCI_MAPREG_MEM_TYPE_32BIT_1M:
966: type = "32-bit-1M";
967: break;
968: case PCI_MAPREG_MEM_TYPE_64BIT:
969: type = "64-bit";
970: break;
971: default:
972: type = "unknown (XXX)";
973: break;
1.22 thorpej 974: }
1.34 drochner 975: if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
976: prefetch = "";
1.27 cgd 977: else
1.34 drochner 978: prefetch = "non";
979: printf("%s %sprefetchable memory\n", type, prefetch);
1.37 nathanw 980: switch (PCI_MAPREG_MEM_TYPE(rval)) {
981: case PCI_MAPREG_MEM_TYPE_64BIT:
1.168 msaitoh 982: printf(" base: 0x%016llx",
1.37 nathanw 983: PCI_MAPREG_MEM64_ADDR(
1.38 cgd 984: ((((long long) rval64h) << 32) | rval)));
1.167 msaitoh 985: if (!memen)
986: printf(", disabled");
1.38 cgd 987: printf("\n");
1.168 msaitoh 988: #ifdef _KERNEL
989: printf(" size: 0x%016llx\n",
990: PCI_MAPREG_MEM64_SIZE(
991: ((((long long) mask64h) << 32) | mask)));
992: #endif
1.37 nathanw 993: break;
994: case PCI_MAPREG_MEM_TYPE_32BIT:
995: case PCI_MAPREG_MEM_TYPE_32BIT_1M:
996: default:
1.168 msaitoh 997: printf(" base: 0x%08x",
998: PCI_MAPREG_MEM_ADDR(rval));
1.167 msaitoh 999: if (!memen)
1000: printf(", disabled");
1.38 cgd 1001: printf("\n");
1.168 msaitoh 1002: #ifdef _KERNEL
1003: printf(" size: 0x%08x\n",
1004: PCI_MAPREG_MEM_SIZE(mask));
1005: #endif
1.37 nathanw 1006: break;
1007: }
1.27 cgd 1008: } else {
1.168 msaitoh 1009: #ifdef _KERNEL
1010: if (ioen)
1011: printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
1012: #endif
1013: printf("I/O\n");
1014: printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval));
1.167 msaitoh 1015: if (!ioen)
1016: printf(", disabled");
1.38 cgd 1017: printf("\n");
1.168 msaitoh 1018: #ifdef _KERNEL
1019: printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask));
1020: #endif
1.22 thorpej 1021: }
1.37 nathanw 1022:
1023: return width;
1.27 cgd 1024: }
1.28 cgd 1025:
1026: static void
1.44 thorpej 1027: pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
1.28 cgd 1028: {
1029: int off, needaddr, neednl;
1030:
1031: needaddr = 1;
1032: neednl = 0;
1033: for (off = first; off < pastlast; off += 4) {
1034: if ((off % 16) == 0 || needaddr) {
1035: printf(" 0x%02x:", off);
1036: needaddr = 0;
1037: }
1038: printf(" 0x%08x", regs[o2i(off)]);
1039: neednl = 1;
1040: if ((off % 16) == 12) {
1041: printf("\n");
1042: neednl = 0;
1043: }
1044: }
1045: if (neednl)
1046: printf("\n");
1047: }
1048:
1.161 msaitoh 1049: static const char *
1050: pci_conf_print_agp_calcycle(uint8_t cal)
1051: {
1052:
1053: switch (cal) {
1054: case 0x0:
1055: return "4ms";
1056: case 0x1:
1057: return "16ms";
1058: case 0x2:
1059: return "64ms";
1060: case 0x3:
1061: return "256ms";
1062: case 0x7:
1063: return "Calibration Cycle Not Needed";
1064: default:
1065: return "(reserved)";
1066: }
1067: }
1068:
1069: static void
1070: pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3)
1071: {
1072: if (isagp3) {
1073: /* AGP 3.0 */
1074: if (reg & AGP_MODE_V3_RATE_4x)
1075: printf("x4");
1076: if (reg & AGP_MODE_V3_RATE_8x)
1077: printf("x8");
1078: } else {
1079: /* AGP 2.0 */
1080: if (reg & AGP_MODE_V2_RATE_1x)
1081: printf("x1");
1082: if (reg & AGP_MODE_V2_RATE_2x)
1083: printf("x2");
1084: if (reg & AGP_MODE_V2_RATE_4x)
1085: printf("x4");
1086: }
1087: printf("\n");
1088: }
1089:
1.132 msaitoh 1090: static void
1091: pci_conf_print_agp_cap(const pcireg_t *regs, int capoff)
1092: {
1093: pcireg_t rval;
1.161 msaitoh 1094: bool isagp3;
1.132 msaitoh 1095:
1096: printf("\n AGP Capabilities Register\n");
1097:
1098: rval = regs[o2i(capoff)];
1099: printf(" Revision: %d.%d\n",
1100: PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval));
1101:
1.161 msaitoh 1102: rval = regs[o2i(capoff + PCI_AGP_STATUS)];
1103: printf(" Status register: 0x%04x\n", rval);
1104: printf(" RQ: %d\n",
1105: (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1);
1106: printf(" ARQSZ: %d\n",
1107: (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ));
1108: printf(" CAL cycle: %s\n",
1109: pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL)));
1110: onoff("SBA", rval, AGP_MODE_SBA);
1111: onoff("htrans#", rval, AGP_MODE_HTRANS);
1112: onoff("Over 4G", rval, AGP_MODE_4G);
1113: onoff("Fast Write", rval, AGP_MODE_FW);
1114: onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3);
1115: isagp3 = rval & AGP_MODE_MODE_3;
1116: printf(" Data Rate Support: ");
1117: pci_conf_print_agp_datarate(rval, isagp3);
1118:
1119: rval = regs[o2i(capoff + PCI_AGP_COMMAND)];
1120: printf(" Command register: 0x%08x\n", rval);
1121: printf(" PRQ: %d\n",
1122: (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1);
1123: printf(" PARQSZ: %d\n",
1124: (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ));
1125: printf(" PCAL cycle: %s\n",
1126: pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL)));
1127: onoff("SBA", rval, AGP_MODE_SBA);
1128: onoff("AGP", rval, AGP_MODE_AGP);
1129: onoff("Over 4G", rval, AGP_MODE_4G);
1130: onoff("Fast Write", rval, AGP_MODE_FW);
1131: if (isagp3) {
1132: printf(" Data Rate Enable: ");
1133: /*
1134: * The Data Rate Enable bits are used only on 3.0 and the
1135: * Command register has no AGP_MODE_MODE_3 bit, so pass the
1136: * flag to print correctly.
1137: */
1138: pci_conf_print_agp_datarate(rval, isagp3);
1139: }
1.132 msaitoh 1140: }
1141:
1.115 msaitoh 1142: static const char *
1143: pci_conf_print_pcipm_cap_aux(uint16_t caps)
1144: {
1145:
1146: switch ((caps >> 6) & 7) {
1147: case 0: return "self-powered";
1148: case 1: return "55 mA";
1149: case 2: return "100 mA";
1150: case 3: return "160 mA";
1151: case 4: return "220 mA";
1152: case 5: return "270 mA";
1153: case 6: return "320 mA";
1154: case 7:
1155: default: return "375 mA";
1156: }
1157: }
1158:
1159: static const char *
1160: pci_conf_print_pcipm_cap_pmrev(uint8_t val)
1161: {
1162: static const char unk[] = "unknown";
1163: static const char *pmrev[8] = {
1164: unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
1165: };
1166: if (val > 7)
1167: return unk;
1168: return pmrev[val];
1169: }
1170:
1.27 cgd 1171: static void
1.115 msaitoh 1172: pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
1.27 cgd 1173: {
1.115 msaitoh 1174: uint16_t caps, pmcsr;
1175:
1176: caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
1.183.2.6 snj 1177: pmcsr = regs[o2i(capoff + PCI_PMCSR)];
1.115 msaitoh 1178:
1179: printf("\n PCI Power Management Capabilities Register\n");
1.27 cgd 1180:
1.115 msaitoh 1181: printf(" Capabilities register: 0x%04x\n", caps);
1182: printf(" Version: %s\n",
1183: pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK));
1184: onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
1185: onoff("Device specific initialization", caps, PCI_PMCR_DSI);
1186: printf(" 3.3V auxiliary current: %s\n",
1187: pci_conf_print_pcipm_cap_aux(caps));
1188: onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
1189: onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
1.117 msaitoh 1190: onoff("PME# support D0", caps, PCI_PMCR_PME_D0);
1191: onoff("PME# support D1", caps, PCI_PMCR_PME_D1);
1192: onoff("PME# support D2", caps, PCI_PMCR_PME_D2);
1193: onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT);
1194: onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD);
1.22 thorpej 1195:
1.183.2.6 snj 1196: printf(" Control/status register: 0x%08x\n", pmcsr);
1.115 msaitoh 1197: printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
1198: onoff("PCI Express reserved", (pmcsr >> 2), 1);
1.117 msaitoh 1199: onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST);
1.115 msaitoh 1200: printf(" PME# assertion: %sabled\n",
1201: (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
1.157 msaitoh 1202: printf(" Data Select: %d\n",
1203: __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK));
1204: printf(" Data Scale: %d\n",
1205: __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK));
1.115 msaitoh 1206: onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
1207: printf(" Bridge Support Extensions register: 0x%02x\n",
1.183.2.6 snj 1208: (pmcsr >> 16) & 0xff);
1209: onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT);
1210: onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN);
1211: printf(" Data register: 0x%02x\n",
1212: __SHIFTOUT(pmcsr, PCI_PMCSR_DATA));
1.115 msaitoh 1213: }
1.22 thorpej 1214:
1.115 msaitoh 1215: /* XXX pci_conf_print_vpd_cap */
1216: /* XXX pci_conf_print_slotid_cap */
1.26 cgd 1217:
1.115 msaitoh 1218: static void
1219: pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
1220: {
1221: uint32_t ctl, mmc, mme;
1.33 kleink 1222:
1.115 msaitoh 1223: regs += o2i(capoff);
1224: ctl = *regs++;
1225: mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
1226: mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
1.33 kleink 1227:
1.115 msaitoh 1228: printf("\n PCI Message Signaled Interrupt\n");
1.26 cgd 1229:
1.115 msaitoh 1230: printf(" Message Control register: 0x%04x\n", ctl >> 16);
1231: onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
1232: printf(" Multiple Message Capable: %s (%d vector%s)\n",
1233: mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : "");
1234: printf(" Multiple Message Enabled: %s (%d vector%s)\n",
1235: mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
1236: onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
1237: onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
1.152 msaitoh 1238: onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP);
1239: onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN);
1.115 msaitoh 1240: printf(" Message Address %sregister: 0x%08x\n",
1241: ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
1242: if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
1243: printf(" Message Address %sregister: 0x%08x\n",
1244: "(upper) ", *regs++);
1245: }
1.183 msaitoh 1246: printf(" Message Data register: ");
1247: if (ctl & PCI_MSI_CTL_EXTMDATA_CAP)
1248: printf("0x%08x\n", *regs);
1249: else
1250: printf("0x%04x\n", *regs & 0xffff);
1.157 msaitoh 1251: regs++;
1.115 msaitoh 1252: if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
1253: printf(" Vector Mask register: 0x%08x\n", *regs++);
1254: printf(" Vector Pending register: 0x%08x\n", *regs++);
1.22 thorpej 1255: }
1.51 drochner 1256: }
1257:
1.115 msaitoh 1258: /* XXX pci_conf_print_cpci_hostwap_cap */
1.122 msaitoh 1259:
1260: /*
1261: * For both command register and status register.
1262: * The argument "idx" is index number (0 to 7).
1263: */
1264: static int
1265: pcix_split_trans(unsigned int idx)
1266: {
1267: static int table[8] = {
1268: 1, 2, 3, 4, 8, 12, 16, 32
1269: };
1270:
1271: if (idx >= __arraycount(table))
1272: return -1;
1273: return table[idx];
1274: }
1275:
1276: static void
1.140 msaitoh 1277: pci_conf_print_pcix_cap_2ndbusmode(int num)
1278: {
1279: const char *maxfreq, *maxperiod;
1280:
1281: printf(" Mode: ");
1282: if (num <= 0x07)
1283: printf("PCI-X Mode 1\n");
1284: else if (num <= 0x0b)
1285: printf("PCI-X 266 (Mode 2)\n");
1286: else
1287: printf("PCI-X 533 (Mode 2)\n");
1288:
1289: printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC");
1290: switch (num & 0x03) {
1291: default:
1292: case 0:
1293: maxfreq = "N/A";
1294: maxperiod = "N/A";
1295: break;
1296: case 1:
1297: maxfreq = "66MHz";
1298: maxperiod = "15ns";
1299: break;
1300: case 2:
1301: maxfreq = "100MHz";
1302: maxperiod = "10ns";
1303: break;
1304: case 3:
1305: maxfreq = "133MHz";
1306: maxperiod = "7.5ns";
1307: break;
1308: }
1309: printf(" Max Clock Freq: %s\n", maxfreq);
1310: printf(" Min Clock Period: %s\n", maxperiod);
1311: }
1312:
1313: static void
1.122 msaitoh 1314: pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff)
1315: {
1316: pcireg_t reg;
1317: int isbridge;
1318: int i;
1319:
1320: isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])
1321: & PCI_HDRTYPE_PPB) != 0 ? 1 : 0;
1322: printf("\n PCI-X %s Capabilities Register\n",
1323: isbridge ? "Bridge" : "Non-bridge");
1324:
1325: reg = regs[o2i(capoff)];
1326: if (isbridge != 0) {
1327: printf(" Secondary status register: 0x%04x\n",
1328: (reg & 0xffff0000) >> 16);
1329: onoff("64bit device", reg, PCIX_STATUS_64BIT);
1330: onoff("133MHz capable", reg, PCIX_STATUS_133);
1331: onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
1332: onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
1333: onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
1334: onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
1.140 msaitoh 1335: pci_conf_print_pcix_cap_2ndbusmode(
1336: __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF));
1.122 msaitoh 1337: printf(" Version: 0x%x\n",
1338: (reg & PCIX_BRIDGE_2NDST_VER_MASK)
1339: >> PCIX_BRIDGE_2NDST_VER_SHIFT);
1340: onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266);
1341: onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533);
1342: } else {
1343: printf(" Command register: 0x%04x\n",
1344: (reg & 0xffff0000) >> 16);
1345: onoff("Data Parity Error Recovery", reg,
1346: PCIX_CMD_PERR_RECOVER);
1347: onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER);
1348: printf(" Maximum Burst Read Count: %u\n",
1349: PCIX_CMD_BYTECNT(reg));
1350: printf(" Maximum Split Transactions: %d\n",
1351: pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK)
1352: >> PCIX_CMD_SPLTRANS_SHIFT));
1353: }
1354: reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */
1355: printf(" %sStatus register: 0x%08x\n",
1356: isbridge ? "Bridge " : "", reg);
1357: printf(" Function: %d\n", PCIX_STATUS_FN(reg));
1358: printf(" Device: %d\n", PCIX_STATUS_DEV(reg));
1359: printf(" Bus: %d\n", PCIX_STATUS_BUS(reg));
1360: onoff("64bit device", reg, PCIX_STATUS_64BIT);
1361: onoff("133MHz capable", reg, PCIX_STATUS_133);
1362: onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
1363: onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
1364: if (isbridge != 0) {
1365: onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
1366: onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
1367: } else {
1368: onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX,
1369: "bridge device", "simple device");
1370: printf(" Designed max memory read byte count: %d\n",
1371: 512 << ((reg & PCIX_STATUS_MAXB_MASK)
1372: >> PCIX_STATUS_MAXB_SHIFT));
1373: printf(" Designed max outstanding split transaction: %d\n",
1374: pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK)
1375: >> PCIX_STATUS_MAXST_SHIFT));
1376: printf(" MAX cumulative Read Size: %u\n",
1377: 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT));
1378: onoff("Received split completion error", reg,
1379: PCIX_STATUS_SCERR);
1380: }
1381: onoff("266MHz capable", reg, PCIX_STATUS_266);
1382: onoff("533MHz capable", reg, PCIX_STATUS_533);
1383:
1384: if (isbridge == 0)
1385: return;
1386:
1387: /* Only for bridge */
1388: for (i = 0; i < 2; i++) {
1.163 msaitoh 1389: reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))];
1.122 msaitoh 1390: printf(" %s split transaction control register: 0x%08x\n",
1391: (i == 0) ? "Upstream" : "Downstream", reg);
1392: printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP);
1393: printf(" Commitment Limit: %d\n",
1394: (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT);
1395: }
1396: }
1397:
1.141 msaitoh 1398: /* pci_conf_print_ht_slave_cap */
1399: /* pci_conf_print_ht_host_cap */
1400: /* pci_conf_print_ht_switch_cap */
1401: /* pci_conf_print_ht_intr_cap */
1402: /* pci_conf_print_ht_revid_cap */
1403: /* pci_conf_print_ht_unitid_cap */
1404: /* pci_conf_print_ht_extcnf_cap */
1405: /* pci_conf_print_ht_addrmap_cap */
1406: /* pci_conf_print_ht_msimap_cap */
1407:
1408: static void
1409: pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff)
1410: {
1411: pcireg_t val;
1412: uint32_t lo, hi;
1413:
1414: /*
1415: * Print the rest of the command register bits. Others are
1416: * printed in pci_conf_print_ht_cap().
1417: */
1418: val = regs[o2i(capoff + PCI_HT_CMD)];
1419: onoff("Enable", val, PCI_HT_MSI_ENABLED);
1420: onoff("Fixed", val, PCI_HT_MSI_FIXED);
1421:
1422: lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)];
1423: hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)];
1424: printf(" Address Low register: 0x%08x\n", lo);
1425: printf(" Address high register: 0x%08x\n", hi);
1426: printf(" Address: 0x%016" PRIx64 "\n",
1427: (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK));
1428: }
1429:
1430: /* pci_conf_print_ht_droute_cap */
1431: /* pci_conf_print_ht_vcset_cap */
1432: /* pci_conf_print_ht_retry_cap */
1433: /* pci_conf_print_ht_x86enc_cap */
1434: /* pci_conf_print_ht_gen3_cap */
1435: /* pci_conf_print_ht_fle_cap */
1436: /* pci_conf_print_ht_pm_cap */
1437: /* pci_conf_print_ht_hnc_cap */
1438:
1439: static const struct ht_types {
1440: pcireg_t cap;
1441: const char *name;
1442: void (*printfunc)(const pcireg_t *, int);
1443: } ht_captab[] = {
1444: {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL },
1445: {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL },
1446: {PCI_HT_CAP_SWITCH, "Switch", NULL },
1447: {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL},
1448: {PCI_HT_CAP_REVID, "Revision ID", NULL },
1449: {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL },
1450: {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL },
1451: {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL },
1452: {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap },
1453: {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL },
1454: {PCI_HT_CAP_VCSET, "VCSet", NULL },
1455: {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL },
1456: {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL },
1457: {PCI_HT_CAP_GEN3, "Gen3", NULL },
1458: {PCI_HT_CAP_FLE, "Function-Level Extension", NULL },
1459: {PCI_HT_CAP_PM, "Power Management", NULL },
1460: {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL },
1461: };
1462:
1463: static void
1464: pci_conf_print_ht_cap(const pcireg_t *regs, int capoff)
1465: {
1466: pcireg_t val, foundcap;
1467: unsigned int off;
1468:
1469: val = regs[o2i(capoff + PCI_HT_CMD)];
1470:
1471: printf("\n HyperTransport Capability Register at 0x%02x\n", capoff);
1472:
1473: printf(" Command register: 0x%04x\n", val >> 16);
1474: foundcap = PCI_HT_CAP(val);
1475: for (off = 0; off < __arraycount(ht_captab); off++) {
1476: if (ht_captab[off].cap == foundcap)
1477: break;
1478: }
1479: printf(" Capability Type: 0x%02x ", foundcap);
1480: if (off >= __arraycount(ht_captab)) {
1481: printf("(unknown)\n");
1482: return;
1483: }
1484: printf("(%s)\n", ht_captab[off].name);
1485: if (ht_captab[off].printfunc != NULL)
1.142 msaitoh 1486: ht_captab[off].printfunc(regs, capoff);
1.141 msaitoh 1487: }
1.118 msaitoh 1488:
1489: static void
1490: pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff)
1491: {
1492: uint16_t caps;
1493:
1494: caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT;
1495:
1496: printf("\n PCI Vendor Specific Capabilities Register\n");
1497: printf(" Capabilities length: 0x%02x\n", caps & 0xff);
1498: }
1499:
1500: static void
1501: pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff)
1502: {
1503: pcireg_t val;
1504:
1505: val = regs[o2i(capoff + PCI_DEBUG_BASER)];
1506:
1507: printf("\n Debugport Capability Register\n");
1508: printf(" Debug base Register: 0x%04x\n",
1509: val >> PCI_DEBUG_BASER_SHIFT);
1510: printf(" port offset: 0x%04x\n",
1511: (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT);
1512: printf(" BAR number: %u\n",
1513: (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT);
1514: }
1515:
1.115 msaitoh 1516: /* XXX pci_conf_print_cpci_rsrcctl_cap */
1517: /* XXX pci_conf_print_hotplug_cap */
1.118 msaitoh 1518:
1519: static void
1520: pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff)
1521: {
1522: pcireg_t reg;
1523:
1524: reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)];
1525:
1526: printf("\n Subsystem ID Capability Register\n");
1527: printf(" Subsystem ID : 0x%08x\n", reg);
1528: }
1529:
1.115 msaitoh 1530: /* XXX pci_conf_print_agp8_cap */
1.183.2.2 martin 1531: static void
1532: pci_conf_print_secure_cap(const pcireg_t *regs, int capoff)
1533: {
1534: pcireg_t reg, reg2, val;
1535: bool havemisc1;
1536:
1537: printf("\n Secure Capability Register\n");
1538: reg = regs[o2i(capoff + PCI_SECURE_CAP)];
1539: printf(" Capability Register: 0x%04x\n", reg >> 16);
1540: val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE);
1541: printf(" Capability block type: ");
1542: /* I know IOMMU Only */
1543: if (val == PCI_SECURE_CAP_TYPE_IOMMU)
1544: printf("IOMMU\n");
1545: else {
1546: printf("0x%x(unknown)\n", val);
1547: return;
1548: }
1549:
1550: val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV);
1551: printf(" Capability revision: 0x%02x ", val);
1552: if (val == PCI_SECURE_CAP_REV_IOMMU)
1553: printf("(IOMMU)\n");
1554: else {
1555: printf("(unknown)\n");
1556: return;
1557: }
1558: onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP);
1559: onoff("HyperTransport tunnel translation support", reg,
1560: PCI_SECURE_CAP_HTTUNNEL);
1561: onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE);
1562: onoff("IOMMU Extended Feature Register support", reg,
1563: PCI_SECURE_CAP_EFRSUP);
1564: onoff("IOMMU Miscellaneous Information Register 1", reg,
1565: PCI_SECURE_CAP_EXT);
1566: havemisc1 = reg & PCI_SECURE_CAP_EXT;
1567:
1568: reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)];
1569: printf(" Base Address Low Register: 0x%08x\n", reg);
1570: onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN);
1571: reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)];
1572: printf(" Base Address High Register: 0x%08x\n", reg2);
1573: printf(" Base Address : 0x%016" PRIx64 "\n",
1574: ((uint64_t)reg2 << 32)
1575: | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L)));
1576:
1577: reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];
1578: printf(" IOMMU Range Register: 0x%08x\n", reg);
1579: printf(" HyperTransport UnitID: 0x%02x\n",
1580: (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID));
1581: onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID);
1582: printf(" Device range bus number: 0x%02x\n",
1583: (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM));
1584: printf(" First device: 0x%04x\n",
1585: (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV));
1586: printf(" Last device: 0x%04x\n",
1587: (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV));
1588:
1589: reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)];
1590: printf(" Miscellaneous Information Register 0: 0x%08x\n", reg);
1591: printf(" MSI Message number: 0x%02x\n",
1592: (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM));
1593: val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE);
1594: printf(" Guest Virtual Address size: ");
1595: if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B)
1596: printf("48bits\n");
1597: else
1598: printf("0x%x(unknown)\n", val);
1599: val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE);
1600: printf(" Physical Address size: %dbits\n", val);
1601: val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE);
1602: printf(" Virtual Address size: %dbits\n", val);
1603: onoff("ATS response address range reserved", reg,
1604: PCI_SECURE_IOMMU_MISC0_ATSRESV);
1605: printf(" Peripheral Page Request MSI Message number: 0x%02x\n",
1606: (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR));
1607:
1608: if (!havemisc1)
1609: return;
1610:
1611: reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];
1612: printf(" Miscellaneous Information Register 1: 0x%08x\n", reg);
1613: printf(" MSI Message number (GA): 0x%02x\n",
1614: (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM));
1615: }
1.115 msaitoh 1616:
1.51 drochner 1617: static void
1.99 msaitoh 1618: pci_print_pcie_L0s_latency(uint32_t val)
1619: {
1620:
1621: switch (val) {
1622: case 0x0:
1623: printf("Less than 64ns\n");
1624: break;
1625: case 0x1:
1626: case 0x2:
1627: case 0x3:
1628: printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1));
1629: break;
1630: case 0x4:
1631: printf("512ns to less than 1us\n");
1632: break;
1633: case 0x5:
1634: printf("1us to less than 2us\n");
1635: break;
1636: case 0x6:
1637: printf("2us - 4us\n");
1638: break;
1639: case 0x7:
1640: printf("More than 4us\n");
1641: break;
1642: }
1643: }
1644:
1645: static void
1646: pci_print_pcie_L1_latency(uint32_t val)
1647: {
1648:
1649: switch (val) {
1650: case 0x0:
1651: printf("Less than 1us\n");
1652: break;
1653: case 0x6:
1654: printf("32us - 64us\n");
1655: break;
1656: case 0x7:
1657: printf("More than 64us\n");
1658: break;
1659: default:
1660: printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val);
1661: break;
1662: }
1663: }
1664:
1665: static void
1.105 msaitoh 1666: pci_print_pcie_compl_timeout(uint32_t val)
1667: {
1668:
1669: switch (val) {
1670: case 0x0:
1671: printf("50us to 50ms\n");
1672: break;
1673: case 0x5:
1674: printf("16ms to 55ms\n");
1675: break;
1676: case 0x6:
1677: printf("65ms to 210ms\n");
1678: break;
1679: case 0x9:
1680: printf("260ms to 900ms\n");
1681: break;
1682: case 0xa:
1683: printf("1s to 3.5s\n");
1684: break;
1685: default:
1686: printf("unknown %u value\n", val);
1687: break;
1688: }
1689: }
1690:
1.183.2.11! martin 1691: static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"};
1.146 msaitoh 1692:
1.183.2.1 martin 1693: /*
1694: * Print link speed. This function is used for the following register bits:
1695: * Maximum Link Speed in LCAP
1696: * Current Link Speed in LCSR
1697: * Target Link Speed in LCSR2
1698: * All of above bitfield's values start from 1.
1699: * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and
1700: * this check also works for devices which compliant to versions of the base
1701: * specification prior to 3.0.
1702: */
1.146 msaitoh 1703: static void
1.183.2.1 martin 1704: pci_print_pcie_linkspeed(int regnum, pcireg_t val)
1.146 msaitoh 1705: {
1706:
1.183.2.1 martin 1707: if ((regnum == PCIE_LCSR2) && (val == 0))
1708: printf("2.5GT/s\n");
1709: else if ((val < 1) || (val > __arraycount(pcie_linkspeeds)))
1.146 msaitoh 1710: printf("unknown value (%u)\n", val);
1711: else
1.183.2.1 martin 1712: printf("%sGT/s\n", pcie_linkspeeds[val - 1]);
1.146 msaitoh 1713: }
1714:
1.183.2.1 martin 1715: /*
1716: * Print link speed "vector".
1717: * This function is used for the following register bits:
1718: * Supported Link Speeds Vector in LCAP2
1719: * Lower SKP OS Generation Supported Speed Vector in LCAP2
1720: * Lower SKP OS Reception Supported Speed Vector in LCAP2
1721: * Enable Lower SKP OS Generation Vector in LCTL3
1722: * All of above bitfield's values start from 0.
1723: */
1.146 msaitoh 1724: static void
1725: pci_print_pcie_linkspeedvector(pcireg_t val)
1726: {
1727: unsigned int i;
1728:
1729: /* Start from 0 */
1730: for (i = 0; i < 16; i++)
1731: if (((val >> i) & 0x01) != 0) {
1732: if (i >= __arraycount(pcie_linkspeeds))
1.157 msaitoh 1733: printf(" unknown vector (0x%x)", 1 << i);
1.146 msaitoh 1734: else
1735: printf(" %sGT/s", pcie_linkspeeds[i]);
1736: }
1737: }
1738:
1.105 msaitoh 1739: static void
1.157 msaitoh 1740: pci_print_pcie_link_deemphasis(pcireg_t val)
1741: {
1742: switch (val) {
1743: case 0:
1744: printf("-6dB");
1745: break;
1746: case 1:
1747: printf("-3.5dB");
1748: break;
1749: default:
1750: printf("(reserved value)");
1751: }
1752: }
1753:
1754: static void
1.72 joerg 1755: pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
1756: {
1.101 msaitoh 1757: pcireg_t reg; /* for each register */
1758: pcireg_t val; /* for each bitfield */
1.72 joerg 1759: bool check_slot = false;
1.183.2.9 martin 1760: unsigned int pcie_devtype;
1.181 msaitoh 1761: bool check_upstreamport = false;
1.105 msaitoh 1762: unsigned int pciever;
1.157 msaitoh 1763: unsigned int i;
1.72 joerg 1764:
1765: printf("\n PCI Express Capabilities Register\n");
1.99 msaitoh 1766: /* Capability Register */
1.101 msaitoh 1767: reg = regs[o2i(capoff)];
1.157 msaitoh 1768: printf(" Capability register: 0x%04x\n", reg >> 16);
1.183.2.4 snj 1769: pciever = (unsigned int)(PCIE_XCAP_VER(reg));
1.105 msaitoh 1770: printf(" Capability version: %u\n", pciever);
1.99 msaitoh 1771: printf(" Device type: ");
1.183.2.9 martin 1772: pcie_devtype = PCIE_XCAP_TYPE(reg);
1773: switch (pcie_devtype) {
1.159 msaitoh 1774: case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */
1.72 joerg 1775: printf("PCI Express Endpoint device\n");
1.181 msaitoh 1776: check_upstreamport = true;
1.72 joerg 1777: break;
1.159 msaitoh 1778: case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */
1.75 jmcneill 1779: printf("Legacy PCI Express Endpoint device\n");
1.181 msaitoh 1780: check_upstreamport = true;
1.72 joerg 1781: break;
1.159 msaitoh 1782: case PCIE_XCAP_TYPE_ROOT: /* 0x4 */
1.72 joerg 1783: printf("Root Port of PCI Express Root Complex\n");
1784: check_slot = true;
1785: break;
1.159 msaitoh 1786: case PCIE_XCAP_TYPE_UP: /* 0x5 */
1.72 joerg 1787: printf("Upstream Port of PCI Express Switch\n");
1.181 msaitoh 1788: check_upstreamport = true;
1.72 joerg 1789: break;
1.159 msaitoh 1790: case PCIE_XCAP_TYPE_DOWN: /* 0x6 */
1.72 joerg 1791: printf("Downstream Port of PCI Express Switch\n");
1792: check_slot = true;
1793: break;
1.159 msaitoh 1794: case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */
1.72 joerg 1795: printf("PCI Express to PCI/PCI-X Bridge\n");
1.181 msaitoh 1796: check_upstreamport = true;
1.72 joerg 1797: break;
1.159 msaitoh 1798: case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */
1.72 joerg 1799: printf("PCI/PCI-X to PCI Express Bridge\n");
1.181 msaitoh 1800: /* Upstream port is not PCIe */
1.179 msaitoh 1801: check_slot = true;
1.72 joerg 1802: break;
1.159 msaitoh 1803: case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
1.96 msaitoh 1804: printf("Root Complex Integrated Endpoint\n");
1805: break;
1.159 msaitoh 1806: case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
1.180 msaitoh 1807: printf("Root Complex Event Collector\n");
1.96 msaitoh 1808: break;
1.72 joerg 1809: default:
1810: printf("unknown\n");
1811: break;
1812: }
1.127 msaitoh 1813: onoff("Slot implemented", reg, PCIE_XCAP_SI);
1.157 msaitoh 1814: printf(" Interrupt Message Number: 0x%02x\n",
1.159 msaitoh 1815: (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ));
1.99 msaitoh 1816:
1817: /* Device Capability Register */
1.103 msaitoh 1818: reg = regs[o2i(capoff + PCIE_DCAP)];
1.101 msaitoh 1819: printf(" Device Capabilities Register: 0x%08x\n", reg);
1.99 msaitoh 1820: printf(" Max Payload Size Supported: %u bytes max\n",
1.116 msaitoh 1821: 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD));
1.99 msaitoh 1822: printf(" Phantom Functions Supported: ");
1.159 msaitoh 1823: switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) {
1.99 msaitoh 1824: case 0x0:
1825: printf("not available\n");
1826: break;
1827: case 0x1:
1828: printf("MSB\n");
1829: break;
1830: case 0x2:
1831: printf("two MSB\n");
1832: break;
1833: case 0x3:
1834: printf("All three bits\n");
1835: break;
1836: }
1837: printf(" Extended Tag Field Supported: %dbit\n",
1.103 msaitoh 1838: (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);
1.99 msaitoh 1839: printf(" Endpoint L0 Acceptable Latency: ");
1.159 msaitoh 1840: pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY));
1.99 msaitoh 1841: printf(" Endpoint L1 Acceptable Latency: ");
1.159 msaitoh 1842: pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY));
1.122 msaitoh 1843: onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);
1844: onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
1.112 msaitoh 1845: onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
1846: onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);
1.181 msaitoh 1847: if (check_upstreamport) {
1848: printf(" Captured Slot Power Limit: ");
1849: pci_conf_print_pcie_power(
1850: __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL),
1851: __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE));
1852: }
1.112 msaitoh 1853: onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);
1.99 msaitoh 1854:
1855: /* Device Control Register */
1.103 msaitoh 1856: reg = regs[o2i(capoff + PCIE_DCSR)];
1.101 msaitoh 1857: printf(" Device Control Register: 0x%04x\n", reg & 0xffff);
1.112 msaitoh 1858: onoff("Correctable Error Reporting Enable", reg,
1859: PCIE_DCSR_ENA_COR_ERR);
1860: onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER);
1861: onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER);
1862: onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR);
1863: onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD);
1.99 msaitoh 1864: printf(" Max Payload Size: %d byte\n",
1.159 msaitoh 1865: 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD));
1.112 msaitoh 1866: onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD);
1867: onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS);
1868: onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM);
1869: onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
1.99 msaitoh 1870: printf(" Max Read Request Size: %d byte\n",
1.159 msaitoh 1871: 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));
1.99 msaitoh 1872:
1873: /* Device Status Register */
1.103 msaitoh 1874: reg = regs[o2i(capoff + PCIE_DCSR)];
1.101 msaitoh 1875: printf(" Device Status Register: 0x%04x\n", reg >> 16);
1.112 msaitoh 1876: onoff("Correctable Error Detected", reg, PCIE_DCSR_CED);
1877: onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED);
1878: onoff("Fatal Error Detected", reg, PCIE_DCSR_FED);
1879: onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD);
1880: onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR);
1881: onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);
1.159 msaitoh 1882: onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD);
1.99 msaitoh 1883:
1.183.2.9 martin 1884: if (PCIE_HAS_LINKREGS(pcie_devtype)) {
1.105 msaitoh 1885: /* Link Capability Register */
1886: reg = regs[o2i(capoff + PCIE_LCAP)];
1887: printf(" Link Capabilities Register: 0x%08x\n", reg);
1888: printf(" Maximum Link Speed: ");
1.183.2.1 martin 1889: pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED);
1.105 msaitoh 1890: printf(" Maximum Link Width: x%u lanes\n",
1.159 msaitoh 1891: (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH));
1.105 msaitoh 1892: printf(" Active State PM Support: ");
1.159 msaitoh 1893: switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) {
1.145 msaitoh 1894: case 0x0:
1895: printf("No ASPM support\n");
1896: break;
1.105 msaitoh 1897: case 0x1:
1.145 msaitoh 1898: printf("L0s supported\n");
1899: break;
1900: case 0x2:
1901: printf("L1 supported\n");
1.105 msaitoh 1902: break;
1903: case 0x3:
1904: printf("L0s and L1 supported\n");
1905: break;
1906: }
1907: printf(" L0 Exit Latency: ");
1.159 msaitoh 1908: pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT));
1.105 msaitoh 1909: printf(" L1 Exit Latency: ");
1.159 msaitoh 1910: pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT));
1911: printf(" Port Number: %u\n",
1912: (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT));
1.117 msaitoh 1913: onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM);
1914: onoff("Surprise Down Error Report", reg,
1915: PCIE_LCAP_SURPRISE_DOWN);
1916: onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE);
1917: onoff("Link BW Notification Capable", reg,
1918: PCIE_LCAP_LINK_BW_NOTIFY);
1919: onoff("ASPM Optionally Compliance", reg,
1920: PCIE_LCAP_ASPM_COMPLIANCE);
1.105 msaitoh 1921:
1922: /* Link Control Register */
1923: reg = regs[o2i(capoff + PCIE_LCSR)];
1924: printf(" Link Control Register: 0x%04x\n", reg & 0xffff);
1925: printf(" Active State PM Control: ");
1.159 msaitoh 1926: switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) {
1.105 msaitoh 1927: case 0:
1928: printf("disabled\n");
1929: break;
1930: case 1:
1931: printf("L0s Entry Enabled\n");
1932: break;
1933: case 2:
1934: printf("L1 Entry Enabled\n");
1935: break;
1936: case 3:
1937: printf("L0s and L1 Entry Enabled\n");
1938: break;
1939: }
1.112 msaitoh 1940: onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB,
1941: "128bytes", "64bytes");
1942: onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS);
1943: onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN);
1944: onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG);
1945: onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC);
1946: onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM);
1.159 msaitoh 1947: onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD);
1.112 msaitoh 1948: onoff("Link Bandwidth Management Interrupt Enable", reg,
1949: PCIE_LCSR_LBMIE);
1950: onoff("Link Autonomous Bandwidth Interrupt Enable", reg,
1951: PCIE_LCSR_LABIE);
1.146 msaitoh 1952: printf(" DRS Signaling Control: ");
1.159 msaitoh 1953: switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) {
1.146 msaitoh 1954: case 0:
1955: printf("not reported\n");
1956: break;
1957: case 1:
1958: printf("Interrupt Enabled\n");
1959: break;
1960: case 2:
1961: printf("DRS to FRS Signaling Enabled\n");
1962: break;
1963: default:
1964: printf("reserved\n");
1965: break;
1966: }
1.105 msaitoh 1967:
1968: /* Link Status Register */
1969: reg = regs[o2i(capoff + PCIE_LCSR)];
1970: printf(" Link Status Register: 0x%04x\n", reg >> 16);
1971: printf(" Negotiated Link Speed: ");
1.183.2.1 martin 1972: pci_print_pcie_linkspeed(PCIE_LCSR,
1973: __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED));
1.105 msaitoh 1974: printf(" Negotiated Link Width: x%u lanes\n",
1.159 msaitoh 1975: (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW));
1.112 msaitoh 1976: onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
1977: onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);
1978: onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);
1979: onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE);
1980: onoff("Link Bandwidth Management Status", reg,
1981: PCIE_LCSR_LINK_BW_MGMT);
1982: onoff("Link Autonomous Bandwidth Status", reg,
1983: PCIE_LCSR_LINK_AUTO_BW);
1.86 matt 1984: }
1.99 msaitoh 1985:
1.102 msaitoh 1986: if (check_slot == true) {
1.183.2.1 martin 1987: pcireg_t slcap;
1988:
1.101 msaitoh 1989: /* Slot Capability Register */
1.183.2.1 martin 1990: slcap = reg = regs[o2i(capoff + PCIE_SLCAP)];
1.157 msaitoh 1991: printf(" Slot Capability Register: 0x%08x\n", reg);
1.117 msaitoh 1992: onoff("Attention Button Present", reg, PCIE_SLCAP_ABP);
1993: onoff("Power Controller Present", reg, PCIE_SLCAP_PCP);
1994: onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP);
1995: onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP);
1996: onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);
1997: onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
1998: onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
1.181 msaitoh 1999: printf(" Slot Power Limit Value: ");
2000: pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV),
2001: __SHIFTOUT(reg, PCIE_SLCAP_SPLS));
1.117 msaitoh 2002: onoff("Electromechanical Interlock Present", reg,
2003: PCIE_SLCAP_EIP);
2004: onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS);
1.101 msaitoh 2005: printf(" Physical Slot Number: %d\n",
1.103 msaitoh 2006: (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19);
1.101 msaitoh 2007:
2008: /* Slot Control Register */
1.103 msaitoh 2009: reg = regs[o2i(capoff + PCIE_SLCSR)];
1.175 msaitoh 2010: printf(" Slot Control Register: 0x%04x\n", reg & 0xffff);
1.117 msaitoh 2011: onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE);
2012: onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE);
2013: onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE);
1.172 msaitoh 2014: onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE);
1.117 msaitoh 2015: onoff("Command Completed Interrupt Enabled", reg,
2016: PCIE_SLCSR_CCE);
2017: onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE);
1.183.2.1 martin 2018: /*
2019: * For Attention Indicator Control and Power Indicator Control,
2020: * it's allowed to be a read only value 0 if corresponding
2021: * capability register bit is 0.
2022: */
2023: if (slcap & PCIE_SLCAP_AIP) {
2024: printf(" Attention Indicator Control: ");
2025: switch ((reg & PCIE_SLCSR_AIC) >> 6) {
2026: case 0x0:
2027: printf("reserved\n");
2028: break;
2029: case PCIE_SLCSR_IND_ON:
2030: printf("on\n");
2031: break;
2032: case PCIE_SLCSR_IND_BLINK:
2033: printf("blink\n");
2034: break;
2035: case PCIE_SLCSR_IND_OFF:
2036: printf("off\n");
2037: break;
2038: }
1.72 joerg 2039: }
1.183.2.1 martin 2040: if (slcap & PCIE_SLCAP_PIP) {
2041: printf(" Power Indicator Control: ");
2042: switch ((reg & PCIE_SLCSR_PIC) >> 8) {
2043: case 0x0:
2044: printf("reserved\n");
2045: break;
2046: case PCIE_SLCSR_IND_ON:
2047: printf("on\n");
2048: break;
2049: case PCIE_SLCSR_IND_BLINK:
2050: printf("blink\n");
2051: break;
2052: case PCIE_SLCSR_IND_OFF:
2053: printf("off\n");
2054: break;
2055: }
1.72 joerg 2056: }
1.156 msaitoh 2057: printf(" Power Controller Control: Power %s\n",
2058: reg & PCIE_SLCSR_PCC ? "off" : "on");
1.117 msaitoh 2059: onoff("Electromechanical Interlock Control",
2060: reg, PCIE_SLCSR_EIC);
1.116 msaitoh 2061: onoff("Data Link Layer State Changed Enable", reg,
2062: PCIE_SLCSR_DLLSCE);
1.146 msaitoh 2063: onoff("Auto Slot Power Limit Disable", reg,
2064: PCIE_SLCSR_AUTOSPLDIS);
1.101 msaitoh 2065:
2066: /* Slot Status Register */
1.157 msaitoh 2067: printf(" Slot Status Register: 0x%04x\n", reg >> 16);
1.117 msaitoh 2068: onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP);
2069: onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD);
2070: onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC);
1.172 msaitoh 2071: onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC);
1.117 msaitoh 2072: onoff("Command Completed", reg, PCIE_SLCSR_CC);
2073: onoff("MRL Open", reg, PCIE_SLCSR_MS);
2074: onoff("Card Present in slot", reg, PCIE_SLCSR_PDS);
2075: onoff("Electromechanical Interlock engaged", reg,
2076: PCIE_SLCSR_EIS);
2077: onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS);
1.101 msaitoh 2078: }
2079:
1.183.2.9 martin 2080: if (PCIE_HAS_ROOTREGS(pcie_devtype)) {
1.101 msaitoh 2081: /* Root Control Register */
1.103 msaitoh 2082: reg = regs[o2i(capoff + PCIE_RCR)];
1.175 msaitoh 2083: printf(" Root Control Register: 0x%04x\n", reg & 0xffff);
1.117 msaitoh 2084: onoff("SERR on Correctable Error Enable", reg,
2085: PCIE_RCR_SERR_CER);
2086: onoff("SERR on Non-Fatal Error Enable", reg,
2087: PCIE_RCR_SERR_NFER);
2088: onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER);
2089: onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE);
2090: onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE);
1.101 msaitoh 2091:
2092: /* Root Capability Register */
1.157 msaitoh 2093: printf(" Root Capability Register: 0x%04x\n",
1.101 msaitoh 2094: reg >> 16);
1.133 msaitoh 2095: onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV);
1.101 msaitoh 2096:
2097: /* Root Status Register */
1.103 msaitoh 2098: reg = regs[o2i(capoff + PCIE_RSR)];
1.157 msaitoh 2099: printf(" Root Status Register: 0x%08x\n", reg);
2100: printf(" PME Requester ID: 0x%04x\n",
1.104 msaitoh 2101: (unsigned int)(reg & PCIE_RSR_PME_REQESTER));
1.117 msaitoh 2102: onoff("PME was asserted", reg, PCIE_RSR_PME_STAT);
2103: onoff("another PME is pending", reg, PCIE_RSR_PME_PEND);
1.72 joerg 2104: }
1.105 msaitoh 2105:
2106: /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
2107: if (pciever < 2)
2108: return;
2109:
2110: /* Device Capabilities 2 */
2111: reg = regs[o2i(capoff + PCIE_DCAP2)];
2112: printf(" Device Capabilities 2: 0x%08x\n", reg);
1.157 msaitoh 2113: printf(" Completion Timeout Ranges Supported: ");
2114: val = reg & PCIE_DCAP2_COMPT_RANGE;
2115: switch (val) {
2116: case 0:
2117: printf("not supported\n");
2118: break;
2119: default:
2120: for (i = 0; i <= 3; i++) {
2121: if (((val >> i) & 0x01) != 0)
2122: printf("%c", 'A' + i);
2123: }
2124: printf("\n");
2125: }
1.112 msaitoh 2126: onoff("Completion Timeout Disable Supported", reg,
2127: PCIE_DCAP2_COMPT_DIS);
2128: onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD);
2129: onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT);
2130: onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM);
2131: onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM);
2132: onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS);
2133: onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS);
2134: onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC);
1.157 msaitoh 2135: printf(" TPH Completer Supported: ");
2136: switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) {
2137: case 0:
1.172 msaitoh 2138: printf("Not supported\n");
1.157 msaitoh 2139: break;
2140: case 1:
2141: printf("TPH\n");
2142: break;
2143: case 3:
2144: printf("TPH and Extended TPH\n");
2145: break;
2146: default:
2147: printf("(reserved value)\n");
2148: break;
2149:
2150: }
1.145 msaitoh 2151: printf(" LN System CLS: ");
2152: switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) {
2153: case 0x0:
2154: printf("Not supported or not in effect\n");
2155: break;
2156: case 0x1:
2157: printf("64byte cachelines in effect\n");
2158: break;
2159: case 0x2:
2160: printf("128byte cachelines in effect\n");
2161: break;
2162: case 0x3:
2163: printf("Reserved\n");
2164: break;
2165: }
1.105 msaitoh 2166: printf(" OBFF Supported: ");
1.183.2.2 martin 2167: switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {
1.105 msaitoh 2168: case 0x0:
2169: printf("Not supported\n");
2170: break;
2171: case 0x1:
2172: printf("Message only\n");
2173: break;
2174: case 0x2:
2175: printf("WAKE# only\n");
2176: break;
2177: case 0x3:
2178: printf("Both\n");
2179: break;
2180: }
1.112 msaitoh 2181: onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD);
2182: onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);
1.157 msaitoh 2183: val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP);
2184: printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val);
1.152 msaitoh 2185: printf(" Emergency Power Reduction Supported: ");
2186: switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) {
2187: case 0x0:
2188: printf("Not supported\n");
2189: break;
2190: case 0x1:
2191: printf("Device Specific mechanism\n");
2192: break;
2193: case 0x2:
2194: printf("Form Factor spec or Device Specific mechanism\n");
2195: break;
2196: case 0x3:
2197: printf("Reserved\n");
2198: break;
2199: }
2200: onoff("Emergency Power Reduction Initialization Required", reg,
2201: PCIE_DCAP2_EMGPWRRED_INI);
1.146 msaitoh 2202: onoff("FRS Supported", reg, PCIE_DCAP2_FRS);
1.105 msaitoh 2203:
2204: /* Device Control 2 */
2205: reg = regs[o2i(capoff + PCIE_DCSR2)];
2206: printf(" Device Control 2: 0x%04x\n", reg & 0xffff);
2207: printf(" Completion Timeout Value: ");
2208: pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL);
1.117 msaitoh 2209: onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS);
2210: onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD);
1.172 msaitoh 2211: onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ);
1.117 msaitoh 2212: onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK);
2213: onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ);
2214: onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP);
2215: onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
1.152 msaitoh 2216: onoff("Emergency Power Reduction Request", reg,
2217: PCIE_DCSR2_EMGPWRRED_REQ);
1.105 msaitoh 2218: printf(" OBFF: ");
1.183.2.2 martin 2219: switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {
1.105 msaitoh 2220: case 0x0:
2221: printf("Disabled\n");
2222: break;
2223: case 0x1:
2224: printf("Enabled with Message Signaling Variation A\n");
2225: break;
2226: case 0x2:
2227: printf("Enabled with Message Signaling Variation B\n");
2228: break;
2229: case 0x3:
2230: printf("Enabled using WAKE# signaling\n");
2231: break;
2232: }
1.117 msaitoh 2233: onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);
1.105 msaitoh 2234:
1.183.2.9 martin 2235: if (PCIE_HAS_LINKREGS(pcie_devtype)) {
1.157 msaitoh 2236: bool drs_supported = false;
1.146 msaitoh 2237:
1.105 msaitoh 2238: /* Link Capability 2 */
2239: reg = regs[o2i(capoff + PCIE_LCAP2)];
1.157 msaitoh 2240: /* If the vector is 0, LCAP2 is not implemented */
2241: if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) {
2242: printf(" Link Capabilities 2: 0x%08x\n", reg);
2243: printf(" Supported Link Speeds Vector:");
2244: pci_print_pcie_linkspeedvector(
2245: __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV));
2246: printf("\n");
2247: onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK);
2248: printf(" "
2249: "Lower SKP OS Generation Supported Speed Vector:");
2250: pci_print_pcie_linkspeedvector(
2251: __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV));
2252: printf("\n");
2253: printf(" "
2254: "Lower SKP OS Reception Supported Speed Vector:");
2255: pci_print_pcie_linkspeedvector(
2256: __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV));
2257: printf("\n");
2258: onoff("DRS Supported", reg, PCIE_LCAP2_DRS);
2259: drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false;
2260: }
1.105 msaitoh 2261:
2262: /* Link Control 2 */
2263: reg = regs[o2i(capoff + PCIE_LCSR2)];
1.183.2.1 martin 2264: /* If the vector is 0, LCAP2 is not implemented */
1.105 msaitoh 2265: printf(" Link Control 2: 0x%04x\n", reg & 0xffff);
2266: printf(" Target Link Speed: ");
1.183.2.1 martin 2267: pci_print_pcie_linkspeed(PCIE_LCSR2,
2268: __SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED));
1.117 msaitoh 2269: onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL);
2270: onoff("HW Autonomous Speed Disabled", reg,
2271: PCIE_LCSR2_HW_AS_DIS);
1.157 msaitoh 2272: printf(" Selectable De-emphasis: ");
2273: pci_print_pcie_link_deemphasis(
2274: __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP));
2275: printf("\n");
1.105 msaitoh 2276: printf(" Transmit Margin: %u\n",
2277: (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
1.117 msaitoh 2278: onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
2279: onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
1.157 msaitoh 2280: printf(" Compliance Present/De-emphasis: ");
2281: pci_print_pcie_link_deemphasis(
2282: __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP));
2283: printf("\n");
1.105 msaitoh 2284:
2285: /* Link Status 2 */
1.117 msaitoh 2286: printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff);
1.157 msaitoh 2287: printf(" Current De-emphasis Level: ");
2288: pci_print_pcie_link_deemphasis(
2289: __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL));
2290: printf("\n");
1.117 msaitoh 2291: onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL);
2292: onoff("Equalization Phase 1 Successful", reg,
2293: PCIE_LCSR2_EQP1_SUC);
2294: onoff("Equalization Phase 2 Successful", reg,
2295: PCIE_LCSR2_EQP2_SUC);
2296: onoff("Equalization Phase 3 Successful", reg,
2297: PCIE_LCSR2_EQP3_SUC);
2298: onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ);
1.146 msaitoh 2299: onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD);
2300: if (drs_supported) {
2301: printf(" Downstream Component Presence: ");
2302: switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) {
2303: case PCIE_DSCOMPN_DOWN_NOTDETERM:
2304: printf("Link Down - Presence Not"
2305: " Determined\n");
2306: break;
2307: case PCIE_DSCOMPN_DOWN_NOTPRES:
2308: printf("Link Down - Component Not Present\n");
2309: break;
2310: case PCIE_DSCOMPN_DOWN_PRES:
2311: printf("Link Down - Component Present\n");
2312: break;
2313: case PCIE_DSCOMPN_UP_PRES:
2314: printf("Link Up - Component Present\n");
2315: break;
2316: case PCIE_DSCOMPN_UP_PRES_DRS:
2317: printf("Link Up - Component Present and DRS"
2318: " received\n");
2319: break;
2320: default:
2321: printf("reserved\n");
2322: break;
2323: }
2324: onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV);
2325: }
1.105 msaitoh 2326: }
2327:
2328: /* Slot Capability 2 */
2329: /* Slot Control 2 */
2330: /* Slot Status 2 */
1.72 joerg 2331: }
2332:
1.120 msaitoh 2333: static void
2334: pci_conf_print_msix_cap(const pcireg_t *regs, int capoff)
2335: {
2336: pcireg_t reg;
2337:
2338: printf("\n MSI-X Capability Register\n");
2339:
2340: reg = regs[o2i(capoff + PCI_MSIX_CTL)];
2341: printf(" Message Control register: 0x%04x\n",
2342: (reg >> 16) & 0xff);
2343: printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg));
2344: onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK);
2345: onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);
2346: reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];
2347: printf(" Table offset register: 0x%08x\n", reg);
1.157 msaitoh 2348: printf(" Table offset: 0x%08x\n",
1.145 msaitoh 2349: (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK));
2350: printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK));
1.120 msaitoh 2351: reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)];
2352: printf(" Pending bit array register: 0x%08x\n", reg);
1.157 msaitoh 2353: printf(" Pending bit array offset: 0x%08x\n",
1.145 msaitoh 2354: (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK));
2355: printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK));
1.120 msaitoh 2356: }
2357:
1.138 msaitoh 2358: static void
2359: pci_conf_print_sata_cap(const pcireg_t *regs, int capoff)
2360: {
2361: pcireg_t reg;
2362:
2363: printf("\n Serial ATA Capability Register\n");
2364:
1.169 msaitoh 2365: reg = regs[o2i(capoff + PCI_SATA_REV)];
1.138 msaitoh 2366: printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff);
1.139 msaitoh 2367: printf(" Revision: %u.%u\n",
2368: (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR),
2369: (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR));
1.138 msaitoh 2370:
2371: reg = regs[o2i(capoff + PCI_SATA_BAR)];
2372:
2373: printf(" BAR Register: 0x%08x\n", reg);
1.140 msaitoh 2374: printf(" Register location: ");
2375: if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF)
2376: printf("in config space\n");
2377: else {
2378: printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg));
2379: printf(" BAR offset: 0x%08x\n",
2380: (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4);
2381: }
1.138 msaitoh 2382: }
2383:
1.118 msaitoh 2384: static void
2385: pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff)
2386: {
2387: pcireg_t reg;
2388:
2389: printf("\n Advanced Features Capability Register\n");
2390:
2391: reg = regs[o2i(capoff + PCI_AFCAPR)];
2392: printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff);
1.145 msaitoh 2393: printf(" AF Structure Length: 0x%02x\n",
2394: (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH));
1.118 msaitoh 2395: onoff("Transaction Pending", reg, PCI_AF_TP_CAP);
2396: onoff("Function Level Reset", reg, PCI_AF_FLR_CAP);
2397: reg = regs[o2i(capoff + PCI_AFCSR)];
2398: printf(" AF Control register: 0x%02x\n", reg & 0xff);
2399: /*
2400: * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register
2401: * and it's always 0 on read
2402: */
2403: printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff);
2404: onoff("Transaction Pending", reg, PCI_AFSR_TP);
2405: }
1.77 jmcneill 2406:
1.183.2.9 martin 2407: static void
2408: pci_conf_print_ea_cap_prop(unsigned int prop)
2409: {
2410:
2411: switch (prop) {
2412: case PCI_EA_PROP_MEM_NONPREF:
2413: printf("Memory Space, Non-Prefetchable\n");
2414: break;
2415: case PCI_EA_PROP_MEM_PREF:
2416: printf("Memory Space, Prefetchable\n");
2417: break;
2418: case PCI_EA_PROP_IO:
2419: printf("I/O Space\n");
2420: break;
2421: case PCI_EA_PROP_VF_MEM_NONPREF:
2422: printf("Resorce for VF use, Memory Space, Non-Prefetchable\n");
2423: break;
2424: case PCI_EA_PROP_VF_MEM_PREF:
2425: printf("Resorce for VF use, Memory Space, Prefetch\n");
2426: break;
2427: case PCI_EA_PROP_BB_MEM_NONPREF:
2428: printf("Behind the Bridge, Memory Space, Non-Pref\n");
2429: break;
2430: case PCI_EA_PROP_BB_MEM_PREF:
2431: printf("Behind the Bridge, Memory Space. Prefetchable\n");
2432: break;
2433: case PCI_EA_PROP_BB_IO:
2434: printf("Behind Bridge, I/O Space\n");
2435: break;
2436: case PCI_EA_PROP_MEM_UNAVAIL:
2437: printf("Memory Space Unavailable\n");
2438: break;
2439: case PCI_EA_PROP_IO_UNAVAIL:
2440: printf("IO Space Unavailable\n");
2441: break;
2442: case PCI_EA_PROP_UNAVAIL:
2443: printf("Entry Unavailable for use\n");
2444: break;
2445: default:
2446: printf("Reserved\n");
2447: break;
2448: }
2449: }
2450:
2451: static void
2452: pci_conf_print_ea_cap(const pcireg_t *regs, int capoff)
2453: {
2454: pcireg_t reg, reg2;
2455: unsigned int entries, entoff, i;
2456:
2457: printf("\n Enhanced Allocation Capability Register\n");
2458:
2459: reg = regs[o2i(capoff + PCI_EA_CAP1)];
2460: printf(" EA Num Entries register: 0x%04x\n", reg >> 16);
2461: entries = __SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES);
2462: printf(" EA Num Entries: %u\n", entries);
2463:
2464: /* Type 1 only */
2465: if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) {
2466: reg = regs[o2i(capoff + PCI_EA_CAP2)];
2467: printf(" EA Capability Second register: 0x%08x\n", reg);
2468: printf(" Fixed Secondary Bus Number: %hhu\n",
2469: (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY));
2470: printf(" Fixed Subordinate Bus Number: %hhu\n",
2471: (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE));
2472: entoff = capoff + 8;
2473: } else
2474: entoff = capoff + 4;
2475:
2476: for (i = 0; i < entries; i++) {
2477: uint64_t base, offset;
2478: bool baseis64, offsetis64;
2479: unsigned int bei, entry_size;
2480:
2481: printf(" Entry %u:\n", i);
2482: /* The first DW */
2483: reg = regs[o2i(entoff)];
2484: printf(" The first register: 0x%08x\n", reg);
2485: entry_size = __SHIFTOUT(reg, PCI_EA_ES);
2486: printf(" Entry size: %u\n", entry_size);
2487: printf(" BAR Equivalent Indicator: ");
2488: bei = __SHIFTOUT(reg, PCI_EA_BEI);
2489: switch (bei) {
2490: case PCI_EA_BEI_BAR0:
2491: case PCI_EA_BEI_BAR1:
2492: case PCI_EA_BEI_BAR2:
2493: case PCI_EA_BEI_BAR3:
2494: case PCI_EA_BEI_BAR4:
2495: case PCI_EA_BEI_BAR5:
2496: printf("BAR %u\n", bei - PCI_EA_BEI_BAR0);
2497: break;
2498: case PCI_EA_BEI_BEHIND:
2499: printf("Behind the function\n");
2500: break;
2501: case PCI_EA_BEI_NOTIND:
2502: printf("Not Indicated\n");
2503: break;
2504: case PCI_EA_BEI_EXPROM:
2505: printf("Expansion ROM\n");
2506: break;
2507: case PCI_EA_BEI_VFBAR0:
2508: case PCI_EA_BEI_VFBAR1:
2509: case PCI_EA_BEI_VFBAR2:
2510: case PCI_EA_BEI_VFBAR3:
2511: case PCI_EA_BEI_VFBAR4:
2512: case PCI_EA_BEI_VFBAR5:
2513: printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0);
2514: break;
2515: case PCI_EA_BEI_RESERVED:
2516: default:
2517: printf("Reserved\n");
2518: break;
2519: }
2520:
2521: printf(" Primary Properties: ");
2522: pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_PP));
2523: printf(" Secondary Properties: ");
2524: pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_SP));
2525: onoff("Writable", reg, PCI_EA_W);
2526: onoff("Enable for this entry", reg, PCI_EA_E);
2527:
2528: if (entry_size == 0) {
2529: entoff += 4;
2530: continue;
2531: }
2532:
2533: /* Base addr */
2534: reg = regs[o2i(entoff + 4)];
2535: base = reg & PCI_EA_LOWMASK;
2536: baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;
2537: printf(" Base Address Register Low: 0x%08x\n", reg);
2538: if (baseis64) {
2539: /* 64bit */
2540: reg2 = regs[o2i(entoff + 12)];
2541: printf(" Base Address Register high: 0x%08x\n",
2542: reg2);
2543: base |= (uint64_t)reg2 << 32;
2544: }
2545:
2546: /* Offset addr */
2547: reg = regs[o2i(entoff + 8)];
2548: offset = reg & PCI_EA_LOWMASK;
2549: offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;
2550: printf(" Max Offset Register Low: 0x%08x\n", reg);
2551: if (offsetis64) {
2552: /* 64bit */
2553: reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))];
2554: printf(" Max Offset Register high: 0x%08x\n",
2555: reg2);
2556: offset |= (uint64_t)reg2 << 32;
2557: }
2558:
2559: printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
2560: "\n", base, base + offset);
2561:
2562: entoff += 4;
2563: entoff += baseis64 ? 8 : 4;
2564: entoff += offsetis64 ? 8 : 4;
2565: }
2566: }
2567:
1.177 msaitoh 2568: /* XXX pci_conf_print_fpb_cap */
2569:
1.132 msaitoh 2570: static struct {
2571: pcireg_t cap;
2572: const char *name;
2573: void (*printfunc)(const pcireg_t *, int);
2574: } pci_captab[] = {
2575: { PCI_CAP_RESERVED0, "reserved", NULL },
2576: { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap },
2577: { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap },
2578: { PCI_CAP_VPD, "VPD", NULL },
2579: { PCI_CAP_SLOTID, "SlotID", NULL },
2580: { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap },
2581: { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL },
2582: { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap },
1.141 msaitoh 2583: { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap },
1.132 msaitoh 2584: { PCI_CAP_VENDSPEC, "Vendor-specific",
2585: pci_conf_print_vendspec_cap },
2586: { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap },
2587: { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL },
2588: { PCI_CAP_HOTPLUG, "Hot-Plug", NULL },
2589: { PCI_CAP_SUBVENDOR, "Subsystem vendor ID",
2590: pci_conf_print_subsystem_cap },
2591: { PCI_CAP_AGP8, "AGP 8x", NULL },
1.183.2.2 martin 2592: { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap },
1.132 msaitoh 2593: { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap },
2594: { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap },
1.138 msaitoh 2595: { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap },
1.145 msaitoh 2596: { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap},
1.183.2.9 martin 2597: { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap },
1.177 msaitoh 2598: { PCI_CAP_FPB, "Flattening Portal Bridge", NULL }
1.132 msaitoh 2599: };
2600:
1.135 msaitoh 2601: static int
1.183.2.4 snj 2602: pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp)
1.135 msaitoh 2603: {
2604: pcireg_t rval;
1.183.2.4 snj 2605: unsigned int capptr;
1.135 msaitoh 2606: int off;
2607:
1.183.2.4 snj 2608: if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT))
2609: return 0;
2610:
2611: /* Determine the Capability List Pointer register to start with. */
2612: switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) {
2613: case 0: /* standard device header */
2614: case 1: /* PCI-PCI bridge header */
2615: capptr = PCI_CAPLISTPTR_REG;
2616: break;
2617: case 2: /* PCI-CardBus Bridge header */
2618: capptr = PCI_CARDBUS_CAPLISTPTR_REG;
2619: break;
2620: default:
2621: return 0;
2622: }
2623:
2624: for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]);
1.141 msaitoh 2625: off != 0; off = PCI_CAPLIST_NEXT(rval)) {
1.135 msaitoh 2626: rval = regs[o2i(off)];
2627: if (capid == PCI_CAPLIST_CAP(rval)) {
2628: if (offsetp != NULL)
2629: *offsetp = off;
2630: return 1;
2631: }
2632: }
2633: return 0;
2634: }
2635:
1.86 matt 2636: static void
1.51 drochner 2637: pci_conf_print_caplist(
2638: #ifdef _KERNEL
1.71 christos 2639: pci_chipset_tag_t pc, pcitag_t tag,
1.51 drochner 2640: #endif
1.52 drochner 2641: const pcireg_t *regs, int capoff)
1.51 drochner 2642: {
2643: int off;
1.132 msaitoh 2644: pcireg_t foundcap;
1.51 drochner 2645: pcireg_t rval;
1.132 msaitoh 2646: bool foundtable[__arraycount(pci_captab)];
2647: unsigned int i;
1.33 kleink 2648:
1.132 msaitoh 2649: /* Clear table */
2650: for (i = 0; i < __arraycount(pci_captab); i++)
2651: foundtable[i] = false;
2652:
2653: /* Print capability register's offset and the type first */
1.52 drochner 2654: for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
1.141 msaitoh 2655: off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
1.51 drochner 2656: rval = regs[o2i(off)];
2657: printf(" Capability register at 0x%02x\n", off);
2658:
2659: printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
1.132 msaitoh 2660: foundcap = PCI_CAPLIST_CAP(rval);
2661: if (foundcap < __arraycount(pci_captab)) {
2662: printf("%s)\n", pci_captab[foundcap].name);
2663: /* Mark as found */
2664: foundtable[foundcap] = true;
2665: } else
2666: printf("unknown)\n");
2667: }
2668:
2669: /*
2670: * And then, print the detail of each capability registers
2671: * in capability value's order.
2672: */
2673: for (i = 0; i < __arraycount(pci_captab); i++) {
2674: if (foundtable[i] == false)
2675: continue;
2676:
2677: /*
2678: * The type was found. Search capability list again and
2679: * print all capabilities that the capabiliy type is
2680: * the same. This is required because some capabilities
2681: * appear multiple times (e.g. HyperTransport capability).
2682: */
1.141 msaitoh 2683: for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
2684: off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
2685: rval = regs[o2i(off)];
2686: if ((PCI_CAPLIST_CAP(rval) == i)
2687: && (pci_captab[i].printfunc != NULL))
2688: pci_captab[i].printfunc(regs, off);
2689: }
1.135 msaitoh 2690: }
2691: }
2692:
2693: /* Extended Capability */
2694:
2695: static void
2696: pci_conf_print_aer_cap_uc(pcireg_t reg)
2697: {
2698:
2699: onoff("Undefined", reg, PCI_AER_UC_UNDEFINED);
2700: onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR);
2701: onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR);
1.146 msaitoh 2702: onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP);
1.135 msaitoh 2703: onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR);
2704: onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT);
2705: onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT);
2706: onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION);
2707: onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW);
2708: onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP);
2709: onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR);
2710: onoff("Unsupported Request Error", reg,
2711: PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR);
2712: onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION);
2713: onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR);
2714: onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP);
2715: onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED);
2716: onoff("TLP Prefix Blocked Error", reg,
1.146 msaitoh 2717: PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR);
2718: onoff("Poisoned TLP Egress Blocked", reg,
2719: PCI_AER_UC_POISONTLP_EGRESS_BLOCKED);
1.135 msaitoh 2720: }
2721:
2722: static void
2723: pci_conf_print_aer_cap_cor(pcireg_t reg)
2724: {
2725:
2726: onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR);
2727: onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP);
2728: onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP);
2729: onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER);
2730: onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT);
2731: onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR);
2732: onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR);
2733: onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW);
2734: }
2735:
2736: static void
2737: pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log)
2738: {
2739:
2740: printf(" First Error Pointer: 0x%04x\n",
2741: (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR));
2742: onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE);
2743: onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE);
2744: onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE);
1.172 msaitoh 2745: onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE);
1.135 msaitoh 2746: onoff("Multiple Header Recording Capable", reg,
2747: PCI_AER_MULT_HDR_CAPABLE);
1.146 msaitoh 2748: onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE);
2749: onoff("Completion Timeout Prefix/Header Log Capable", reg,
2750: PCI_AER_COMPTOUTPRFXHDRLOG_CAP);
1.135 msaitoh 2751:
2752: /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */
2753: if (!tlp_prefix_log)
2754: return;
2755: onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT);
2756: *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false;
2757: }
2758:
2759: static void
2760: pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg)
2761: {
2762:
2763: onoff("Correctable Error Reporting Enable", reg,
2764: PCI_AER_ROOTERR_COR_ENABLE);
2765: onoff("Non-Fatal Error Reporting Enable", reg,
2766: PCI_AER_ROOTERR_NF_ENABLE);
2767: onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE);
2768: }
2769:
2770: static void
2771: pci_conf_print_aer_cap_rooterr_status(pcireg_t reg)
2772: {
2773:
2774: onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR);
2775: onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR);
2776: onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR);
2777: onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg,
2778: PCI_AER_ROOTERR_MULTI_UC_ERR);
1.159 msaitoh 2779: onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL);
2780: onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR);
1.135 msaitoh 2781: onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR);
1.158 msaitoh 2782: printf(" Advanced Error Interrupt Message Number: 0x%02x\n",
1.159 msaitoh 2783: (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE));
1.135 msaitoh 2784: }
2785:
2786: static void
2787: pci_conf_print_aer_cap_errsrc_id(pcireg_t reg)
2788: {
2789:
2790: printf(" Correctable Source ID: 0x%04x\n",
2791: (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR));
2792: printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n",
2793: (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC));
2794: }
2795:
2796: static void
1.183.2.4 snj 2797: pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 2798: {
2799: pcireg_t reg;
2800: int pcie_capoff;
2801: int pcie_devtype = -1;
2802: bool tlp_prefix_log = false;
2803:
1.183.2.4 snj 2804: if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
1.135 msaitoh 2805: reg = regs[o2i(pcie_capoff)];
1.143 msaitoh 2806: pcie_devtype = PCIE_XCAP_TYPE(reg);
1.135 msaitoh 2807: /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
2808: if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) {
2809: reg = regs[o2i(pcie_capoff + PCIE_DCAP2)];
2810: /* End-End TLP Prefix Supported */
2811: if (reg & PCIE_DCAP2_EETLP_PREF) {
2812: tlp_prefix_log = true;
2813: }
2814: }
2815: }
2816:
2817: printf("\n Advanced Error Reporting Register\n");
2818:
2819: reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)];
2820: printf(" Uncorrectable Error Status register: 0x%08x\n", reg);
2821: pci_conf_print_aer_cap_uc(reg);
2822: reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)];
2823: printf(" Uncorrectable Error Mask register: 0x%08x\n", reg);
2824: pci_conf_print_aer_cap_uc(reg);
2825: reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)];
2826: printf(" Uncorrectable Error Severity register: 0x%08x\n", reg);
2827: pci_conf_print_aer_cap_uc(reg);
2828:
2829: reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)];
2830: printf(" Correctable Error Status register: 0x%08x\n", reg);
2831: pci_conf_print_aer_cap_cor(reg);
2832: reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)];
2833: printf(" Correctable Error Mask register: 0x%08x\n", reg);
2834: pci_conf_print_aer_cap_cor(reg);
2835:
2836: reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)];
2837: printf(" Advanced Error Capabilities and Control register: 0x%08x\n",
2838: reg);
2839: pci_conf_print_aer_cap_control(reg, &tlp_prefix_log);
2840: reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)];
2841: printf(" Header Log register:\n");
2842: pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG,
2843: extcapoff + PCI_AER_ROOTERR_CMD);
2844:
2845: switch (pcie_devtype) {
2846: case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
2847: case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
2848: reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
2849: printf(" Root Error Command register: 0x%08x\n", reg);
2850: pci_conf_print_aer_cap_rooterr_cmd(reg);
2851: reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)];
2852: printf(" Root Error Status register: 0x%08x\n", reg);
2853: pci_conf_print_aer_cap_rooterr_status(reg);
2854:
2855: reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)];
1.183.2.3 martin 2856: printf(" Error Source Identification register: 0x%08x\n",
2857: reg);
1.135 msaitoh 2858: pci_conf_print_aer_cap_errsrc_id(reg);
2859: break;
2860: }
2861:
2862: if (tlp_prefix_log) {
2863: reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)];
2864: printf(" TLP Prefix Log register: 0x%08x\n", reg);
2865: }
2866: }
2867:
2868: static void
2869: pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
2870: pcireg_t parbsel, int parbsize)
2871: {
2872: pcireg_t reg;
2873: int num = 16 << parbsel;
2874: int num_per_reg = sizeof(pcireg_t) / parbsize;
2875: int i, j;
2876:
2877: /* First, dump the table */
2878: for (i = 0; i < num; i += num_per_reg) {
2879: reg = regs[o2i(off + i / num_per_reg)];
2880: printf(" %s Arbitration Table: 0x%08x\n", name, reg);
2881: }
2882: /* And then, decode each entry */
2883: for (i = 0; i < num; i += num_per_reg) {
2884: reg = regs[o2i(off + i / num_per_reg)];
2885: for (j = 0; j < num_per_reg; j++)
2886: printf(" Phase[%d]: %d\n", j, reg);
2887: }
2888: }
2889:
2890: static void
1.183.2.4 snj 2891: pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 2892: {
2893: pcireg_t reg, n;
2894: int parbtab, parbsize;
2895: pcireg_t parbsel;
2896: int varbtab, varbsize;
2897: pcireg_t varbsel;
2898: int i, count;
2899:
2900: printf("\n Virtual Channel Register\n");
2901: reg = regs[o2i(extcapoff + PCI_VC_CAP1)];
2902: printf(" Port VC Capability register 1: 0x%08x\n", reg);
2903: count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT);
2904: printf(" Extended VC Count: %d\n", count);
2905: n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT);
2906: printf(" Low Priority Extended VC Count: %u\n", n);
2907: n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK);
2908: printf(" Reference Clock: %s\n",
1.140 msaitoh 2909: (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown");
1.135 msaitoh 2910: parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE);
2911: printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize);
2912:
2913: reg = regs[o2i(extcapoff + PCI_VC_CAP2)];
2914: printf(" Port VC Capability register 2: 0x%08x\n", reg);
2915: onoff("Hardware fixed arbitration scheme",
2916: reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME);
2917: onoff("WRR arbitration with 32 phases",
2918: reg, PCI_VC_CAP2_ARB_CAP_WRR_32);
2919: onoff("WRR arbitration with 64 phases",
2920: reg, PCI_VC_CAP2_ARB_CAP_WRR_64);
2921: onoff("WRR arbitration with 128 phases",
2922: reg, PCI_VC_CAP2_ARB_CAP_WRR_128);
2923: varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
2924: printf(" VC Arbitration Table Offset: 0x%x\n", varbtab);
2925:
2926: reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;
2927: printf(" Port VC Control register: 0x%04x\n", reg);
2928: varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
2929: printf(" VC Arbitration Select: 0x%x\n", varbsel);
2930:
2931: reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;
2932: printf(" Port VC Status register: 0x%04x\n", reg);
2933: onoff("VC Arbitration Table Status",
2934: reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);
2935:
2936: for (i = 0; i < count + 1; i++) {
2937: reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];
2938: printf(" VC number %d\n", i);
2939: printf(" VC Resource Capability Register: 0x%08x\n", reg);
2940: onoff(" Non-configurable Hardware fixed arbitration scheme",
2941: reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME);
2942: onoff(" WRR arbitration with 32 phases",
2943: reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32);
2944: onoff(" WRR arbitration with 64 phases",
2945: reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64);
2946: onoff(" WRR arbitration with 128 phases",
2947: reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128);
2948: onoff(" Time-based WRR arbitration with 128 phases",
2949: reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128);
2950: onoff(" WRR arbitration with 256 phases",
2951: reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256);
2952: onoff(" Advanced Packet Switching",
2953: reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH);
2954: onoff(" Reject Snoop Transaction",
2955: reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);
2956: n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;
2957: printf(" Maximum Time Slots: %d\n", n);
2958: parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S;
2959: printf(" Port Arbitration Table offset: 0x%02x\n",
2960: parbtab);
2961:
2962: reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];
2963: printf(" VC Resource Control Register: 0x%08x\n", reg);
1.157 msaitoh 2964: printf(" TC/VC Map: 0x%02x\n",
1.135 msaitoh 2965: (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP));
2966: /*
2967: * The load Port Arbitration Table bit is used to update
2968: * the Port Arbitration logic and it's always 0 on read, so
2969: * we don't print it.
2970: */
2971: parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
1.157 msaitoh 2972: printf(" Port Arbitration Select: 0x%x\n", parbsel);
1.135 msaitoh 2973: n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);
1.174 msaitoh 2974: printf(" VC ID: %d\n", n);
1.135 msaitoh 2975: onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
2976:
2977: reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16;
2978: printf(" VC Resource Status Register: 0x%08x\n", reg);
2979: onoff(" Port Arbitration Table Status",
2980: reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE);
2981: onoff(" VC Negotiation Pending",
2982: reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);
2983:
2984: if ((parbtab != 0) && (parbsel != 0))
2985: pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab,
2986: "Port", parbsel, parbsize);
2987: }
2988:
2989: varbsize = 8;
2990: if ((varbtab != 0) && (varbsel != 0))
2991: pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab,
2992: " VC", varbsel, varbsize);
2993: }
2994:
1.181 msaitoh 2995: /*
2996: * Print Power limit. This encoding is the same among the following registers:
2997: * - The Captured Slot Power Limit in the PCIe Device Capability Register.
2998: * - The Slot Power Limit in the PCIe Slot Capability Register.
2999: * - The Base Power in the Data register of Power Budgeting capability.
3000: */
1.160 msaitoh 3001: static void
1.181 msaitoh 3002: pci_conf_print_pcie_power(uint8_t base, unsigned int scale)
1.135 msaitoh 3003: {
1.181 msaitoh 3004: unsigned int sdiv = 1;
1.162 christos 3005:
1.181 msaitoh 3006: if ((scale == 0) && (base > 0xef)) {
3007: const char *s;
1.162 christos 3008:
1.181 msaitoh 3009: switch (base) {
3010: case 0xf0:
3011: s = "239W < x <= 250W";
3012: break;
3013: case 0xf1:
3014: s = "250W < x <= 275W";
3015: break;
3016: case 0xf2:
3017: s = "275W < x <= 300W";
3018: break;
3019: default:
1.183.2.4 snj 3020: s = "reserved for greater than 300W";
1.181 msaitoh 3021: break;
1.160 msaitoh 3022: }
1.181 msaitoh 3023: printf("%s\n", s);
1.183.2.1 martin 3024: return;
1.160 msaitoh 3025: }
1.162 christos 3026:
1.181 msaitoh 3027: for (unsigned int i = scale; i > 0; i--)
3028: sdiv *= 10;
3029:
3030: printf("%u", base / sdiv);
1.162 christos 3031:
1.181 msaitoh 3032: if (scale != 0) {
3033: printf(".%u", base % sdiv);
1.135 msaitoh 3034: }
1.181 msaitoh 3035: printf ("W\n");
3036: return;
1.135 msaitoh 3037: }
3038:
3039: static const char *
3040: pci_conf_print_pwrbdgt_type(uint8_t reg)
3041: {
3042:
3043: switch (reg) {
3044: case 0x00:
3045: return "PME Aux";
3046: case 0x01:
3047: return "Auxilary";
3048: case 0x02:
3049: return "Idle";
3050: case 0x03:
3051: return "Sustained";
1.152 msaitoh 3052: case 0x04:
3053: return "Sustained (Emergency Power Reduction)";
3054: case 0x05:
3055: return "Maximum (Emergency Power Reduction)";
1.135 msaitoh 3056: case 0x07:
1.160 msaitoh 3057: return "Maximum";
1.135 msaitoh 3058: default:
3059: return "Unknown";
3060: }
3061: }
3062:
3063: static const char *
3064: pci_conf_print_pwrbdgt_pwrrail(uint8_t reg)
3065: {
3066:
3067: switch (reg) {
3068: case 0x00:
3069: return "Power(12V)";
3070: case 0x01:
3071: return "Power(3.3V)";
3072: case 0x02:
3073: return "Power(1.5V or 1.8V)";
3074: case 0x07:
3075: return "Thermal";
3076: default:
3077: return "Unknown";
3078: }
3079: }
3080:
3081: static void
1.183.2.4 snj 3082: pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3083: {
3084: pcireg_t reg;
3085:
1.160 msaitoh 3086: printf("\n Power Budgeting\n");
1.135 msaitoh 3087:
3088: reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)];
3089: printf(" Data Select register: 0x%08x\n", reg);
3090:
3091: reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)];
3092: printf(" Data register: 0x%08x\n", reg);
1.160 msaitoh 3093: printf(" Base Power: ");
1.181 msaitoh 3094: pci_conf_print_pcie_power(
3095: __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR),
3096: __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE));
1.135 msaitoh 3097: printf(" PM Sub State: 0x%hhx\n",
3098: (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT));
3099: printf(" PM State: D%u\n",
3100: (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT));
3101: printf(" Type: %s\n",
3102: pci_conf_print_pwrbdgt_type(
3103: (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE))));
3104: printf(" Power Rail: %s\n",
3105: pci_conf_print_pwrbdgt_pwrrail(
3106: (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL))));
3107:
3108: reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)];
3109: printf(" Power Budget Capability register: 0x%08x\n", reg);
3110: onoff("System Allocated",
3111: reg, PCI_PWRBDGT_CAP_SYSALLOC);
3112: }
3113:
3114: static const char *
3115: pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type)
3116: {
3117:
3118: switch (type) {
3119: case 0x00:
3120: return "Configuration Space Element";
3121: case 0x01:
3122: return "System Egress Port or internal sink (memory)";
3123: case 0x02:
3124: return "Internal Root Complex Link";
3125: default:
3126: return "Unknown";
3127: }
3128: }
3129:
3130: static void
1.183.2.4 snj 3131: pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3132: {
3133: pcireg_t reg;
3134: unsigned char nent, linktype;
3135: int i;
3136:
3137: printf("\n Root Complex Link Declaration\n");
3138:
3139: reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)];
3140: printf(" Element Self Description Register: 0x%08x\n", reg);
3141: printf(" Element Type: %s\n",
3142: pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg));
3143: nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT);
3144: printf(" Number of Link Entries: %hhu\n", nent);
3145: printf(" Component ID: %hhu\n",
3146: (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID));
3147: printf(" Port Number: %hhu\n",
3148: (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM));
3149: for (i = 0; i < nent; i++) {
3150: reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))];
1.140 msaitoh 3151: printf(" Link Entry %d:\n", i + 1);
3152: printf(" Link Description Register: 0x%08x\n", reg);
3153: onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID);
1.135 msaitoh 3154: linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE;
1.140 msaitoh 3155: onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE,
1.135 msaitoh 3156: "Configuration Space", "Memory-Mapped Space");
1.140 msaitoh 3157: onoff(" Associated RCRB Header", reg,
1.135 msaitoh 3158: PCI_RCLINK_DCL_LINKDESC_ARCRBH);
1.140 msaitoh 3159: printf(" Target Component ID: %hhu\n",
1.135 msaitoh 3160: (unsigned char)__SHIFTOUT(reg,
3161: PCI_RCLINK_DCL_LINKDESC_TCOMPID));
1.140 msaitoh 3162: printf(" Target Port Number: %hhu\n",
1.135 msaitoh 3163: (unsigned char)__SHIFTOUT(reg,
3164: PCI_RCLINK_DCL_LINKDESC_TPNUM));
3165:
3166: if (linktype == 0) {
3167: /* Memory-Mapped Space */
3168: reg = regs[o2i(extcapoff
3169: + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))];
1.140 msaitoh 3170: printf(" Link Address Low Register: 0x%08x\n",
3171: reg);
1.135 msaitoh 3172: reg = regs[o2i(extcapoff
3173: + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))];
1.140 msaitoh 3174: printf(" Link Address High Register: 0x%08x\n",
3175: reg);
1.135 msaitoh 3176: } else {
3177: unsigned int nb;
3178: pcireg_t lo, hi;
3179:
3180: /* Configuration Space */
3181: lo = regs[o2i(extcapoff
3182: + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))];
1.140 msaitoh 3183: printf(" Configuration Space Low Register: "
3184: "0x%08x\n", lo);
1.135 msaitoh 3185: hi = regs[o2i(extcapoff
3186: + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))];
1.140 msaitoh 3187: printf(" Configuration Space High Register: "
3188: "0x%08x\n", hi);
1.135 msaitoh 3189: nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N);
1.140 msaitoh 3190: printf(" N: %u\n", nb);
3191: printf(" Func: %hhu\n",
1.135 msaitoh 3192: (unsigned char)__SHIFTOUT(lo,
3193: PCI_RCLINK_DCL_LINKADDR_LT1_FUNC));
1.140 msaitoh 3194: printf(" Dev: %hhu\n",
1.135 msaitoh 3195: (unsigned char)__SHIFTOUT(lo,
3196: PCI_RCLINK_DCL_LINKADDR_LT1_DEV));
1.140 msaitoh 3197: printf(" Bus: %hhu\n",
1.135 msaitoh 3198: (unsigned char)__SHIFTOUT(lo,
3199: PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb)));
3200: lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i);
1.140 msaitoh 3201: printf(" Configuration Space Base Address: "
3202: "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo);
1.135 msaitoh 3203: }
3204: }
3205: }
3206:
3207: /* XXX pci_conf_print_rclink_ctl_cap */
3208:
3209: static void
1.183.2.4 snj 3210: pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3211: {
3212: pcireg_t reg;
3213:
3214: printf("\n Root Complex Event Collector Association\n");
3215:
3216: reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)];
3217: printf(" Association Bitmap for Root Complex Integrated Devices:"
3218: " 0x%08x\n", reg);
1.183.2.8 sborrill 3219:
3220: if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) {
3221: reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)];
3222: printf(" RCEC Associated Bus Numbers register: 0x%08x\n",
3223: reg);
3224: printf(" RCEC Next Bus: %u\n",
3225: (unsigned int)__SHIFTOUT(reg,
3226: PCI_RCEC_ASSOCBUSNUM_RCECNEXT));
3227: printf(" RCEC Last Bus: %u\n",
3228: (unsigned int)__SHIFTOUT(reg,
3229: PCI_RCEC_ASSOCBUSNUM_RCECLAST));
3230: }
1.135 msaitoh 3231: }
3232:
3233: /* XXX pci_conf_print_mfvc_cap */
3234: /* XXX pci_conf_print_vc2_cap */
3235: /* XXX pci_conf_print_rcrb_cap */
3236: /* XXX pci_conf_print_vendor_cap */
3237: /* XXX pci_conf_print_cac_cap */
3238:
3239: static void
1.183.2.4 snj 3240: pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3241: {
3242: pcireg_t reg, cap, ctl;
3243: unsigned int size, i;
3244:
3245: printf("\n Access Control Services\n");
3246:
3247: reg = regs[o2i(extcapoff + PCI_ACS_CAP)];
3248: cap = reg & 0xffff;
3249: ctl = reg >> 16;
3250: printf(" ACS Capability register: 0x%08x\n", cap);
3251: onoff("ACS Source Validation", cap, PCI_ACS_CAP_V);
3252: onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B);
3253: onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R);
3254: onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C);
3255: onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U);
3256: onoff("ACS Egress Control", cap, PCI_ACS_CAP_E);
3257: onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T);
3258: size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE);
3259: if (size == 0)
3260: size = 256;
3261: printf(" Egress Control Vector Size: %u\n", size);
3262: printf(" ACS Control register: 0x%08x\n", ctl);
3263: onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V);
3264: onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B);
3265: onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R);
3266: onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C);
3267: onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U);
3268: onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E);
3269: onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T);
3270:
3271: /*
3272: * If the P2P Egress Control Capability bit is 0, ignore the Egress
3273: * Control vector.
3274: */
3275: if ((cap & PCI_ACS_CAP_E) == 0)
3276: return;
3277: for (i = 0; i < size; i += 32)
1.157 msaitoh 3278: printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31,
1.135 msaitoh 3279: i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]);
3280: }
3281:
3282: static void
1.183.2.4 snj 3283: pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3284: {
3285: pcireg_t reg, cap, ctl;
3286:
3287: printf("\n Alternative Routing-ID Interpretation Register\n");
3288:
3289: reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
3290: cap = reg & 0xffff;
3291: ctl = reg >> 16;
3292: printf(" Capability register: 0x%08x\n", cap);
3293: onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M);
3294: onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A);
3295: printf(" Next Function Number: %u\n",
3296: (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN));
3297: printf(" Control register: 0x%08x\n", ctl);
3298: onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M);
3299: onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A);
3300: printf(" Function Group: %u\n",
3301: (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP));
3302: }
3303:
3304: static void
1.183.2.4 snj 3305: pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3306: {
3307: pcireg_t reg, cap, ctl;
3308: unsigned int num;
3309:
3310: printf("\n Address Translation Services\n");
3311:
3312: reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
3313: cap = reg & 0xffff;
3314: ctl = reg >> 16;
3315: printf(" Capability register: 0x%04x\n", cap);
3316: num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH);
3317: if (num == 0)
3318: num = 32;
3319: printf(" Invalidate Queue Depth: %u\n", num);
3320: onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ);
1.145 msaitoh 3321: onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL);
1.183.2.7 martin 3322: onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD);
1.135 msaitoh 3323:
3324: printf(" Control register: 0x%04x\n", ctl);
3325: printf(" Smallest Translation Unit: %u\n",
3326: (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU));
3327: onoff("Enable", reg, PCI_ATS_CTL_EN);
3328: }
3329:
3330: static void
1.183.2.4 snj 3331: pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3332: {
3333: pcireg_t lo, hi;
3334:
3335: printf("\n Device Serial Number Register\n");
3336:
3337: lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)];
3338: hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)];
3339: printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
3340: hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff,
3341: lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff);
3342: }
3343:
3344: static void
1.183.2.4 snj 3345: pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3346: {
3347: char buf[sizeof("99999 MB")];
3348: pcireg_t reg;
3349: pcireg_t total_vfs;
3350: int i;
3351: bool first;
3352:
3353: printf("\n Single Root IO Virtualization Register\n");
3354:
3355: reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)];
3356: printf(" Capabilities register: 0x%08x\n", reg);
3357: onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION);
3358: onoff("ARI Capable Hierarchy Preserved", reg,
3359: PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED);
3360: if (reg & PCI_SRIOV_CAP_VF_MIGRATION) {
1.158 msaitoh 3361: printf(" VF Migration Interrupt Message Number: 0x%03x\n",
1.135 msaitoh 3362: (pcireg_t)__SHIFTOUT(reg,
3363: PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N));
3364: }
3365:
3366: reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff;
3367: printf(" Control register: 0x%04x\n", reg);
3368: onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE);
3369: onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT);
3370: onoff("VF Migration Interrupt Enable", reg,
3371: PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE);
3372: onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE);
3373: onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER);
3374:
3375: reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16;
3376: printf(" Status register: 0x%04x\n", reg);
3377: onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION);
3378:
3379: reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff;
3380: printf(" InitialVFs register: 0x%04x\n", reg);
3381: total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16;
3382: printf(" TotalVFs register: 0x%04x\n", reg);
3383: reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff;
3384: printf(" NumVFs register: 0x%04x\n", reg);
3385:
3386: reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16;
3387: printf(" Function Dependency Link register: 0x%04x\n", reg);
3388:
3389: reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff;
3390: printf(" First VF Offset register: 0x%04x\n", reg);
3391: reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16;
3392: printf(" VF Stride register: 0x%04x\n", reg);
1.157 msaitoh 3393: reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16;
3394: printf(" Device ID: 0x%04x\n", reg);
1.135 msaitoh 3395:
3396: reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)];
3397: printf(" Supported Page Sizes register: 0x%08x\n", reg);
3398: printf(" Supported Page Size:");
3399: for (i = 0, first = true; i < 32; i++) {
3400: if (reg & __BIT(i)) {
3401: #ifdef _KERNEL
3402: format_bytes(buf, sizeof(buf), 1LL << (i + 12));
3403: #else
3404: humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B",
3405: HN_AUTOSCALE, 0);
3406: #endif
3407: printf("%s %s", first ? "" : ",", buf);
3408: first = false;
3409: }
3410: }
3411: printf("\n");
3412:
3413: reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)];
3414: printf(" System Page Sizes register: 0x%08x\n", reg);
3415: printf(" Page Size: ");
3416: if (reg != 0) {
1.171 msaitoh 3417: int bitpos = ffs(reg) -1;
3418:
3419: /* Assume only one bit is set. */
1.135 msaitoh 3420: #ifdef _KERNEL
1.171 msaitoh 3421: format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12));
1.135 msaitoh 3422: #else
1.171 msaitoh 3423: humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12),
3424: "B", HN_AUTOSCALE, 0);
1.135 msaitoh 3425: #endif
3426: printf("%s", buf);
3427: } else {
3428: printf("unknown");
3429: }
3430: printf("\n");
3431:
3432: for (i = 0; i < 6; i++) {
3433: reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))];
3434: printf(" VF BAR%d register: 0x%08x\n", i, reg);
3435: }
3436:
3437: if (total_vfs > 0) {
3438: reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)];
3439: printf(" VF Migration State Array Offset register: 0x%08x\n",
3440: reg);
3441: printf(" VF Migration State Offset: 0x%08x\n",
3442: (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET));
3443: i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR);
3444: printf(" VF Migration State BIR: ");
3445: if (i >= 0 && i <= 5) {
3446: printf("BAR%d", i);
3447: } else {
3448: printf("unknown BAR (%d)", i);
3449: }
3450: printf("\n");
3451: }
3452: }
3453:
3454: /* XXX pci_conf_print_mriov_cap */
1.138 msaitoh 3455:
3456: static void
1.183.2.4 snj 3457: pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff)
1.138 msaitoh 3458: {
3459: pcireg_t reg, cap, ctl;
3460: pcireg_t regl, regh;
3461: uint64_t addr;
3462: int n;
3463:
3464: printf("\n Multicast\n");
3465:
3466: reg = regs[o2i(extcapoff + PCI_MCAST_CTL)];
3467: cap = reg & 0xffff;
3468: ctl = reg >> 16;
3469: printf(" Capability Register: 0x%04x\n", cap);
1.139 msaitoh 3470: printf(" Max Group: %u\n",
3471: (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1);
1.138 msaitoh 3472:
3473: /* Endpoint Only */
3474: n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ);
3475: if (n > 0)
3476: printf(" Windw Size Requested: %d\n", 1 << (n - 1));
3477:
3478: onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN);
3479:
3480: printf(" Control Register: 0x%04x\n", ctl);
1.139 msaitoh 3481: printf(" Num Group: %u\n",
3482: (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1);
1.138 msaitoh 3483: onoff("Enable", reg, PCI_MCAST_CTL_ENA);
3484:
3485: regl = regs[o2i(extcapoff + PCI_MCAST_BARL)];
3486: regh = regs[o2i(extcapoff + PCI_MCAST_BARH)];
3487: printf(" Base Address Register 0: 0x%08x\n", regl);
3488: printf(" Base Address Register 1: 0x%08x\n", regh);
1.139 msaitoh 3489: printf(" Index Position: %u\n",
3490: (unsigned int)(regl & PCI_MCAST_BARL_INDPOS));
1.138 msaitoh 3491: addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR);
3492: printf(" Base Address: 0x%016" PRIx64 "\n", addr);
3493:
3494: regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)];
3495: regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)];
3496: printf(" Receive Register 0: 0x%08x\n", regl);
3497: printf(" Receive Register 1: 0x%08x\n", regh);
3498:
3499: regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)];
3500: regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)];
3501: printf(" Block All Register 0: 0x%08x\n", regl);
3502: printf(" Block All Register 1: 0x%08x\n", regh);
3503:
3504: regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)];
3505: regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)];
3506: printf(" Block Untranslated Register 0: 0x%08x\n", regl);
3507: printf(" Block Untranslated Register 1: 0x%08x\n", regh);
3508:
3509: regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)];
3510: regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)];
3511: printf(" Overlay BAR 0: 0x%08x\n", regl);
3512: printf(" Overlay BAR 1: 0x%08x\n", regh);
3513:
3514: n = regl & PCI_MCAST_OVERLAYL_SIZE;
3515: printf(" Overlay Size: ");
3516: if (n >= 6)
3517: printf("%d\n", n);
3518: else
3519: printf("off\n");
3520: addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR);
3521: printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr);
3522: }
1.135 msaitoh 3523:
3524: static void
1.183.2.4 snj 3525: pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3526: {
3527: pcireg_t reg, ctl, sta;
3528:
3529: printf("\n Page Request\n");
3530:
3531: reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)];
3532: ctl = reg & 0xffff;
3533: sta = reg >> 16;
3534: printf(" Control Register: 0x%04x\n", ctl);
3535: onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E);
3536: onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);
3537:
3538: printf(" Status Register: 0x%04x\n", sta);
3539: onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF);
3540: onoff("Unexpected Page Request Group Index", reg,
3541: PCI_PAGE_REQ_STA_UPRGI);
3542: onoff("Stopped", reg, PCI_PAGE_REQ_STA_S);
1.145 msaitoh 3543: onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR);
1.135 msaitoh 3544:
3545: reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)];
3546: printf(" Outstanding Page Request Capacity: %u\n", reg);
3547: reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)];
3548: printf(" Outstanding Page Request Allocation: %u\n", reg);
3549: }
3550:
3551: /* XXX pci_conf_print_amd_cap */
1.153 msaitoh 3552:
3553: #define MEM_PBUFSIZE sizeof("999GB")
3554:
3555: static void
1.183.2.4 snj 3556: pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff)
1.153 msaitoh 3557: {
3558: pcireg_t cap, ctl;
3559: unsigned int bars, i, n;
3560: char pbuf[MEM_PBUFSIZE];
3561:
3562: printf("\n Resizable BAR\n");
3563:
3564: /* Get Number of Resizable BARs */
3565: ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))];
3566: bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR);
3567: printf(" Number of Resizable BARs: ");
3568: if (bars <= 6)
3569: printf("%u\n", bars);
3570: else {
3571: printf("incorrect (%u)\n", bars);
3572: return;
3573: }
3574:
3575: for (n = 0; n < 6; n++) {
3576: cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))];
3577: printf(" Capability register(%u): 0x%08x\n", n, cap);
3578: if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0)
3579: continue; /* Not Used */
3580: printf(" Acceptable BAR sizes:");
3581: for (i = 4; i <= 23; i++) {
3582: if ((cap & (1 << i)) != 0) {
3583: humanize_number(pbuf, MEM_PBUFSIZE,
3584: (int64_t)1024 * 1024 << (i - 4), "B",
1.154 martin 3585: #ifdef _KERNEL
3586: 1);
3587: #else
1.153 msaitoh 3588: HN_AUTOSCALE, HN_NOSPACE);
1.154 martin 3589: #endif
1.153 msaitoh 3590: printf(" %s", pbuf);
3591: }
3592: }
3593: printf("\n");
3594:
3595: ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))];
3596: printf(" Control register(%u): 0x%08x\n", n, ctl);
3597: printf(" BAR Index: %u\n",
3598: (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX));
3599: humanize_number(pbuf, MEM_PBUFSIZE,
3600: (int64_t)1024 * 1024
3601: << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ),
1.154 martin 3602: "B",
3603: #ifdef _KERNEL
3604: 1);
3605: #else
3606: HN_AUTOSCALE, HN_NOSPACE);
3607: #endif
1.153 msaitoh 3608: printf(" BAR Size: %s\n", pbuf);
3609: }
3610: }
1.149 msaitoh 3611:
3612: static void
1.183.2.4 snj 3613: pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff)
1.149 msaitoh 3614: {
3615: pcireg_t reg;
3616: unsigned int substmax, i;
3617:
3618: printf("\n Dynamic Power Allocation\n");
3619:
3620: reg = regs[o2i(extcapoff + PCI_DPA_CAP)];
3621: printf(" Capability register: 0x%08x\n", reg);
3622: substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX);
3623: printf(" Substate Max: %u\n", substmax);
3624: printf(" Transition Latency Unit: ");
3625: switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) {
3626: case 0:
3627: printf("1ms\n");
3628: break;
3629: case 1:
3630: printf("10ms\n");
3631: break;
3632: case 2:
3633: printf("100ms\n");
3634: break;
3635: default:
3636: printf("reserved\n");
3637: break;
3638: }
3639: printf(" Power Allocation Scale: ");
3640: switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) {
3641: case 0:
3642: printf("10.0x\n");
3643: break;
3644: case 1:
3645: printf("1.0x\n");
3646: break;
3647: case 2:
3648: printf("0.1x\n");
3649: break;
3650: case 3:
3651: printf("0.01x\n");
3652: break;
3653: }
3654: printf(" Transition Latency Value 0: %u\n",
3655: (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0));
3656: printf(" Transition Latency Value 1: %u\n",
3657: (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1));
3658:
3659: reg = regs[o2i(extcapoff + PCI_DPA_LATIND)];
3660: printf(" Latency Indicatior register: 0x%08x\n", reg);
3661:
3662: reg = regs[o2i(extcapoff + PCI_DPA_CS)];
3663: printf(" Status register: 0x%04x\n", reg & 0xffff);
1.157 msaitoh 3664: printf(" Substate Status: 0x%02x\n",
1.149 msaitoh 3665: (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT));
3666: onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN);
3667: printf(" Control register: 0x%04x\n", reg >> 16);
1.157 msaitoh 3668: printf(" Substate Control: 0x%02x\n",
1.149 msaitoh 3669: (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL));
3670:
3671: for (i = 0; i <= substmax; i++)
3672: printf(" Substate Power Allocation register %d: 0x%02x\n",
3673: i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff));
3674: }
1.135 msaitoh 3675:
3676: static const char *
1.183.2.2 martin 3677: pci_conf_print_tph_req_cap_sttabloc(uint8_t val)
1.135 msaitoh 3678: {
3679:
3680: switch (val) {
1.183.2.2 martin 3681: case PCI_TPH_REQ_STTBLLOC_NONE:
1.135 msaitoh 3682: return "Not Present";
1.183.2.2 martin 3683: case PCI_TPH_REQ_STTBLLOC_TPHREQ:
1.135 msaitoh 3684: return "in the TPH Requester Capability Structure";
1.183.2.2 martin 3685: case PCI_TPH_REQ_STTBLLOC_MSIX:
1.135 msaitoh 3686: return "in the MSI-X Table";
3687: default:
3688: return "Unknown";
3689: }
3690: }
3691:
3692: static void
1.183.2.4 snj 3693: pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3694: {
3695: pcireg_t reg;
1.183.2.8 sborrill 3696: int size = 0, i, j;
1.183.2.2 martin 3697: uint8_t sttbloc;
1.135 msaitoh 3698:
3699: printf("\n TPH Requester Extended Capability\n");
3700:
3701: reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)];
3702: printf(" TPH Requester Capabililty register: 0x%08x\n", reg);
3703: onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);
3704: onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
3705: onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
3706: onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
1.183.2.2 martin 3707: sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC);
1.135 msaitoh 3708: printf(" ST Table Location: %s\n",
1.183.2.2 martin 3709: pci_conf_print_tph_req_cap_sttabloc(sttbloc));
1.183.2.8 sborrill 3710: if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) {
3711: size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1;
3712: printf(" ST Table Size: %d\n", size);
3713: }
1.182 msaitoh 3714:
3715: reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)];
3716: printf(" TPH Requester Control register: 0x%08x\n", reg);
3717: printf(" ST Mode Select: ");
3718: switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) {
3719: case PCI_TPH_REQ_CTL_STSEL_NO:
3720: printf("No ST Mode\n");
3721: break;
3722: case PCI_TPH_REQ_CTL_STSEL_IV:
3723: printf("Interrupt Vector Mode\n");
3724: break;
3725: case PCI_TPH_REQ_CTL_STSEL_DS:
3726: printf("Device Specific Mode\n");
3727: break;
3728: default:
1.183.2.10 martin 3729: printf("(reserved value)\n");
1.182 msaitoh 3730: break;
3731: }
3732: printf(" TPH Requester Enable: ");
3733: switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) {
3734: case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */
3735: printf("Not permitted\n");
3736: break;
3737: case PCI_TPH_REQ_CTL_TPHREQEN_TPH:
3738: printf("TPH and not Extended TPH\n");
3739: break;
3740: case PCI_TPH_REQ_CTL_TPHREQEN_ETPH:
3741: printf("TPH and Extended TPH");
3742: break;
3743: default:
1.183.2.10 martin 3744: printf("(reserved value)\n");
1.182 msaitoh 3745: break;
3746: }
1.183.2.2 martin 3747:
3748: if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ)
3749: return;
3750:
1.135 msaitoh 3751: for (i = 0; i < size ; i += 2) {
3752: reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)];
3753: for (j = 0; j < 2 ; j++) {
1.136 msaitoh 3754: uint32_t entry = reg;
1.135 msaitoh 3755:
3756: if (j != 0)
3757: entry >>= 16;
3758: entry &= 0xffff;
1.137 joerg 3759: printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n",
1.135 msaitoh 3760: i + j, entry);
3761: }
3762: }
3763: }
3764:
3765: static void
1.183.2.4 snj 3766: pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3767: {
3768: pcireg_t reg;
3769:
3770: printf("\n Latency Tolerance Reporting\n");
1.183.2.1 martin 3771: reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)];
3772: printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff);
3773: printf(" Max Snoop Latency: %juns\n",
3774: (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)
3775: * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))));
3776: printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16);
3777: printf(" Max No-Snoop Latency: %juns\n",
3778: (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)
3779: * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))));
1.135 msaitoh 3780: }
3781:
3782: static void
1.183.2.4 snj 3783: pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3784: {
3785: int pcie_capoff;
3786: pcireg_t reg;
3787: int i, maxlinkwidth;
3788:
3789: printf("\n Secondary PCI Express Register\n");
3790:
3791: reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)];
3792: printf(" Link Control 3 register: 0x%08x\n", reg);
3793: onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ);
3794: onoff("Link Equalization Request Interrupt Enable",
3795: reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE);
1.146 msaitoh 3796: printf(" Enable Lower SKP OS Generation Vector:");
3797: pci_print_pcie_linkspeedvector(
3798: __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV));
3799: printf("\n");
1.135 msaitoh 3800:
3801: reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)];
3802: printf(" Lane Error Status register: 0x%08x\n", reg);
3803:
3804: /* Get Max Link Width */
1.183.2.4 snj 3805: if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
1.135 msaitoh 3806: reg = regs[o2i(pcie_capoff + PCIE_LCAP)];
3807: maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
3808: } else {
3809: printf("error: falied to get PCIe capablity\n");
3810: return;
3811: }
3812: for (i = 0; i < maxlinkwidth; i++) {
3813: reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))];
3814: if (i % 2 != 0)
3815: reg >>= 16;
3816: else
3817: reg &= 0xffff;
1.157 msaitoh 3818: printf(" Equalization Control Register (Link %d): 0x%04x\n",
1.135 msaitoh 3819: i, reg);
3820: printf(" Downstream Port Transmit Preset: 0x%x\n",
3821: (pcireg_t)__SHIFTOUT(reg,
3822: PCI_SECPCIE_EQCTL_DP_XMIT_PRESET));
3823: printf(" Downstream Port Receive Hint: 0x%x\n",
3824: (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT));
3825: printf(" Upstream Port Transmit Preset: 0x%x\n",
3826: (pcireg_t)__SHIFTOUT(reg,
3827: PCI_SECPCIE_EQCTL_UP_XMIT_PRESET));
3828: printf(" Upstream Port Receive Hint: 0x%x\n",
3829: (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT));
3830: }
3831: }
3832:
3833: /* XXX pci_conf_print_pmux_cap */
3834:
3835: static void
1.183.2.4 snj 3836: pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3837: {
3838: pcireg_t reg, cap, ctl;
3839: unsigned int num;
3840:
3841: printf("\n Process Address Space ID\n");
3842:
3843: reg = regs[o2i(extcapoff + PCI_PASID_CAP)];
3844: cap = reg & 0xffff;
3845: ctl = reg >> 16;
3846: printf(" PASID Capability Register: 0x%04x\n", cap);
3847: onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM);
3848: onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE);
3849: num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1;
3850: printf(" Max PASID Width: %u\n", num);
3851:
3852: printf(" PASID Control Register: 0x%04x\n", ctl);
3853: onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN);
3854: onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN);
3855: onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN);
3856: }
3857:
3858: static void
1.183.2.4 snj 3859: pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 3860: {
3861: pcireg_t reg, cap, ctl;
3862: unsigned int num;
3863:
3864: printf("\n LN Requester\n");
3865:
3866: reg = regs[o2i(extcapoff + PCI_LNR_CAP)];
3867: cap = reg & 0xffff;
3868: ctl = reg >> 16;
3869: printf(" LNR Capability register: 0x%04x\n", cap);
3870: onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64);
3871: onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128);
3872: num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX);
3873: printf(" LNR Registration MAX: %u\n", num);
3874:
3875: printf(" LNR Control register: 0x%04x\n", ctl);
3876: onoff("LNR Enable", reg, PCI_LNR_CTL_EN);
3877: onoff("LNR CLS", reg, PCI_LNR_CTL_CLS);
3878: num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM);
3879: printf(" LNR Registration Limit: %u\n", num);
3880: }
3881:
1.176 msaitoh 3882: static void
3883: pci_conf_print_dpc_pio(pcireg_t r)
3884: {
3885: onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL);
3886: onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL);
3887: onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO);
3888: onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL);
3889: onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL);
3890: onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO);
3891: onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL);
3892: onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL);
3893: onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO);
3894: }
3895:
3896: static void
1.183.2.4 snj 3897: pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff)
1.176 msaitoh 3898: {
3899: pcireg_t reg, cap, ctl, stat, errsrc;
3900: const char *trigstr;
3901: bool rpext;
3902:
3903: printf("\n Downstream Port Containment\n");
3904:
3905: reg = regs[o2i(extcapoff + PCI_DPC_CCR)];
3906: cap = reg & 0xffff;
3907: ctl = reg >> 16;
3908: rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false;
3909: printf(" DPC Capability register: 0x%04x\n", cap);
3910: printf(" DPC Interrupt Message Number: %02x\n",
3911: (unsigned int)(cap & PCI_DPCCAP_IMSGN));
3912: onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT);
3913: onoff("Poisoned TLP Egress Blocking Supported", reg,
3914: PCI_DPCCAP_POISONTLPEB);
3915: onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG);
3916: printf(" RP PIO Log Size: %u\n",
3917: (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ));
3918: onoff("DL_Active ERR_COR Signaling Supported", reg,
3919: PCI_DPCCAP_DLACTECORS);
3920: printf(" DPC Control register: 0x%04x\n", ctl);
3921: switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) {
3922: case 0:
3923: trigstr = "disabled";
3924: break;
3925: case 1:
3926: trigstr = "enabled(ERR_FATAL)";
3927: break;
3928: case 2:
3929: trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)";
3930: break;
3931: default:
3932: trigstr = "(reserverd)";
3933: break;
3934: }
3935: printf(" DPC Trigger Enable: %s\n", trigstr);
3936: printf(" DPC Completion Control: %s Completion Status\n",
3937: (reg & PCI_DPCCTL_COMPCTL)
3938: ? "Unsupported Request(UR)" : "Completer Abort(CA)");
3939: onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE);
3940: onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN);
3941: onoff("Poisoned TLP Egress Blocking Enable", reg,
3942: PCI_DPCCTL_POISONTLPEB);
3943: onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG);
3944: onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR);
3945:
3946: reg = regs[o2i(extcapoff + PCI_DPC_STATESID)];
3947: stat = reg & 0xffff;
3948: errsrc = reg >> 16;
3949: printf(" DPC Status register: 0x%04x\n", stat);
3950: onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT);
3951: switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {
3952: case 0:
3953: trigstr = "an unmasked uncorrectable error";
3954: break;
3955: case 1:
3956: trigstr = "receiving an ERR_NONFATAL";
3957: break;
3958: case 2:
3959: trigstr = "receiving an ERR_FATAL";
3960: break;
3961: case 3:
3962: trigstr = "DPC Trigger Reason Extension field";
3963: break;
3964: }
3965: printf(" DPC Trigger Reason: Due to %s\n", trigstr);
3966: onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT);
3967: if (rpext)
3968: onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY);
3969: switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {
3970: case 0:
3971: trigstr = "Due to RP PIO error";
3972: break;
3973: case 1:
3974: trigstr = "Due to the DPC Software trigger bit";
3975: break;
3976: default:
3977: trigstr = "(reserved)";
3978: break;
3979: }
3980: printf(" DPC Trigger Reason Extension: %s\n", trigstr);
3981: if (rpext)
3982: printf(" RP PIO First Error Pointer: %02x\n",
3983: (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP));
3984: printf(" DPC Error Source ID register: 0x%04x\n", errsrc);
3985:
3986: if (!rpext)
3987: return;
3988: /*
3989: * All of the following registers are implemented by a device which has
3990: * RP Extensions for DPC
3991: */
3992:
3993: reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)];
3994: printf(" RP PIO Status Register: 0x%04x\n", reg);
3995: pci_conf_print_dpc_pio(reg);
3996:
3997: reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)];
3998: printf(" RP PIO Mask Register: 0x%04x\n", reg);
3999: pci_conf_print_dpc_pio(reg);
4000:
4001: reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)];
4002: printf(" RP PIO Severity Register: 0x%04x\n", reg);
4003: pci_conf_print_dpc_pio(reg);
4004:
4005: reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)];
4006: printf(" RP PIO SysError Register: 0x%04x\n", reg);
4007: pci_conf_print_dpc_pio(reg);
4008:
4009: reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)];
4010: printf(" RP PIO Exception Register: 0x%04x\n", reg);
4011: pci_conf_print_dpc_pio(reg);
4012:
4013: printf(" RP PIO Header Log Register: start from 0x%03x\n",
4014: extcapoff + PCI_DPC_RPPIO_HLOG);
4015: printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n",
4016: extcapoff + PCI_DPC_RPPIO_IMPSLOG);
1.183.2.5 snj 4017: printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n",
1.176 msaitoh 4018: extcapoff + PCI_DPC_RPPIO_TLPPLOG);
4019: }
4020:
1.135 msaitoh 4021:
4022: static int
4023: pci_conf_l1pm_cap_tposcale(unsigned char scale)
4024: {
4025:
4026: /* Return scale in us */
4027: switch (scale) {
4028: case 0x0:
4029: return 2;
4030: case 0x1:
4031: return 10;
4032: case 0x2:
4033: return 100;
4034: default:
4035: return -1;
4036: }
4037: }
4038:
4039: static void
1.183.2.4 snj 4040: pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff)
1.135 msaitoh 4041: {
4042: pcireg_t reg;
4043: int scale, val;
1.183.2.4 snj 4044: int pcie_capoff;
1.135 msaitoh 4045:
4046: printf("\n L1 PM Substates\n");
4047:
4048: reg = regs[o2i(extcapoff + PCI_L1PM_CAP)];
4049: printf(" L1 PM Substates Capability register: 0x%08x\n", reg);
4050: onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12);
4051: onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11);
4052: onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12);
4053: onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11);
4054: onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM);
1.183.2.4 snj 4055: /* The Link Activation Supported bit is only for Downstream Port */
4056: if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
4057: uint32_t t = regs[o2i(pcie_capoff)];
4058:
4059: if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN))
4060: onoff("Link Activation Supported", reg,
4061: PCI_L1PM_CAP_LA);
4062: }
1.135 msaitoh 4063: printf(" Port Common Mode Restore Time: %uus\n",
4064: (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT));
4065: scale = pci_conf_l1pm_cap_tposcale(
4066: __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE));
4067: val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL);
4068: printf(" Port T_POWER_ON: ");
4069: if (scale == -1)
4070: printf("unknown\n");
4071: else
4072: printf("%dus\n", val * scale);
4073:
4074: reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)];
4075: printf(" L1 PM Substates Control register 1: 0x%08x\n", reg);
4076: onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN);
4077: onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN);
4078: onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN);
4079: onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN);
1.183.2.4 snj 4080: onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE);
4081: onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA);
1.135 msaitoh 4082: printf(" Common Mode Restore Time: %uus\n",
4083: (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT));
4084: scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE));
4085: val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL);
4086: printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale);
4087:
4088: reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];
4089: printf(" L1 PM Substates Control register 2: 0x%08x\n", reg);
4090: scale = pci_conf_l1pm_cap_tposcale(
4091: __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE));
4092: val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL);
4093: printf(" T_POWER_ON: ");
4094: if (scale == -1)
4095: printf("unknown\n");
4096: else
4097: printf("%dus\n", val * scale);
1.183.2.4 snj 4098:
4099: if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) {
4100: reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];
4101: printf(" L1 PM Substates Status register: 0x%08x\n", reg);
4102: onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA);
4103: }
1.135 msaitoh 4104: }
4105:
1.147 msaitoh 4106: static void
1.183.2.4 snj 4107: pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff)
1.147 msaitoh 4108: {
4109: pcireg_t reg;
4110: uint32_t val;
4111:
4112: printf("\n Precision Time Management\n");
4113:
4114: reg = regs[o2i(extcapoff + PCI_PTM_CAP)];
4115: printf(" PTM Capability register: 0x%08x\n", reg);
4116: onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ);
4117: onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP);
4118: onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT);
4119: printf(" Local Clock Granularity: ");
4120: val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL);
4121: switch (val) {
4122: case 0:
4123: printf("Not implemented\n");
4124: break;
4125: case 0xffff:
4126: printf("> 254ns\n");
4127: break;
4128: default:
4129: printf("%uns\n", val);
4130: break;
4131: }
4132:
4133: reg = regs[o2i(extcapoff + PCI_PTM_CTL)];
4134: printf(" PTM Control register: 0x%08x\n", reg);
4135: onoff("PTM Enable", reg, PCI_PTM_CTL_EN);
4136: onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL);
4137: printf(" Effective Granularity: ");
4138: val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL);
4139: switch (val) {
4140: case 0:
4141: printf("Unknown\n");
4142: break;
4143: case 0xffff:
4144: printf("> 254ns\n");
4145: break;
4146: default:
4147: printf("%uns\n", val);
4148: break;
4149: }
4150: }
4151:
1.135 msaitoh 4152: /* XXX pci_conf_print_mpcie_cap */
4153: /* XXX pci_conf_print_frsq_cap */
4154: /* XXX pci_conf_print_rtr_cap */
4155: /* XXX pci_conf_print_desigvndsp_cap */
1.153 msaitoh 4156: /* XXX pci_conf_print_vf_resizbar_cap */
1.177 msaitoh 4157: /* XXX pci_conf_print_hierarchyid_cap */
1.183.2.2 martin 4158: /* XXX pci_conf_print_npem_cap */
1.135 msaitoh 4159:
4160: #undef MS
4161: #undef SM
4162: #undef RW
4163:
4164: static struct {
4165: pcireg_t cap;
4166: const char *name;
1.183.2.4 snj 4167: void (*printfunc)(const pcireg_t *, int);
1.135 msaitoh 4168: } pci_extcaptab[] = {
4169: { 0, "reserved",
4170: NULL },
4171: { PCI_EXTCAP_AER, "Advanced Error Reporting",
4172: pci_conf_print_aer_cap },
4173: { PCI_EXTCAP_VC, "Virtual Channel",
4174: pci_conf_print_vc_cap },
4175: { PCI_EXTCAP_SERNUM, "Device Serial Number",
4176: pci_conf_print_sernum_cap },
4177: { PCI_EXTCAP_PWRBDGT, "Power Budgeting",
4178: pci_conf_print_pwrbdgt_cap },
4179: { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration",
4180: pci_conf_print_rclink_dcl_cap },
4181: { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control",
4182: NULL },
4183: { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association",
4184: pci_conf_print_rcec_assoc_cap },
4185: { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel",
4186: NULL },
4187: { PCI_EXTCAP_VC2, "Virtual Channel",
4188: NULL },
4189: { PCI_EXTCAP_RCRB, "RCRB Header",
4190: NULL },
4191: { PCI_EXTCAP_VENDOR, "Vendor Unique",
4192: NULL },
4193: { PCI_EXTCAP_CAC, "Configuration Access Correction",
4194: NULL },
4195: { PCI_EXTCAP_ACS, "Access Control Services",
4196: pci_conf_print_acs_cap },
4197: { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation",
4198: pci_conf_print_ari_cap },
4199: { PCI_EXTCAP_ATS, "Address Translation Services",
4200: pci_conf_print_ats_cap },
4201: { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization",
4202: pci_conf_print_sriov_cap },
4203: { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization",
4204: NULL },
1.138 msaitoh 4205: { PCI_EXTCAP_MCAST, "Multicast",
4206: pci_conf_print_multicast_cap },
1.135 msaitoh 4207: { PCI_EXTCAP_PAGE_REQ, "Page Request",
4208: pci_conf_print_page_req_cap },
4209: { PCI_EXTCAP_AMD, "Reserved for AMD",
4210: NULL },
1.153 msaitoh 4211: { PCI_EXTCAP_RESIZBAR, "Resizable BAR",
4212: pci_conf_print_resizbar_cap },
1.135 msaitoh 4213: { PCI_EXTCAP_DPA, "Dynamic Power Allocation",
1.149 msaitoh 4214: pci_conf_print_dpa_cap },
1.135 msaitoh 4215: { PCI_EXTCAP_TPH_REQ, "TPH Requester",
4216: pci_conf_print_tph_req_cap },
4217: { PCI_EXTCAP_LTR, "Latency Tolerance Reporting",
4218: pci_conf_print_ltr_cap },
4219: { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express",
4220: pci_conf_print_sec_pcie_cap },
4221: { PCI_EXTCAP_PMUX, "Protocol Multiplexing",
4222: NULL },
4223: { PCI_EXTCAP_PASID, "Process Address Space ID",
4224: pci_conf_print_pasid_cap },
1.183.2.2 martin 4225: { PCI_EXTCAP_LNR, "LN Requester",
1.135 msaitoh 4226: pci_conf_print_lnr_cap },
4227: { PCI_EXTCAP_DPC, "Downstream Port Containment",
1.176 msaitoh 4228: pci_conf_print_dpc_cap },
1.135 msaitoh 4229: { PCI_EXTCAP_L1PM, "L1 PM Substates",
4230: pci_conf_print_l1pm_cap },
4231: { PCI_EXTCAP_PTM, "Precision Time Management",
1.147 msaitoh 4232: pci_conf_print_ptm_cap },
1.135 msaitoh 4233: { PCI_EXTCAP_MPCIE, "M-PCIe",
4234: NULL },
4235: { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing",
4236: NULL },
4237: { PCI_EXTCAP_RTR, "Readiness Time Reporting",
4238: NULL },
4239: { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific",
4240: NULL },
1.153 msaitoh 4241: { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs",
1.151 msaitoh 4242: NULL },
1.183.2.10 martin 4243: { 0x25, "unknown", NULL },
4244: { 0x26, "unknown", NULL },
4245: { 0x27, "unknown", NULL },
1.177 msaitoh 4246: { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
4247: NULL },
1.183.2.2 martin 4248: { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management",
4249: NULL },
1.135 msaitoh 4250: };
4251:
4252: static int
1.183.2.4 snj 4253: pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp)
1.135 msaitoh 4254: {
4255: int off;
4256: pcireg_t rval;
4257:
4258: for (off = PCI_EXTCAPLIST_BASE;
4259: off != 0;
4260: off = PCI_EXTCAPLIST_NEXT(rval)) {
4261: rval = regs[o2i(off)];
4262: if (capid == PCI_EXTCAPLIST_CAP(rval)) {
4263: if (offsetp != NULL)
4264: *offsetp = off;
4265: return 1;
1.33 kleink 4266: }
4267: }
1.135 msaitoh 4268: return 0;
4269: }
4270:
4271: static void
4272: pci_conf_print_extcaplist(
4273: #ifdef _KERNEL
4274: pci_chipset_tag_t pc, pcitag_t tag,
4275: #endif
1.183.2.4 snj 4276: const pcireg_t *regs)
1.135 msaitoh 4277: {
4278: int off;
4279: pcireg_t foundcap;
4280: pcireg_t rval;
4281: bool foundtable[__arraycount(pci_extcaptab)];
4282: unsigned int i;
4283:
4284: /* Check Extended capability structure */
4285: off = PCI_EXTCAPLIST_BASE;
4286: rval = regs[o2i(off)];
4287: if (rval == 0xffffffff || rval == 0)
4288: return;
4289:
4290: /* Clear table */
4291: for (i = 0; i < __arraycount(pci_extcaptab); i++)
4292: foundtable[i] = false;
4293:
4294: /* Print extended capability register's offset and the type first */
4295: for (;;) {
4296: printf(" Extended Capability Register at 0x%02x\n", off);
4297:
4298: foundcap = PCI_EXTCAPLIST_CAP(rval);
4299: printf(" type: 0x%04x (", foundcap);
4300: if (foundcap < __arraycount(pci_extcaptab)) {
4301: printf("%s)\n", pci_extcaptab[foundcap].name);
4302: /* Mark as found */
4303: foundtable[foundcap] = true;
4304: } else
4305: printf("unknown)\n");
4306: printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval));
4307:
4308: off = PCI_EXTCAPLIST_NEXT(rval);
4309: if (off == 0)
4310: break;
1.150 msaitoh 4311: else if (off <= PCI_CONF_SIZE) {
4312: printf(" next pointer: 0x%03x (incorrect)\n", off);
4313: return;
4314: }
1.135 msaitoh 4315: rval = regs[o2i(off)];
4316: }
4317:
4318: /*
4319: * And then, print the detail of each capability registers
4320: * in capability value's order.
4321: */
4322: for (i = 0; i < __arraycount(pci_extcaptab); i++) {
4323: if (foundtable[i] == false)
4324: continue;
4325:
4326: /*
4327: * The type was found. Search capability list again and
4328: * print all capabilities that the capabiliy type is
4329: * the same.
4330: */
1.183.2.4 snj 4331: if (pci_conf_find_extcap(regs, i, &off) == 0)
1.135 msaitoh 4332: continue;
4333: rval = regs[o2i(off)];
4334: if ((PCI_EXTCAPLIST_VERSION(rval) <= 0)
4335: || (pci_extcaptab[i].printfunc == NULL))
4336: continue;
4337:
1.183.2.4 snj 4338: pci_extcaptab[i].printfunc(regs, off);
1.135 msaitoh 4339:
4340: }
1.26 cgd 4341: }
4342:
1.79 dyoung 4343: /* Print the Secondary Status Register. */
4344: static void
4345: pci_conf_print_ssr(pcireg_t rval)
4346: {
4347: pcireg_t devsel;
4348:
4349: printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */
1.112 msaitoh 4350: onoff("66 MHz capable", rval, __BIT(5));
4351: onoff("User Definable Features (UDF) support", rval, __BIT(6));
4352: onoff("Fast back-to-back capable", rval, __BIT(7));
4353: onoff("Data parity error detected", rval, __BIT(8));
1.79 dyoung 4354:
4355: printf(" DEVSEL timing: ");
4356: devsel = __SHIFTOUT(rval, __BITS(10, 9));
4357: switch (devsel) {
4358: case 0:
4359: printf("fast");
4360: break;
4361: case 1:
4362: printf("medium");
4363: break;
4364: case 2:
4365: printf("slow");
4366: break;
4367: default:
4368: printf("unknown/reserved"); /* XXX */
4369: break;
4370: }
4371: printf(" (0x%x)\n", devsel);
4372:
1.112 msaitoh 4373: onoff("Signalled target abort", rval, __BIT(11));
4374: onoff("Received target abort", rval, __BIT(12));
4375: onoff("Received master abort", rval, __BIT(13));
4376: onoff("Received system error", rval, __BIT(14));
4377: onoff("Detected parity error", rval, __BIT(15));
1.79 dyoung 4378: }
4379:
1.27 cgd 4380: static void
1.115 msaitoh 4381: pci_conf_print_type0(
4382: #ifdef _KERNEL
4383: pci_chipset_tag_t pc, pcitag_t tag,
4384: #endif
1.167 msaitoh 4385: const pcireg_t *regs)
1.115 msaitoh 4386: {
4387: int off, width;
4388: pcireg_t rval;
1.183.2.2 martin 4389: const char *str;
1.115 msaitoh 4390:
4391: for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
4392: #ifdef _KERNEL
1.167 msaitoh 4393: width = pci_conf_print_bar(pc, tag, regs, off, NULL);
1.115 msaitoh 4394: #else
4395: width = pci_conf_print_bar(regs, off, NULL);
4396: #endif
4397: }
4398:
1.170 msaitoh 4399: printf(" Cardbus CIS Pointer: 0x%08x\n",
4400: regs[o2i(PCI_CARDBUS_CIS_REG)]);
1.115 msaitoh 4401:
4402: rval = regs[o2i(PCI_SUBSYS_ID_REG)];
4403: printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
4404: printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
4405:
1.183.2.2 martin 4406: rval = regs[o2i(PCI_MAPREG_ROM)];
4407: printf(" Expansion ROM Base Address Register: 0x%08x\n", rval);
4408: printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval));
4409: onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE);
4410: printf(" Validation Status: ");
4411: switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) {
4412: case PCI_MAPREG_ROM_VSTAT_NOTSUPP:
4413: str = "Validation not supported";
4414: break;
4415: case PCI_MAPREG_ROM_VSTAT_INPROG:
4416: str = "Validation in Progress";
4417: break;
4418: case PCI_MAPREG_ROM_VSTAT_VPASS:
4419: str = "Validation Pass. "
4420: "Valid contents, trust test was not performed";
4421: break;
4422: case PCI_MAPREG_ROM_VSTAT_VPASSTRUST:
4423: str = "Validation Pass. Valid and trusted contents";
4424: break;
4425: case PCI_MAPREG_ROM_VSTAT_VFAIL:
4426: str = "Validation Fail. Invalid contents";
4427: break;
4428: case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST:
4429: str = "Validation Fail. Valid but untrusted contents";
4430: break;
4431: case PCI_MAPREG_ROM_VSTAT_WPASS:
4432: str = "Warning Pass. Validation passed with warning. "
4433: "Valid contents, trust test was not performed";
4434: break;
4435: case PCI_MAPREG_ROM_VSTAT_WPASSTRUST:
4436: str = "Warning Pass. Validation passed with warning. "
4437: "Valid and trusted contents";
4438: break;
4439: }
4440: printf("%s\n", str);
4441: printf(" Validation Details: 0x%x\n",
4442: (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL));
1.115 msaitoh 4443:
4444: if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
4445: printf(" Capability list pointer: 0x%02x\n",
4446: PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
4447: else
4448: printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
4449:
4450: printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
4451:
4452: rval = regs[o2i(PCI_INTERRUPT_REG)];
1.170 msaitoh 4453: printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval));
4454: printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval));
1.115 msaitoh 4455: printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
4456: switch (PCI_INTERRUPT_PIN(rval)) {
4457: case PCI_INTERRUPT_PIN_NONE:
4458: printf("(none)");
4459: break;
4460: case PCI_INTERRUPT_PIN_A:
4461: printf("(pin A)");
4462: break;
4463: case PCI_INTERRUPT_PIN_B:
4464: printf("(pin B)");
4465: break;
4466: case PCI_INTERRUPT_PIN_C:
4467: printf("(pin C)");
4468: break;
4469: case PCI_INTERRUPT_PIN_D:
4470: printf("(pin D)");
4471: break;
4472: default:
4473: printf("(? ? ?)");
4474: break;
4475: }
4476: printf("\n");
4477: printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
4478: }
4479:
4480: static void
1.45 thorpej 4481: pci_conf_print_type1(
4482: #ifdef _KERNEL
4483: pci_chipset_tag_t pc, pcitag_t tag,
4484: #endif
1.167 msaitoh 4485: const pcireg_t *regs)
1.27 cgd 4486: {
1.37 nathanw 4487: int off, width;
1.183.2.4 snj 4488: pcireg_t rval, csreg;
1.110 msaitoh 4489: uint32_t base, limit;
4490: uint32_t base_h, limit_h;
4491: uint64_t pbase, plimit;
4492: int use_upper;
1.27 cgd 4493:
4494: /*
4495: * This layout was cribbed from the TI PCI2030 PCI-to-PCI
4496: * Bridge chip documentation, and may not be correct with
4497: * respect to various standards. (XXX)
4498: */
4499:
1.45 thorpej 4500: for (off = 0x10; off < 0x18; off += width) {
4501: #ifdef _KERNEL
1.167 msaitoh 4502: width = pci_conf_print_bar(pc, tag, regs, off, NULL);
1.45 thorpej 4503: #else
4504: width = pci_conf_print_bar(regs, off, NULL);
4505: #endif
4506: }
1.27 cgd 4507:
1.109 msaitoh 4508: rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
1.27 cgd 4509: printf(" Primary bus number: 0x%02x\n",
1.114 msaitoh 4510: PCI_BRIDGE_BUS_PRIMARY(rval));
1.27 cgd 4511: printf(" Secondary bus number: 0x%02x\n",
1.114 msaitoh 4512: PCI_BRIDGE_BUS_SECONDARY(rval));
1.27 cgd 4513: printf(" Subordinate bus number: 0x%02x\n",
1.114 msaitoh 4514: PCI_BRIDGE_BUS_SUBORDINATE(rval));
1.27 cgd 4515: printf(" Secondary bus latency timer: 0x%02x\n",
1.114 msaitoh 4516: PCI_BRIDGE_BUS_SEC_LATTIMER(rval));
1.27 cgd 4517:
1.109 msaitoh 4518: rval = regs[o2i(PCI_BRIDGE_STATIO_REG)];
4519: pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
1.27 cgd 4520:
1.110 msaitoh 4521: /* I/O region */
1.27 cgd 4522: printf(" I/O region:\n");
1.109 msaitoh 4523: printf(" base register: 0x%02x\n", (rval >> 0) & 0xff);
4524: printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff);
1.110 msaitoh 4525: if (PCI_BRIDGE_IO_32BITS(rval))
4526: use_upper = 1;
4527: else
4528: use_upper = 0;
1.112 msaitoh 4529: onoff("32bit I/O", rval, use_upper);
1.110 msaitoh 4530: base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8;
4531: limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT)
4532: & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8;
4533: limit |= 0x00000fff;
4534:
1.109 msaitoh 4535: rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)];
1.110 msaitoh 4536: base_h = (rval >> 0) & 0xffff;
4537: limit_h = (rval >> 16) & 0xffff;
4538: printf(" base upper 16 bits register: 0x%04x\n", base_h);
4539: printf(" limit upper 16 bits register: 0x%04x\n", limit_h);
4540:
4541: if (use_upper == 1) {
4542: base |= base_h << 16;
4543: limit |= limit_h << 16;
4544: }
4545: if (base < limit) {
4546: if (use_upper == 1)
1.183.2.3 martin 4547: printf(" range: 0x%08x-0x%08x\n", base, limit);
1.110 msaitoh 4548: else
1.183.2.3 martin 4549: printf(" range: 0x%04x-0x%04x\n", base, limit);
1.121 msaitoh 4550: } else
4551: printf(" range: not set\n");
1.27 cgd 4552:
1.110 msaitoh 4553: /* Non-prefetchable memory region */
1.109 msaitoh 4554: rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)];
1.27 cgd 4555: printf(" Memory region:\n");
4556: printf(" base register: 0x%04x\n",
1.109 msaitoh 4557: (rval >> 0) & 0xffff);
1.27 cgd 4558: printf(" limit register: 0x%04x\n",
1.109 msaitoh 4559: (rval >> 16) & 0xffff);
1.110 msaitoh 4560: base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT)
4561: & PCI_BRIDGE_MEMORY_BASE_MASK) << 20;
4562: limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT)
4563: & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff;
4564: if (base < limit)
1.183.2.3 martin 4565: printf(" range: 0x%08x-0x%08x\n", base, limit);
1.121 msaitoh 4566: else
1.183.2.3 martin 4567: printf(" range: not set\n");
1.27 cgd 4568:
1.110 msaitoh 4569: /* Prefetchable memory region */
1.109 msaitoh 4570: rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)];
1.27 cgd 4571: printf(" Prefetchable memory region:\n");
4572: printf(" base register: 0x%04x\n",
1.109 msaitoh 4573: (rval >> 0) & 0xffff);
1.27 cgd 4574: printf(" limit register: 0x%04x\n",
1.109 msaitoh 4575: (rval >> 16) & 0xffff);
1.110 msaitoh 4576: base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)];
4577: limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)];
1.109 msaitoh 4578: printf(" base upper 32 bits register: 0x%08x\n",
1.110 msaitoh 4579: base_h);
1.109 msaitoh 4580: printf(" limit upper 32 bits register: 0x%08x\n",
1.110 msaitoh 4581: limit_h);
4582: if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval))
4583: use_upper = 1;
4584: else
4585: use_upper = 0;
1.112 msaitoh 4586: onoff("64bit memory address", rval, use_upper);
1.110 msaitoh 4587: pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT)
4588: & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20;
4589: plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT)
4590: & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff;
4591: if (use_upper == 1) {
4592: pbase |= (uint64_t)base_h << 32;
4593: plimit |= (uint64_t)limit_h << 32;
4594: }
4595: if (pbase < plimit) {
4596: if (use_upper == 1)
1.183.2.3 martin 4597: printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
1.115 msaitoh 4598: "\n", pbase, plimit);
1.110 msaitoh 4599: else
1.183.2.3 martin 4600: printf(" range: 0x%08x-0x%08x\n",
1.110 msaitoh 4601: (uint32_t)pbase, (uint32_t)plimit);
1.121 msaitoh 4602: } else
1.183.2.3 martin 4603: printf(" range: not set\n");
1.27 cgd 4604:
1.183.2.4 snj 4605: csreg = regs[o2i(PCI_COMMAND_STATUS_REG)];
4606: if (csreg & PCI_STATUS_CAPLIST_SUPPORT)
1.53 drochner 4607: printf(" Capability list pointer: 0x%02x\n",
4608: PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
4609: else
4610: printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
4611:
1.27 cgd 4612: /* XXX */
4613: printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
4614:
1.109 msaitoh 4615: rval = regs[o2i(PCI_INTERRUPT_REG)];
1.27 cgd 4616: printf(" Interrupt line: 0x%02x\n",
1.109 msaitoh 4617: (rval >> 0) & 0xff);
1.27 cgd 4618: printf(" Interrupt pin: 0x%02x ",
1.109 msaitoh 4619: (rval >> 8) & 0xff);
4620: switch ((rval >> 8) & 0xff) {
1.27 cgd 4621: case PCI_INTERRUPT_PIN_NONE:
4622: printf("(none)");
4623: break;
4624: case PCI_INTERRUPT_PIN_A:
4625: printf("(pin A)");
4626: break;
4627: case PCI_INTERRUPT_PIN_B:
4628: printf("(pin B)");
4629: break;
4630: case PCI_INTERRUPT_PIN_C:
4631: printf("(pin C)");
4632: break;
4633: case PCI_INTERRUPT_PIN_D:
4634: printf("(pin D)");
4635: break;
4636: default:
1.36 mrg 4637: printf("(? ? ?)");
1.27 cgd 4638: break;
4639: }
4640: printf("\n");
1.109 msaitoh 4641: rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT)
4642: & PCI_BRIDGE_CONTROL_MASK;
1.27 cgd 4643: printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */
1.159 msaitoh 4644: onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE);
4645: onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR);
4646: onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA);
4647: onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA);
1.183.2.4 snj 4648: /*
4649: * VGA 16bit decode bit has meaning if the VGA enable bit or the
4650: * VGA Palette Snoop Enable bit is set.
4651: */
4652: if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0)
4653: || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0))
4654: onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16);
1.159 msaitoh 4655: onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT);
4656: onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR);
4657: onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B);
1.27 cgd 4658: }
4659:
4660: static void
1.45 thorpej 4661: pci_conf_print_type2(
4662: #ifdef _KERNEL
4663: pci_chipset_tag_t pc, pcitag_t tag,
4664: #endif
1.167 msaitoh 4665: const pcireg_t *regs)
1.27 cgd 4666: {
4667: pcireg_t rval;
4668:
4669: /*
4670: * XXX these need to be printed in more detail, need to be
4671: * XXX checked against specs/docs, etc.
4672: *
1.79 dyoung 4673: * This layout was cribbed from the TI PCI1420 PCI-to-CardBus
1.27 cgd 4674: * controller chip documentation, and may not be correct with
4675: * respect to various standards. (XXX)
4676: */
4677:
1.45 thorpej 4678: #ifdef _KERNEL
1.28 cgd 4679: pci_conf_print_bar(pc, tag, regs, 0x10,
1.167 msaitoh 4680: "CardBus socket/ExCA registers");
1.45 thorpej 4681: #else
4682: pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers");
4683: #endif
1.27 cgd 4684:
1.109 msaitoh 4685: /* Capability list pointer and secondary status register */
4686: rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)];
1.53 drochner 4687: if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
4688: printf(" Capability list pointer: 0x%02x\n",
1.109 msaitoh 4689: PCI_CAPLIST_PTR(rval));
1.53 drochner 4690: else
1.135 msaitoh 4691: printf(" Reserved @ 0x14: 0x%04x\n",
4692: (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0)));
1.109 msaitoh 4693: pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
1.27 cgd 4694:
1.109 msaitoh 4695: rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
1.27 cgd 4696: printf(" PCI bus number: 0x%02x\n",
1.109 msaitoh 4697: (rval >> 0) & 0xff);
1.27 cgd 4698: printf(" CardBus bus number: 0x%02x\n",
1.109 msaitoh 4699: (rval >> 8) & 0xff);
1.27 cgd 4700: printf(" Subordinate bus number: 0x%02x\n",
1.109 msaitoh 4701: (rval >> 16) & 0xff);
1.27 cgd 4702: printf(" CardBus latency timer: 0x%02x\n",
1.109 msaitoh 4703: (rval >> 24) & 0xff);
1.27 cgd 4704:
4705: /* XXX Print more prettily */
4706: printf(" CardBus memory region 0:\n");
4707: printf(" base register: 0x%08x\n", regs[o2i(0x1c)]);
4708: printf(" limit register: 0x%08x\n", regs[o2i(0x20)]);
4709: printf(" CardBus memory region 1:\n");
4710: printf(" base register: 0x%08x\n", regs[o2i(0x24)]);
4711: printf(" limit register: 0x%08x\n", regs[o2i(0x28)]);
4712: printf(" CardBus I/O region 0:\n");
4713: printf(" base register: 0x%08x\n", regs[o2i(0x2c)]);
4714: printf(" limit register: 0x%08x\n", regs[o2i(0x30)]);
4715: printf(" CardBus I/O region 1:\n");
4716: printf(" base register: 0x%08x\n", regs[o2i(0x34)]);
4717: printf(" limit register: 0x%08x\n", regs[o2i(0x38)]);
4718:
1.109 msaitoh 4719: rval = regs[o2i(PCI_INTERRUPT_REG)];
1.27 cgd 4720: printf(" Interrupt line: 0x%02x\n",
1.109 msaitoh 4721: (rval >> 0) & 0xff);
1.27 cgd 4722: printf(" Interrupt pin: 0x%02x ",
1.109 msaitoh 4723: (rval >> 8) & 0xff);
4724: switch ((rval >> 8) & 0xff) {
1.27 cgd 4725: case PCI_INTERRUPT_PIN_NONE:
4726: printf("(none)");
4727: break;
4728: case PCI_INTERRUPT_PIN_A:
4729: printf("(pin A)");
4730: break;
4731: case PCI_INTERRUPT_PIN_B:
4732: printf("(pin B)");
4733: break;
4734: case PCI_INTERRUPT_PIN_C:
4735: printf("(pin C)");
4736: break;
4737: case PCI_INTERRUPT_PIN_D:
4738: printf("(pin D)");
4739: break;
4740: default:
1.36 mrg 4741: printf("(? ? ?)");
1.27 cgd 4742: break;
4743: }
4744: printf("\n");
1.170 msaitoh 4745: rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff;
1.27 cgd 4746: printf(" Bridge control register: 0x%04x\n", rval);
1.112 msaitoh 4747: onoff("Parity error response", rval, __BIT(0));
4748: onoff("SERR# enable", rval, __BIT(1));
4749: onoff("ISA enable", rval, __BIT(2));
4750: onoff("VGA enable", rval, __BIT(3));
4751: onoff("Master abort mode", rval, __BIT(5));
4752: onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
1.115 msaitoh 4753: onoff("Functional interrupts routed by ExCA registers", rval,
4754: __BIT(7));
1.112 msaitoh 4755: onoff("Memory window 0 prefetchable", rval, __BIT(8));
4756: onoff("Memory window 1 prefetchable", rval, __BIT(9));
4757: onoff("Write posting enable", rval, __BIT(10));
1.28 cgd 4758:
4759: rval = regs[o2i(0x40)];
4760: printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
4761: printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
4762:
1.45 thorpej 4763: #ifdef _KERNEL
1.167 msaitoh 4764: pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers");
1.45 thorpej 4765: #else
4766: pci_conf_print_bar(regs, 0x44, "legacy-mode registers");
4767: #endif
1.27 cgd 4768: }
4769:
1.26 cgd 4770: void
1.45 thorpej 4771: pci_conf_print(
4772: #ifdef _KERNEL
4773: pci_chipset_tag_t pc, pcitag_t tag,
4774: void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)
4775: #else
4776: int pcifd, u_int bus, u_int dev, u_int func
4777: #endif
4778: )
1.26 cgd 4779: {
1.135 msaitoh 4780: pcireg_t regs[o2i(PCI_EXTCONF_SIZE)];
1.52 drochner 4781: int off, capoff, endoff, hdrtype;
1.125 matt 4782: const char *type_name;
1.45 thorpej 4783: #ifdef _KERNEL
1.167 msaitoh 4784: void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *);
1.45 thorpej 4785: #else
1.125 matt 4786: void (*type_printfn)(const pcireg_t *);
1.45 thorpej 4787: #endif
1.26 cgd 4788:
4789: printf("PCI configuration registers:\n");
4790:
1.135 msaitoh 4791: for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) {
1.45 thorpej 4792: #ifdef _KERNEL
1.26 cgd 4793: regs[o2i(off)] = pci_conf_read(pc, tag, off);
1.45 thorpej 4794: #else
4795: if (pcibus_conf_read(pcifd, bus, dev, func, off,
4796: ®s[o2i(off)]) == -1)
4797: regs[o2i(off)] = 0;
4798: #endif
4799: }
1.26 cgd 4800:
4801: /* common header */
4802: printf(" Common header:\n");
1.28 cgd 4803: pci_conf_print_regs(regs, 0, 16);
4804:
1.26 cgd 4805: printf("\n");
1.45 thorpej 4806: #ifdef _KERNEL
1.26 cgd 4807: pci_conf_print_common(pc, tag, regs);
1.45 thorpej 4808: #else
4809: pci_conf_print_common(regs);
4810: #endif
1.26 cgd 4811: printf("\n");
4812:
4813: /* type-dependent header */
4814: hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
4815: switch (hdrtype) { /* XXX make a table, eventually */
4816: case 0:
1.27 cgd 4817: /* Standard device header */
1.125 matt 4818: type_name = "\"normal\" device";
4819: type_printfn = &pci_conf_print_type0;
1.52 drochner 4820: capoff = PCI_CAPLISTPTR_REG;
1.28 cgd 4821: endoff = 64;
1.27 cgd 4822: break;
4823: case 1:
4824: /* PCI-PCI bridge header */
1.125 matt 4825: type_name = "PCI-PCI bridge";
4826: type_printfn = &pci_conf_print_type1;
1.52 drochner 4827: capoff = PCI_CAPLISTPTR_REG;
1.28 cgd 4828: endoff = 64;
1.26 cgd 4829: break;
1.27 cgd 4830: case 2:
4831: /* PCI-CardBus bridge header */
1.125 matt 4832: type_name = "PCI-CardBus bridge";
4833: type_printfn = &pci_conf_print_type2;
1.52 drochner 4834: capoff = PCI_CARDBUS_CAPLISTPTR_REG;
1.28 cgd 4835: endoff = 72;
1.27 cgd 4836: break;
1.26 cgd 4837: default:
1.125 matt 4838: type_name = NULL;
4839: type_printfn = 0;
1.52 drochner 4840: capoff = -1;
1.28 cgd 4841: endoff = 64;
4842: break;
1.26 cgd 4843: }
1.27 cgd 4844: printf(" Type %d ", hdrtype);
1.125 matt 4845: if (type_name != NULL)
4846: printf("(%s) ", type_name);
1.27 cgd 4847: printf("header:\n");
1.28 cgd 4848: pci_conf_print_regs(regs, 16, endoff);
1.27 cgd 4849: printf("\n");
1.125 matt 4850: if (type_printfn) {
1.45 thorpej 4851: #ifdef _KERNEL
1.167 msaitoh 4852: (*type_printfn)(pc, tag, regs);
1.45 thorpej 4853: #else
1.125 matt 4854: (*type_printfn)(regs);
1.45 thorpej 4855: #endif
4856: } else
1.26 cgd 4857: printf(" Don't know how to pretty-print type %d header.\n",
4858: hdrtype);
4859: printf("\n");
1.51 drochner 4860:
1.55 jdolecek 4861: /* capability list, if present */
1.52 drochner 4862: if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
4863: && (capoff > 0)) {
1.51 drochner 4864: #ifdef _KERNEL
1.52 drochner 4865: pci_conf_print_caplist(pc, tag, regs, capoff);
1.51 drochner 4866: #else
1.52 drochner 4867: pci_conf_print_caplist(regs, capoff);
1.51 drochner 4868: #endif
4869: printf("\n");
4870: }
1.26 cgd 4871:
4872: /* device-dependent header */
4873: printf(" Device-dependent header:\n");
1.135 msaitoh 4874: pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE);
1.49 nathanw 4875: #ifdef _KERNEL
1.183.2.8 sborrill 4876: printf("\n");
1.26 cgd 4877: if (printfn)
4878: (*printfn)(pc, tag, regs);
4879: else
4880: printf(" Don't know how to pretty-print device-dependent header.\n");
1.45 thorpej 4881: #endif /* _KERNEL */
1.135 msaitoh 4882:
4883: if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff ||
4884: regs[o2i(PCI_EXTCAPLIST_BASE)] == 0)
4885: return;
4886:
1.183.2.8 sborrill 4887: printf("\n");
1.135 msaitoh 4888: #ifdef _KERNEL
1.183.2.4 snj 4889: pci_conf_print_extcaplist(pc, tag, regs);
1.135 msaitoh 4890: #else
1.183.2.4 snj 4891: pci_conf_print_extcaplist(regs);
1.135 msaitoh 4892: #endif
4893: printf("\n");
4894:
4895: /* Extended Configuration Space, if present */
4896: printf(" Extended Configuration Space:\n");
4897: pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE);
1.1 mycroft 4898: }
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