CVS log for src/sys/dev/pci/pci_subr.c

Up to [cvs.NetBSD.org] / src / sys / dev / pci

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

s/Resorce/Resource/ in comment and log message.

fix typos in comments.

Fix typo. Found by rillig. s/vendor specific/vendor-specific/

Decode SCSI programming interface. Whitespace fix.

Add three new extended capabilities:

  - Physical Layer 32.0 GT/s
  - Alternate Protocol
  - System Firmware Intermediary

Pull up the following revisions, requested by msaitoh in ticket #1728:

	sys/dev/pci/pci_subr.c				1.232-1.239 via patch
	sys/dev/pci/pcireg.h				1.62-1.63

- Decode link control2's Compliance Preset/De-emphasis more.
- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Print "reserved" instead of "unknown" when printing equalization
  preset. One of them is known to be the default value.
- Fix typo.

Pull up the following revisions, requested by msaitoh in ticket #1412:

	sys/dev/pci/pci_subr.c				1.232-1.239 via patch
	sys/dev/pci/pcireg.h				1.62-1.63

- Decode link control2's Compliance Preset/De-emphasis more.
- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Print "reserved" instead of "unknown" when printing equalization
  preset. One of them is known to be the default value.
- Fix typo.

place additional parens around multiline string constant to appease clang

Two fixes:

  - Fix previous again. The missing comma is intended to split the long line.
  - Add missing right parenthesis.

Add missing comma. Found by tnn@.

Print Physical Layer 16.0 GT/s and Lane Margining at the Receiver extended cap.

 - Decode Physical Layer 16.0 GT/s extended capability.
 - Decode Lane Margining at the Receiver extended capability.
 - Rename pcie_link_compliance_preset_deemphasis to
   pcie_link_preset_preshoot_deemphasis because the table is referenced from
   multiple places.
 - Print "reserved" instead of "unknown" when printing equalization preset.
   One of them is known to be the default value.
 - Rename PCI_EXTCAP_PYSLAY_16GT to PCI_EXTCAP_PL16G.

%hhx -> %x

Decode link control2's Compliance Preset/De-emphasis more. Fix typo.

Pull up the following revisions, requested by msaitoh in ticket #1714:

	sys/dev/pci/pcireg.h			1.148-1.154, 1.156-1.161
	sys/dev/pci/pci_subr.c			1.217-1.222, 1.224, 1.227-1.232
						via patch
	sys/dev/pci/nvme_pci.c			1.31
	sys/dev/pci/pci.c			1.158
	sys/dev/pci/ppb.c			1.74

- Print Bridge Config Retry Enable bit and Retimer Presence Detect
  Supported bit.
- Add PCIe 4.0 stuff a little:
  - 10-bit Tag Requester/Completer.
  - Add Data link Feature extended capability.
  - Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
- Change pci_conf_print() to allocate memory for the regs dynamically
  instead of on-stack.
- Print some DPC register values not with %04x but with %08x because
  those are 32bit.
- Fix a bug that the virtual channel extended configuration's
  arbitration phase register can't be decoded correctly.
- When parsing Enhanced Allocation entries, use the correct calculation
  for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
  - Lane Margining at the Receiver
  - NVME admin interface
  - UFSHCI
  - InfiniBand
  - Host fabric
  - HDA 1.0 with vendor ext
  - USB4 HCI
  - MIPI I3C
  - Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
  prevent sign extension of product ID when shifted up into place in
  PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Remove unused shift and mask definitions.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.

Pull up the following revisions, requested by msaitoh in ticket #1384:

	sys/dev/pci/pcireg.h			1.152-1.154, 1.156-1.161
	sys/dev/pci/pci_subr.c			1.222, 1.227-1.232 via patch
	sys/dev/pci/nvme_pci.c			1.31
	sys/dev/pci/pci.c			1.158, 1.163
	sys/dev/pci/ppb.c			1.74

- When parsing Enhanced Allocation entries, use the correct calculation
  for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
  - Lane Margining at the Receiver
  - NVME admin interface
  - UFSHCI
  - InfiniBand
  - Host fabric
  - HDA 1.0 with vendor ext
  - USB4 HCI
  - MIPI I3C
  - Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
  prevent sign extension of product ID when shifted up into place in
  PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.

fix various typos in comments, log messages and documentation.

Use PCI-SIG official acronyms:

 - RP stands for Root Port.
 - RC stands for Root Complex.
 - RCIEP stands for Root Complex Integrated End Point.

Add Some PCI config information:

 - Lane Margining at the Receiver
 - NVME admin interface
 - UFSHCI
 - InfiniBand
 - Host fabric
 - HDA 1.0 with vendor ext
 - USB4 HCI
 - MIPI I3C
 - Cellular controller/modem (+ Ethernet)

add 32.0GT/s to the list of pcie speeds (PCIe 5.x.)

fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.

s/Windw/Window/ in log message.

Sync with HEAD.

s/Precision Time Management/Precision Time Measurement/

Rework the xxxVERBOSE option to share the common module-hook-based
verbose mechanism with MIIVERBOSE.  This reduces some duplicated code
and allows us to once again permit auto-unload of MIIVERBOSE.

Change details:
* Update dev/devlist2h.awk to accomodate miidevs, including generation
  of MII_STR_oui_model definitions and use of oui and model rather than
  vendor and product.  This also changes the compressed data in the
  xxxdevs_data.h files to uint32_t (since mii oui's are up to 6 hex
  digits long)
* Update a couple of phy drivers to use new calls to get verbose data
* Regen all of the xxxdevs{,_data}.h files (separate commit, coming
  very soon)
* Update mii/mii_verbose.[ch] and mii/mii_physubr.c to use the various
  DEV_VERBOSE_xxx macros
* Update the pci, usb, and hdaudio code as needed, to #include the
  xxxdevs.h files (in order to get the proper printf format strings)
* Since dev/dev_verbose.c now uses non-literal printf format strings,
  (to deal with the vendor/product vs oui/model issue), we need to
  make sure it gets compiled with -Wno-error=format-nonliteral, even
  in userland's libpci and librumpdev!
* Bump kernel version for the change in module interfaces

Welcome to 9.99.86!

XXX It might be useful in the future to extend the MII_STR_oui_model
XXX definitions to PCI as well (and perhaps USB and HDAUDIO).  This
XXX would allow for a single centralized location for the products'
XXX descriptions, rather than being dispersed among individual
XXX drivers' xxx_match tables.

Sync with HEAD.

Introduce autoconfiguration helpers based around device_compatible_entry:
- pci_compatible_match(): matches against the PCI ID.
- pci_compatible_match_subsys(): matches against PCI SUBSYS ID.
- pci_compatible_lookup(): look up entry by PCI ID.
- pci_compatible_lookup_subsys(): look up entry by PCI SUBSYS ID.
- pci_compatible_lookup_id(): look up entry by an arbitrary ID using the
  PCI ID code conventions.

- Define PCI_COMPAT_EOL as a compat data array sentinel.

Pull up following revision(s) (requested by jdolecek in ticket #1024):

	sys/dev/pci/pci_subr.c: revision 1.224

change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack

change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack

Sync with HEAD

Mostly merge changes from HEAD upto 20200411

Fix all the random __SHIFTOUT casts by introducing an intermediate macho,
and then deleting and fixing the rest.

When parsing Enhanced Allocation entries, use the correct calulation for
finding the next entry.

Pull up following revision(s) (requested by msaitoh in ticket #782):

	sys/dev/pci/pcireg.h: revision 1.150
	sys/dev/pci/pcireg.h: revision 1.151
	sys/dev/pci/pci_subr.c: revision 1.220
	sys/dev/pci/pci_subr.c: revision 1.221
	sys/dev/pci/pcireg.h: revision 1.149

- Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
   bit.
- Avoid using magic number.

Add PCIe 4.0 stuff a little:
  - 10-bit Tag Requester/Completer.
  - Add Data link Feature extended capability.
  - Add Physical Layer 16.0 GT/s extended capability. Not decode yet.

  Remove unused shift and mask definitions.

  Add comment.

Sync with head.

Add PCIe 4.0 stuff a little:

 - 10-bit Tag Requester/Completer.
 - Add Data link Feature extended capability.
 - Add Physical Layer 16.0 GT/s extended capability. Not decode yet.

- Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
  bit.
- Avoid using magic number.

Pull up the following, requested by msaitoh in ticket #629:

	sys/dev/pci/pcireg.h			1.148
	sys/dev/pci/pci_subr.c			1.218-1.219

- Fix a bug that the virtual channel extended configuration's
  arbitration phase register can't be decoded correctly.
- Fix typo.

Sync with head.

 Fix a bug that the virtual channel extended configuraton's arbitration phase
register can't be decoded correcty. Found by jmcneill.

s/enalbe/enable/

Pull up following revision(s) (requested by msaitoh in ticket #243):

	sys/dev/pci/pci_subr.c: revision 1.216
	sys/dev/pci/pci_subr.c: revision 1.217

Whitespace fixes. No functional change.

 -

Print some DPC register values not with %04x but with %08x because those
are 32bit.

Pull up the following revisions, requested by msaitoh in ticket #1388:

	sys/dev/pci/pcireg.h				1.147 via patch
	sys/dev/pci/pci_subr.c				1.212, 1.215-1.217 via patch

- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard
  Timer Status and Discard Timer SERR# Enable bit in pci_subr.c.
- Print some DPC register values not with %04x but with %08x because
  those are 32bit.
- Remove whitespace for consistency.
- Use macro.
- Whitespace fixes.

 Print some DPC register values not with %04x but with %08x because those
are 32bit.

 Whitespace fixes. No functional change.

 Remove whitespace for consistency.

Pull up following revision(s) (requested by msaitoh in ticket #1295):

	sys/dev/pci/pci_subr.c: revision 1.213
	sys/dev/pci/ppb.c: revision 1.69

Identify 16GT/s.

Pull up following revision(s) (requested by msaitoh in ticket #1292):

	sys/dev/pci/pci_subr.c: revision 1.211
	sys/dev/pci/pci_subr.c: revision 1.214

Typo (s/vaule/value/)
Print extend capability from 0x25 to 0x29 correctly.

 Print extend capability from 0x25 to 0x29 correctly.

Identify 16GT/s.

Sync with HEAD

- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
  definitions from ppbreg.h and move some definitions from ppbreg.h to
  pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
  and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
  "upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.

Typo (s/vaule/value/)

Sync with HEAD, resolve a few conflicts

Pull up following revision(s) (requested by msaitoh in ticket #1118):

	sys/dev/pci/pci_subr.c: revision 1.210
	sys/dev/pci/pci_subr.c: revision 1.207
	sys/dev/pci/pcireg.h: revision 1.143
	sys/dev/pci/pci_subr.c: revision 1.208
	sys/dev/pci/pcireg.h: revision 1.144
	sys/dev/pci/pci_subr.c: revision 1.209
	sys/dev/pci/pcireg.h: revision 1.145
	sys/dev/pci/pcireg.h: revision 1.146

  Decode PCI Enhanced Allocation.

  The register offset of the mask and pending register is depend on the 64bit
address capable bit, so fix the definition of PCI MSI vector mask and pending
register. This problem was not a real bug because PCI_MSI{MASK,PENDING} were
not used from anywhere.

  The downstream port of PCIe switch is not a root port, so don't print
root port related register. For example, Intel 63xxESB controller's
downstream port device was printed by pcictl(8) with this bug:

-----------------------------
PCI configuration registers:
   Common header:
     0x00: 0x35108086 0x00100147 0x06040001 0x00010010
     Vendor Name: Intel (0x8086)
     Device Name: 63xxESB PCI Express Downstream Port #1 (0x3510)
(snip)
   Capability register at 0x44       <=============
     type: 0x10 (PCI Express)
   Capability register at 0x60       <============= 0x60 - 0x44 = 0x1c
     type: 0x05 (MSI)
   Capability register at 0x70
     type: 0x01 (Power Management)
   Capability register at 0x80
     type: 0x0d (Subsystem vendor ID)
(snip)
   PCI Message Signaled Interrupt
     Message Control register: 0x0080
       MSI Enabled: off
       Multiple Message Capable: no (1 vector)
       Multiple Message Enabled: off (1 vector)
       64 Bit Address Capable: on
       Per-Vector Masking Capable: off
       Extended Message Data Capable: off
       Extended Message Data Enable: off
     Message Address (lower) register: 0x00000000
     Message Address (upper) register: 0x00000000
     Message Data register: 0x0000
(snip)
   PCI Express Capabilities Register
(snip)
     Root Control Register: 0x7005	<=== 0x7005 is the first two byte
       SERR on Correctable Error Enable: on   of the MSI capability structure
       SERR on Non-Fatal Error Enable: off
       SERR on Fatal Error Enable: on
       PME Interrupt Enable: off
       CRS Software Visibility Enable: off
     Root Capability Register: 0x0080
       CRS Software Visibility: off
     Root Status Register: 0x00000000
       PME Requester ID: 0x0000
       PME was asserted: off
       another PME is pending: off
   Device-dependent header:
     0x40: 0x00c00000 0x00616010 0x00000001 0x00005026  |   |<- PCIe      |
     0x50: 0x0203f441 0x10010020 0x00000000 0x004803c0  |               ->|
     0x60: 0x00807005 0x00000000 0x00000000 0x00000000  |<-     MSI     ->|
     0x70: 0xc8028001 0x00000100 0x00000000 0x00000000  |<-     PM      ->|
     0x80: 0x0000000d 0x00000000 0x00000000 0x00000000  |<- subsystem ID  |
--------------------------------------

  Add new macro PCIE_HAS_ROOTREGS(pcie_devtype) and use it. No functional
change.

  Add new PCIE_HAS_LINKREGS(pcie_devtype) and use it. No functional change.

 Add new PCIE_HAS_LINKREGS(pcie_devtype) and use it. No functional change.

 Add new macro PCIE_HAS_ROOTREGS(pcie_devtype) and use it. No functional
change.

 The downstream port of PCIe switch is not a root port, so don't print
root port related register. For example, Intel 63xxESB controller's
downstream port device was printed by pcictl(8) with this bug:

-----------------------------
PCI configuration registers:
  Common header:
    0x00: 0x35108086 0x00100147 0x06040001 0x00010010

    Vendor Name: Intel (0x8086)
    Device Name: 63xxESB PCI Express Downstream Port #1 (0x3510)
(snip)
  Capability register at 0x44       <=============
    type: 0x10 (PCI Express)
  Capability register at 0x60       <============= 0x60 - 0x44 = 0x1c
    type: 0x05 (MSI)
  Capability register at 0x70
    type: 0x01 (Power Management)
  Capability register at 0x80
    type: 0x0d (Subsystem vendor ID)
(snip)
  PCI Message Signaled Interrupt
    Message Control register: 0x0080
      MSI Enabled: off
      Multiple Message Capable: no (1 vector)
      Multiple Message Enabled: off (1 vector)
      64 Bit Address Capable: on
      Per-Vector Masking Capable: off
      Extended Message Data Capable: off
      Extended Message Data Enable: off
    Message Address (lower) register: 0x00000000
    Message Address (upper) register: 0x00000000
    Message Data register: 0x0000
(snip)
  PCI Express Capabilities Register
(snip)
    Root Control Register: 0x7005	<=== 0x7005 is the first two byte
      SERR on Correctable Error Enable: on   of the MSI capability structure
      SERR on Non-Fatal Error Enable: off
      SERR on Fatal Error Enable: on
      PME Interrupt Enable: off
      CRS Software Visibility Enable: off
    Root Capability Register: 0x0080
      CRS Software Visibility: off
    Root Status Register: 0x00000000
      PME Requester ID: 0x0000
      PME was asserted: off
      another PME is pending: off

  Device-dependent header:
    0x40: 0x00c00000 0x00616010 0x00000001 0x00005026  |   |<- PCIe      |
    0x50: 0x0203f441 0x10010020 0x00000000 0x004803c0  |               ->|
    0x60: 0x00807005 0x00000000 0x00000000 0x00000000  |<-     MSI     ->|
    0x70: 0xc8028001 0x00000100 0x00000000 0x00000000  |<-     PM      ->|
    0x80: 0x0000000d 0x00000000 0x00000000 0x00000000  |<- subsystem ID  |
--------------------------------------

Sync with HEAD, resolve a couple of conflicts

 Decode PCI Enhanced Allocation.

Pull up the following revisions(s) (requested by msaitoh in ticket #1074):
	sys/dev/pci/pci_subr.c:	revision 1.204-1.206
	sys/dev/pci/pcireg.h:	revision 1.141-1.142

Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
  register.
- Don't print TPH requester's ST Table Size if the ST table location field
  is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicable
  for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.

Sync with head

 Don't print extra newline if the PCI extended configuration space doesn't exist.

- Don't print TPH requester's ST Table Size if the ST table location field
  is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicaple
  for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.

Ssync with HEAD

Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
  register.

Pull up following revision(s) (requested by msaitoh in ticket #1028):

	sys/dev/pci/pci_subr.c: revision 1.203
	sys/dev/pci/pcireg.h: revision 1.140

  Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.

 Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.

Sync with HEAD

Pull up following revision(s) (requested by msaitoh in ticket #933):
	sys/dev/pci/pci_subr.c: revision 1.202
	sys/dev/pci/pcireg.h: revision 1.139
	sys/dev/pci/ppbreg.h: revision 1.9
VGA 16 bit decode bit is not bit 3 but bit 4.
--
- Print Power Management Control/status register in 32bit.
- Simplify.

Pull up following revision(s) (requested by msaitoh in ticket #930):
	sys/dev/pci/pci_subr.c: revision 1.201
	sys/dev/pci/pcireg.h: revision 1.138
  Fix typo. s/TPL/TLP/

- Print Power Management Control/status register in 32bit.
- Simplify.

Sync with HEAD

 Fix typo. s/TPL/TLP/

Pull up following revision(s) (requested by msaitoh in ticket #576):
	sys/dev/pci/pci_subr.c: 1.197-1.200
	sys/dev/pci/pcireg.h: 1.136-1.137
	sys/dev/pci/ppbreg.h: 1.8
 Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.
 NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.
 "s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.
Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
  determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
  because it's not used.
- Remove unsed code.
- Add PCie Link Activation ECN.
- Use macro.
- KNF.

- Add PCie Link Activation ECN.
- Use macro.
- KNF.

Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
  determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
  because it's not used.
- Remove unsed code.

 "s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.

 Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.

 NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.

update from HEAD

Pull up following revision(s) (requested by msaitoh in ticket #371):
	sys/dev/pci/pci_subr.c: revision 1.195
	sys/dev/pci/pci_subr.c: revision 1.196
  Print Error Source Identification register correctly.
  Whitespace fix.

Pull up following revision(s) (requested by msaitoh in ticket #362):
	sys/dev/pci/pcireg.h: revision 1.133
	sys/dev/pci/pcireg.h: revision 1.134
	sys/dev/pci/pcireg.h: revision 1.135
	sys/dev/pci/pci_subr.c: revision 1.190
	sys/dev/pci/pci_subr.c: revision 1.191
	sys/dev/pci/pci_subr.c: revision 1.192
	sys/dev/pci/pci_subr.c: revision 1.193
	sys/dev/pci/pci_subr.c: revision 1.194
	sys/dev/pci/pcireg.h: revision 1.132
- Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
   to PCI_EXTCAP_LNR
- Use macro.
- Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
   Not decoded yet.
  Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".
IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x
  Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.

 Whitespace fix.

 Print Error Source Identification register correctly.

 Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.

IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x

 Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".

- Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
  Not decoded yet.

Sync with HEAD

- Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
  to PCI_EXTCAP_LNR
- Use macro.

Pull up following revision(s) (requested by msaitoh in ticket #80):
	sys/dev/pci/pci_subr.c: revision 1.184
	sys/dev/pci/pci_subr.c: revision 1.185
	sys/dev/pci/pci_subr.c: revision 1.186
	sys/dev/pci/pci_subr.c: revision 1.187
	sys/dev/pci/pci_subr.c: revision 1.188
	sys/dev/pci/pci_subr.c: revision 1.189
	sys/dev/pci/pcireg.h: revision 1.131
 Add missing return to print the Slot Power Limit Value correctly.
 Fix to print the following bit fields correctly.
  -  Supported Link Speeds Vector in LCAP2
  -  Lower SKP OS Generation Supported Speed Vector  in LCAP2
  -  Lower SKP OS Reception Supported Speed Vector in LCAP2
  -  Enable Lower SKP OS Generation Vector in LCTL3
Note that the above bitfields start from 0 and the follwing bitfields start
from 1:
  -  Maximum Link Speed in LCAP
  -  Current Link Speed in LCSR
  -  Target Link Speed in LCSR2
 For the Target Link Speed in LCSR2, 0 is allowed for a device which supports
2.5GT/s only (and this check also works for devices which compliant to
versions of the base specification prior to 3.0.
Tested with BCM5709:
-      Target Link Speed: unknown value (0)
+      Target Link Speed: 2.5GT/s
 For Attention Indicator Control bit and Power Indicator Control bit, it's
allowed to be a read only value 0 if corresponding capability register bit
is 0.
 Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.
Fix printf format/argument.

Fix printf format/argument.

 Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.

 For Attention Indicator Control bit and Power Indicator Control bit, it's
allowed to be a read only value 0 if corresponding capability register bit
is 0.

 For the Target Link Speed in LCSR2, 0 is allowed for a device which supports
2.5GT/s only (and this check also works for devices which compliant to
versions of the base specification prior to 3.0.

Tested with BCM5709:
-      Target Link Speed: unknown value (0)
+      Target Link Speed: 2.5GT/s

 Fix to print the following bit fields correctly.
  -  Supported Link Speeds Vector in LCAP2
  -  Lower SKP OS Generation Supported Speed Vector  in LCAP2
  -  Lower SKP OS Reception Supported Speed Vector in LCAP2
  -  Enable Lower SKP OS Generation Vector in LCTL3

Note that the above bitfields start from 0 and the follwing bitfields start
from 1:
  -  Maximum Link Speed in LCAP
  -  Current Link Speed in LCSR
  -  Target Link Speed in LCSR2

 Add missing return to print the Slot Power Limit Value correctly.

 Print MSI Message data in 32bits when the Extended Message Data Capable bit
is set.

 Decode TPH Requester Control register.

- The Captured Slot Power Limit value is only for device which has upsteam
   port.
- The following three registers are the same encoding, so use the same
  function:
   - the Captured Slot Power Limit in the Device Capability register of PICe
     capability.
   - the Slot Power Limit in Slot Capability register of PCIe capability.
   - the Base Power and Data Scale in the Data Register of Power Budgeting
     capability.
- Fix the alternative encoding check of power limit as document. Add check if
  scale equals to 0.

Sync with HEAD

 A device except Root Complex integrated has a link, so print link related
registers on device except Root Complex Integrated Endpoint and Root Complex
Event Collector.

Sync with HEAD - tag prg-localcount2-base1

 Check slot registers if a device is PCI/PCI-X to PCI Express Bridge. Tested
with Pericom Semiconductors(Diodes) PI7C9X111SL PCIe to PCI Reverse Bridge.

Sync with HEAD

Sync with HEAD

For want of a comma, the compiler was lost.

 Add Flattening Portal Bridge capability ID and Hierarchy ID extended
capability ID.

 Add Downstream Port Containment (DPC) ECN and Enhanced DPC(eDPC) ECN.

 Add 0x for register output.

 Add missing ':'

 Use macro. No functional change.

Fix typos:
- s/Readness/Readiness/
- s/Presense/Presence/
- s/supportted/supported/
- s/Rquester/Requester/
- s/Check Enab/Check Enable/

 Fix a bug that SR-IOV's system page size was doubled. ffs()'s bit are
numbered starting from 1.

 Use macro. No functional change.

 Use correct macro "PCI_SATA_REV" instead of PCI_MSIX_CTL for SATA revision
register. This is not a real bug because PCI_SATA_REV and PCI_MSIX_CTL have
the same value.

Sync with HEAD

 Don't print BAR's window size on pcictl pciN dump again
because there is no way to know it's correct value from
userland now.

- Don't try to sizing a BAR not if a device is host bridge but a device's
  PCI_COMMAND_MEM_ENABLE is set.
- Fix 17 years old bug that all effective BARs are marked "not sized" on
  pcictl pciN dump.
- Print  BAR's window size on pcictl pciN dump.
- remove extra "(?)"

ECN: Change Root Complex Event Collector Class Code
 - Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type in PCIe
   extend capability to know whether it's RCEC or IOMMU.

 Pint PCI Interface name if available.

Add two new PCI classes:
 - processing accelerators
 - non-essential instrumentation

No functional change:
 - modify variable names
 - KNF

fix printf formats (clang build)

 Decode AGP capability.

 - Fix the base power's value in the power budget capability.
 - Fix typo (s/Maximun/Maximum/)

 Use macro. KNF. No functional change.

Fix 0x%u...

- Print Data Select and Data Scale in pci_conf_print_pcipm_cap().
- The Message Data register of MSI cap is not 32bit but 16bit.
- When the PCIE_LCAP_MAX_SPEED bitfiled is 0, it means it supports 2.5GT/s only.
- Print link de-emphasis value by "-X dB".
- Print Completion Timeout Ranges Supported filed with alphabets.
- Print TPH Completer Supported fileld's meaning.
- Print PCIE_DCAP2_MAX_EETLP correctly. 0 means 4 End-End TLP Prefixes.
- If the Supported Link Speed Vector is 0, the Link Capability 2 register is not
  implemented. Don't decode LCAP2 when the vector is 0.
- The ACS's Egress Control Vector is 32bit, so print with 0x%08x.
- Print SR-IOV's device ID.
- Use __SHIFTOUT() to avoid using magic number.
- Prefix "0x" for hexadecimal value.

Sync with HEAD

Sync with netbsd-5

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

 The Power Controller Control bit (PCIE_SLCSR_PCC) in the Slot Control & Status
Register is 0 on power on. Print "Power <on|off>" instead of "<on|off>".

Pull up following revision(s) (requested by pgoyette in ticket #1296):
	sys/dev/pci/pci_subr.c: revision 1.155 via patch
Protect against buffer overflow.

Sync with HEAD

Sync with HEAD

Protect against buffer overflow.

Stopgap fix for in-kernel compilation (differences between humanize_number(3)
and humanize_number(9)), ok: msaitoh

Decode Resizable BAR.

- pci_conf_print_pwrbdgt_base_power(): From 0xf3 to 0xff of the Base power are
  reserved above 300W (PCI 3.0 Errata).
- Emergency Power Reduction mechanism with PWRBRK signal ECN.
- Extended Message Data for MSI ECN.
- Fix typo in comment.

Add VF Resizable BARs ECN.

Sync with HEAD

 Don't follow an incorrect pointer in an extended capability header. Tested
with Super Micro X10SDV-8C-TLN4F bus 255, device 12, function 0 (BIOS 1.1b).

Add Dynamic Power Allocation (DPA) ECN support.

Sync with HEAD

 B260 "Slot Power Limit" ECN. PCIe 3.1 ECN. September 18, 2015.

Sync with HEAD

Add Precision Time Management (PTM) ECN.

Sync with HEAD (as of 26th Dec)

- Add the Auto Slot Power Limit Disable bit in Slot Control register and
  the Completion Timeout Prefix/Header Log Capable bit in the AER capability
  and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
  Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
  register and the Retimer Presence Detected bit in the Link Status 2 register
  (ECN: Extension Devices)

- ARI's function group is not bit 32-24 but 22-20.
- Add the Structure Length field in AF capability register.
- Add Enhanced Allocation extended capability ID (ECN: Enhanced Allocation (EA)
  for Memory and I/O Resources).
- Add LN System CLS (ECN: Lightweight Notification (LN) Protocol).
- Add ST Upper and Lower bit definitions (ECN: TLP Processiong Hints).
- Add the Global Invalidate bit in the ATS capability register and the PRG
  Response PASID Required bit in the Page Request status register (ECN: PASID
  Translation)
- Decode ASPM support bit more (ECN: ASPM Optionally)
- Use __BITS()

No functional change:
 - Add comments.
 - Remove obsolete comment.
 - Move definitions to better location.
 - Rename bit definition.
 - KNF.
 - Indent.

Define PCIE_XCAP_{VER,TYPE}(x) and use them.

 Fix register offset to print HyperTransport registers correctly.

- Restore pci_subr.c rev. 1.135's change in pci_conf_print_caplist().
  As wrote in the comment, HyperTransport capability appears multiple times.
  pci_conf_cap() reruns only the first entry, so it can't be used here.
- Try to decode HyperTransport capability. Currently, the capability type
  of each HyperTransport capability is printed and only the MSI Mapping
  capability is decoded.
- Style change.

 - Move PCI_INTRSTR_LEN from pcireg.h to pcivar.h.
 - In PCI-X cap, print 2nd bus's PCI-X mode, error protection type, Max clock
   frequency and Max clock period.
 - In SATA cap, print register location correctly.
 - In Virtual Channel cap, print reference clock with "ns".
 - In Root Complex Link Declaration, print Link Entry number.

Fix compile error...

 Decode SATA Capability and Multicast Extendeded Capability.

Fix format string.

 Fix a bug that the TPH ST Table is wrongly decoded. Found by llvm.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
  if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
  Currently the following extended capabilities are decoded:
   - Advanced Error Reporting
   - Virtual Channel
   - Device Serial Number
   - Power Budgeting
   - Root Complex Link Declaration
   - Root Complex Event Collector Association
   - Access Control Services
   - Alternative Routing-ID Interpretation
   - Address Translation Services
   - Single Root IO Virtualization
   - Page Request
   - TPH Requester
   - Latency Tolerance Reporting
   - Secondary PCI Express
   - Process Address Space ID
   - LN Requester
   - L1 PM Substates
  The following extended capabilities are not decoded yet:
   - Root Complex Internal Link Control
   - Multi-Function Virtual Channel
   - RCRB Header
   - Vendor Unique
   - Configuration Access Correction
   - Multiple Root IO Virtualization
   - Multicast
   - Resizable BAR
   - Dynamic Power Allocation
   - Protocol Multiplexing
   - Downstream Port Containment
   - Precision Time Management
   - M-PCIe
   - Function Reading Status Queueing
   - Readiness Time Reporting
   - Designated Vendor-Specific

Sync with HEAD

 Add NVMe.

Pull up following revision(s) (requested by msaitoh in ticket #325):
	sys/dev/pci/pcireg.h: revision 1.100
	sys/dev/pci/pci_subr.c: revision 1.133
Add PCIe CRS Software Visibility bit.

Pull up following revision(s) (requested by msaitoh in ticket #312):
	sys/dev/pci/pci_subr.c: revision 1.130
	sys/dev/pci/pci_subr.c: revision 1.131
	sys/dev/pci/pci_subr.c: revision 1.132
	sys/dev/pci/pcireg.h: revision 1.97
	sys/dev/pci/pcireg.h: revision 1.98
	sys/dev/pci/pcireg.h: revision 1.99
	sys/dev/pci/pci_subr.c: revision 1.127
	sys/dev/pci/pci_subr.c: revision 1.128
	sys/dev/pci/pci_subr.c: revision 1.129
 Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().
- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
s/genric/generic/
Add comment.
Fix typo in comment.
 Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.
- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
  is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
  the capability list part but in the detail part.
 Add some HyperTransport related defines. It's required for the MSI.

Add PCIe CRS Software Visibility bit.

- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
  is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
  the capability list part but in the detail part.

 Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.

Fix typo in comment.

s/genric/generic/

- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.

 Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().

Merge the 3 copies of devlist2h.awk that deal with 16 bit key and value
pairs to the compressed one that matt wrote.

Don't use class or typename as a variable name.

Rebase to HEAD as of a few days ago.

Rebase.

Add IOMMU and the Root Complex Event Collector.

- Remove some obsoleted comments.
- KNF.

- Add PCI-X capability stuff.
- remove extra ':' in pci_conf_print_pcie_cap()
- Add comments.

Print "range:  not set" if the decode window isn't set.

- Add some register definition for MSI and MSI-X
- print MSI-X capability

Do not crash if subclassp == NULL, seen while attaching rstx(4) which
match PCI_CLASS_UNDEFINED class.

Print some PCI Capabilities:
- Vendor specific (ID:0x09)
- Debugport (ID:0x0a)
- Subsystem (ID:0x0d)
- PCI Advanced Features (ID:0x13)

- Decode the programming interface field in the Class Code register and print
  it.
- Print the cache line size in bytes.
- Print the Link Status 2 register itself.
- Some bits were not printed if the bit is 0. Always print them using with
  onoff() macro.
- Print more bits.
- KNF.
- Use macro.
- Add comments.

- Fix calculation of supported max payload size in PCIe device capability
  register.
- Fix for PCIE_SLCSR_DLLSCE flag.
- invert PCIE_SLCSR_PCC

No functional change:
- KNF
- Sort in PCI capability ID order.
- Add comments.

- Add some register definitions (subclass, power management, etc.)
- Print some information (subclass, power management)
- Use macro.

PME# clock is not bit 2 but bit 3. Use the macro!

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Use onoff() macro.

Print 32bit I/O region flag and 64bit memory region flag.

Print the range of I/O, non-prefechable memory and prefechable memory.

Use macro.

Fix newline problem which was added in previous commit.

Print the CRS Software Visibility Enable bit and the Crosslink Supported bit.

Pull in support for pci_aprint_devinfo_fancy

sync with head

Pullup

sys/dev/pci/pcireg.h            1.74-1.82 and 1.84 via patch
sys/dev/pci/pci_subr.c          1.92-1.102, 1.104-1.105 via patch

	Add some PCI(e) register and bit definitions in pcireg.h.
	Fix the definition of PCI_PCIE_SLCAP_PSN.
	Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
	decoded.
	Print more registers in "pcictl dump".
	Fix bug in comment.

Requested by msaitoh in ticket #928

One more Gb/s -> GT/s fix.

resync from head

- Print PCIe 2.0 or higher capability registers.
- Print Link related registers only if the device is PCI Express Endpoint,
  Legacy PCI Express Endpoint or Root Port of PCI Express Root Complex.
- Don't print Root related registers if the device is Root Complex
  Integrated Endpoint and print if the device is Root Complex Event Collector.
- Not Gb/s but GT/s.

- Add some PCIe 2.0 or higher capability register definitions.
- Rename some registers.
- Add comments.
- Indent.

Delete "PCI_" from PCIX and PICE capability registers.

 Don't check whether PCIe Slot Control Register is all 0 or not.
For example, 82801I PCI Express Port #1 (devid 0x2940) is really
Root Port and it has the Root Control Register and the default
value is 0 (the document say so and really 0 (Tested with my
machine)).

- Add slot related registers
- Add root port related registers
- Fix the definition of PCI_PCIE_SLCAP_PSN
- Cleanup

Add PCI_CAP_SUBVENDOR (= 0x0d).

Decode some PCIe capability register bits.

Use macro.

 Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded. The bit field is not 0x4e000000 but 0x3e000000.

Print some PCIE device type.

Resync to 2012-11-19 00:00:00 UTC

sync with head

split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

Add NVM to the pci mass storage subclass

add an entry for subclass HD audio.

sync with head.

sync to latest -current.

print correct link speed for PCIexpress Gen2+
(the decoding code needs to be rewritten, sorry for only adding to
the mess)

sync with head

sync to latest -current.

Use an unsigned value to hold the pci_class

merge to -current.

extend the pci_aprint_devinfo slightly to cover the cases commonly
used by drivers: a short name for the quiet/naive case and a string
to override the "pcidevs" based name by one provided by the driver,
ride on yesterday's kernel minor version bump

put printing of the pci_devinfo into its own function (not inlined
by purpose) - this is a stack hog, and with this change my uTCA amd64
system boots again
a lot of similar code can be eliminated from pci device drivers this way,
but before doing so (and making the new function part of the module API)
I'd like to consider a modification to make it work with drivers which
prefer to print names from other sources (like pciide)

Merge -HEAD changes (except for PCIVERBOSE chagnes).

Redefine PCI_MSI_* and PCI_PCIE_* constants in terms of bits(3).

Use named constants and more conventional variable names in
pci_msi_establish() and pci_msi_disestablish().  Fix a couple of bugs:
pci_msi_establish() returned a pointer to the struct intrhand instead of
to the struct msi_hdl as it was intended to, and pci_msi_disestablish()
did not free(9) the msi_hdl.

Catchup with rmind-uvmplock merge.

sync with head

Add two new capabilities(PCI_CAP_SATA and PCI_CAP_PCIAF).

sync with head

Add/define some MSI support

Add code to display MSI capabilities.

Sync with HEAD (-D20101022).

sync with head

Update the various xxx_verbose modules to conform to the module subsystem's
new locking protocol.

Sync with HEAD.

sync with head.

Move setting of pci_verbose_loaded flag into the module's init routine.
This ensures that the flag is set even if the module was manually loaded
by the user rather than just auto-loaded.

sync with head

Update pciverbose module to use module_autoload() rather than module_load().
Load the module right before each attempt to use its features, and let the
module subsystem handle unloading.

sync with head

Do not try to unload the pciverbose module if it had never been loaded.

Rework the pciverbose module dispatch vectors to avoid renaming the
externally-visible entrypoint name.  Also this avoids a potential
need to bump kernel version.

Requested by dyoung@ and mrg@

Extract the vendor/product tables and related access routines into a
separate kernel module.  Update pci bus attach routine to load the
module (if available) when we're about to start scanning the bus, and
unload the module after the scan is finished.

On architectures which support loading of modules by the boot loader,
the 'pciverbose' module can be loaded and executed without needing to
rebuild the kernel.  On all architectures, using 'options PCIVERBOSE'
in the kernel configuration file will create a 'builtin' module which
is functionally equivalent to previous behavior.

XXX Although not nearly as large as the vendor and product tables,
XXX the PCI class and subclass tables might also be offloaded into
XXX the module at a future time.

XXX Cardbus (and possibly other) drivers should also be modified to
XXX load the module before scanning/attaching devices.

Sync with HEAD.

sync with head

Extract both instances of the code that prints the PCI Secondary Status
Register into a subroutine.  Use terminology similar to that which
PCI System Architecture (4th Edition) uses.  For comparison with PCI
reference books, specify flags and fields with __BIT(n) and __BITS(m, n)
instead of hexadecimal constants.

fix some bitmask in PCI Express capabilities decoding
being here, fix some typos and add a comma for clarity

sync with head.

Sync with HEAD.

Pull up following revision(s) (requested by jmcneill in ticket #485):
	sys/dev/pci/pci_subr.c: revision 1.77
Decode and display PCI Power Management registers when available.

Decode and display PCI Power Management registers when available.

Sync with HEAD.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

Store pcidevs in a more compact manner.  Instead of many string with duplicate
words, store each word individual in a long string and then store offsets
in the string to that word.  This reduces the space needed by half.

Sync with HEAD.

sync with head.

sync with head.

Oh, so that's how you spell Legacy -- thanks spellcheck!

use aprint_*_dev and device_xname

sync with HEAD

sync with head.

Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.

Sync with HEAD.

Sync with head.

machine/{bus,cpu,intr}.h -> sys/{bus,cpu,intr}.h

sync with head.

Sync with head.

Add some basic parsing of the PCI Express capabilities register.
This is enough to help detect the source of interrupt storms at least
for my Thinkpad.

sync with head.

sync with head.

Sync with head.

__unused removal on arguments; approved by core.

while we are here, also print the interrupt disable bit
in VERBOSE/pcictl

sync with head

now that we have -Wno-unused-parameter, back out all the tremendously ugly
code to gratuitously access said parameters.

more __unused

more unused variable fallout.

- sprinkle __unused on function decls.
- fix a couple of unused bugs
- no more -Wno-unused for i386

sync with head

sync with head.

add missing initializers

sync with head.

sync with head.

Sync with head.

Sync with head.

-add 2 subclasses new in rev. 3.0 of the spec, and fix a pasto in another
-get power management rev printing right

merge ktrace-lwp.

Sync with HEAD. Here we go again...

sync with head.

Only include <sys/systm.h> if _KERNEL is defined.

Use ANSI function decls and static.

sync with -current

sync with head.  xen and whitespace.  xen part is not finished.

Sync with HEAD.

Hi Perry!

nuke trailing whitespace

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

For the PCIVERBOSE case, separate vendors and products into separate tables.
Eliminating redundant pointers in the tables saves nearly 20K (20% of the table
size).  In the process, add a pci_findproduct() and make that and
pci_findvendor() return a "const char *".

pass string length (= boundary info) to pci_devinfo so that we do not run over
the end of memory region

Use the right bits for the AGP version.

Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.

fix typo in comment

Sync with HEAD.

Quell an uninitialised variable warning.

Catch up to -current.

sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work

call the capability list ptr by its name

correct caplist head for Cardbus bridges

-corrected "MSI" capability
-added some new subclasses and capabilities
-move capability list printing into a separate function and call it
 for each header type (not type 0 only)

catch up with -current on kqueue branch

Catch up to -current.

Catch up with -current.

Fortunately for us, all interrupt controllers are not 8259's

Make pci_conf_print() dump the device-dependent header in userspace, too.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

iadd subclass codes from the 2.3 spec

Sync kqueue branch with -current.

Catch up to -current.

add RCSID

Include stdio.h when compiled in userland to pull in declaration of printf etc.

Pull up revisions 1.39-1.40 (requested by ad):
  Add Mylex DACC960, CAC-EISA, and I2O block/SCSI drivers.

Catch up with -current.

Catch up to -current.

Allow this file to be used in userspace, as well.

ANSI'ify.

Update the kqueue branch to HEAD.

Fix sample code in comment; pci_conf_print() takes three arguments.

Sync with HEAD.

adapt to pci_knowndevs[] being const, make local constant arrays const

Sync with HEAD.

s/iRDA/IrDA/

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Update for current PCI device class/subclass and capability codes.
(also, tweak the I2O subclass string to be "standard" -- the removal
of version info didn't extend that far.)

I2O subclasses currently have nothing to do with the protocol version.

don't attempt to size Host Bridge BARs.  (it's a good way to die.)
provide a clue about 16-bit vs. 32-bit I/O BARs.

Pull up to netbsd-1-5 branch
Approved by: thorpej

When performing pci_config_dump:
Display the full value of 64-bit BARs.
Avoid displaying the upper 32 bits of 64-bit BARs as a separate 32-bit BAR.
  by Nathan J Williams <nathanw@netbsd.org>

Revisions pulled up:
 > cvs rdiff -r1.36 -r1.37 syssrc/sys/dev/pci/pci_subr.c

When performing pci_config_dump:
 - Display the full value of 64-bit BARs.
 - Avoid displaying the upper 32 bits of 64-bit BARs as a separate 32-bit BAR.