src/sys/dev/pci/if_wm.c - diff

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Diff for /src/sys/dev/pci/if_wm.c between version 1.289 and 1.289.2.6

version 1.289, 2014/08/10 16:44:36

version 1.289.2.6, 2015/04/19 06:50:22

Line 73

* TODO (in order of importance):

* - Check XXX'ed comments

* - Internal SERDES mode newer than or equal to 82575.

* - EEE (Energy Efficiency Ethernet)

* - MSI/MSI-X

* - Virtual Function

Line 273 struct wm_softc {

Line 272 struct wm_softc {

int sc_bus_speed; /* PCI/PCIX bus speed */

int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */

const struct wm_product *sc_wmp; /* Pointer to the wm_product entry */

uint16_t sc_pcidevid; /* PCI device ID */

wm_chip_type sc_type; /* MAC type */

int sc_rev; /* MAC revision */

wm_phy_type sc_phytype; /* PHY type */

uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/

#define WM_MEDIATYPE_UNKNOWN 0x00

#define WM_MEDIATYPE_FIBER 0x01

#define WM_MEDIATYPE_COPPER 0x02

#define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */

int sc_funcid; /* unit number of the chip (0 to 3) */

int sc_flags; /* flags; see below */

int sc_if_flags; /* last if_flags */

Line 287 struct wm_softc {

Line 291 struct wm_softc {

callout_t sc_tick_ch; /* tick callout */

bool sc_stopping;

int sc_ee_addrbits; /* EEPROM address bits */

int sc_nvm_addrbits; /* NVM address bits */

unsigned int sc_nvm_wordsize; /* NVM word size */

int sc_ich8_flash_base;

int sc_ich8_flash_bank_size;

int sc_nvm_k1_enabled;

Line 545 static void wm_tick(void *);

Line 550 static void wm_tick(void *);

static int wm_ifflags_cb(struct ethercom *);

static int wm_ioctl(struct ifnet *, u_long, void *);

/* MAC address related */

static int wm_check_alt_mac_addr(struct wm_softc *);

static uint16_t wm_check_alt_mac_addr(struct wm_softc *);

static int wm_read_mac_addr(struct wm_softc *, uint8_t *);

static void wm_set_ral(struct wm_softc *, const uint8_t *, int);

static uint32_t wm_mchash(struct wm_softc *, const uint8_t *);

Line 556 static void wm_set_pcie_completion_timeo

Line 561 static void wm_set_pcie_completion_timeo

static void wm_get_auto_rd_done(struct wm_softc *);

static void wm_lan_init_done(struct wm_softc *);

static void wm_get_cfg_done(struct wm_softc *);

static void wm_initialize_hardware_bits(struct wm_softc *);

static void wm_reset(struct wm_softc *);

static int wm_add_rxbuf(struct wm_softc *, int);

static void wm_rxdrain(struct wm_softc *);

Line 585 static int wm_intr(void *);

Line 591 static int wm_intr(void *);

* Media related.

* GMII, SGMII, TBI (and SERDES)

* GMII, SGMII, TBI, SERDES and SFP.

/* GMII related */

static void wm_gmii_reset(struct wm_softc *);

Line 622 static void wm_tbi_mediastatus(struct if

Line 628 static void wm_tbi_mediastatus(struct if

static int wm_tbi_mediachange(struct ifnet *);

static void wm_tbi_set_linkled(struct wm_softc *);

static void wm_tbi_check_link(struct wm_softc *);

/* SFP related */

static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);

static uint32_t wm_sfp_get_media_type(struct wm_softc *);

* NVM related.

* Microwire, SPI (w/wo EERD) and Flash.

/* Both spi and uwire */

/* Misc functions */

static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);

static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);

static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *);

/* Microwire */

static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);

/* SPI */

static void wm_set_spiaddrbits(struct wm_softc *);

static int wm_nvm_ready_spi(struct wm_softc *);

static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);

/* Using with EERD */

Line 718 static const struct wm_product {

Line 727 static const struct wm_product {

pci_product_id_t wmp_product;

const char *wmp_name;

wm_chip_type wmp_type;

int wmp_flags;

uint32_t wmp_flags;

#define WMP_F_1000X 0x01

#define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN

#define WMP_F_1000T 0x02

#define WMP_F_FIBER WM_MEDIATYPE_FIBER

#define WMP_F_SERDES 0x04

#define WMP_F_COPPER WM_MEDIATYPE_COPPER

#define WMP_F_SERDES WM_MEDIATYPE_SERDES

#define WMP_MEDIATYPE(x) ((x) & 0x03)

} wm_products[] = {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542,

"Intel i82542 1000BASE-X Ethernet",

WM_T_82542_2_1, WMP_F_1000X },

WM_T_82542_2_1, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER,

"Intel i82543GC 1000BASE-X Ethernet",

WM_T_82543, WMP_F_1000X },

WM_T_82543, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER,

"Intel i82543GC 1000BASE-T Ethernet",

WM_T_82543, WMP_F_1000T },

WM_T_82543, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER,

"Intel i82544EI 1000BASE-T Ethernet",

WM_T_82544, WMP_F_1000T },

WM_T_82544, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER,

"Intel i82544EI 1000BASE-X Ethernet",

WM_T_82544, WMP_F_1000X },

WM_T_82544, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER,

"Intel i82544GC 1000BASE-T Ethernet",

WM_T_82544, WMP_F_1000T },

WM_T_82544, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM,

"Intel i82544GC (LOM) 1000BASE-T Ethernet",

WM_T_82544, WMP_F_1000T },

WM_T_82544, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM,

"Intel i82540EM 1000BASE-T Ethernet",

WM_T_82540, WMP_F_1000T },

WM_T_82540, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM,

"Intel i82540EM (LOM) 1000BASE-T Ethernet",

WM_T_82540, WMP_F_1000T },

WM_T_82540, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM,

"Intel i82540EP 1000BASE-T Ethernet",

WM_T_82540, WMP_F_1000T },

WM_T_82540, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP,

"Intel i82540EP 1000BASE-T Ethernet",

WM_T_82540, WMP_F_1000T },

WM_T_82540, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP,

"Intel i82540EP 1000BASE-T Ethernet",

WM_T_82540, WMP_F_1000T },

WM_T_82540, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER,

"Intel i82545EM 1000BASE-T Ethernet",

WM_T_82545, WMP_F_1000T },

WM_T_82545, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER,

"Intel i82545GM 1000BASE-T Ethernet",

WM_T_82545_3, WMP_F_1000T },

WM_T_82545_3, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER,

"Intel i82545GM 1000BASE-X Ethernet",

WM_T_82545_3, WMP_F_1000X },

WM_T_82545_3, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES,

"Intel i82545GM Gigabit Ethernet (SERDES)",

Line 789 static const struct wm_product {

Line 800 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER,

"Intel i82546EB 1000BASE-T Ethernet",

WM_T_82546, WMP_F_1000T },

WM_T_82546, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD,

"Intel i82546EB 1000BASE-T Ethernet",

WM_T_82546, WMP_F_1000T },

WM_T_82546, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER,

"Intel i82545EM 1000BASE-X Ethernet",

WM_T_82545, WMP_F_1000X },

WM_T_82545, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER,

"Intel i82546EB 1000BASE-X Ethernet",

WM_T_82546, WMP_F_1000X },

WM_T_82546, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER,

"Intel i82546GB 1000BASE-T Ethernet",

WM_T_82546_3, WMP_F_1000T },

WM_T_82546_3, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER,

"Intel i82546GB 1000BASE-X Ethernet",

WM_T_82546_3, WMP_F_1000X },

WM_T_82546_3, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES,

"Intel i82546GB Gigabit Ethernet (SERDES)",

Line 817 static const struct wm_product {

Line 828 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,

"i82546GB quad-port Gigabit Ethernet",

WM_T_82546_3, WMP_F_1000T },

WM_T_82546_3, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,

"i82546GB quad-port Gigabit Ethernet (KSP3)",

WM_T_82546_3, WMP_F_1000T },

WM_T_82546_3, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE,

"Intel PRO/1000MT (82546GB)",

WM_T_82546_3, WMP_F_1000T },

WM_T_82546_3, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI,

"Intel i82541EI 1000BASE-T Ethernet",

WM_T_82541, WMP_F_1000T },

WM_T_82541, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM,

"Intel i82541ER (LOM) 1000BASE-T Ethernet",

WM_T_82541, WMP_F_1000T },

WM_T_82541, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE,

"Intel i82541EI Mobile 1000BASE-T Ethernet",

WM_T_82541, WMP_F_1000T },

WM_T_82541, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER,

"Intel i82541ER 1000BASE-T Ethernet",

WM_T_82541_2, WMP_F_1000T },

WM_T_82541_2, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI,

"Intel i82541GI 1000BASE-T Ethernet",

WM_T_82541_2, WMP_F_1000T },

WM_T_82541_2, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE,

"Intel i82541GI Mobile 1000BASE-T Ethernet",

WM_T_82541_2, WMP_F_1000T },

WM_T_82541_2, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI,

"Intel i82541PI 1000BASE-T Ethernet",

WM_T_82541_2, WMP_F_1000T },

WM_T_82541_2, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI,

"Intel i82547EI 1000BASE-T Ethernet",

WM_T_82547, WMP_F_1000T },

WM_T_82547, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE,

"Intel i82547EI Mobile 1000BASE-T Ethernet",

WM_T_82547, WMP_F_1000T },

WM_T_82547, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI,

"Intel i82547GI 1000BASE-T Ethernet",

WM_T_82547_2, WMP_F_1000T },

WM_T_82547_2, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER,

"Intel PRO/1000 PT (82571EB)",

WM_T_82571, WMP_F_1000T },

WM_T_82571, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER,

"Intel PRO/1000 PF (82571EB)",

WM_T_82571, WMP_F_1000X },

WM_T_82571, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES,

"Intel PRO/1000 PB (82571EB)",

Line 881 static const struct wm_product {

Line 892 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,

"Intel PRO/1000 QT (82571EB)",

WM_T_82571, WMP_F_1000T },

WM_T_82571, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER,

"Intel i82572EI 1000baseT Ethernet",

WM_T_82572, WMP_F_1000T },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,

"Intel PRO/1000 PT Quad Port Server Adapter",

WM_T_82571, WMP_F_1000T, },

WM_T_82571, WMP_F_COPPER, },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER,

"Intel Gigabit PT Quad Port Server ExpressModule",

WM_T_82571, WMP_F_COPPER, },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES,

"Intel 82571EB Dual Gigabit Ethernet (SERDES)",

WM_T_82571, WMP_F_SERDES, },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES,

"Intel 82571EB Quad Gigabit Ethernet (SERDES)",

WM_T_82571, WMP_F_SERDES, },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER,

"Intel 82571EB Quad 1000baseX Ethernet",

WM_T_82571, WMP_F_FIBER, },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER,

"Intel i82572EI 1000baseT Ethernet",

WM_T_82572, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER,

"Intel i82572EI 1000baseX Ethernet",

WM_T_82572, WMP_F_1000X },

WM_T_82572, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES,

"Intel i82572EI Gigabit Ethernet (SERDES)",

Line 901 static const struct wm_product {

Line 928 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI,

"Intel i82572EI 1000baseT Ethernet",

WM_T_82572, WMP_F_1000T },

WM_T_82572, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E,

"Intel i82573E",

WM_T_82573, WMP_F_1000T },

WM_T_82573, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT,

"Intel i82573E IAMT",

WM_T_82573, WMP_F_1000T },

WM_T_82573, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L,

"Intel i82573L Gigabit Ethernet",

WM_T_82573, WMP_F_1000T },

WM_T_82573, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L,

"Intel i82574L",

WM_T_82574, WMP_F_1000T },

WM_T_82574, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA,

"Intel i82574L",

WM_T_82574, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V,

"Intel i82583V",

WM_T_82583, WMP_F_1000T },

WM_T_82583, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,

"i80003 dual 1000baseT Ethernet",

WM_T_80003, WMP_F_1000T },

WM_T_80003, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,

"i80003 dual 1000baseX Ethernet",

WM_T_80003, WMP_F_1000T },

WM_T_80003, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,

"Intel i80003ES2 dual Gigabit Ethernet (SERDES)",

Line 937 static const struct wm_product {

Line 968 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,

"Intel i80003 1000baseT Ethernet",

WM_T_80003, WMP_F_1000T },

WM_T_80003, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,

"Intel i80003 Gigabit Ethernet (SERDES)",

Line 945 static const struct wm_product {

Line 976 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT,

"Intel i82801H (M_AMT) LAN Controller",

WM_T_ICH8, WMP_F_1000T },

WM_T_ICH8, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT,

"Intel i82801H (AMT) LAN Controller",

WM_T_ICH8, WMP_F_1000T },

WM_T_ICH8, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN,

"Intel i82801H LAN Controller",

WM_T_ICH8, WMP_F_1000T },

WM_T_ICH8, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN,

"Intel i82801H (IFE) LAN Controller",

WM_T_ICH8, WMP_F_1000T },

WM_T_ICH8, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN,

"Intel i82801H (M) LAN Controller",

WM_T_ICH8, WMP_F_1000T },

WM_T_ICH8, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT,

"Intel i82801H IFE (GT) LAN Controller",

WM_T_ICH8, WMP_F_1000T },

WM_T_ICH8, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G,

"Intel i82801H IFE (G) LAN Controller",

WM_T_ICH8, WMP_F_1000T },

WM_T_ICH8, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT,

"82801I (AMT) LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE,

"82801I LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G,

"82801I (G) LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT,

"82801I (GT) LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C,

"82801I (C) LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M,

"82801I mobile LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V,

"82801I mobile (V) LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,

"82801I mobile (AMT) LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM,

"82567LM-4 LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3,

"82567V-3 LAN Controller",

WM_T_ICH9, WMP_F_1000T },

WM_T_ICH9, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM,

"82567LM-2 LAN Controller",

WM_T_ICH10, WMP_F_1000T },

WM_T_ICH10, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF,

"82567LF-2 LAN Controller",

WM_T_ICH10, WMP_F_1000T },

WM_T_ICH10, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM,

"82567LM-3 LAN Controller",

WM_T_ICH10, WMP_F_1000T },

WM_T_ICH10, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF,

"82567LF-3 LAN Controller",

WM_T_ICH10, WMP_F_1000T },

WM_T_ICH10, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V,

"82567V-2 LAN Controller",

WM_T_ICH10, WMP_F_1000T },

WM_T_ICH10, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V,

"82567V-3? LAN Controller",

WM_T_ICH10, WMP_F_1000T },

WM_T_ICH10, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE,

"HANKSVILLE LAN Controller",

WM_T_ICH10, WMP_F_1000T },

WM_T_ICH10, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM,

"PCH LAN (82577LM) Controller",

WM_T_PCH, WMP_F_1000T },

WM_T_PCH, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC,

"PCH LAN (82577LC) Controller",

WM_T_PCH, WMP_F_1000T },

WM_T_PCH, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM,

"PCH LAN (82578DM) Controller",

WM_T_PCH, WMP_F_1000T },

WM_T_PCH, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC,

"PCH LAN (82578DC) Controller",

WM_T_PCH, WMP_F_1000T },

WM_T_PCH, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM,

"PCH2 LAN (82579LM) Controller",

WM_T_PCH2, WMP_F_1000T },

WM_T_PCH2, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V,

"PCH2 LAN (82579V) Controller",

WM_T_PCH2, WMP_F_1000T },

WM_T_PCH2, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER,

"82575EB dual-1000baseT Ethernet",

WM_T_82575, WMP_F_1000T },

WM_T_82575, WMP_F_COPPER },

#if 0

* not sure if WMP_F_1000X or WMP_F_SERDES - we do not have it - so

* disabled for now ...

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES,

"82575EB dual-1000baseX Ethernet (SERDES)",

WM_T_82575, WMP_F_SERDES },

#endif

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER,

"82575GB quad-1000baseT Ethernet",

WM_T_82575, WMP_F_1000T },

WM_T_82575, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM,

"82575GB quad-1000baseT Ethernet (PM)",

WM_T_82575, WMP_F_1000T },

WM_T_82575, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER,

"82576 1000BaseT Ethernet",

WM_T_82576, WMP_F_1000T },

WM_T_82576, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER,

"82576 1000BaseX Ethernet",

WM_T_82576, WMP_F_1000X },

WM_T_82576, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES,

"82576 gigabit Ethernet (SERDES)",

Line 1064 static const struct wm_product {

Line 1089 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER,

"82576 quad-1000BaseT Ethernet",

WM_T_82576, WMP_F_1000T },

WM_T_82576, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2,

"82576 Gigabit ET2 Quad Port Server Adapter",

WM_T_82576, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS,

"82576 gigabit Ethernet",

WM_T_82576, WMP_F_1000T },

WM_T_82576, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES,

"82576 gigabit Ethernet (SERDES)",

Line 1078 static const struct wm_product {

Line 1108 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER,

"82580 1000BaseT Ethernet",

WM_T_82580, WMP_F_1000T },

WM_T_82580, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER,

"82580 1000BaseX Ethernet",

WM_T_82580, WMP_F_1000X },

WM_T_82580, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES,

"82580 1000BaseT Ethernet (SERDES)",

Line 1089 static const struct wm_product {

Line 1119 static const struct wm_product {

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII,

"82580 gigabit Ethernet (SGMII)",

WM_T_82580, WMP_F_1000T },

WM_T_82580, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL,

"82580 dual-1000BaseT Ethernet",

WM_T_82580, WMP_F_1000T },

WM_T_82580, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_ER,

"82580 1000BaseT Ethernet",

WM_T_82580ER, WMP_F_1000T },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_ER_DUAL,

"82580 dual-1000BaseT Ethernet",

WM_T_82580ER, WMP_F_1000T },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER,

"82580 quad-1000BaseX Ethernet",

WM_T_82580, WMP_F_1000X },

WM_T_82580, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII,

"DH89XXCC Gigabit Ethernet (SGMII)",

WM_T_82580, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES,

"DH89XXCC Gigabit Ethernet (SERDES)",

WM_T_82580, WMP_F_SERDES },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE,

"DH89XXCC 1000BASE-KX Ethernet",

WM_T_82580, WMP_F_SERDES },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP,

"DH89XXCC Gigabit Ethernet (SFP)",

WM_T_82580, WMP_F_SERDES },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER,

"I350 Gigabit Network Connection",

WM_T_I350, WMP_F_1000T },

WM_T_I350, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER,

"I350 Gigabit Fiber Network Connection",

WM_T_I350, WMP_F_1000X },

WM_T_I350, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES,

"I350 Gigabit Backplane Connection",

WM_T_I350, WMP_F_SERDES },

#if 0

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4,

"I350 Quad Port Gigabit Ethernet",

WM_T_I350, WMP_F_SERDES },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII,

"I350 Gigabit Connection",

WM_T_I350, WMP_F_1000T },

WM_T_I350, WMP_F_COPPER },

#endif

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII,

"I354 Gigabit Connection",

WM_T_I354, WMP_F_1000T },

WM_T_I354, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1,

"I210-T1 Ethernet Server Adapter",

WM_T_I210, WMP_F_1000T },

WM_T_I210, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1,

"I210 Ethernet (Copper OEM)",

WM_T_I210, WMP_F_1000T },

WM_T_I210, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT,

"I210 Ethernet (Copper IT)",

WM_T_I210, WMP_F_1000T },

WM_T_I210, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF,

"I210 Ethernet (FLASH less)",

WM_T_I210, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER,

"I210 Gigabit Ethernet (Fiber)",

WM_T_I210, WMP_F_1000X },

WM_T_I210, WMP_F_FIBER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES,

"I210 Gigabit Ethernet (SERDES)",

WM_T_I210, WMP_F_SERDES },

#if 0

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF,

"I210 Gigabit Ethernet (FLASH less)",

WM_T_I210, WMP_F_SERDES },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII,

"I210 Gigabit Ethernet (SGMII)",

WM_T_I210, WMP_F_SERDES },

WM_T_I210, WMP_F_COPPER },

#endif

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER,

"I211 Ethernet (COPPER)",

WM_T_I211, WMP_F_1000T },

WM_T_I211, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V,

"I217 V Ethernet Connection",

WM_T_PCH_LPT, WMP_F_1000T },

WM_T_PCH_LPT, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM,

"I217 LM Ethernet Connection",

WM_T_PCH_LPT, WMP_F_1000T },

WM_T_PCH_LPT, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V,

"I218 V Ethernet Connection",

WM_T_PCH_LPT, WMP_F_1000T },

WM_T_PCH_LPT, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2,

"I218 V Ethernet Connection",

WM_T_PCH_LPT, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3,

"I218 V Ethernet Connection",

WM_T_PCH_LPT, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM,

"I218 LM Ethernet Connection",

WM_T_PCH_LPT, WMP_F_1000T },

WM_T_PCH_LPT, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2,

"I218 LM Ethernet Connection",

WM_T_PCH_LPT, WMP_F_COPPER },

{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3,

"I218 LM Ethernet Connection",

WM_T_PCH_LPT, WMP_F_COPPER },

{ 0, 0,

NULL,

0, 0 },

Line 1278 wm_attach(device_t parent, device_t self

Line 1348 wm_attach(device_t parent, device_t self

pcireg_t preg, memtype;

uint16_t eeprom_data, apme_mask;

bool force_clear_smbi;

uint32_t link_mode;

uint32_t reg;

char intrbuf[PCI_INTRSTR_LEN];

Line 1285 wm_attach(device_t parent, device_t self

Line 1356 wm_attach(device_t parent, device_t self

callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS);

sc->sc_stopping = false;

sc->sc_wmp = wmp = wm_lookup(pa);

wmp = wm_lookup(pa);

#ifdef DIAGNOSTIC

if (wmp == NULL) {

printf("\n");

panic("wm_attach: impossible");

}

#endif

sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags);

sc->sc_pc = pa->pa_pc;

sc->sc_pcitag = pa->pa_tag;

Line 1299 wm_attach(device_t parent, device_t self

Line 1373 wm_attach(device_t parent, device_t self

else

sc->sc_dmat = pa->pa_dmat;

sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);

sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));

pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);

Line 1314 wm_attach(device_t parent, device_t self

Line 1389 wm_attach(device_t parent, device_t self

}

if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)

|| (sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)

|| (sc->sc_type == WM_T_82580)

|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)

|| (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))

sc->sc_flags |= WM_F_NEWQUEUE;

Line 1433 wm_attach(device_t parent, device_t self

Line 1508 wm_attach(device_t parent, device_t self

if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)

|| (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003)

|| (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)

|| (sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)

|| (sc->sc_type == WM_T_82580)

|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))

sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)

>> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;

Line 1646 wm_attach(device_t parent, device_t self

Line 1721 wm_attach(device_t parent, device_t self

case WM_T_82543:

case WM_T_82544:

/* Microwire */

sc->sc_ee_addrbits = 6;

sc->sc_nvm_wordsize = 64;

sc->sc_nvm_addrbits = 6;

break;

case WM_T_82540:

case WM_T_82545:

Line 1655 wm_attach(device_t parent, device_t self

Line 1731 wm_attach(device_t parent, device_t self

case WM_T_82546_3:

/* Microwire */

reg = CSR_READ(sc, WMREG_EECD);

if (reg & EECD_EE_SIZE)

if (reg & EECD_EE_SIZE) {

sc->sc_ee_addrbits = 8;

sc->sc_nvm_wordsize = 256;

else

sc->sc_nvm_addrbits = 8;

sc->sc_ee_addrbits = 6;

} else {

sc->sc_nvm_wordsize = 64;

sc->sc_nvm_addrbits = 6;

}

sc->sc_flags |= WM_F_LOCK_EECD;

break;

case WM_T_82541:

case WM_T_82541_2:

case WM_T_82547:

case WM_T_82547_2:

sc->sc_flags |= WM_F_LOCK_EECD;

reg = CSR_READ(sc, WMREG_EECD);

if (reg & EECD_EE_TYPE) {

/* SPI */

wm_set_spiaddrbits(sc);

sc->sc_flags |= WM_F_EEPROM_SPI;

} else

wm_nvm_set_addrbits_size_eecd(sc);

} else {

/* Microwire */

sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6;

if ((reg & EECD_EE_ABITS) != 0) {

sc->sc_flags |= WM_F_LOCK_EECD;

sc->sc_nvm_wordsize = 256;

sc->sc_nvm_addrbits = 8;

} else {

sc->sc_nvm_wordsize = 64;

sc->sc_nvm_addrbits = 6;

}

break;

case WM_T_82571:

case WM_T_82572:

/* SPI */

wm_set_spiaddrbits(sc);

sc->sc_flags |= WM_F_EEPROM_SPI;

wm_nvm_set_addrbits_size_eecd(sc);

sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM;

break;

case WM_T_82573:

Line 1685 wm_attach(device_t parent, device_t self

Line 1773 wm_attach(device_t parent, device_t self

/* FALLTHROUGH */

case WM_T_82574:

case WM_T_82583:

if (wm_nvm_is_onboard_eeprom(sc) == 0)

if (wm_nvm_is_onboard_eeprom(sc) == 0) {

sc->sc_flags |= WM_F_EEPROM_FLASH;

else {

sc->sc_nvm_wordsize = 2048;

} else {

/* SPI */

wm_set_spiaddrbits(sc);

sc->sc_flags |= WM_F_EEPROM_SPI;

wm_nvm_set_addrbits_size_eecd(sc);

}

sc->sc_flags |= WM_F_EEPROM_EERDEEWR;

break;

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_80003:

/* SPI */

wm_set_spiaddrbits(sc);

sc->sc_flags |= WM_F_EEPROM_SPI;

wm_nvm_set_addrbits_size_eecd(sc);

sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW

| WM_F_LOCK_SWSM;

break;

Line 1713 wm_attach(device_t parent, device_t self

Line 1803 wm_attach(device_t parent, device_t self

case WM_T_PCH_LPT:

/* FLASH */

sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF;

sc->sc_nvm_wordsize = 2048;

memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH);

if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,

&sc->sc_flasht, &sc->sc_flashh, NULL, NULL)) {

aprint_error_dev(sc->sc_dev,

"can't map FLASH registers\n");

return;

goto fail_5;

}

reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);

sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *

Line 1732 wm_attach(device_t parent, device_t self

Line 1823 wm_attach(device_t parent, device_t self

break;

case WM_T_I210:

case WM_T_I211:

wm_nvm_set_addrbits_size_eecd(sc);

sc->sc_flags |= WM_F_EEPROM_FLASH_HW;

sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW;

break;

Line 1744 wm_attach(device_t parent, device_t self

Line 1836 wm_attach(device_t parent, device_t self

case WM_T_82571:

case WM_T_82572:

reg = CSR_READ(sc, WMREG_SWSM2);

if ((reg & SWSM2_LOCK) != 0) {

if ((reg & SWSM2_LOCK) == 0) {

CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);

force_clear_smbi = true;

} else

Line 1790 wm_attach(device_t parent, device_t self

Line 1882 wm_attach(device_t parent, device_t self

if (sc->sc_flags & WM_F_EEPROM_INVALID)

aprint_verbose_dev(sc->sc_dev, "No EEPROM\n");

else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) {

else {

aprint_verbose_dev(sc->sc_dev, "FLASH(HW)\n");

aprint_verbose_dev(sc->sc_dev, "%u words ",

} else if (sc->sc_flags & WM_F_EEPROM_FLASH) {

sc->sc_nvm_wordsize);

aprint_verbose_dev(sc->sc_dev, "FLASH\n");

if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) {

} else {

aprint_verbose("FLASH(HW)\n");

if (sc->sc_flags & WM_F_EEPROM_SPI)

} else if (sc->sc_flags & WM_F_EEPROM_FLASH) {

eetype = "SPI";

aprint_verbose("FLASH\n");

else

} else {

eetype = "MicroWire";

if (sc->sc_flags & WM_F_EEPROM_SPI)

aprint_verbose_dev(sc->sc_dev,

eetype = "SPI";

"%u word (%d address bits) %s EEPROM\n",

else

1U << sc->sc_ee_addrbits,

eetype = "MicroWire";

sc->sc_ee_addrbits, eetype);

aprint_verbose("(%d address bits) %s EEPROM\n",

sc->sc_nvm_addrbits, eetype);

}

switch (sc->sc_type) {

Line 1838 wm_attach(device_t parent, device_t self

Line 1932 wm_attach(device_t parent, device_t self

if (wm_read_mac_addr(sc, enaddr) != 0) {

aprint_error_dev(sc->sc_dev,

"unable to read Ethernet address\n");

return;

goto fail_5;

}

Line 1854 wm_attach(device_t parent, device_t self

Line 1948 wm_attach(device_t parent, device_t self

KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);

cfg1 = (uint16_t) prop_number_integer_value(pn);

} else {

if (wm_nvm_read(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {

if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {

aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");

return;

goto fail_5;

}

Line 1865 wm_attach(device_t parent, device_t self

Line 1959 wm_attach(device_t parent, device_t self

KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);

cfg2 = (uint16_t) prop_number_integer_value(pn);

} else {

if (wm_nvm_read(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {

if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {

aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");

return;

goto fail_5;

}

Line 1878 wm_attach(device_t parent, device_t self

Line 1972 wm_attach(device_t parent, device_t self

case WM_T_82543:

/* dummy? */

eeprom_data = 0;

apme_mask = EEPROM_CFG3_APME;

apme_mask = NVM_CFG3_APME;

break;

case WM_T_82544:

apme_mask = EEPROM_CFG2_82544_APM_EN;

apme_mask = NVM_CFG2_82544_APM_EN;

eeprom_data = cfg2;

break;

case WM_T_82546:

Line 1893 wm_attach(device_t parent, device_t self

Line 1987 wm_attach(device_t parent, device_t self

case WM_T_82583:

case WM_T_80003:

default:

apme_mask = EEPROM_CFG3_APME;

apme_mask = NVM_CFG3_APME;

wm_nvm_read(sc, (sc->sc_funcid == 1) ? EEPROM_OFF_CFG3_PORTB

wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB

: EEPROM_OFF_CFG3_PORTA, 1, &eeprom_data);

: NVM_OFF_CFG3_PORTA, 1, &eeprom_data);

break;

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354: /* XXX ok? */

case WM_T_ICH8:

Line 1934 wm_attach(device_t parent, device_t self

Line 2027 wm_attach(device_t parent, device_t self

KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);

swdpin = (uint16_t) prop_number_integer_value(pn);

} else {

if (wm_nvm_read(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {

if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {

aprint_error_dev(sc->sc_dev,

"unable to read SWDPIN\n");

return;

goto fail_5;

}

if (cfg1 & EEPROM_CFG1_ILOS)

if (cfg1 & NVM_CFG1_ILOS)

sc->sc_ctrl |= CTRL_ILOS;

if (sc->sc_type >= WM_T_82544) {

sc->sc_ctrl |=

((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<

((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<

CTRL_SWDPIO_SHIFT;

sc->sc_ctrl |=

((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<

((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<

CTRL_SWDPINS_SHIFT;

} else {

sc->sc_ctrl |=

((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) <<

((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<

CTRL_SWDPIO_SHIFT;

}

#if 0

if (sc->sc_type >= WM_T_82544) {

if (cfg1 & EEPROM_CFG1_IPS0)

if (cfg1 & NVM_CFG1_IPS0)

sc->sc_ctrl_ext |= CTRL_EXT_IPS;

if (cfg1 & EEPROM_CFG1_IPS1)

if (cfg1 & NVM_CFG1_IPS1)

sc->sc_ctrl_ext |= CTRL_EXT_IPS1;

sc->sc_ctrl_ext |=

((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<

((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<

CTRL_EXT_SWDPIO_SHIFT;

sc->sc_ctrl_ext |=

((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<

((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<

CTRL_EXT_SWDPINS_SHIFT;

} else {

sc->sc_ctrl_ext |=

((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) <<

((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<

CTRL_EXT_SWDPIO_SHIFT;

}

#endif

Line 1997 wm_attach(device_t parent, device_t self

Line 2090 wm_attach(device_t parent, device_t self

uint16_t val;

/* Save the NVM K1 bit setting */

wm_nvm_read(sc, EEPROM_OFF_K1_CONFIG, 1, &val);

wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);

if ((val & EEPROM_K1_CONFIG_ENABLE) != 0)

if ((val & NVM_K1_CONFIG_ENABLE) != 0)

sc->sc_nvm_k1_enabled = 1;

else

sc->sc_nvm_k1_enabled = 0;

Line 2018 wm_attach(device_t parent, device_t self

Line 2111 wm_attach(device_t parent, device_t self

wm_gmii_mediainit(sc, wmp->wmp_product);

} else if (sc->sc_type < WM_T_82543 ||

(CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {

if (wmp->wmp_flags & WMP_F_1000T)

if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {

aprint_error_dev(sc->sc_dev,

"WARNING: TBIMODE set on 1000BASE-T product!\n");

sc->sc_mediatype = WM_MEDIATYPE_FIBER;

}

wm_tbi_mediainit(sc);

} else {

switch (sc->sc_type) {

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

case WM_T_I211:

reg = CSR_READ(sc, WMREG_CTRL_EXT);

switch (reg & CTRL_EXT_LINK_MODE_MASK) {

link_mode = reg & CTRL_EXT_LINK_MODE_MASK;

switch (link_mode) {

case CTRL_EXT_LINK_MODE_1000KX:

aprint_verbose_dev(sc->sc_dev, "1000KX\n");

CSR_WRITE(sc, WMREG_CTRL_EXT,

sc->sc_mediatype = WM_MEDIATYPE_SERDES;

reg | CTRL_EXT_I2C_ENA);

panic("not supported yet\n");

break;

case CTRL_EXT_LINK_MODE_SGMII:

if (wm_sgmii_uses_mdio(sc)) {

aprint_verbose_dev(sc->sc_dev,

"SGMII(MDIO)\n");

sc->sc_flags |= WM_F_SGMII;

wm_gmii_mediainit(sc,

sc->sc_mediatype = WM_MEDIATYPE_COPPER;

wmp->wmp_product);

break;

}

aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n");

/*FALLTHROUGH*/

case CTRL_EXT_LINK_MODE_PCIE_SERDES:

aprint_verbose_dev(sc->sc_dev, "SERDES\n");

sc->sc_mediatype = wm_sfp_get_media_type(sc);

CSR_WRITE(sc, WMREG_CTRL_EXT,

if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) {

reg | CTRL_EXT_I2C_ENA);

if (link_mode

panic("not supported yet\n");

== CTRL_EXT_LINK_MODE_SGMII) {

sc->sc_mediatype

= WM_MEDIATYPE_COPPER;

sc->sc_flags |= WM_F_SGMII;

} else {

sc->sc_mediatype

= WM_MEDIATYPE_SERDES;

aprint_verbose_dev(sc->sc_dev,

"SERDES\n");

}

break;

}

if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)

aprint_verbose_dev(sc->sc_dev,

"SERDES\n");

/* Change current link mode setting */

reg &= ~CTRL_EXT_LINK_MODE_MASK;

switch (sc->sc_mediatype) {

case WM_MEDIATYPE_COPPER:

reg |= CTRL_EXT_LINK_MODE_SGMII;

break;

case WM_MEDIATYPE_SERDES:

reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;

break;

default:

break;

}

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

break;

case CTRL_EXT_LINK_MODE_GMII:

default:

CSR_WRITE(sc, WMREG_CTRL_EXT,

aprint_verbose_dev(sc->sc_dev, "Copper\n");

reg & ~CTRL_EXT_I2C_ENA);

sc->sc_mediatype = WM_MEDIATYPE_COPPER;

wm_gmii_mediainit(sc, wmp->wmp_product);

break;

}

reg &= ~CTRL_EXT_I2C_ENA;

if ((sc->sc_flags & WM_F_SGMII) != 0)

reg |= CTRL_EXT_I2C_ENA;

else

reg &= ~CTRL_EXT_I2C_ENA;

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)

wm_gmii_mediainit(sc, wmp->wmp_product);

else

wm_tbi_mediainit(sc);

break;

default:

if (wmp->wmp_flags & WMP_F_1000X)

if (sc->sc_mediatype == WM_MEDIATYPE_FIBER)

aprint_error_dev(sc->sc_dev,

"WARNING: TBIMODE clear on 1000BASE-X product!\n");

sc->sc_mediatype = WM_MEDIATYPE_COPPER;

wm_gmii_mediainit(sc, wmp->wmp_product);

}

Line 2093 wm_attach(device_t parent, device_t self

Line 2225 wm_attach(device_t parent, device_t self

switch (sc->sc_type) {

case WM_T_82573:

/* XXX limited to 9234 if ASPM is disabled */

wm_nvm_read(sc, EEPROM_INIT_3GIO_3, 1, &io3);

wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &io3);

if ((io3 & EEPROM_3GIO_3_ASPM_MASK) != 0)

if ((io3 & NVM_3GIO_3_ASPM_MASK) != 0)

sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;

break;

case WM_T_82571:

Line 2103 wm_attach(device_t parent, device_t self

Line 2235 wm_attach(device_t parent, device_t self

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354: /* XXXX ok? */

case WM_T_I210:

Line 2253 wm_attach(device_t parent, device_t self

Line 2384 wm_attach(device_t parent, device_t self

else

aprint_error_dev(self, "couldn't establish power handler\n");

sc->sc_flags |= WM_F_ATTACHED;

return;

Line 2292 wm_detach(device_t self, int flags __unu

Line 2424 wm_detach(device_t self, int flags __unu

int i;

#ifndef WM_MPSAFE

int s;

#endif

if ((sc->sc_flags & WM_F_ATTACHED) == 0)

return 0;

#ifndef WM_MPSAFE

s = splnet();

#endif

/* Stop the interface. Callouts are stopped in it. */

Line 2623 wm_ioctl(struct ifnet *ifp, u_long cmd,

Line 2760 wm_ioctl(struct ifnet *ifp, u_long cmd,

/* MAC address related */

static int

* Get the offset of MAC address and return it.

* If error occured, use offset 0.

static uint16_t

wm_check_alt_mac_addr(struct wm_softc *sc)

{

uint16_t myea[ETHER_ADDR_LEN / 2];

uint16_t offset = EEPROM_OFF_MACADDR;

uint16_t offset = NVM_OFF_MACADDR;

/* Try to read alternative MAC address pointer */

if (wm_nvm_read(sc, EEPROM_ALT_MAC_ADDR_PTR, 1, &offset) != 0)

if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0)

return -1;

return 0;

/* Check pointer */

/* Check pointer if it's valid or not. */

if (offset == 0xffff)

if ((offset == 0x0000) || (offset == 0xffff))

return -1;

return 0;

offset += NVM_OFF_MACADDR_82571(sc->sc_funcid);

* Check whether alternative MAC address is valid or not.

* Some cards have non 0xffff pointer but those don't use

Line 2646 wm_check_alt_mac_addr(struct wm_softc *s

Line 2788 wm_check_alt_mac_addr(struct wm_softc *s

if (wm_nvm_read(sc, offset, 1, myea) == 0)

if (((myea[0] & 0xff) & 0x01) == 0)

return 0; /* found! */

return offset; /* Found */

/* not found */

/* Not found */

return -1;

return 0;

}

static int

wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)

{

uint16_t myea[ETHER_ADDR_LEN / 2];

uint16_t offset = EEPROM_OFF_MACADDR;

uint16_t offset = NVM_OFF_MACADDR;

int do_invert = 0;

switch (sc->sc_type) {

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

switch (sc->sc_funcid) {

/* EEPROM Top Level Partitioning */

case 0:

offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0;

/* default value (== EEPROM_OFF_MACADDR) */

break;

case 1:

offset = EEPROM_OFF_LAN1;

break;

case 2:

offset = EEPROM_OFF_LAN2;

break;

case 3:

offset = EEPROM_OFF_LAN3;

break;

default:

goto bad;

/* NOTREACHED */

break;

}

break;

case WM_T_82571:

case WM_T_82575:

Line 2689 wm_read_mac_addr(struct wm_softc *sc, ui

Line 2814 wm_read_mac_addr(struct wm_softc *sc, ui

case WM_T_80003:

case WM_T_I210:

case WM_T_I211:

if (wm_check_alt_mac_addr(sc) != 0) {

offset = wm_check_alt_mac_addr(sc);

/* reset the offset to LAN0 */

if (offset == 0)

offset = EEPROM_OFF_MACADDR;

if ((sc->sc_funcid & 0x01) == 1)

do_invert = 1;

goto do_read;

}

switch (sc->sc_funcid) {

case 0:

* The offset is the value in EEPROM_ALT_MAC_ADDR_PTR

* itself.

break;

case 1:

offset += EEPROM_OFF_MACADDR_LAN1;

break;

case 2:

offset += EEPROM_OFF_MACADDR_LAN2;

break;

case 3:

offset += EEPROM_OFF_MACADDR_LAN3;

break;

default:

goto bad;

/* NOTREACHED */

break;

}

break;

default:

if ((sc->sc_funcid & 0x01) == 1)

Line 2724 wm_read_mac_addr(struct wm_softc *sc, ui

Line 2825 wm_read_mac_addr(struct wm_softc *sc, ui

break;

}

do_read:

if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]),

myea) != 0) {

myea) != 0)

goto bad;

}

enaddr[0] = myea[0] & 0xff;

enaddr[1] = myea[0] >> 8;

Line 2982 wm_get_auto_rd_done(struct wm_softc *sc)

Line 3081 wm_get_auto_rd_done(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 3074 wm_get_cfg_done(struct wm_softc *sc)

Line 3172 wm_get_cfg_done(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 3117 wm_get_cfg_done(struct wm_softc *sc)

Line 3214 wm_get_cfg_done(struct wm_softc *sc)

}

/* Init hardware bits */

void

wm_initialize_hardware_bits(struct wm_softc *sc)

{

uint32_t tarc0, tarc1, reg;

/* For 82571 variant, 80003 and ICHs */

if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583))

|| (sc->sc_type >= WM_T_80003)) {

/* Transmit Descriptor Control 0 */

reg = CSR_READ(sc, WMREG_TXDCTL(0));

reg |= TXDCTL_COUNT_DESC;

CSR_WRITE(sc, WMREG_TXDCTL(0), reg);

/* Transmit Descriptor Control 1 */

reg = CSR_READ(sc, WMREG_TXDCTL(1));

reg |= TXDCTL_COUNT_DESC;

CSR_WRITE(sc, WMREG_TXDCTL(1), reg);

/* TARC0 */

tarc0 = CSR_READ(sc, WMREG_TARC0);

switch (sc->sc_type) {

case WM_T_82571:

case WM_T_82572:

case WM_T_82573:

case WM_T_82574:

case WM_T_82583:

case WM_T_80003:

/* Clear bits 30..27 */

tarc0 &= ~__BITS(30, 27);

break;

default:

break;

}

switch (sc->sc_type) {

case WM_T_82571:

case WM_T_82572:

tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */

tarc1 = CSR_READ(sc, WMREG_TARC1);

tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */

tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */

/* 8257[12] Errata No.7 */

tarc1 |= __BIT(22); /* TARC1 bits 22 */

/* TARC1 bit 28 */

if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)

tarc1 &= ~__BIT(28);

else

tarc1 |= __BIT(28);

CSR_WRITE(sc, WMREG_TARC1, tarc1);

* 8257[12] Errata No.13

* Disable Dyamic Clock Gating.

reg = CSR_READ(sc, WMREG_CTRL_EXT);

reg &= ~CTRL_EXT_DMA_DYN_CLK;

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

break;

case WM_T_82573:

case WM_T_82574:

case WM_T_82583:

if ((sc->sc_type == WM_T_82574)

|| (sc->sc_type == WM_T_82583))

tarc0 |= __BIT(26); /* TARC0 bit 26 */

/* Extended Device Control */

reg = CSR_READ(sc, WMREG_CTRL_EXT);

reg &= ~__BIT(23); /* Clear bit 23 */

reg |= __BIT(22); /* Set bit 22 */

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

/* Device Control */

sc->sc_ctrl &= ~__BIT(29); /* Clear bit 29 */

CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);

/* PCIe Control Register */

if ((sc->sc_type == WM_T_82574)

|| (sc->sc_type == WM_T_82583)) {

* Document says this bit must be set for

* proper operation.

reg = CSR_READ(sc, WMREG_GCR);

reg |= __BIT(22);

CSR_WRITE(sc, WMREG_GCR, reg);

* Apply workaround for hardware errata

* documented in errata docs Fixes issue where

* some error prone or unreliable PCIe

* completions are occurring, particularly

* with ASPM enabled. Without fix, issue can

* cause Tx timeouts.

reg = CSR_READ(sc, WMREG_GCR2);

reg |= __BIT(0);

CSR_WRITE(sc, WMREG_GCR2, reg);

}

break;

case WM_T_80003:

/* TARC0 */

if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)

|| (sc->sc_mediatype == WM_MEDIATYPE_SERDES))

tarc0 &= ~__BIT(20); /* Clear bits 20 */

/* TARC1 bit 28 */

tarc1 = CSR_READ(sc, WMREG_TARC1);

if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)

tarc1 &= ~__BIT(28);

else

tarc1 |= __BIT(28);

CSR_WRITE(sc, WMREG_TARC1, tarc1);

break;

case WM_T_ICH8:

case WM_T_ICH9:

case WM_T_ICH10:

case WM_T_PCH:

case WM_T_PCH2:

case WM_T_PCH_LPT:

/* TARC 0 */

if (sc->sc_type == WM_T_ICH8) {

/* Set TARC0 bits 29 and 28 */

tarc0 |= __BITS(29, 28);

}

/* Set TARC0 bits 23,24,26,27 */

tarc0 |= __BITS(27, 26) | __BITS(24, 23);

/* CTRL_EXT */

reg = CSR_READ(sc, WMREG_CTRL_EXT);

reg |= __BIT(22); /* Set bit 22 */

* Enable PHY low-power state when MAC is at D3

* w/o WoL

if (sc->sc_type >= WM_T_PCH)

reg |= CTRL_EXT_PHYPDEN;

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

/* TARC1 */

tarc1 = CSR_READ(sc, WMREG_TARC1);

/* bit 28 */

if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)

tarc1 &= ~__BIT(28);

else

tarc1 |= __BIT(28);

tarc1 |= __BIT(24) | __BIT(26) | __BIT(30);

CSR_WRITE(sc, WMREG_TARC1, tarc1);

/* Device Status */

if (sc->sc_type == WM_T_ICH8) {

reg = CSR_READ(sc, WMREG_STATUS);

reg &= ~__BIT(31);

CSR_WRITE(sc, WMREG_STATUS, reg);

}

* Work-around descriptor data corruption issue during

* NFS v2 UDP traffic, just disable the NFS filtering

* capability.

reg = CSR_READ(sc, WMREG_RFCTL);

reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS;

CSR_WRITE(sc, WMREG_RFCTL, reg);

break;

default:

break;

}

CSR_WRITE(sc, WMREG_TARC0, tarc0);

* 8257[12] Errata No.52 and some others.

* Avoid RSS Hash Value bug.

switch (sc->sc_type) {

case WM_T_82571:

case WM_T_82572:

case WM_T_82573:

case WM_T_80003:

case WM_T_ICH8:

reg = CSR_READ(sc, WMREG_RFCTL);

reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS;

CSR_WRITE(sc, WMREG_RFCTL, reg);

break;

default:

break;

}

* wm_reset:

Line 3154 wm_reset(struct wm_softc *sc)

Line 3445 wm_reset(struct wm_softc *sc)

sc->sc_pba = PBA_32K;

break;

case WM_T_82580:

case WM_T_82580ER:

sc->sc_pba = PBA_35K;

break;

case WM_T_I210:

Line 3172 wm_reset(struct wm_softc *sc)

Line 3462 wm_reset(struct wm_softc *sc)

sc->sc_pba = PBA_20K;

break;

case WM_T_ICH8:

/* Workaround for a bit corruption issue in FIFO memory */

sc->sc_pba = PBA_8K;

CSR_WRITE(sc, WMREG_PBS, PBA_16K);

break;

Line 3208 wm_reset(struct wm_softc *sc)

Line 3499 wm_reset(struct wm_softc *sc)

/* Set the completion timeout for interface */

if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)

|| (sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)

|| (sc->sc_type == WM_T_82580)

|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)

|| (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))

wm_set_pcie_completion_timeout(sc);

Line 3310 wm_reset(struct wm_softc *sc)

Line 3601 wm_reset(struct wm_softc *sc)

delay(20*1000);

wm_put_swfwhw_semaphore(sc);

break;

case WM_T_82580:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

case WM_T_I211:

CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);

if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII)

CSR_WRITE_FLUSH(sc);

delay(5000);

break;

case WM_T_82542_2_0:

case WM_T_82542_2_1:

case WM_T_82543:

Line 3322 wm_reset(struct wm_softc *sc)

Line 3623 wm_reset(struct wm_softc *sc)

case WM_T_82574:

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_82583:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

case WM_T_I211:

default:

/* Everything else can safely use the documented method. */

CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);

Line 3401 wm_reset(struct wm_softc *sc)

Line 3696 wm_reset(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 3427 wm_reset(struct wm_softc *sc)

Line 3721 wm_reset(struct wm_softc *sc)

case WM_T_82576:

#if 0 /* XXX */

case WM_T_82580:

case WM_T_82580ER:

#endif

case WM_T_I350:

case WM_T_I354:

Line 3439 wm_reset(struct wm_softc *sc)

Line 3732 wm_reset(struct wm_softc *sc)

if ((sc->sc_type == WM_T_82575)

|| (sc->sc_type == WM_T_82576)

|| (sc->sc_type == WM_T_82580)

|| (sc->sc_type == WM_T_82580ER)

|| (sc->sc_type == WM_T_I350)

|| (sc->sc_type == WM_T_I354))

wm_reset_init_script_82575(sc);

Line 3449 wm_reset(struct wm_softc *sc)

Line 3741 wm_reset(struct wm_softc *sc)

break;

}

if ((sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)

if ((sc->sc_type == WM_T_82580)

|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {

/* clear global device reset status bit */

CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);

Line 3634 wm_init_locked(struct ifnet *ifp)

Line 3926 wm_init_locked(struct ifnet *ifp)

break;

}

/* Init hardware bits */

wm_initialize_hardware_bits(sc);

/* Reset the PHY. */

if (sc->sc_flags & WM_F_HAS_MII)

wm_gmii_reset(sc);

reg = CSR_READ(sc, WMREG_CTRL_EXT);

/* Enable PHY low-power state when MAC is at D3 w/o WoL */

if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)

|| (sc->sc_type == WM_T_PCH_LPT))

CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_PHYPDEN);

/* Initialize the transmit descriptor ring. */

memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc));

WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc),

Line 3671 wm_init_locked(struct ifnet *ifp)

Line 3960 wm_init_locked(struct ifnet *ifp)

* Don't write TDT before TCTL.EN is set.

* See the document.

CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_QUEUE_ENABLE

CSR_WRITE(sc, WMREG_TXDCTL(0), TXDCTL_QUEUE_ENABLE

| TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)

| TXDCTL_WTHRESH(0));

else {

CSR_WRITE(sc, WMREG_TDT, 0);

CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |

CSR_WRITE(sc, WMREG_TXDCTL(0), TXDCTL_PTHRESH(0) |

TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));

CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |

RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));

Line 5786 wm_gmii_reset(struct wm_softc *sc)

Line 6075 wm_gmii_reset(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 5863 wm_gmii_reset(struct wm_softc *sc)

Line 6151 wm_gmii_reset(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 5919 wm_gmii_reset(struct wm_softc *sc)

Line 6206 wm_gmii_reset(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 5964 wm_gmii_reset(struct wm_softc *sc)

Line 6250 wm_gmii_reset(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 6075 wm_gmii_mediainit(struct wm_softc *sc, p

Line 6360 wm_gmii_mediainit(struct wm_softc *sc, p

struct mii_data *mii = &sc->sc_mii;

uint32_t reg;

/* We have MII. */

/* We have GMII. */

sc->sc_flags |= WM_F_HAS_MII;

if (sc->sc_type == WM_T_80003)

Line 6084 wm_gmii_mediainit(struct wm_softc *sc, p

Line 6369 wm_gmii_mediainit(struct wm_softc *sc, p

sc->sc_tipg = TIPG_1000T_DFLT;

/* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */

if ((sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)

if ((sc->sc_type == WM_T_82580)

|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)

|| (sc->sc_type == WM_T_I211)) {

reg = CSR_READ(sc, WMREG_PHPM);

Line 6112 wm_gmii_mediainit(struct wm_softc *sc, p

Line 6397 wm_gmii_mediainit(struct wm_softc *sc, p

* For some devices, we can determine the PHY access method

* from sc_type.

* For ICH8 variants, it's difficult to detemine the PHY access

* For ICH and PCH variants, it's difficult to determine the PHY

* method by sc_type, so use the PCI product ID for some devices.

* access method by sc_type, so use the PCI product ID for some

* devices.

* For other ICH8 variants, try to use igp's method. If the PHY

* can't detect, then use bm's method.

Line 6122 wm_gmii_mediainit(struct wm_softc *sc, p

Line 6408 wm_gmii_mediainit(struct wm_softc *sc, p

case PCI_PRODUCT_INTEL_PCH_M_LC:

/* 82577 */

sc->sc_phytype = WMPHY_82577;

mii->mii_readreg = wm_gmii_hv_readreg;

mii->mii_writereg = wm_gmii_hv_writereg;

break;

case PCI_PRODUCT_INTEL_PCH_D_DM:

case PCI_PRODUCT_INTEL_PCH_D_DC:

/* 82578 */

sc->sc_phytype = WMPHY_82578;

mii->mii_readreg = wm_gmii_hv_readreg;

mii->mii_writereg = wm_gmii_hv_writereg;

break;

case PCI_PRODUCT_INTEL_PCH2_LV_LM:

case PCI_PRODUCT_INTEL_PCH2_LV_V:

/* 82579 */

sc->sc_phytype = WMPHY_82579;

mii->mii_readreg = wm_gmii_hv_readreg;

mii->mii_writereg = wm_gmii_hv_writereg;

break;

case PCI_PRODUCT_INTEL_I217_LM:

case PCI_PRODUCT_INTEL_I217_V:

case PCI_PRODUCT_INTEL_I218_LM:

case PCI_PRODUCT_INTEL_I218_V:

/* I21[78] */

mii->mii_readreg = wm_gmii_hv_readreg;

mii->mii_writereg = wm_gmii_hv_writereg;

break;

case PCI_PRODUCT_INTEL_82801I_BM:

case PCI_PRODUCT_INTEL_82801J_R_BM_LM:

Line 6182 wm_gmii_mediainit(struct wm_softc *sc, p

Line 6454 wm_gmii_mediainit(struct wm_softc *sc, p

}

break;

}

if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_LPT)) {

/* All PCH* use _hv_ */

mii->mii_readreg = wm_gmii_hv_readreg;

mii->mii_writereg = wm_gmii_hv_writereg;

}

mii->mii_statchg = wm_gmii_statchg;

wm_gmii_reset(sc);

Line 6191 wm_gmii_mediainit(struct wm_softc *sc, p

Line 6468 wm_gmii_mediainit(struct wm_softc *sc, p

wm_gmii_mediastatus);

if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)

|| (sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)

|| (sc->sc_type == WM_T_82580)

|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)

|| (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) {

if ((sc->sc_flags & WM_F_SGMII) == 0) {

Line 7035 wm_sgmii_uses_mdio(struct wm_softc *sc)

Line 7312 wm_sgmii_uses_mdio(struct wm_softc *sc)

ismdio = ((reg & MDIC_DEST) != 0);

break;

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

Line 7106 wm_sgmii_writereg(device_t self, int phy

Line 7382 wm_sgmii_writereg(device_t self, int phy

struct wm_softc *sc = device_private(self);

uint32_t i2ccmd;

int i;

int val_swapped;

if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) {

aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",

__func__);

return;

}

/* Swap the data bytes for the I2C interface */

val_swapped = ((val >> 8) & 0x00FF) | ((val << 8) & 0xFF00);

i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)

| (phy << I2CCMD_PHY_ADDR_SHIFT)

| I2CCMD_OPCODE_WRITE;

| I2CCMD_OPCODE_WRITE | val_swapped;

CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);

/* Poll the ready bit */

Line 7145 wm_check_for_link(struct wm_softc *sc)

Line 7423 wm_check_for_link(struct wm_softc *sc)

uint32_t status;

uint32_t sig;

if (sc->sc_wmp->wmp_flags & WMP_F_SERDES) {

if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {

sc->sc_tbi_linkup = 1;

return 0;

}

Line 7244 wm_tbi_mediainit(struct wm_softc *sc)

Line 7522 wm_tbi_mediainit(struct wm_softc *sc)

sc->sc_ctrl |= CTRL_SWDPIO(0);

sc->sc_ctrl &= ~CTRL_SWDPIO(1);

if (sc->sc_wmp->wmp_flags & WMP_F_SERDES)

if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)

sc->sc_ctrl &= ~CTRL_LRST;

CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);

Line 7324 wm_tbi_mediachange(struct ifnet *ifp)

Line 7602 wm_tbi_mediachange(struct ifnet *ifp)

uint32_t status;

int i;

if (sc->sc_wmp->wmp_flags & WMP_F_SERDES)

if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)

return 0;

if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)

Line 7454 wm_tbi_check_link(struct wm_softc *sc)

Line 7732 wm_tbi_check_link(struct wm_softc *sc)

KASSERT(WM_TX_LOCKED(sc));

if (sc->sc_wmp->wmp_flags & WMP_F_SERDES) {

if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {

sc->sc_tbi_linkup = 1;

return;

}

Line 7509 wm_tbi_check_link(struct wm_softc *sc)

Line 7787 wm_tbi_check_link(struct wm_softc *sc)

wm_tbi_set_linkled(sc);

}

/* SFP related */

static int

wm_sfp_read_data_byte(struct wm_softc *sc, uint16_t offset, uint8_t *data)

{

uint32_t i2ccmd;

int i;

i2ccmd = (offset << I2CCMD_REG_ADDR_SHIFT) | I2CCMD_OPCODE_READ;

CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);

/* Poll the ready bit */

for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {

delay(50);

i2ccmd = CSR_READ(sc, WMREG_I2CCMD);

if (i2ccmd & I2CCMD_READY)

break;

}

if ((i2ccmd & I2CCMD_READY) == 0)

return -1;

if ((i2ccmd & I2CCMD_ERROR) != 0)

return -1;

*data = i2ccmd & 0x00ff;

return 0;

}

static uint32_t

wm_sfp_get_media_type(struct wm_softc *sc)

{

uint32_t ctrl_ext;

uint8_t val = 0;

int timeout = 3;

uint32_t mediatype = WM_MEDIATYPE_UNKNOWN;

int rv = -1;

ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);

ctrl_ext &= ~CTRL_EXT_SWDPIN(3);

CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_I2C_ENA);

CSR_WRITE_FLUSH(sc);

/* Read SFP module data */

while (timeout) {

rv = wm_sfp_read_data_byte(sc, SFF_SFP_ID_OFF, &val);

if (rv == 0)

break;

delay(100*1000); /* XXX too big */

timeout--;

}

if (rv != 0)

goto out;

switch (val) {

case SFF_SFP_ID_SFF:

aprint_normal_dev(sc->sc_dev,

"Module/Connector soldered to board\n");

break;

case SFF_SFP_ID_SFP:

aprint_normal_dev(sc->sc_dev, "SFP\n");

break;

case SFF_SFP_ID_UNKNOWN:

goto out;

default:

break;

}

rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val);

if (rv != 0) {

goto out;

}

if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0)

mediatype = WM_MEDIATYPE_SERDES;

else if ((val & SFF_SFP_ETH_FLAGS_1000T) != 0){

sc->sc_flags |= WM_F_SGMII;

mediatype = WM_MEDIATYPE_COPPER;

} else if ((val & SFF_SFP_ETH_FLAGS_100FX) != 0){

sc->sc_flags |= WM_F_SGMII;

mediatype = WM_MEDIATYPE_SERDES;

}

out:

/* Restore I2C interface setting */

CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);

return mediatype;

}

* NVM related.

* Microwire, SPI (w/wo EERD) and Flash.

Line 7618 wm_nvm_read_uwire(struct wm_softc *sc, i

Line 7983 wm_nvm_read_uwire(struct wm_softc *sc, i

wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);

/* Shift in address. */

wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);

wm_eeprom_sendbits(sc, word + i, sc->sc_nvm_addrbits);

/* Shift out the data. */

wm_eeprom_recvbits(sc, &val, 16);

Line 7636 wm_nvm_read_uwire(struct wm_softc *sc, i

Line 8001 wm_nvm_read_uwire(struct wm_softc *sc, i

/* SPI */

/* Set SPI related information */

static void

* Set SPI and FLASH related information from the EECD register.

wm_set_spiaddrbits(struct wm_softc *sc)

* For 82541 and 82547, the word size is taken from EEPROM.

static int

wm_nvm_set_addrbits_size_eecd(struct wm_softc *sc)

{

int size;

uint32_t reg;

uint16_t data;

sc->sc_flags |= WM_F_EEPROM_SPI;

reg = CSR_READ(sc, WMREG_EECD);

sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;

sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;

/* Read the size of NVM from EECD by default */

size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);

switch (sc->sc_type) {

case WM_T_82541:

case WM_T_82541_2:

case WM_T_82547:

case WM_T_82547_2:

/* Set dummy value to access EEPROM */

sc->sc_nvm_wordsize = 64;

wm_nvm_read(sc, NVM_OFF_EEPROM_SIZE, 1, &data);

reg = data;

size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);

if (size == 0)

size = 6; /* 64 word size */

else

size += NVM_WORD_SIZE_BASE_SHIFT + 1;

break;

case WM_T_80003:

case WM_T_82571:

case WM_T_82572:

case WM_T_82573: /* SPI case */

case WM_T_82574: /* SPI case */

case WM_T_82583: /* SPI case */

size += NVM_WORD_SIZE_BASE_SHIFT;

if (size > 14)

size = 14;

break;

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_I350:

case WM_T_I354:

case WM_T_I210:

case WM_T_I211:

size += NVM_WORD_SIZE_BASE_SHIFT;

if (size > 15)

size = 15;

break;

default:

aprint_error_dev(sc->sc_dev,

"%s: unknown device(%d)?\n", __func__, sc->sc_type);

return -1;

break;

}

sc->sc_nvm_wordsize = 1 << size;

return 0;

}

Line 7701 wm_nvm_read_spi(struct wm_softc *sc, int

Line 8119 wm_nvm_read_spi(struct wm_softc *sc, int

delay(2);

opc = SPI_OPC_READ;

if (sc->sc_ee_addrbits == 8 && word >= 128)

if (sc->sc_nvm_addrbits == 8 && word >= 128)

opc |= SPI_OPC_A8;

wm_eeprom_sendbits(sc, opc, 8);

wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits);

wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits);

for (i = 0; i < wordcnt; i++) {

wm_eeprom_recvbits(sc, &val, 16);

Line 8059 wm_nvm_read_ich8(struct wm_softc *sc, in

Line 8477 wm_nvm_read_ich8(struct wm_softc *sc, in

error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);

if (error) {

aprint_error_dev(sc->sc_dev, "%s: failed to detect NVM bank\n",

DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",

__func__);

device_xname(sc->sc_dev)));

flash_bank = 0;

}

Line 8205 wm_nvm_is_onboard_eeprom(struct wm_softc

Line 8623 wm_nvm_is_onboard_eeprom(struct wm_softc

return 1;

}

#define NVM_CHECKSUM 0xBABA

#define EEPROM_SIZE 0x0040

#define NVM_COMPAT 0x0003

#define NVM_COMPAT_VALID_CHECKSUM 0x0001

#define NVM_FUTURE_INIT_WORD1 0x0019

#define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM 0x0040

* wm_nvm_validate_checksum

Line 8235 wm_nvm_validate_checksum(struct wm_softc

Line 8646 wm_nvm_validate_checksum(struct wm_softc

#ifdef WM_DEBUG

if (sc->sc_type == WM_T_PCH_LPT) {

csum_wordaddr = NVM_COMPAT;

csum_wordaddr = NVM_OFF_COMPAT;

valid_checksum = NVM_COMPAT_VALID_CHECKSUM;

} else {

csum_wordaddr = NVM_FUTURE_INIT_WORD1;

csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1;

valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;

}

Line 8257 wm_nvm_validate_checksum(struct wm_softc

Line 8668 wm_nvm_validate_checksum(struct wm_softc

if ((wm_debug & WM_DEBUG_NVM) != 0) {

printf("%s: NVM dump:\n", device_xname(sc->sc_dev));

for (i = 0; i < EEPROM_SIZE; i++) {

for (i = 0; i < NVM_SIZE; i++) {

if (wm_nvm_read(sc, i, 1, &eeprom_data))

printf("XX ");

printf("XXXX ");

else

printf("%04x ", eeprom_data);

printf("%04hx ", eeprom_data);

if (i % 8 == 7)

printf("\n");

}

Line 8269 wm_nvm_validate_checksum(struct wm_softc

Line 8680 wm_nvm_validate_checksum(struct wm_softc

#endif /* WM_DEBUG */

for (i = 0; i < EEPROM_SIZE; i++) {

for (i = 0; i < NVM_SIZE; i++) {

if (wm_nvm_read(sc, i, 1, &eeprom_data))

return 1;

checksum += eeprom_data;

Line 8329 wm_get_swsm_semaphore(struct wm_softc *s

Line 8740 wm_get_swsm_semaphore(struct wm_softc *s

if (sc->sc_flags & WM_F_LOCK_SWSM) {

/* Get the SW semaphore. */

timeout = 1000 + 1; /* XXX */

timeout = sc->sc_nvm_wordsize + 1;

while (timeout) {

swsm = CSR_READ(sc, WMREG_SWSM);

Line 8348 wm_get_swsm_semaphore(struct wm_softc *s

Line 8759 wm_get_swsm_semaphore(struct wm_softc *s

}

/* Get the FW semaphore. */

timeout = 1000 + 1; /* XXX */

timeout = sc->sc_nvm_wordsize + 1;

while (timeout) {

swsm = CSR_READ(sc, WMREG_SWSM);

swsm |= SWSM_SWESMBI;

Line 8554 wm_check_mng_mode_82574(struct wm_softc

Line 8965 wm_check_mng_mode_82574(struct wm_softc

{

uint16_t data;

wm_nvm_read(sc, EEPROM_OFF_CFG2, 1, &data);

wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);

if ((data & EEPROM_CFG2_MNGM_MASK) != 0)

if ((data & NVM_CFG2_MNGM_MASK) != 0)

return 1;

return 0;

Line 8601 wm_enable_mng_pass_thru(struct wm_softc

Line 9012 wm_enable_mng_pass_thru(struct wm_softc

uint16_t data;

factps = CSR_READ(sc, WMREG_FACTPS);

wm_nvm_read(sc, EEPROM_OFF_CFG2, 1, &data);

wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);

DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n",

device_xname(sc->sc_dev), factps, data));

if (((factps & FACTPS_MNGCG) == 0)

&& ((data & EEPROM_CFG2_MNGM_MASK)

&& ((data & NVM_CFG2_MNGM_MASK)

== (EEPROM_CFG2_MNGM_PT << EEPROM_CFG2_MNGM_SHIFT)))

== (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT)))

return 1;

} else if (((manc & MANC_SMBUS_EN) != 0)

&& ((manc & MANC_ASF_EN) == 0))

Line 8799 wm_get_wakeup(struct wm_softc *sc)

Line 9210 wm_get_wakeup(struct wm_softc *sc)

case WM_T_82575:

case WM_T_82576:

case WM_T_82580:

case WM_T_82580ER:

case WM_T_I350:

case WM_T_I354:

if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE_MASK) != 0)

Line 8948 wm_enable_wakeup(struct wm_softc *sc)

Line 9358 wm_enable_wakeup(struct wm_softc *sc)

}

/* Keep the laser running on fiber adapters */

if (((sc->sc_wmp->wmp_flags & WMP_F_1000X) != 0)

if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)

|| (sc->sc_wmp->wmp_flags & WMP_F_SERDES) != 0) {

|| (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) {

reg = CSR_READ(sc, WMREG_CTRL_EXT);

reg |= CTRL_EXT_SWDPIN(3);

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

Line 9200 wm_reset_init_script_82575(struct wm_sof

Line 9610 wm_reset_init_script_82575(struct wm_sof

{

* remark: this is untested code - we have no board without EEPROM

* same setup as mentioned int the freeBSD driver for the i82575

* same setup as mentioned int the FreeBSD driver for the i82575

/* SerDes configuration via SERDESCTRL */

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