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Annotation of src/sys/dev/pci/if_tireg.h, Revision 1.29

1.29    ! msaitoh     1: /* $NetBSD: if_tireg.h,v 1.28 2020/03/05 16:05:45 msaitoh Exp $ */
1.1       drochner    2:
                      3: /*
                      4:  * Copyright (c) 1997, 1998, 1999
                      5:  *     Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
                      6:  *
                      7:  * Redistribution and use in source and binary forms, with or without
                      8:  * modification, are permitted provided that the following conditions
                      9:  * are met:
                     10:  * 1. Redistributions of source code must retain the above copyright
                     11:  *    notice, this list of conditions and the following disclaimer.
                     12:  * 2. Redistributions in binary form must reproduce the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer in the
                     14:  *    documentation and/or other materials provided with the distribution.
                     15:  * 3. All advertising materials mentioning features or use of this software
                     16:  *    must display the following acknowledgement:
                     17:  *     This product includes software developed by Bill Paul.
                     18:  * 4. Neither the name of the author nor the names of any co-contributors
                     19:  *    may be used to endorse or promote products derived from this software
                     20:  *    without specific prior written permission.
                     21:  *
                     22:  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
                     23:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
                     24:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
                     25:  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
                     26:  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
                     27:  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
                     28:  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
                     29:  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
                     30:  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
                     31:  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
                     32:  * THE POSSIBILITY OF SUCH DAMAGE.
                     33:  *
                     34:  *     FreeBSD Id: if_tireg.h,v 1.9 1999/07/27 03:54:48 wpaul Exp
                     35:  */
                     36:
                     37: /*
                     38:  * Tigon register offsets. These are memory mapped registers
                     39:  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
                     40:  * Each register must be accessed using 32 bit operations.
                     41:  *
1.26      msaitoh    42:  * All registers are accessed through a 16K shared memory block.
1.1       drochner   43:  * The first group of registers are actually copies of the PCI
                     44:  * configuration space registers.
                     45:  */
                     46:
                     47: /*
                     48:  * Tigon configuration and control registers.
                     49:  */
                     50: #define TI_MISC_HOST_CTL               0x040
                     51: #define TI_MISC_LOCAL_CTL              0x044
                     52: #define TI_SEM_AB                      0x048 /* Tigon 2 only */
                     53: #define TI_MISC_CONF                   0x050 /* Tigon 2 only */
                     54: #define TI_TIMER_BITS                  0x054
                     55: #define TI_TIMERREF                    0x058
                     56: #define TI_PCI_STATE                   0x05C
                     57: #define TI_MAIN_EVENT_A                        0x060
                     58: #define TI_MAILBOX_EVENT_A             0x064
                     59: #define TI_WINBASE                     0x068
                     60: #define TI_WINDATA                     0x06C
                     61: #define TI_MAIN_EVENT_B                        0x070 /* Tigon 2 only */
                     62: #define TI_MAILBOX_EVENT_B             0x074 /* Tigon 2 only */
                     63: #define TI_TIMERREF_B                  0x078 /* Tigon 2 only */
                     64: #define TI_SERIAL                      0x07C
                     65:
                     66: /*
                     67:  * Misc host control bits.
                     68:  */
                     69: #define TI_MHC_INTSTATE                        0x00000001
                     70: #define TI_MHC_CLEARINT                        0x00000002
                     71: #define TI_MHC_RESET                   0x00000008
                     72: #define TI_MHC_BYTE_SWAP_ENB           0x00000010
                     73: #define TI_MHC_WORD_SWAP_ENB           0x00000020
                     74: #define TI_MHC_MASK_INTS               0x00000040
                     75: #define TI_MHC_CHIP_REV_MASK           0xF0000000
                     76:
                     77: #define TI_MHC_BIGENDIAN_INIT  \
                     78:        (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
                     79:
                     80: #define TI_MHC_LITTLEENDIAN_INIT       \
                     81:        (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
                     82:
                     83: /*
                     84:  * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2.
                     85:  * Rev 5 is also the Tigon 2, but is a broken version which was never
                     86:  * used in any actual hardware, so we ignore it.
                     87:  */
                     88: #define TI_REV_TIGON_I                 0x40000000
                     89: #define TI_REV_TIGON_II                        0x60000000
                     90:
                     91: /*
                     92:  * Firmware revision that we want.
                     93:  */
                     94: #define TI_FIRMWARE_MAJOR              0xc
1.3       bouyer     95: #define TI_FIRMWARE_MINOR              0x4
                     96: #define TI_FIRMWARE_FIX                        0xd
1.1       drochner   97:
                     98: /*
1.27      msaitoh    99:  * Miscellaneous Local Control register.
1.1       drochner  100:  */
                    101: #define TI_MLC_EE_WRITE_ENB            0x00000010
                    102: #define TI_MLC_SRAM_BANK_256K          0x00000200
                    103: #define TI_MLC_SRAM_BANK_SIZE          0x00000300 /* Tigon 2 only */
                    104: #define TI_MLC_LOCALADDR_21            0x00004000
                    105: #define TI_MLC_LOCALADDR_22            0x00008000
                    106: #define TI_MLC_SBUS_WRITEERR           0x00080000
                    107: #define TI_MLC_EE_CLK                  0x00100000
                    108: #define TI_MLC_EE_TXEN                 0x00200000
                    109: #define TI_MLC_EE_DOUT                 0x00400000
                    110: #define TI_MLC_EE_DIN                  0x00800000
                    111:
                    112: /*
                    113:  * Offset of MAC address inside EEPROM.
                    114:  */
                    115: #define TI_EE_MAC_OFFSET               0x8c
                    116:
                    117: #define TI_DMA_ASSIST                  0x11C
                    118: #define TI_CPU_STATE                   0x140
                    119: #define TI_CPU_PROGRAM_COUNTER         0x144
                    120: #define TI_SRAM_ADDR                   0x154
                    121: #define TI_SRAM_DATA                   0x158
                    122: #define TI_GEN_0                       0x180
                    123: #define TI_GEN_X                       0x1FC
                    124: #define TI_MAC_TX_STATE                        0x200
                    125: #define TI_MAC_RX_STATE                        0x220
                    126: #define TI_CPU_CTL_B                   0x240 /* Tigon 2 only */
                    127: #define TI_CPU_PROGRAM_COUNTER_B       0x244 /* Tigon 2 only */
                    128: #define TI_SRAM_ADDR_B                 0x254 /* Tigon 2 only */
                    129: #define TI_SRAM_DATA_B                 0x258 /* Tigon 2 only */
                    130: #define TI_GEN_B_0                     0x280 /* Tigon 2 only */
                    131: #define TI_GEN_B_X                     0x2FC /* Tigon 2 only */
                    132:
                    133: /*
                    134:  * Misc config register.
                    135:  */
                    136: #define TI_MCR_SRAM_SYNCHRONOUS                0x00100000 /* Tigon 2 only */
                    137:
                    138: /*
                    139:  * PCI state register.
                    140:  */
                    141: #define TI_PCISTATE_FORCE_RESET                0x00000001
                    142: #define TI_PCISTATE_PROVIDE_LEN                0x00000002
                    143: #define TI_PCISTATE_READ_MAXDMA                0x0000001C
                    144: #define TI_PCISTATE_WRITE_MAXDMA       0x000000E0
                    145: #define TI_PCISTATE_MINDMA             0x0000FF00
                    146: #define TI_PCISTATE_FIFO_RETRY_ENB     0x00010000
                    147: #define TI_PCISTATE_USE_MEM_RD_MULT    0x00020000
                    148: #define TI_PCISTATE_NO_SWAP_READ_DMA   0x00040000
                    149: #define TI_PCISTATE_NO_SWAP_WRITE_DMA  0x00080000
                    150: #define TI_PCISTATE_66MHZ_BUS          0x00080000 /* Tigon 2 only */
                    151: #define TI_PCISTATE_32BIT_BUS          0x00100000 /* Tigon 2 only */
                    152: #define TI_PCISTATE_ENB_BYTE_ENABLES   0x00800000 /* Tigon 2 only */
                    153: #define TI_PCISTATE_READ_CMD           0x0F000000
                    154: #define TI_PCISTATE_WRITE_CMD          0xF0000000
                    155:
                    156: #define TI_PCI_READMAX_4               0x04
                    157: #define TI_PCI_READMAX_16              0x08
                    158: #define TI_PCI_READMAX_32              0x0C
                    159: #define TI_PCI_READMAX_64              0x10
                    160: #define TI_PCI_READMAX_128             0x14
                    161: #define TI_PCI_READMAX_256             0x18
                    162: #define TI_PCI_READMAX_1024            0x1C
                    163:
                    164: #define TI_PCI_WRITEMAX_4              0x20
                    165: #define TI_PCI_WRITEMAX_16             0x40
                    166: #define TI_PCI_WRITEMAX_32             0x60
                    167: #define TI_PCI_WRITEMAX_64             0x80
                    168: #define TI_PCI_WRITEMAX_128            0xA0
                    169: #define TI_PCI_WRITEMAX_256            0xC0
                    170: #define TI_PCI_WRITEMAX_1024           0xE0
                    171:
                    172: #define TI_PCI_READ_CMD                        0x06000000
                    173: #define TI_PCI_WRITE_CMD               0x70000000
                    174:
                    175: /*
                    176:  * DMA state register.
                    177:  */
                    178: #define TI_DMASTATE_ENABLE             0x00000001
                    179: #define TI_DMASTATE_PAUSE              0x00000002
                    180:
                    181: /*
                    182:  * CPU state register.
                    183:  */
                    184: #define TI_CPUSTATE_RESET              0x00000001
                    185: #define TI_CPUSTATE_STEP               0x00000002
                    186: #define TI_CPUSTATE_ROMFAIL            0x00000010
                    187: #define TI_CPUSTATE_HALT               0x00010000
                    188: /*
                    189:  * MAC TX state register
                    190:  */
                    191: #define TI_TXSTATE_RESET               0x00000001
                    192: #define TI_TXSTATE_ENB                 0x00000002
                    193: #define TI_TXSTATE_STOP                        0x00000004
                    194:
                    195: /*
                    196:  * MAC RX state register
                    197:  */
                    198: #define TI_RXSTATE_RESET               0x00000001
                    199: #define TI_RXSTATE_ENB                 0x00000002
                    200: #define TI_RXSTATE_STOP                        0x00000004
                    201:
                    202: /*
                    203:  * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes
                    204:  * split into 64 bit registers. Only the lower 32 bits of each mailbox
                    205:  * are used.
                    206:  */
                    207: #define TI_MB_HOSTINTR_HI              0x500
                    208: #define TI_MB_HOSTINTR_LO              0x504
                    209: #define TI_MB_HOSTINTR                 TI_MB_HOSTINTR_LO
                    210: #define TI_MB_CMDPROD_IDX_HI           0x508
                    211: #define TI_MB_CMDPROD_IDX_LO           0x50C
                    212: #define TI_MB_CMDPROD_IDX              TI_MB_CMDPROD_IDX_LO
                    213: #define TI_MB_SENDPROD_IDX_HI          0x510
                    214: #define TI_MB_SENDPROD_IDX_LO          0x514
                    215: #define TI_MB_SENDPROD_IDX             TI_MB_SENDPROD_IDX_LO
                    216: #define TI_MB_STDRXPROD_IDX_HI         0x518 /* Tigon 2 only */
                    217: #define TI_MB_STDRXPROD_IDX_LO         0x51C /* Tigon 2 only */
                    218: #define TI_MB_STDRXPROD_IDX            TI_MB_STDRXPROD_IDX_LO
                    219: #define TI_MB_JUMBORXPROD_IDX_HI       0x520 /* Tigon 2 only */
                    220: #define TI_MB_JUMBORXPROD_IDX_LO       0x524 /* Tigon 2 only */
                    221: #define TI_MB_JUMBORXPROD_IDX          TI_MB_JUMBORXPROD_IDX_LO
                    222: #define TI_MB_MINIRXPROD_IDX_HI                0x528 /* Tigon 2 only */
                    223: #define TI_MB_MINIRXPROD_IDX_LO                0x52C /* Tigon 2 only */
                    224: #define TI_MB_MINIRXPROD_IDX           TI_MB_MINIRXPROD_IDX_LO
                    225: #define TI_MB_RSVD                     0x530
                    226:
                    227: /*
                    228:  * Tigon 2 general communication registers. These are 64 and 32 bit
                    229:  * registers which are only valid after the firmware has been
                    230:  * loaded and started. They actually exist in NIC memory but are
                    231:  * mapped into the host memory via the shared memory region.
                    232:  *
                    233:  * The NIC internally maps these registers starting at address 0,
                    234:  * so to determine the NIC address of any of these registers, we
                    235:  * subtract 0x600 (the address of the first register).
                    236:  */
                    237:
                    238: #define TI_GCR_BASE                    0x600
                    239: #define TI_GCR_MACADDR                 0x600
                    240: #define TI_GCR_PAR0                    0x600
                    241: #define TI_GCR_PAR1                    0x604
                    242: #define TI_GCR_GENINFO_HI              0x608
                    243: #define TI_GCR_GENINFO_LO              0x60C
                    244: #define TI_GCR_MCASTADDR               0x610 /* obsolete */
                    245: #define TI_GCR_MAR0                    0x610 /* obsolete */
                    246: #define TI_GCR_MAR1                    0x614 /* obsolete */
                    247: #define TI_GCR_OPMODE                  0x618
                    248: #define TI_GCR_DMA_READCFG             0x61C
                    249: #define TI_GCR_DMA_WRITECFG            0x620
                    250: #define TI_GCR_TX_BUFFER_RATIO         0x624
                    251: #define TI_GCR_EVENTCONS_IDX           0x628
                    252: #define TI_GCR_CMDCONS_IDX             0x62C
                    253: #define TI_GCR_TUNEPARMS               0x630
                    254: #define TI_GCR_RX_COAL_TICKS           0x630
                    255: #define TI_GCR_TX_COAL_TICKS           0x634
                    256: #define TI_GCR_STAT_TICKS              0x638
                    257: #define TI_GCR_TX_MAX_COAL_BD          0x63C
                    258: #define TI_GCR_RX_MAX_COAL_BD          0x640
                    259: #define TI_GCR_NIC_TRACING             0x644
                    260: #define TI_GCR_GLINK                   0x648
                    261: #define TI_GCR_LINK                    0x64C
                    262: #define TI_GCR_NICTRACE_PTR            0x650
                    263: #define TI_GCR_NICTRACE_START          0x654
                    264: #define TI_GCR_NICTRACE_LEN            0x658
                    265: #define TI_GCR_IFINDEX                 0x65C
                    266: #define TI_GCR_IFMTU                   0x660
                    267: #define TI_GCR_MASK_INTRS              0x664
                    268: #define TI_GCR_GLINK_STAT              0x668
                    269: #define TI_GCR_LINK_STAT               0x66C
                    270: #define TI_GCR_RXRETURNCONS_IDX                0x680
                    271: #define TI_GCR_CMDRING                 0x700
                    272:
1.24      thorpej   273: #define TI_GCR_NIC_ADDR(x)             (x - TI_GCR_BASE)
1.1       drochner  274:
                    275: /*
                    276:  * Local memory window. The local memory window is a 2K shared
                    277:  * memory region which can be used to access the NIC's internal
                    278:  * SRAM. The window can be mapped to a given 2K region using
                    279:  * the TI_WINDOW_BASE register.
                    280:  */
                    281: #define TI_WINDOW                      0x800
                    282: #define TI_WINLEN                      0x800
                    283:
                    284: #define TI_TICKS_PER_SEC               1000000
                    285:
                    286: /*
                    287:  * Operation mode register.
                    288:  */
                    289: #define TI_OPMODE_BYTESWAP_BD          0x00000002
                    290: #define TI_OPMODE_WORDSWAP_BD          0x00000004
1.29    ! msaitoh   291: #define TI_OPMODE_WARN_ENB             0x00000008 /* not yet implemented */
1.1       drochner  292: #define TI_OPMODE_BYTESWAP_DATA                0x00000010
                    293: #define TI_OPMODE_1_DMA_ACTIVE         0x00000040
                    294: #define TI_OPMODE_SBUS                 0x00000100
                    295: #define TI_OPMODE_DONT_FRAG_JUMBO      0x00000200
                    296: #define TI_OPMODE_INCLUDE_CRC          0x00000400
                    297: #define TI_OPMODE_RX_BADFRAMES         0x00000800
                    298: #define TI_OPMODE_NO_EVENT_INTRS       0x00001000
                    299: #define TI_OPMODE_NO_TX_INTRS          0x00002000
                    300: #define TI_OPMODE_NO_RX_INTRS          0x00004000
1.29    ! msaitoh   301: #define TI_OPMODE_FATAL_ENB            0x40000000 /* not yet implemented */
1.1       drochner  302:
                    303: /*
                    304:  * DMA configuration thresholds.
                    305:  */
                    306: #define TI_DMA_STATE_THRESH_16W                0x00000100
                    307: #define TI_DMA_STATE_THRESH_8W         0x00000080
                    308: #define TI_DMA_STATE_THRESH_4W         0x00000040
                    309: #define TI_DMA_STATE_THRESH_2W         0x00000020
                    310: #define TI_DMA_STATE_THRESH_1W         0x00000010
                    311:
                    312: #define TI_DMA_STATE_FORCE_32_BIT      0x00000008
                    313:
                    314: /*
                    315:  * Gigabit link status bits.
                    316:  */
                    317: #define TI_GLNK_SENSE_NO_BEG           0x00002000
                    318: #define TI_GLNK_LOOPBACK               0x00004000
                    319: #define TI_GLNK_PREF                   0x00008000
                    320: #define TI_GLNK_1000MB                 0x00040000
                    321: #define TI_GLNK_FULL_DUPLEX            0x00080000
                    322: #define TI_GLNK_TX_FLOWCTL_Y           0x00200000 /* Tigon 2 only */
                    323: #define TI_GLNK_RX_FLOWCTL_Y           0x00800000
                    324: #define TI_GLNK_AUTONEGENB             0x20000000
                    325: #define TI_GLNK_ENB                    0x40000000
                    326:
                    327: /*
                    328:  * Link status bits.
                    329:  */
                    330: #define TI_LNK_LOOPBACK                        0x00004000
                    331: #define TI_LNK_PREF                    0x00008000
                    332: #define TI_LNK_10MB                    0x00010000
                    333: #define TI_LNK_100MB                   0x00020000
                    334: #define TI_LNK_1000MB                  0x00040000
                    335: #define TI_LNK_FULL_DUPLEX             0x00080000
                    336: #define TI_LNK_HALF_DUPLEX             0x00100000
                    337: #define TI_LNK_TX_FLOWCTL_Y            0x00200000 /* Tigon 2 only */
                    338: #define TI_LNK_RX_FLOWCTL_Y            0x00800000
                    339: #define TI_LNK_AUTONEGENB              0x20000000
                    340: #define TI_LNK_ENB                     0x40000000
                    341:
                    342: /*
                    343:  * Ring size constants.
                    344:  */
                    345: #define TI_EVENT_RING_CNT      256
                    346: #define TI_CMD_RING_CNT                64
                    347: #define TI_STD_RX_RING_CNT     512
                    348: #define TI_JUMBO_RX_RING_CNT   256
                    349: #define TI_MINI_RX_RING_CNT    1024
                    350: #define TI_RETURN_RING_CNT     2048
                    351:
                    352: /*
                    353:  * Possible TX ring sizes.
                    354:  */
                    355: #define TI_TX_RING_CNT_128     128
                    356: #define TI_TX_RING_BASE_128    0x3800
                    357:
                    358: #define TI_TX_RING_CNT_256     256
                    359: #define TI_TX_RING_BASE_256    0x3000
                    360:
                    361: #define TI_TX_RING_CNT_512     512
                    362: #define TI_TX_RING_BASE_512    0x2000
                    363:
                    364: #define TI_TX_RING_CNT         TI_TX_RING_CNT_512
                    365: #define TI_TX_RING_BASE                TI_TX_RING_BASE_512
                    366:
                    367: /*
                    368:  * The Tigon can have up to 8MB of external SRAM, however the Tigon 1
                    369:  * is limited to 2MB total, and in general I think most adapters have
                    370:  * around 1MB. We use this value for zeroing the NIC's SRAM, so to
                    371:  * be safe we use the largest possible value (zeroing memory that
                    372:  * isn't there doesn't hurt anything).
                    373:  */
                    374: #define TI_MEM_MAX             0x7FFFFF
                    375:
                    376: typedef struct {
1.28      msaitoh   377:        uint32_t        ti_addr_hi;
                    378:        uint32_t        ti_addr_lo;
1.1       drochner  379: } ti_hostaddr;
                    380:
                    381: /*
                    382:  * Ring control block structure. The rules for the max_len field
                    383:  * are as follows:
1.15      perry     384:  *
1.1       drochner  385:  * For the send ring, max_len indicates the number of entries in the
                    386:  * ring (128, 256 or 512).
                    387:  *
                    388:  * For the standard receive ring, max_len indicates the threshold
                    389:  * used to decide when a frame should be put in the jumbo receive ring
                    390:  * instead of the standard one.
                    391:  *
                    392:  * For the mini ring, max_len indicates the size of the buffers in the
                    393:  * ring. This is the value used to decide when a frame is small enough
                    394:  * to be placed in the mini ring.
                    395:  *
                    396:  * For the return receive ring, max_len indicates the number of entries
                    397:  * in the ring. It can be one of 2048, 1024 or 0 (which is the same as
                    398:  * 2048 for backwards compatibility). The value 1024 can only be used
                    399:  * if the mini ring is disabled.
                    400:  */
                    401: struct ti_rcb {
                    402:        ti_hostaddr             ti_hostaddr;
                    403: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   404:        uint16_t                ti_max_len;
                    405:        uint16_t                ti_flags;
1.1       drochner  406: #else
1.28      msaitoh   407:        uint16_t                ti_flags;
                    408:        uint16_t                ti_max_len;
1.1       drochner  409: #endif
1.28      msaitoh   410:        uint32_t                ti_unused;
1.1       drochner  411: };
                    412:
                    413: #define TI_RCB_FLAG_TCP_UDP_CKSUM      0x00000001
                    414: #define TI_RCB_FLAG_IP_CKSUM           0x00000002
                    415: #define TI_RCB_FLAG_NO_PHDR_CKSUM      0x00000008
                    416: #define TI_RCB_FLAG_VLAN_ASSIST                0x00000010
                    417: #define TI_RCB_FLAG_COAL_UPD_ONLY      0x00000020
                    418: #define TI_RCB_FLAG_HOST_RING          0x00000040
                    419: #define TI_RCB_FLAG_IEEE_SNAP_CKSUM    0x00000080
                    420: #define TI_RCB_FLAG_USE_EXT_RX_BD      0x00000100
                    421: #define TI_RCB_FLAG_RING_DISABLED      0x00000200
                    422:
                    423: struct ti_producer {
1.28      msaitoh   424:        uint32_t                ti_idx;
                    425:        uint32_t                ti_unused;
1.1       drochner  426: };
                    427:
                    428: /*
                    429:  * Tigon statistics counters.
                    430:  */
                    431: struct ti_stats {
                    432:        /*
                    433:         * MAC stats, taken from RFC 1643, ethernet-like MIB
                    434:         */
1.28      msaitoh   435:        volatile uint32_t dot3StatsAlignmentErrors;             /* 0 */
                    436:        volatile uint32_t dot3StatsFCSErrors;                   /* 1 */
                    437:        volatile uint32_t dot3StatsSingleCollisionFrames;       /* 2 */
                    438:        volatile uint32_t dot3StatsMultipleCollisionFrames;     /* 3 */
                    439:        volatile uint32_t dot3StatsSQETestErrors;               /* 4 */
                    440:        volatile uint32_t dot3StatsDeferredTransmissions;       /* 5 */
                    441:        volatile uint32_t dot3StatsLateCollisions;              /* 6 */
                    442:        volatile uint32_t dot3StatsExcessiveCollisions; /* 7 */
                    443:        volatile uint32_t dot3StatsInternalMacTransmitErrors;   /* 8 */
                    444:        volatile uint32_t dot3StatsCarrierSenseErrors;          /* 9 */
                    445:        volatile uint32_t dot3StatsFrameTooLongs;               /* 10 */
                    446:        volatile uint32_t dot3StatsInternalMacReceiveErrors;    /* 11 */
1.1       drochner  447:        /*
                    448:         * interface stats, taken from RFC 1213, MIB-II, interfaces group
                    449:         */
1.28      msaitoh   450:        volatile uint32_t ifIndex;                              /* 12 */
                    451:        volatile uint32_t ifType;                               /* 13 */
                    452:        volatile uint32_t ifMtu;                                /* 14 */
                    453:        volatile uint32_t ifSpeed;                              /* 15 */
                    454:        volatile uint32_t ifAdminStatus;                        /* 16 */
1.1       drochner  455: #define IF_ADMIN_STATUS_UP      1
                    456: #define IF_ADMIN_STATUS_DOWN    2
                    457: #define IF_ADMIN_STATUS_TESTING 3
1.28      msaitoh   458:        volatile uint32_t ifOperStatus;                 /* 17 */
1.1       drochner  459: #define IF_OPER_STATUS_UP       1
                    460: #define IF_OPER_STATUS_DOWN     2
                    461: #define IF_OPER_STATUS_TESTING  3
                    462: #define IF_OPER_STATUS_UNKNOWN  4
                    463: #define IF_OPER_STATUS_DORMANT  5
1.28      msaitoh   464:        volatile uint32_t ifLastChange;                 /* 18 */
                    465:        volatile uint32_t ifInDiscards;                 /* 19 */
                    466:        volatile uint32_t ifInErrors;                           /* 20 */
                    467:        volatile uint32_t ifInUnknownProtos;                    /* 21 */
                    468:        volatile uint32_t ifOutDiscards;                        /* 22 */
                    469:        volatile uint32_t ifOutErrors;                          /* 23 */
                    470:        volatile uint32_t ifOutQLen;     /* deprecated */       /* 24 */
                    471:        volatile uint8_t  ifPhysAddress[8]; /* 8 bytes */       /* 25 - 26 */
                    472:        volatile uint8_t  ifDescr[32];                          /* 27 - 34 */
                    473:        uint32_t alignIt;      /* align to 64 bit for u_int64_ts following */
1.1       drochner  474:        /*
                    475:         * more interface stats, taken from RFC 1573, MIB-IIupdate,
                    476:         * interfaces group
                    477:         */
                    478:        volatile u_int64_t ifHCInOctets;                        /* 36 - 37 */
                    479:        volatile u_int64_t ifHCInUcastPkts;                     /* 38 - 39 */
                    480:        volatile u_int64_t ifHCInMulticastPkts;                 /* 40 - 41 */
                    481:        volatile u_int64_t ifHCInBroadcastPkts;                 /* 42 - 43 */
                    482:        volatile u_int64_t ifHCOutOctets;                       /* 44 - 45 */
                    483:        volatile u_int64_t ifHCOutUcastPkts;                    /* 46 - 47 */
                    484:        volatile u_int64_t ifHCOutMulticastPkts;                /* 48 - 49 */
                    485:        volatile u_int64_t ifHCOutBroadcastPkts;                /* 50 - 51 */
1.28      msaitoh   486:        volatile uint32_t ifLinkUpDownTrapEnable;               /* 52 */
                    487:        volatile uint32_t ifHighSpeed;                          /* 53 */
                    488:        volatile uint32_t ifPromiscuousMode;                    /* 54 */
                    489:        volatile uint32_t ifConnectorPresent; /* follow link state 55 */
1.1       drochner  490:        /*
                    491:         * Host Commands
                    492:         */
1.28      msaitoh   493:        volatile uint32_t nicCmdsHostState;                     /* 56 */
                    494:        volatile uint32_t nicCmdsFDRFiltering;                  /* 57 */
                    495:        volatile uint32_t nicCmdsSetRecvProdIndex;              /* 58 */
                    496:        volatile uint32_t nicCmdsUpdateGencommStats;            /* 59 */
                    497:        volatile uint32_t nicCmdsResetJumboRing;                /* 60 */
                    498:        volatile uint32_t nicCmdsAddMCastAddr;                  /* 61 */
                    499:        volatile uint32_t nicCmdsDelMCastAddr;                  /* 62 */
                    500:        volatile uint32_t nicCmdsSetPromiscMode;                /* 63 */
                    501:        volatile uint32_t nicCmdsLinkNegotiate;         /* 64 */
                    502:        volatile uint32_t nicCmdsSetMACAddr;                    /* 65 */
                    503:        volatile uint32_t nicCmdsClearProfile;                  /* 66 */
                    504:        volatile uint32_t nicCmdsSetMulticastMode;              /* 67 */
                    505:        volatile uint32_t nicCmdsClearStats;                    /* 68 */
                    506:        volatile uint32_t nicCmdsSetRecvJumboProdIndex; /* 69 */
                    507:        volatile uint32_t nicCmdsSetRecvMiniProdIndex;          /* 70 */
                    508:        volatile uint32_t nicCmdsRefreshStats;                  /* 71 */
                    509:        volatile uint32_t nicCmdsUnknown;                       /* 72 */
1.1       drochner  510:        /*
                    511:         * NIC Events
                    512:         */
1.28      msaitoh   513:        volatile uint32_t nicEventsNICFirmwareOperational;      /* 73 */
                    514:        volatile uint32_t nicEventsStatsUpdated;                /* 74 */
                    515:        volatile uint32_t nicEventsLinkStateChanged;            /* 75 */
                    516:        volatile uint32_t nicEventsError;                       /* 76 */
                    517:        volatile uint32_t nicEventsMCastListUpdated;            /* 77 */
                    518:        volatile uint32_t nicEventsResetJumboRing;              /* 78 */
1.1       drochner  519:        /*
                    520:         * Ring manipulation
                    521:         */
1.28      msaitoh   522:        volatile uint32_t nicRingSetSendProdIndex;              /* 79 */
                    523:        volatile uint32_t nicRingSetSendConsIndex;              /* 80 */
                    524:        volatile uint32_t nicRingSetRecvReturnProdIndex;        /* 81 */
1.1       drochner  525:        /*
                    526:         * Interrupts
                    527:         */
1.28      msaitoh   528:        volatile uint32_t nicInterrupts;                        /* 82 */
                    529:        volatile uint32_t nicAvoidedInterrupts;         /* 83 */
1.1       drochner  530:        /*
1.12      wiz       531:         * BD Coalescing Thresholds
1.1       drochner  532:         */
1.28      msaitoh   533:        volatile uint32_t nicEventThresholdHit;         /* 84 */
                    534:        volatile uint32_t nicSendThresholdHit;                  /* 85 */
                    535:        volatile uint32_t nicRecvThresholdHit;                  /* 86 */
1.1       drochner  536:        /*
                    537:         * DMA Attentions
                    538:         */
1.28      msaitoh   539:        volatile uint32_t nicDmaRdOverrun;                      /* 87 */
                    540:        volatile uint32_t nicDmaRdUnderrun;                     /* 88 */
                    541:        volatile uint32_t nicDmaWrOverrun;                      /* 89 */
                    542:        volatile uint32_t nicDmaWrUnderrun;                     /* 90 */
                    543:        volatile uint32_t nicDmaWrMasterAborts;         /* 91 */
                    544:        volatile uint32_t nicDmaRdMasterAborts;         /* 92 */
1.1       drochner  545:        /*
                    546:         * NIC Resources
                    547:         */
1.28      msaitoh   548:        volatile uint32_t nicDmaWriteRingFull;                  /* 93 */
                    549:        volatile uint32_t nicDmaReadRingFull;                   /* 94 */
                    550:        volatile uint32_t nicEventRingFull;                     /* 95 */
                    551:        volatile uint32_t nicEventProducerRingFull;             /* 96 */
                    552:        volatile uint32_t nicTxMacDescrRingFull;                /* 97 */
                    553:        volatile uint32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */
                    554:        volatile uint32_t nicNoMoreWrDMADescriptors;            /* 99 */
                    555:        volatile uint32_t nicNoMoreRxBDs;                       /* 100 */
                    556:        volatile uint32_t nicNoSpaceInReturnRing;               /* 101 */
                    557:        volatile uint32_t nicSendBDs;            /* current count 102 */
                    558:        volatile uint32_t nicRecvBDs;            /* current count 103 */
                    559:        volatile uint32_t nicJumboRecvBDs;       /* current count 104 */
                    560:        volatile uint32_t nicMiniRecvBDs;        /* current count 105 */
                    561:        volatile uint32_t nicTotalRecvBDs;       /* current count 106 */
                    562:        volatile uint32_t nicTotalSendBDs;       /* current count 107 */
                    563:        volatile uint32_t nicJumboSpillOver;                    /* 108 */
                    564:        volatile uint32_t nicSbusHangCleared;                   /* 109 */
                    565:        volatile uint32_t nicEnqEventDelayed;                   /* 110 */
1.1       drochner  566:        /*
                    567:         * Stats from MAC rx completion
                    568:         */
1.28      msaitoh   569:        volatile uint32_t nicMacRxLateColls;                    /* 111 */
                    570:        volatile uint32_t nicMacRxLinkLostDuringPkt;            /* 112 */
                    571:        volatile uint32_t nicMacRxPhyDecodeErr;         /* 113 */
                    572:        volatile uint32_t nicMacRxMacAbort;                     /* 114 */
                    573:        volatile uint32_t nicMacRxTruncNoResources;             /* 115 */
1.1       drochner  574:        /*
                    575:         * Stats from the mac_stats area
                    576:         */
1.28      msaitoh   577:        volatile uint32_t nicMacRxDropUla;                      /* 116 */
                    578:        volatile uint32_t nicMacRxDropMcast;                    /* 117 */
                    579:        volatile uint32_t nicMacRxFlowControl;                  /* 118 */
                    580:        volatile uint32_t nicMacRxDropSpace;                    /* 119 */
                    581:        volatile uint32_t nicMacRxColls;                        /* 120 */
1.1       drochner  582:        /*
                    583:         * MAC RX Attentions
                    584:         */
1.28      msaitoh   585:        volatile uint32_t nicMacRxTotalAttns;                   /* 121 */
                    586:        volatile uint32_t nicMacRxLinkAttns;                    /* 122 */
                    587:        volatile uint32_t nicMacRxSyncAttns;                    /* 123 */
                    588:        volatile uint32_t nicMacRxConfigAttns;                  /* 124 */
                    589:        volatile uint32_t nicMacReset;                          /* 125 */
                    590:        volatile uint32_t nicMacRxBufDescrAttns;                /* 126 */
                    591:        volatile uint32_t nicMacRxBufAttns;                     /* 127 */
                    592:        volatile uint32_t nicMacRxZeroFrameCleanup;             /* 128 */
                    593:        volatile uint32_t nicMacRxOneFrameCleanup;              /* 129 */
                    594:        volatile uint32_t nicMacRxMultipleFrameCleanup; /* 130 */
                    595:        volatile uint32_t nicMacRxTimerCleanup;         /* 131 */
                    596:        volatile uint32_t nicMacRxDmaCleanup;                   /* 132 */
1.1       drochner  597:        /*
                    598:         * Stats from the mac_stats area
                    599:         */
1.28      msaitoh   600:        volatile uint32_t nicMacTxCollisionHistogram[15];       /* 133 */
1.1       drochner  601:        /*
                    602:         * MAC TX Attentions
                    603:         */
1.28      msaitoh   604:        volatile uint32_t nicMacTxTotalAttns;                   /* 134 */
1.1       drochner  605:        /*
                    606:         * NIC Profile
                    607:         */
1.28      msaitoh   608:        volatile uint32_t nicProfile[32];                       /* 135 */
1.1       drochner  609:        /*
                    610:         * Pat to 1024 bytes.
                    611:         */
1.28      msaitoh   612:        uint32_t                pad[75];
1.1       drochner  613: };
                    614: /*
                    615:  * Tigon general information block. This resides in host memory
                    616:  * and contains the status counters, ring control blocks and
                    617:  * producer pointers.
                    618:  */
                    619:
                    620: struct ti_gib {
                    621:        struct ti_stats         ti_stats;
                    622:        struct ti_rcb           ti_ev_rcb;
                    623:        struct ti_rcb           ti_cmd_rcb;
                    624:        struct ti_rcb           ti_tx_rcb;
                    625:        struct ti_rcb           ti_std_rx_rcb;
                    626:        struct ti_rcb           ti_jumbo_rx_rcb;
                    627:        struct ti_rcb           ti_mini_rx_rcb;
                    628:        struct ti_rcb           ti_return_rcb;
                    629:        ti_hostaddr             ti_ev_prodidx_ptr;
                    630:        ti_hostaddr             ti_return_prodidx_ptr;
                    631:        ti_hostaddr             ti_tx_considx_ptr;
                    632:        ti_hostaddr             ti_refresh_stats_ptr;
                    633: };
                    634:
                    635: /*
                    636:  * Buffer descriptor structures. There are basically three types
                    637:  * of structures: normal receive descriptors, extended receive
                    638:  * descriptors and transmit descriptors. The extended receive
                    639:  * descriptors are optionally used only for the jumbo receive ring.
                    640:  */
                    641:
                    642: struct ti_rx_desc {
                    643:        ti_hostaddr             ti_addr;
                    644: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   645:        uint16_t                ti_idx;
                    646:        uint16_t                ti_len;
1.1       drochner  647: #else
1.28      msaitoh   648:        uint16_t                ti_len;
                    649:        uint16_t                ti_idx;
1.1       drochner  650: #endif
                    651: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   652:        uint16_t                ti_type;
                    653:        uint16_t                ti_flags;
1.1       drochner  654: #else
1.28      msaitoh   655:        uint16_t                ti_flags;
                    656:        uint16_t                ti_type;
1.1       drochner  657: #endif
                    658: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   659:        uint16_t                ti_ip_cksum;
                    660:        uint16_t                ti_tcp_udp_cksum;
1.1       drochner  661: #else
1.28      msaitoh   662:        uint16_t                ti_tcp_udp_cksum;
                    663:        uint16_t                ti_ip_cksum;
1.1       drochner  664: #endif
                    665: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   666:        uint16_t                ti_error_flags;
                    667:        uint16_t                ti_vlan_tag;
1.1       drochner  668: #else
1.28      msaitoh   669:        uint16_t                ti_vlan_tag;
                    670:        uint16_t                ti_error_flags;
1.1       drochner  671: #endif
1.28      msaitoh   672:        uint32_t                ti_rsvd;
                    673:        uint32_t                ti_opaque;
1.1       drochner  674: };
                    675:
                    676: struct ti_rx_desc_ext {
                    677:        ti_hostaddr             ti_addr1;
                    678:        ti_hostaddr             ti_addr2;
                    679:        ti_hostaddr             ti_addr3;
                    680: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   681:        uint16_t                ti_len1;
                    682:        uint16_t                ti_len2;
1.1       drochner  683: #else
1.28      msaitoh   684:        uint16_t                ti_len2;
                    685:        uint16_t                ti_len1;
1.1       drochner  686: #endif
                    687: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   688:        uint16_t                ti_len3;
                    689:        uint16_t                ti_rsvd0;
1.1       drochner  690: #else
1.28      msaitoh   691:        uint16_t                ti_rsvd0;
                    692:        uint16_t                ti_len3;
1.1       drochner  693: #endif
                    694:        ti_hostaddr             ti_addr0;
                    695: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   696:        uint16_t                ti_idx;
                    697:        uint16_t                ti_len0;
1.1       drochner  698: #else
1.28      msaitoh   699:        uint16_t                ti_len0;
                    700:        uint16_t                ti_idx;
1.1       drochner  701: #endif
                    702: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   703:        uint16_t                ti_type;
                    704:        uint16_t                ti_flags;
1.1       drochner  705: #else
1.28      msaitoh   706:        uint16_t                ti_flags;
                    707:        uint16_t                ti_type;
1.1       drochner  708: #endif
                    709: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   710:        uint16_t                ti_ip_cksum;
                    711:        uint16_t                ti_tcp_udp_cksum;
1.1       drochner  712: #else
1.28      msaitoh   713:        uint16_t                ti_tcp_udp_cksum;
                    714:        uint16_t                ti_ip_cksum;
1.1       drochner  715: #endif
                    716: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   717:        uint16_t                ti_error_flags;
                    718:        uint16_t                ti_vlan_tag;
1.1       drochner  719: #else
1.28      msaitoh   720:        uint16_t                ti_vlan_tag;
                    721:        uint16_t                ti_error_flags;
1.1       drochner  722: #endif
1.28      msaitoh   723:        uint32_t                ti_rsvd1;
                    724:        uint32_t                ti_opaque;
1.1       drochner  725: };
                    726:
                    727: /*
                    728:  * Transmit descriptors are, mercifully, very small.
                    729:  */
                    730: struct ti_tx_desc {
                    731:        ti_hostaddr             ti_addr;
                    732: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   733:        uint16_t                ti_len;
                    734:        uint16_t                ti_flags;
1.1       drochner  735: #else
1.28      msaitoh   736:        uint16_t                ti_flags;
                    737:        uint16_t                ti_len;
1.1       drochner  738: #endif
                    739: #if BYTE_ORDER == BIG_ENDIAN
1.28      msaitoh   740:        uint16_t                ti_rsvd;
                    741:        uint16_t                ti_vlan_tag;
1.1       drochner  742: #else
1.28      msaitoh   743:        uint16_t                ti_vlan_tag;
                    744:        uint16_t                ti_rsvd;
1.1       drochner  745: #endif
                    746: };
                    747:
                    748: /*
                    749:  * NOTE!  On the Alpha, we have an alignment constraint.
                    750:  * The first thing in the packet is a 14-byte Ethernet header.
                    751:  * This means that the packet is misaligned.  To compensate,
                    752:  * we actually offset the data 2 bytes into the cluster.  This
                    753:  * alignes the packet after the Ethernet header at a 32-bit
                    754:  * boundary.
                    755:  */
                    756:
                    757: #define TI_PAGE_SIZE           PAGE_SIZE
                    758:
                    759: /*
                    760:  * Buffer descriptor error flags.
                    761:  */
                    762: #define TI_BDERR_CRC                   0x0001
                    763: #define TI_BDERR_COLLDETECT            0x0002
                    764: #define TI_BDERR_LINKLOST              0x0004
                    765: #define TI_BDERR_DECODE                        0x0008
                    766: #define TI_BDERR_ODD_NIBBLES           0x0010
                    767: #define TI_BDERR_MAC_ABRT              0x0020
                    768: #define TI_BDERR_RUNT                  0x0040
                    769: #define TI_BDERR_TRUNC                 0x0080
                    770: #define TI_BDERR_GIANT                 0x0100
                    771:
                    772: /*
                    773:  * Buffer descriptor flags.
                    774:  */
                    775: #define TI_BDFLAG_TCP_UDP_CKSUM                0x0001
                    776: #define TI_BDFLAG_IP_CKSUM             0x0002
                    777: #define TI_BDFLAG_END                  0x0004
                    778: #define TI_BDFLAG_MORE                 0x0008
                    779: #define TI_BDFLAG_JUMBO_RING           0x0010
                    780: #define TI_BDFLAG_UCAST_PKT            0x0020
                    781: #define TI_BDFLAG_MCAST_PKT            0x0040
                    782: #define TI_BDFLAG_BCAST_PKT            0x0060
                    783: #define TI_BDFLAG_IP_FRAG              0x0080
                    784: #define TI_BDFLAG_IP_FRAG_END          0x0100
                    785: #define TI_BDFLAG_VLAN_TAG             0x0200
                    786: #define TI_BDFLAG_ERROR                        0x0400
                    787: #define TI_BDFLAG_COAL_NOW             0x0800
                    788: #define        TI_BDFLAG_MINI_RING             0x1000
                    789:
                    790: /*
                    791:  * Descriptor type flags. I think these only have meaning for
                    792:  * the Tigon 1. I had to extract them from the sample driver source
                    793:  * since they aren't in the manual.
                    794:  */
                    795: #define TI_BDTYPE_TYPE_NULL                    0x0000
                    796: #define TI_BDTYPE_SEND_BD                      0x0001
                    797: #define TI_BDTYPE_RECV_BD                      0x0002
                    798: #define TI_BDTYPE_RECV_JUMBO_BD                        0x0003
                    799: #define TI_BDTYPE_RECV_BD_LAST                 0x0004
                    800: #define TI_BDTYPE_SEND_DATA                    0x0005
                    801: #define TI_BDTYPE_SEND_DATA_LAST               0x0006
                    802: #define TI_BDTYPE_RECV_DATA                    0x0007
                    803: #define TI_BDTYPE_RECV_DATA_LAST               0x000b
                    804: #define TI_BDTYPE_EVENT_RUPT                   0x000c
                    805: #define TI_BDTYPE_EVENT_NO_RUPT                        0x000d
                    806: #define TI_BDTYPE_ODD_START                    0x000e
                    807: #define TI_BDTYPE_UPDATE_STATS                 0x000f
                    808: #define TI_BDTYPE_SEND_DUMMY_DMA               0x0010
                    809: #define TI_BDTYPE_EVENT_PROD                   0x0011
                    810: #define TI_BDTYPE_TX_CONS                      0x0012
                    811: #define TI_BDTYPE_RX_PROD                      0x0013
                    812: #define TI_BDTYPE_REFRESH_STATS                        0x0014
                    813: #define TI_BDTYPE_SEND_DATA_LAST_VLAN          0x0015
                    814: #define TI_BDTYPE_SEND_DATA_COAL               0x0016
                    815: #define TI_BDTYPE_SEND_DATA_LAST_COAL          0x0017
                    816: #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL     0x0018
                    817: #define TI_BDTYPE_TX_CONS_NO_INTR              0x0019
                    818:
                    819: /*
                    820:  * Tigon command structure.
                    821:  */
                    822: struct ti_cmd_desc {
1.28      msaitoh   823:        uint32_t                ti_cmdx;
1.1       drochner  824: };
                    825:
1.19      tnn       826: #define TI_CMD_CMD(cmd)                (((((cmd)->ti_cmdx)) >> 24) & 0xff)
                    827: #define TI_CMD_CODE(cmd)       (((((cmd)->ti_cmdx)) >> 12) & 0xfff)
                    828: #define TI_CMD_IDX(cmd)                ((((cmd)->ti_cmdx)) & 0xfff)
                    829:
1.1       drochner  830: #define TI_CMD_HOST_STATE              0x01
                    831: #define TI_CMD_CODE_STACK_UP           0x01
                    832: #define TI_CMD_CODE_STACK_DOWN         0x02
                    833:
                    834: /*
                    835:  * This command enables software address filtering. It's a workaround
                    836:  * for a bug in the Tigon 1 and not implemented for the Tigon 2.
                    837:  */
                    838: #define TI_CMD_FDR_FILTERING           0x02
                    839: #define TI_CMD_CODE_FILT_ENB           0x01
                    840: #define TI_CMD_CODE_FILT_DIS           0x02
                    841:
                    842: #define TI_CMD_SET_RX_PROD_IDX         0x03 /* obsolete */
                    843: #define TI_CMD_UPDATE_GENCOM           0x04
                    844: #define TI_CMD_RESET_JUMBO_RING                0x05
                    845: #define TI_CMD_SET_PARTIAL_RX_CNT      0x06
                    846: #define TI_CMD_ADD_MCAST_ADDR          0x08 /* obsolete */
                    847: #define TI_CMD_DEL_MCAST_ADDR          0x09 /* obsolete */
                    848:
                    849: #define TI_CMD_SET_PROMISC_MODE                0x0A
                    850: #define TI_CMD_CODE_PROMISC_ENB                0x01
                    851: #define TI_CMD_CODE_PROMISC_DIS                0x02
                    852:
                    853: #define TI_CMD_LINK_NEGOTIATION                0x0B
                    854: #define TI_CMD_CODE_NEGOTIATE_BOTH     0x00
                    855: #define TI_CMD_CODE_NEGOTIATE_GIGABIT  0x01
                    856: #define TI_CMD_CODE_NEGOTIATE_10_100   0x02
                    857:
                    858: #define TI_CMD_SET_MAC_ADDR            0x0C
                    859: #define TI_CMD_CLR_PROFILE             0x0D
                    860:
                    861: #define TI_CMD_SET_ALLMULTI            0x0E
                    862: #define TI_CMD_CODE_ALLMULTI_ENB       0x01
                    863: #define TI_CMD_CODE_ALLMULTI_DIS       0x02
                    864:
                    865: #define TI_CMD_CLR_STATS               0x0F
                    866: #define TI_CMD_SET_RX_JUMBO_PROD_IDX   0x10 /* obsolete */
                    867: #define TI_CMD_RFRSH_STATS             0x11
                    868:
                    869: #define TI_CMD_EXT_ADD_MCAST           0x12
                    870: #define TI_CMD_EXT_DEL_MCAST           0x13
                    871:
                    872: /*
                    873:  * Utility macros to make issuing commands a little simpler. Assumes
                    874:  * that 'sc' and 'cmd' are in local scope.
                    875:  */
1.19      tnn       876: #define TI_DO_CMD(x, y, z)     do {                            \
                    877:        cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z)));      \
                    878:        ti_cmd(sc, &cmd);                                       \
                    879: } while(0)
                    880:
                    881: #define TI_DO_CMD_EXT(x, y, z, v, w)   do {                    \
                    882:        cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z)));      \
                    883:        ti_cmd_ext(sc, &cmd, (v), (w));                         \
                    884: } while(0)
1.1       drochner  885:
                    886: /*
                    887:  * Other utility macros.
                    888:  */
1.19      tnn       889: #define TI_INC(x, y)   do { (x) = ((x) + 1) % (y); } while(0)
1.1       drochner  890:
1.19      tnn       891: #define TI_UPDATE_JUMBOPROD(x, y)      do {                            \
                    892:        if ((x)->ti_hwrev == TI_HWREV_TIGON)                            \
1.1       drochner  893:                TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y);  \
1.19      tnn       894:        else                                                            \
1.1       drochner  895:                CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y);               \
1.19      tnn       896: } while(0)
1.1       drochner  897:
                    898: #define TI_UPDATE_MINIPROD(x, y)                                       \
1.19      tnn       899:                CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y)
1.1       drochner  900:
1.19      tnn       901: #define TI_UPDATE_STDPROD(x, y)                do {                            \
                    902:        if ((x)->ti_hwrev == TI_HWREV_TIGON)                            \
1.1       drochner  903:                TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y);                \
1.19      tnn       904:        else                                                            \
1.1       drochner  905:                CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y);                 \
1.19      tnn       906: } while(0)
1.1       drochner  907:
                    908:
                    909: /*
                    910:  * Tigon event structure.
                    911:  */
                    912: struct ti_event_desc {
1.28      msaitoh   913:        uint32_t                ti_eventx;
                    914:        uint32_t                ti_rsvd;
1.1       drochner  915: };
                    916:
1.19      tnn       917: #define TI_EVENT_EVENT(e)      (((((e)->ti_eventx)) >> 24) & 0xff)
                    918: #define TI_EVENT_CODE(e)       (((((e)->ti_eventx)) >> 12) & 0xfff)
                    919: #define TI_EVENT_IDX(e)                (((((e)->ti_eventx))) & 0xfff)
                    920:
1.1       drochner  921: /*
                    922:  * Tigon events.
                    923:  */
                    924: #define TI_EV_FIRMWARE_UP              0x01
                    925: #define TI_EV_STATS_UPDATED            0x04
                    926:
                    927: #define TI_EV_LINKSTAT_CHANGED         0x06
                    928: #define TI_EV_CODE_GIG_LINK_UP         0x01
                    929: #define TI_EV_CODE_LINK_DOWN           0x02
                    930: #define TI_EV_CODE_LINK_UP             0x03
                    931:
                    932: #define TI_EV_ERROR                    0x07
                    933: #define TI_EV_CODE_ERR_INVAL_CMD       0x01
                    934: #define TI_EV_CODE_ERR_UNIMP_CMD       0x02
                    935: #define TI_EV_CODE_ERR_BADCFG          0x03
                    936:
                    937: #define TI_EV_MCAST_UPDATED            0x08
                    938: #define TI_EV_CODE_MCAST_ADD           0x01
                    939: #define TI_EV_CODE_MCAST_DEL           0x02
                    940:
                    941: #define TI_EV_RESET_JUMBO_RING         0x09
                    942: /*
                    943:  * Register access macros. The Tigon always uses memory mapped register
                    944:  * accesses and all registers must be accessed with 32 bit operations.
1.13      bouyer    945:  * The Tigon can operate in big-endian mode, so we always write to the
                    946:  * registers in native byte order. We assume that all big-endian hosts
                    947:  * with a PCI bus have __BUS_SPACE_HAS_STREAM_METHODS defined.
1.1       drochner  948:  */
                    949:
1.13      bouyer    950: #ifdef __BUS_SPACE_HAS_STREAM_METHODS
                    951: #define CSR_WRITE_4(sc, reg, val)      \
1.19      tnn       952:        bus_space_write_stream_4((sc)->ti_btag, (sc)->ti_bhandle, reg, val)
1.13      bouyer    953:
                    954: #define CSR_READ_4(sc, reg)            \
1.19      tnn       955:        bus_space_read_stream_4((sc)->ti_btag, (sc)->ti_bhandle, reg)
1.13      bouyer    956: #else
1.1       drochner  957: #define CSR_WRITE_4(sc, reg, val)      \
1.19      tnn       958:        bus_space_write_4((sc)->ti_btag, (sc)->ti_bhandle, reg, val)
1.1       drochner  959:
                    960: #define CSR_READ_4(sc, reg)            \
1.19      tnn       961:        bus_space_read_4((sc)->ti_btag, (sc)->ti_bhandle, reg)
1.13      bouyer    962: #endif
1.1       drochner  963:
                    964: #define TI_SETBIT(sc, reg, x)  \
1.19      tnn       965:        CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
1.1       drochner  966: #define TI_CLRBIT(sc, reg, x)  \
1.19      tnn       967:        CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
1.1       drochner  968:
                    969: /*
                    970:  * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
                    971:  * values are tuneable. They control the actual amount of buffers
                    972:  * allocated for the standard, mini and jumbo receive rings.
                    973:  */
                    974:
1.14      he        975: #ifndef TI_SSLOTS
                    976: #define TI_SSLOTS      256
                    977: #endif
                    978: #ifndef TI_MSLOTS
                    979: #define TI_MSLOTS      256
                    980: #endif
                    981: #ifndef TI_JSLOTS
                    982: #define TI_JSLOTS      384
                    983: #endif
1.1       drochner  984: #define TI_RSLOTS      128
                    985:
1.5       thorpej   986: #define TI_JRAWLEN (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN + sizeof(u_int64_t))
1.1       drochner  987: #define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \
                    988:        (TI_JRAWLEN % sizeof(u_int64_t))))
1.2       thorpej   989: #define TI_JPAGESZ PAGE_SIZE
1.1       drochner  990: #define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ)
                    991: #define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID)
                    992:
                    993: /*
                    994:  * Ring structures. Most of these reside in host memory and we tell
                    995:  * the NIC where they are via the ring control blocks. The exceptions
                    996:  * are the tx and command rings, which live in NIC memory and which
                    997:  * we access via the shared memory window.
                    998:  */
                    999: struct ti_ring_data {
                   1000:        struct ti_rx_desc       ti_rx_std_ring[TI_STD_RX_RING_CNT];
                   1001:        struct ti_rx_desc       ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT];
                   1002:        struct ti_rx_desc       ti_rx_mini_ring[TI_MINI_RX_RING_CNT];
                   1003:        struct ti_rx_desc       ti_rx_return_ring[TI_RETURN_RING_CNT];
                   1004:        struct ti_event_desc    ti_event_ring[TI_EVENT_RING_CNT];
                   1005:        struct ti_tx_desc       ti_tx_ring[TI_TX_RING_CNT];
                   1006:        /*
                   1007:         * Make sure producer structures are aligned on 32-byte cache
                   1008:         * line boundaries.
                   1009:         */
                   1010:        struct ti_producer      ti_ev_prodidx_r;
1.28      msaitoh  1011:        uint32_t                ti_pad0[6];
1.1       drochner 1012:        struct ti_producer      ti_return_prodidx_r;
1.28      msaitoh  1013:        uint32_t                ti_pad1[6];
1.1       drochner 1014:        struct ti_producer      ti_tx_considx_r;
1.28      msaitoh  1015:        uint32_t                ti_pad2[6];
1.1       drochner 1016:        struct ti_gib           ti_info;
                   1017: };
                   1018:
1.9       thorpej  1019: #define        TI_CDOFF(x)             offsetof(struct ti_ring_data, x)
                   1020: #define        TI_CDRXSTDOFF(x)        TI_CDOFF(ti_rx_std_ring[(x)])
                   1021: #define        TI_CDRXJUMBOOFF(x)      TI_CDOFF(ti_rx_jumbo_ring[(x)])
                   1022: #define        TI_CDRXMINIOFF(x)       TI_CDOFF(ti_rx_mini_ring[(x)])
                   1023: #define        TI_CDRXRTNOFF(x)        TI_CDOFF(ti_rx_return_ring[(x)])
                   1024: #define        TI_CDEVENTOFF(x)        TI_CDOFF(ti_event_ring[(x)])
                   1025: #define        TI_CDTXOFF(x)           TI_CDOFF(ti_tx_ring[(x)])
                   1026: #define        TI_CDEVPRODOFF          TI_CDOFF(ti_ev_prodidx_r)
                   1027: #define        TI_CDRTNPRODOFF         TI_CDOFF(ti_return_prodidx_r)
                   1028: #define        TI_CDTXCONSOFF          TI_CDOFF(ti_tx_considx_r)
                   1029: #define        TI_CDGIBOFF             TI_CDOFF(ti_info)
                   1030: #define        TI_CDSTATSOFF           TI_CDOFF(ti_info.ti_stats)
                   1031:
1.1       drochner 1032: /*
                   1033:  * Mbuf pointers. We need these to keep track of the virtual addresses
                   1034:  * of our mbuf chains since we can only convert from physical to virtual,
                   1035:  * not the other way around.
                   1036:  */
                   1037: struct ti_chain_data {
                   1038:        struct mbuf             *ti_tx_chain[TI_TX_RING_CNT];
                   1039:        struct mbuf             *ti_rx_std_chain[TI_STD_RX_RING_CNT];
                   1040:        struct mbuf             *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT];
                   1041:        struct mbuf             *ti_rx_mini_chain[TI_MINI_RX_RING_CNT];
                   1042:        /* Stick the jumbo mem management stuff here too. */
1.18      christos 1043:        void *                  ti_jslots[TI_JSLOTS];
1.1       drochner 1044:        void                    *ti_jumbo_buf;
                   1045: };
                   1046:
                   1047: struct ti_type {
1.28      msaitoh  1048:        uint16_t                ti_vid;
                   1049:        uint16_t                ti_did;
1.16      christos 1050:        const char              *ti_name;
1.1       drochner 1051: };
                   1052:
                   1053: #define TI_HWREV_TIGON         0x01
                   1054: #define TI_HWREV_TIGON_II      0x02
                   1055: #define TI_TIMEOUT             1000
                   1056: #define TI_TXCONS_UNSET                0xFFFF  /* impossible value */
                   1057:
                   1058: struct ti_mc_entry {
                   1059:        struct ether_addr               mc_addr;
                   1060:        SIMPLEQ_ENTRY(ti_mc_entry)      mc_entries;
                   1061: };
                   1062:
                   1063: struct ti_jpool_entry {
                   1064:        int                             slot;
                   1065:        SIMPLEQ_ENTRY(ti_jpool_entry)   jpool_entries;
                   1066: };
                   1067:
                   1068: struct txdmamap_pool_entry {
                   1069:        bus_dmamap_t dmamap;
                   1070:        SIMPLEQ_ENTRY(txdmamap_pool_entry) link;
                   1071: };
                   1072:
                   1073: struct ti_softc {
1.20      chs      1074:        device_t sc_dev;
1.1       drochner 1075:        struct ethercom         ethercom;       /* interface info */
                   1076:        bus_space_handle_t      ti_bhandle;
                   1077:        char                    *ti_vhandle;
                   1078:        bus_space_tag_t         ti_btag;
                   1079:        void                    *ti_intrhand;
1.7       thorpej  1080:
1.1       drochner 1081:        struct ifmedia          ifmedia;        /* media info */
1.7       thorpej  1082:
1.28      msaitoh  1083:        uint8_t                 ti_hwrev;       /* Tigon rev (1 or 2) */
                   1084:        uint8_t                 ti_copper;      /* 1000baseT card */
                   1085:        uint8_t                 ti_linkstat;    /* Link state */
1.1       drochner 1086:        struct ti_ring_data     *ti_rdata;      /* rings */
                   1087: #define ti_ev_prodidx          ti_rdata->ti_ev_prodidx_r
                   1088: #define ti_return_prodidx      ti_rdata->ti_return_prodidx_r
                   1089: #define ti_tx_considx          ti_rdata->ti_tx_considx_r
1.7       thorpej  1090:
                   1091:        struct ti_tx_desc       *ti_tx_ring_nic;/* pointer to shared mem */
                   1092:
                   1093:        struct ti_chain_data    ti_cdata;       /* mbufs */
                   1094:
1.23      thorpej  1095:        uint64_t                ti_if_collisions;
                   1096:
1.7       thorpej  1097:        /*
                   1098:         * Function pointers to deal with Tigon 1 vs. Tigon 2 differences.
                   1099:         */
                   1100:        int                     (*sc_tx_encap)(struct ti_softc *,
                   1101:                                    struct mbuf *, uint32_t *);
1.8       thorpej  1102:        void                    (*sc_tx_eof)(struct ti_softc *);
1.7       thorpej  1103:
1.28      msaitoh  1104:        uint16_t                ti_tx_saved_considx;
                   1105:        uint16_t                ti_rx_saved_considx;
                   1106:        uint16_t                ti_ev_saved_considx;
                   1107:        uint16_t                ti_cmd_saved_prodidx;
                   1108:        uint16_t                ti_std;         /* current std ring head */
                   1109:        uint16_t                ti_mini;        /* current mini ring head */
                   1110:        uint16_t                ti_jumbo;       /* current jumo ring head */
1.1       drochner 1111:        SIMPLEQ_HEAD(, ti_mc_entry)     ti_mc_listhead;
                   1112:        SIMPLEQ_HEAD(, ti_jpool_entry)  ti_jfree_listhead;
                   1113:        SIMPLEQ_HEAD(, ti_jpool_entry)  ti_jinuse_listhead;
1.28      msaitoh  1114:        uint32_t                ti_stat_ticks;
                   1115:        uint32_t                ti_rx_coal_ticks;
                   1116:        uint32_t                ti_tx_coal_ticks;
                   1117:        uint32_t                ti_rx_max_coal_bds;
                   1118:        uint32_t                ti_tx_max_coal_bds;
                   1119:        uint32_t                ti_tx_buf_ratio;
1.22      msaitoh  1120:        u_short                 ti_if_flags;
1.1       drochner 1121:        int                     ti_txcnt;
                   1122:        void *sc_ih;
                   1123:        bus_dma_tag_t sc_dmat;
                   1124:        bus_dmamap_t info_dmamap; /* holds ti_rdata */
1.28      msaitoh  1125:        uint32_t info_dmaaddr; /* XXX 64-bit PCI addresses? */
1.1       drochner 1126:        bus_dmamap_t jumbo_dmamap;
1.28      msaitoh  1127:        uint32_t jumbo_dmaaddr; /* XXX 64-bit PCI addresses? */
1.1       drochner 1128:        bus_dmamap_t mini_dmamap[TI_MINI_RX_RING_CNT];
                   1129:        bus_dmamap_t std_dmamap[TI_STD_RX_RING_CNT];
                   1130:        SIMPLEQ_HEAD(, txdmamap_pool_entry) txdma_list;
                   1131:        struct txdmamap_pool_entry *txdma[TI_TX_RING_CNT];
                   1132: };
1.9       thorpej  1133:
                   1134: #define        TI_CDRXSTDADDR(sc, x)   ((sc)->info_dmaaddr + TI_CDRXSTDOFF((x)))
                   1135: #define        TI_CDRXJUMBOADDR(sc, x) ((sc)->info_dmaaddr + TI_CDRXJUMBOOFF((x)))
                   1136: #define        TI_CDRXMINIADDR(sc, x)  ((sc)->info_dmaaddr + TI_CDRXMINIOFF((x)))
                   1137: #define        TI_CDRXRTNADDR(sc, x)   ((sc)->info_dmaaddr + TI_CDRXRTNOFF((x)))
                   1138: #define        TI_CDEVENTADDR(sc, x)   ((sc)->info_dmaaddr + TI_CDEVENTOFF((x)))
                   1139: #define        TI_CDTXADDR(sc, x)      ((sc)->info_dmaaddr + TI_CDTXOFF((x)))
                   1140: #define        TI_CDEVPRODADDR(sc)     ((sc)->info_dmaaddr + TI_CDEVPRODOFF)
                   1141: #define        TI_CDRTNPRODADDR(sc)    ((sc)->info_dmaaddr + TI_CDRTNPRODOFF)
                   1142: #define        TI_CDTXCONSADDR(sc)     ((sc)->info_dmaaddr + TI_CDTXCONSOFF)
                   1143: #define        TI_CDGIBADDR(sc)        ((sc)->info_dmaaddr + TI_CDGIBOFF)
                   1144: #define        TI_CDSTATSADDR(sc)      ((sc)->info_dmaaddr + TI_CDSTATSOFF)
1.10      thorpej  1145:
                   1146: #define        TI_CDRXSTDSYNC(sc, x, ops)                                      \
                   1147:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1148:            TI_CDRXSTDOFF((x)), sizeof(struct ti_rx_desc), (ops))
                   1149:
                   1150: #define        TI_CDRXJUMBOSYNC(sc, x, ops)                                    \
                   1151:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1152:            TI_CDRXJUMBOOFF((x)), sizeof(struct ti_rx_desc), (ops))
                   1153:
                   1154: #define        TI_CDRXMINISYNC(sc, x, ops)                                     \
                   1155:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1156:            TI_CDRXMINIOFF((x)), sizeof(struct ti_rx_desc), (ops))
                   1157:
                   1158: #define        TI_CDRXRTNSYNC(sc, x, ops)                                      \
                   1159:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1160:            TI_CDRXRTNOFF((x)), sizeof(struct ti_rx_desc), (ops))
                   1161:
                   1162: #define        TI_CDEVENTSYNC(sc, x, ops)                                      \
                   1163:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1164:            TI_CDEVENTOFF((x)), sizeof(struct ti_event_desc), (ops))
                   1165:
                   1166: #define        TI_CDTXSYNC(sc, x, n, ops)                                      \
                   1167: do {                                                                   \
                   1168:        int __x, __n;                                                   \
                   1169:                                                                        \
                   1170:        __x = (x);                                                      \
                   1171:        __n = (n);                                                      \
                   1172:                                                                        \
                   1173:        /* If it will wrap around, sync to the end of the ring. */      \
                   1174:        if ((__x + __n) > TI_TX_RING_CNT) {                             \
                   1175:                bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,       \
                   1176:                    TI_CDTXOFF(__x), sizeof(struct ti_tx_desc) *        \
                   1177:                    (TI_TX_RING_CNT - __x), (ops));                     \
                   1178:                __n -= (TI_TX_RING_CNT - __x);                          \
                   1179:                __x = 0;                                                \
                   1180:        }                                                               \
                   1181:                                                                        \
                   1182:        /* Now sync whatever is left. */                                \
                   1183:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1184:            TI_CDTXOFF(__x), sizeof(struct ti_tx_desc) * (__n), (ops)); \
                   1185: } while (/*CONSTCOND*/0)
                   1186:
                   1187: #define        TI_CEVPRODSYNC(sc, ops)                                         \
                   1188:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1189:            TI_CDEVPRODOFF, sizeof(struct ti_producer), (ops))
                   1190:
                   1191: #define        TI_CDRTNPRODSYNC(sc, ops)                                       \
                   1192:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1193:            TI_CDRTNPRODOFF, sizeof(struct ti_producer), (ops))
                   1194:
                   1195: #define        TI_CDTXCONSSYNC(sc, ops)                                        \
                   1196:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1197:            TI_CDTXCONSOFF, sizeof(struct ti_producer), (ops))
                   1198:
                   1199: #define        TI_CDGIBSYNC(sc, ops)                                           \
                   1200:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1201:            TI_CDGIBOFF, sizeof(struct ti_gib), (ops))
                   1202:
                   1203: #define        TI_CDSTATSSYNC(sc, ops)                                         \
                   1204:        bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap,               \
                   1205:            TI_CDSTATSOFF, sizeof(struct ti_stats), (ops))
1.1       drochner 1206:
                   1207: /*
                   1208:  * Microchip Technology 24Cxx EEPROM control bytes
                   1209:  */
                   1210: #define EEPROM_CTL_READ                        0xA1    /* 0101 0001 */
                   1211: #define EEPROM_CTL_WRITE               0xA0    /* 0101 0000 */
                   1212:
                   1213: /*
                   1214:  * Note that EEPROM_START leaves transmission enabled.
                   1215:  */
1.19      tnn      1216: #define EEPROM_START() do {                                            \
1.1       drochner 1217:        TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\
                   1218:        TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */       \
                   1219:        TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\
                   1220:        TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\
1.19      tnn      1221:        TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */     \
                   1222: } while(0)
1.1       drochner 1223:
                   1224: /*
                   1225:  * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
                   1226:  * that no further data can be written to the EEPROM I/O pin.
                   1227:  */
1.19      tnn      1228: #define EEPROM_STOP()  do {                                                    \
1.1       drochner 1229:        TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */    \
                   1230:        TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */  \
                   1231:        TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */  \
                   1232:        TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */     \
                   1233:        TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */        \
                   1234:        TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */   \
1.19      tnn      1235:        TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \
                   1236: } while(0)

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