Annotation of src/sys/dev/pci/if_sip.c, Revision 1.17
1.17 ! thorpej 1: /* $NetBSD: if_sip.c,v 1.16 2000/10/01 23:32:43 thorpej Exp $ */
1.1 thorpej 2:
3: /*-
4: * Copyright (c) 1999 Network Computer, Inc.
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. Neither the name of Network Computer, Inc. nor the names of its
16: * contributors may be used to endorse or promote products derived
17: * from this software without specific prior written permission.
18: *
19: * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
20: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29: * POSSIBILITY OF SUCH DAMAGE.
30: */
31:
32: /*
1.5 thorpej 33: * Device driver for the Silicon Integrated Systems SiS 900 and
34: * SiS 7016 10/100 PCI Ethernet controllers.
1.1 thorpej 35: *
36: * Written by Jason R. Thorpe for Network Computer, Inc.
37: */
38:
39: #include "opt_inet.h"
40: #include "opt_ns.h"
41: #include "bpfilter.h"
42:
43: #include <sys/param.h>
44: #include <sys/systm.h>
1.9 thorpej 45: #include <sys/callout.h>
1.1 thorpej 46: #include <sys/mbuf.h>
47: #include <sys/malloc.h>
48: #include <sys/kernel.h>
49: #include <sys/socket.h>
50: #include <sys/ioctl.h>
51: #include <sys/errno.h>
52: #include <sys/device.h>
53: #include <sys/queue.h>
54:
1.12 mrg 55: #include <uvm/uvm_extern.h> /* for PAGE_SIZE */
1.1 thorpej 56:
57: #include <net/if.h>
58: #include <net/if_dl.h>
59: #include <net/if_media.h>
60: #include <net/if_ether.h>
61:
62: #if NBPFILTER > 0
63: #include <net/bpf.h>
64: #endif
65:
66: #ifdef INET
67: #include <netinet/in.h>
68: #include <netinet/if_inarp.h>
69: #endif
70:
71: #ifdef NS
72: #include <netns/ns.h>
73: #include <netns/ns_if.h>
74: #endif
75:
76: #include <machine/bus.h>
77: #include <machine/intr.h>
1.14 tsutsui 78: #include <machine/endian.h>
1.1 thorpej 79:
1.15 thorpej 80: #include <dev/mii/mii.h>
1.1 thorpej 81: #include <dev/mii/miivar.h>
82:
83: #include <dev/pci/pcireg.h>
84: #include <dev/pci/pcivar.h>
85: #include <dev/pci/pcidevs.h>
86:
87: #include <dev/pci/if_sipreg.h>
88:
89: /*
90: * Transmit descriptor list size. This is arbitrary, but allocate
91: * enough descriptors for 64 pending transmissions, and 16 segments
92: * per packet. This MUST work out to a power of 2.
93: */
94: #define SIP_NTXSEGS 16
95:
96: #define SIP_TXQUEUELEN 64
97: #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS)
98: #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1)
99: #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK)
100:
101: /*
102: * Receive descriptor list size. We have one Rx buffer per incoming
103: * packet, so this logic is a little simpler.
104: */
105: #define SIP_NRXDESC 64
106: #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1)
107: #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK)
108:
109: /*
110: * Control structures are DMA'd to the SiS900 chip. We allocate them in
111: * a single clump that maps to a single DMA segment to make several things
112: * easier.
113: */
114: struct sip_control_data {
115: /*
116: * The transmit descriptors.
117: */
118: struct sip_desc scd_txdescs[SIP_NTXDESC];
119:
120: /*
121: * The receive descriptors.
122: */
123: struct sip_desc scd_rxdescs[SIP_NRXDESC];
124: };
125:
126: #define SIP_CDOFF(x) offsetof(struct sip_control_data, x)
127: #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)])
128: #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)])
129:
130: /*
131: * Software state for transmit jobs.
132: */
133: struct sip_txsoft {
134: struct mbuf *txs_mbuf; /* head of our mbuf chain */
135: bus_dmamap_t txs_dmamap; /* our DMA map */
136: int txs_firstdesc; /* first descriptor in packet */
137: int txs_lastdesc; /* last descriptor in packet */
138: SIMPLEQ_ENTRY(sip_txsoft) txs_q;
139: };
140:
141: SIMPLEQ_HEAD(sip_txsq, sip_txsoft);
142:
143: /*
144: * Software state for receive jobs.
145: */
146: struct sip_rxsoft {
147: struct mbuf *rxs_mbuf; /* head of our mbuf chain */
148: bus_dmamap_t rxs_dmamap; /* our DMA map */
149: };
150:
151: /*
152: * Software state per device.
153: */
154: struct sip_softc {
155: struct device sc_dev; /* generic device information */
156: bus_space_tag_t sc_st; /* bus space tag */
157: bus_space_handle_t sc_sh; /* bus space handle */
158: bus_dma_tag_t sc_dmat; /* bus DMA tag */
159: struct ethercom sc_ethercom; /* ethernet common data */
160: void *sc_sdhook; /* shutdown hook */
1.15 thorpej 161:
162: const struct sip_product *sc_model; /* which model are we? */
1.1 thorpej 163:
164: void *sc_ih; /* interrupt cookie */
165:
166: struct mii_data sc_mii; /* MII/media information */
167:
1.9 thorpej 168: struct callout sc_tick_ch; /* tick callout */
169:
1.1 thorpej 170: bus_dmamap_t sc_cddmamap; /* control data DMA map */
171: #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
172:
173: /*
174: * Software state for transmit and receive descriptors.
175: */
176: struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN];
177: struct sip_rxsoft sc_rxsoft[SIP_NRXDESC];
178:
179: /*
180: * Control data structures.
181: */
182: struct sip_control_data *sc_control_data;
183: #define sc_txdescs sc_control_data->scd_txdescs
184: #define sc_rxdescs sc_control_data->scd_rxdescs
185:
186: u_int32_t sc_txcfg; /* prototype TXCFG register */
187: u_int32_t sc_rxcfg; /* prototype RXCFG register */
188: u_int32_t sc_imr; /* prototype IMR register */
189: u_int32_t sc_rfcr; /* prototype RFCR register */
190:
191: u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */
192: u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */
193:
194: u_int32_t sc_rx_drain_thresh; /* receive drain threshold */
195:
196: int sc_flags; /* misc. flags; see below */
197:
198: int sc_txfree; /* number of free Tx descriptors */
199: int sc_txnext; /* next ready Tx descriptor */
200:
201: struct sip_txsq sc_txfreeq; /* free Tx descsofts */
202: struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */
203:
204: int sc_rxptr; /* next ready Rx descriptor/descsoft */
205: };
206:
207: /* sc_flags */
208: #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */
209:
210: #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x)))
211: #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x)))
212:
213: #define SIP_CDTXSYNC(sc, x, n, ops) \
214: do { \
215: int __x, __n; \
216: \
217: __x = (x); \
218: __n = (n); \
219: \
220: /* If it will wrap around, sync to the end of the ring. */ \
221: if ((__x + __n) > SIP_NTXDESC) { \
222: bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
223: SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \
224: (SIP_NTXDESC - __x), (ops)); \
225: __n -= (SIP_NTXDESC - __x); \
226: __x = 0; \
227: } \
228: \
229: /* Now sync whatever is left. */ \
230: bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
231: SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \
232: } while (0)
233:
234: #define SIP_CDRXSYNC(sc, x, ops) \
235: bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
236: SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops))
237:
238: /*
239: * Note we rely on MCLBYTES being a power of two below.
240: */
241: #define SIP_INIT_RXDESC(sc, x) \
242: do { \
243: struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \
244: struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \
245: \
1.15 thorpej 246: __sipd->sipd_link = htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \
247: __sipd->sipd_bufptr = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \
1.14 tsutsui 248: __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \
249: ((MCLBYTES - 1) & CMDSTS_SIZE_MASK)); \
1.1 thorpej 250: SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
251: } while (0)
252:
1.14 tsutsui 253: #define SIP_TIMEOUT 1000
254:
1.1 thorpej 255: void sip_start __P((struct ifnet *));
256: void sip_watchdog __P((struct ifnet *));
257: int sip_ioctl __P((struct ifnet *, u_long, caddr_t));
1.17 ! thorpej 258: int sip_init __P((struct ifnet *));
! 259: void sip_stop __P((struct ifnet *, int));
1.1 thorpej 260:
261: void sip_shutdown __P((void *));
262:
263: void sip_reset __P((struct sip_softc *));
1.2 thorpej 264: void sip_rxdrain __P((struct sip_softc *));
1.1 thorpej 265: int sip_add_rxbuf __P((struct sip_softc *, int));
266: void sip_read_eeprom __P((struct sip_softc *, int, int, u_int16_t *));
267: void sip_tick __P((void *));
268:
1.15 thorpej 269: void sip_sis900_set_filter __P((struct sip_softc *));
270: void sip_dp83815_set_filter __P((struct sip_softc *));
271:
1.1 thorpej 272: int sip_intr __P((void *));
273: void sip_txintr __P((struct sip_softc *));
274: void sip_rxintr __P((struct sip_softc *));
275:
1.15 thorpej 276: int sip_sis900_mii_readreg __P((struct device *, int, int));
277: void sip_sis900_mii_writereg __P((struct device *, int, int, int));
278: void sip_sis900_mii_statchg __P((struct device *));
279:
280: int sip_dp83815_mii_readreg __P((struct device *, int, int));
281: void sip_dp83815_mii_writereg __P((struct device *, int, int, int));
282: void sip_dp83815_mii_statchg __P((struct device *));
1.1 thorpej 283:
284: int sip_mediachange __P((struct ifnet *));
285: void sip_mediastatus __P((struct ifnet *, struct ifmediareq *));
286:
287: int sip_match __P((struct device *, struct cfdata *, void *));
288: void sip_attach __P((struct device *, struct device *, void *));
289:
1.2 thorpej 290: int sip_copy_small = 0;
291:
1.1 thorpej 292: struct cfattach sip_ca = {
293: sizeof(struct sip_softc), sip_match, sip_attach,
294: };
295:
1.15 thorpej 296: /*
297: * Descriptions of the variants of the SiS900.
298: */
299: struct sip_variant {
300: int (*sipv_mii_readreg) __P((struct device *, int, int));
301: void (*sipv_mii_writereg) __P((struct device *, int, int, int));
302: void (*sipv_mii_statchg) __P((struct device *));
303: void (*sipv_set_filter) __P((struct sip_softc *));
304: };
305:
306: const struct sip_variant sip_variant_sis900 = {
307: sip_sis900_mii_readreg, sip_sis900_mii_writereg,
308: sip_sis900_mii_statchg, sip_sis900_set_filter
309: };
310:
311: const struct sip_variant sip_variant_dp83815 = {
312: sip_dp83815_mii_readreg, sip_dp83815_mii_writereg,
313: sip_dp83815_mii_statchg, sip_dp83815_set_filter
314: };
315:
316: /*
317: * Devices supported by this driver.
318: */
319: const struct sip_product {
320: pci_vendor_id_t sip_vendor;
321: pci_product_id_t sip_product;
322: const char *sip_name;
323: const struct sip_variant *sip_variant;
324: } sip_products[] = {
325: { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900,
326: "SiS 900 10/100 Ethernet",
327: &sip_variant_sis900 },
328: { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016,
329: "SiS 7016 10/100 Ethernet",
330: &sip_variant_sis900 },
331:
332: { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815,
333: "NatSemi DP83815 10/100 Ethernet",
334: &sip_variant_dp83815 },
335:
336: { 0, 0,
337: NULL,
338: NULL },
339: };
340:
1.1 thorpej 341: const struct sip_product *sip_lookup __P((const struct pci_attach_args *));
342:
343: const struct sip_product *
344: sip_lookup(pa)
345: const struct pci_attach_args *pa;
346: {
347: const struct sip_product *sip;
348:
349: for (sip = sip_products; sip->sip_name != NULL; sip++) {
350: if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor &&
351: PCI_PRODUCT(pa->pa_id) == sip->sip_product)
352: return (sip);
353: }
354: return (NULL);
355: }
356:
357: int
358: sip_match(parent, cf, aux)
359: struct device *parent;
360: struct cfdata *cf;
361: void *aux;
362: {
363: struct pci_attach_args *pa = aux;
364:
365: if (sip_lookup(pa) != NULL)
366: return (1);
367:
368: return (0);
369: }
370:
371: void
372: sip_attach(parent, self, aux)
373: struct device *parent, *self;
374: void *aux;
375: {
376: struct sip_softc *sc = (struct sip_softc *) self;
377: struct pci_attach_args *pa = aux;
378: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
379: pci_chipset_tag_t pc = pa->pa_pc;
380: pci_intr_handle_t ih;
381: const char *intrstr = NULL;
382: bus_space_tag_t iot, memt;
383: bus_space_handle_t ioh, memh;
384: bus_dma_segment_t seg;
385: int ioh_valid, memh_valid;
386: int i, rseg, error;
387: const struct sip_product *sip;
388: pcireg_t pmode;
1.14 tsutsui 389: u_int16_t myea[ETHER_ADDR_LEN / 2];
390: u_int8_t enaddr[ETHER_ADDR_LEN];
1.10 mycroft 391: int pmreg;
1.1 thorpej 392:
1.9 thorpej 393: callout_init(&sc->sc_tick_ch);
394:
1.1 thorpej 395: sip = sip_lookup(pa);
396: if (sip == NULL) {
397: printf("\n");
398: panic("sip_attach: impossible");
399: }
400:
401: printf(": %s\n", sip->sip_name);
402:
1.15 thorpej 403: sc->sc_model = sip;
1.5 thorpej 404:
1.1 thorpej 405: /*
406: * Map the device.
407: */
408: ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA,
409: PCI_MAPREG_TYPE_IO, 0,
410: &iot, &ioh, NULL, NULL) == 0);
411: memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA,
412: PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
413: &memt, &memh, NULL, NULL) == 0);
414:
415: if (memh_valid) {
416: sc->sc_st = memt;
417: sc->sc_sh = memh;
418: } else if (ioh_valid) {
419: sc->sc_st = iot;
420: sc->sc_sh = ioh;
421: } else {
422: printf("%s: unable to map device registers\n",
423: sc->sc_dev.dv_xname);
424: return;
425: }
426:
427: sc->sc_dmat = pa->pa_dmat;
428:
429: /* Enable bus mastering. */
430: pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
431: pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
432: PCI_COMMAND_MASTER_ENABLE);
433:
434: /* Get it out of power save mode if needed. */
1.10 mycroft 435: if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
436: pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3;
1.1 thorpej 437: if (pmode == 3) {
438: /*
439: * The card has lost all configuration data in
440: * this state, so punt.
441: */
442: printf("%s: unable to wake up from power state D3\n",
443: sc->sc_dev.dv_xname);
444: return;
445: }
446: if (pmode != 0) {
447: printf("%s: waking up from power state D%d\n",
448: sc->sc_dev.dv_xname, pmode);
1.10 mycroft 449: pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0);
1.1 thorpej 450: }
451: }
452:
453: /*
454: * Map and establish our interrupt.
455: */
456: if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
457: pa->pa_intrline, &ih)) {
458: printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname);
459: return;
460: }
461: intrstr = pci_intr_string(pc, ih);
462: sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sip_intr, sc);
463: if (sc->sc_ih == NULL) {
464: printf("%s: unable to establish interrupt",
465: sc->sc_dev.dv_xname);
466: if (intrstr != NULL)
467: printf(" at %s", intrstr);
468: printf("\n");
469: return;
470: }
471: printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
472:
473: SIMPLEQ_INIT(&sc->sc_txfreeq);
474: SIMPLEQ_INIT(&sc->sc_txdirtyq);
475:
476: /*
477: * Allocate the control data structures, and create and load the
478: * DMA map for it.
479: */
480: if ((error = bus_dmamem_alloc(sc->sc_dmat,
481: sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
482: 0)) != 0) {
483: printf("%s: unable to allocate control data, error = %d\n",
484: sc->sc_dev.dv_xname, error);
485: goto fail_0;
486: }
487:
488: if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
489: sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data,
490: BUS_DMA_COHERENT)) != 0) {
491: printf("%s: unable to map control data, error = %d\n",
492: sc->sc_dev.dv_xname, error);
493: goto fail_1;
494: }
495:
496: if ((error = bus_dmamap_create(sc->sc_dmat,
497: sizeof(struct sip_control_data), 1,
498: sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
499: printf("%s: unable to create control data DMA map, "
500: "error = %d\n", sc->sc_dev.dv_xname, error);
501: goto fail_2;
502: }
503:
504: if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
505: sc->sc_control_data, sizeof(struct sip_control_data), NULL,
506: 0)) != 0) {
507: printf("%s: unable to load control data DMA map, error = %d\n",
508: sc->sc_dev.dv_xname, error);
509: goto fail_3;
510: }
511:
512: /*
513: * Create the transmit buffer DMA maps.
514: */
515: for (i = 0; i < SIP_TXQUEUELEN; i++) {
516: if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
517: SIP_NTXSEGS, MCLBYTES, 0, 0,
518: &sc->sc_txsoft[i].txs_dmamap)) != 0) {
519: printf("%s: unable to create tx DMA map %d, "
520: "error = %d\n", sc->sc_dev.dv_xname, i, error);
521: goto fail_4;
522: }
523: }
524:
525: /*
526: * Create the receive buffer DMA maps.
527: */
528: for (i = 0; i < SIP_NRXDESC; i++) {
529: if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
530: MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
531: printf("%s: unable to create rx DMA map %d, "
532: "error = %d\n", sc->sc_dev.dv_xname, i, error);
533: goto fail_5;
534: }
1.2 thorpej 535: sc->sc_rxsoft[i].rxs_mbuf = NULL;
1.1 thorpej 536: }
537:
538: /*
539: * Reset the chip to a known state.
540: */
541: sip_reset(sc);
542:
543: /*
544: * Read the Ethernet address from the EEPROM.
545: */
546: sip_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1,
1.14 tsutsui 547: sizeof(myea) / sizeof(myea[0]), myea);
548:
549: enaddr[0] = myea[0] & 0xff;
550: enaddr[1] = myea[0] >> 8;
551: enaddr[2] = myea[1] & 0xff;
552: enaddr[3] = myea[1] >> 8;
553: enaddr[4] = myea[2] & 0xff;
554: enaddr[5] = myea[2] >> 8;
1.1 thorpej 555:
556: printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
1.14 tsutsui 557: ether_sprintf(enaddr));
1.1 thorpej 558:
559: /*
560: * Initialize our media structures and probe the MII.
561: */
562: sc->sc_mii.mii_ifp = ifp;
1.15 thorpej 563: sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg;
564: sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg;
565: sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg;
1.1 thorpej 566: ifmedia_init(&sc->sc_mii.mii_media, 0, sip_mediachange,
567: sip_mediastatus);
1.6 thorpej 568: mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1.7 thorpej 569: MII_OFFSET_ANY, 0);
1.1 thorpej 570: if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
571: ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
572: ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
573: } else
574: ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
575:
576: ifp = &sc->sc_ethercom.ec_if;
577: strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
578: ifp->if_softc = sc;
579: ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
580: ifp->if_ioctl = sip_ioctl;
581: ifp->if_start = sip_start;
582: ifp->if_watchdog = sip_watchdog;
1.17 ! thorpej 583: ifp->if_init = sip_init;
! 584: ifp->if_stop = sip_stop;
1.1 thorpej 585:
586: /*
587: * Attach the interface.
588: */
589: if_attach(ifp);
1.14 tsutsui 590: ether_ifattach(ifp, enaddr);
1.1 thorpej 591: #if NBPFILTER > 0
592: bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB,
593: sizeof(struct ether_header));
594: #endif
595:
596: /*
597: * Make sure the interface is shutdown during reboot.
598: */
599: sc->sc_sdhook = shutdownhook_establish(sip_shutdown, sc);
600: if (sc->sc_sdhook == NULL)
601: printf("%s: WARNING: unable to establish shutdown hook\n",
602: sc->sc_dev.dv_xname);
603: return;
604:
605: /*
606: * Free any resources we've allocated during the failed attach
607: * attempt. Do this in reverse order and fall through.
608: */
609: fail_5:
610: for (i = 0; i < SIP_NRXDESC; i++) {
611: if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
612: bus_dmamap_destroy(sc->sc_dmat,
613: sc->sc_rxsoft[i].rxs_dmamap);
614: }
615: fail_4:
616: for (i = 0; i < SIP_TXQUEUELEN; i++) {
617: if (sc->sc_txsoft[i].txs_dmamap != NULL)
618: bus_dmamap_destroy(sc->sc_dmat,
619: sc->sc_txsoft[i].txs_dmamap);
620: }
621: bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
622: fail_3:
623: bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
624: fail_2:
625: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
626: sizeof(struct sip_control_data));
627: fail_1:
628: bus_dmamem_free(sc->sc_dmat, &seg, rseg);
629: fail_0:
630: return;
631: }
632:
633: /*
634: * sip_shutdown:
635: *
636: * Make sure the interface is stopped at reboot time.
637: */
638: void
639: sip_shutdown(arg)
640: void *arg;
641: {
642: struct sip_softc *sc = arg;
643:
1.17 ! thorpej 644: sip_stop(&sc->sc_ethercom.ec_if, 1);
1.1 thorpej 645: }
646:
647: /*
648: * sip_start: [ifnet interface function]
649: *
650: * Start packet transmission on the interface.
651: */
652: void
653: sip_start(ifp)
654: struct ifnet *ifp;
655: {
656: struct sip_softc *sc = ifp->if_softc;
657: struct mbuf *m0, *m;
658: struct sip_txsoft *txs;
659: bus_dmamap_t dmamap;
660: int error, firsttx, nexttx, lasttx, ofree, seg;
661:
662: /*
663: * If we've been told to pause, don't transmit any more packets.
664: */
665: if (sc->sc_flags & SIPF_PAUSED)
666: ifp->if_flags |= IFF_OACTIVE;
667:
668: if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
669: return;
670:
671: /*
672: * Remember the previous number of free descriptors and
673: * the first descriptor we'll use.
674: */
675: ofree = sc->sc_txfree;
676: firsttx = sc->sc_txnext;
677:
678: /*
679: * Loop through the send queue, setting up transmit descriptors
680: * until we drain the queue, or use up all available transmit
681: * descriptors.
682: */
683: while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL &&
684: sc->sc_txfree != 0) {
685: /*
686: * Grab a packet off the queue.
687: */
688: IF_DEQUEUE(&ifp->if_snd, m0);
689: if (m0 == NULL)
690: break;
691:
692: dmamap = txs->txs_dmamap;
693:
694: /*
695: * Load the DMA map. If this fails, the packet either
696: * didn't fit in the alloted number of segments, or we
697: * were short on resources. In this case, we'll copy
698: * and try again.
699: */
700: if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
701: BUS_DMA_NOWAIT) != 0) {
702: MGETHDR(m, M_DONTWAIT, MT_DATA);
703: if (m == NULL) {
704: printf("%s: unable to allocate Tx mbuf\n",
705: sc->sc_dev.dv_xname);
706: IF_PREPEND(&ifp->if_snd, m0);
707: break;
708: }
709: if (m0->m_pkthdr.len > MHLEN) {
710: MCLGET(m, M_DONTWAIT);
711: if ((m->m_flags & M_EXT) == 0) {
712: printf("%s: unable to allocate Tx "
713: "cluster\n", sc->sc_dev.dv_xname);
714: m_freem(m);
715: IF_PREPEND(&ifp->if_snd, m0);
716: break;
717: }
718: }
719: m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
720: m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
721: m_freem(m0);
722: m0 = m;
723: error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
724: m0, BUS_DMA_NOWAIT);
725: if (error) {
726: printf("%s: unable to load Tx buffer, "
727: "error = %d\n", sc->sc_dev.dv_xname, error);
728: IF_PREPEND(&ifp->if_snd, m0);
729: break;
730: }
731: }
732:
733: /*
734: * Ensure we have enough descriptors free to describe
735: * the packet.
736: */
737: if (dmamap->dm_nsegs > sc->sc_txfree) {
738: /*
739: * Not enough free descriptors to transmit this
740: * packet. We haven't committed anything yet,
741: * so just unload the DMA map, put the packet
742: * back on the queue, and punt. Notify the upper
743: * layer that there are not more slots left.
744: *
745: * XXX We could allocate an mbuf and copy, but
746: * XXX is it worth it?
747: */
748: ifp->if_flags |= IFF_OACTIVE;
749: bus_dmamap_unload(sc->sc_dmat, dmamap);
750: IF_PREPEND(&ifp->if_snd, m0);
751: break;
752: }
753:
754: /*
755: * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
756: */
757:
758: /* Sync the DMA map. */
759: bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
760: BUS_DMASYNC_PREWRITE);
761:
762: /*
763: * Initialize the transmit descriptors.
764: */
765: for (nexttx = sc->sc_txnext, seg = 0;
766: seg < dmamap->dm_nsegs;
767: seg++, nexttx = SIP_NEXTTX(nexttx)) {
768: /*
769: * If this is the first descriptor we're
770: * enqueueing, don't set the OWN bit just
771: * yet. That could cause a race condition.
772: * We'll do it below.
773: */
774: sc->sc_txdescs[nexttx].sipd_bufptr =
1.14 tsutsui 775: htole32(dmamap->dm_segs[seg].ds_addr);
1.1 thorpej 776: sc->sc_txdescs[nexttx].sipd_cmdsts =
1.14 tsutsui 777: htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) |
778: CMDSTS_MORE | dmamap->dm_segs[seg].ds_len);
1.1 thorpej 779: lasttx = nexttx;
780: }
781:
782: /* Clear the MORE bit on the last segment. */
1.14 tsutsui 783: sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE);
1.1 thorpej 784:
785: /* Sync the descriptors we're using. */
786: SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
787: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
788:
789: /*
790: * Store a pointer to the packet so we can free it later,
791: * and remember what txdirty will be once the packet is
792: * done.
793: */
794: txs->txs_mbuf = m0;
795: txs->txs_firstdesc = sc->sc_txnext;
796: txs->txs_lastdesc = lasttx;
797:
798: /* Advance the tx pointer. */
799: sc->sc_txfree -= dmamap->dm_nsegs;
800: sc->sc_txnext = nexttx;
801:
802: SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q);
803: SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
804:
805: #if NBPFILTER > 0
806: /*
807: * Pass the packet to any BPF listeners.
808: */
809: if (ifp->if_bpf)
810: bpf_mtap(ifp->if_bpf, m0);
811: #endif /* NBPFILTER > 0 */
812: }
813:
814: if (txs == NULL || sc->sc_txfree == 0) {
815: /* No more slots left; notify upper layer. */
816: ifp->if_flags |= IFF_OACTIVE;
817: }
818:
819: if (sc->sc_txfree != ofree) {
820: /*
821: * Cause a descriptor interrupt to happen on the
822: * last packet we enqueued.
823: */
1.14 tsutsui 824: sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR);
1.1 thorpej 825: SIP_CDTXSYNC(sc, lasttx, 1,
826: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
827:
828: /*
829: * The entire packet chain is set up. Give the
830: * first descrptor to the chip now.
831: */
1.14 tsutsui 832: sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN);
1.1 thorpej 833: SIP_CDTXSYNC(sc, firsttx, 1,
834: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
835:
836: /* Start the transmit process. */
837: if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) &
838: CR_TXE) == 0) {
839: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP,
840: SIP_CDTXADDR(sc, firsttx));
841: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE);
842: }
843:
844: /* Set a watchdog timer in case the chip flakes out. */
845: ifp->if_timer = 5;
846: }
847: }
848:
849: /*
850: * sip_watchdog: [ifnet interface function]
851: *
852: * Watchdog timer handler.
853: */
854: void
855: sip_watchdog(ifp)
856: struct ifnet *ifp;
857: {
858: struct sip_softc *sc = ifp->if_softc;
859:
860: /*
861: * The chip seems to ignore the CMDSTS_INTR bit sometimes!
862: * If we get a timeout, try and sweep up transmit descriptors.
863: * If we manage to sweep them all up, ignore the lack of
864: * interrupt.
865: */
866: sip_txintr(sc);
867:
868: if (sc->sc_txfree != SIP_NTXDESC) {
869: printf("%s: device timeout\n", sc->sc_dev.dv_xname);
870: ifp->if_oerrors++;
871:
872: /* Reset the interface. */
1.17 ! thorpej 873: (void) sip_init(ifp);
1.1 thorpej 874: } else if (ifp->if_flags & IFF_DEBUG)
875: printf("%s: recovered from device timeout\n",
876: sc->sc_dev.dv_xname);
877:
878: /* Try to get more packets going. */
879: sip_start(ifp);
880: }
881:
882: /*
883: * sip_ioctl: [ifnet interface function]
884: *
885: * Handle control requests from the operator.
886: */
887: int
888: sip_ioctl(ifp, cmd, data)
889: struct ifnet *ifp;
890: u_long cmd;
891: caddr_t data;
892: {
893: struct sip_softc *sc = ifp->if_softc;
894: struct ifreq *ifr = (struct ifreq *)data;
1.17 ! thorpej 895: int s, error;
1.1 thorpej 896:
897: s = splnet();
898:
899: switch (cmd) {
1.17 ! thorpej 900: case SIOCSIFMEDIA:
! 901: case SIOCGIFMEDIA:
! 902: error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1.1 thorpej 903: break;
904:
1.17 ! thorpej 905: default:
! 906: error = ether_ioctl(ifp, cmd, data);
1.1 thorpej 907: if (error == ENETRESET) {
908: /*
909: * Multicast list has changed; set the hardware filter
910: * accordingly.
911: */
1.15 thorpej 912: (*sc->sc_model->sip_variant->sipv_set_filter)(sc);
1.1 thorpej 913: error = 0;
914: }
915: break;
916: }
917:
918: /* Try to get more packets going. */
919: sip_start(ifp);
920:
921: splx(s);
922: return (error);
923: }
924:
925: /*
926: * sip_intr:
927: *
928: * Interrupt service routine.
929: */
930: int
931: sip_intr(arg)
932: void *arg;
933: {
934: struct sip_softc *sc = arg;
935: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
936: u_int32_t isr;
937: int handled = 0;
938:
939: for (;;) {
940: /* Reading clears interrupt. */
941: isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR);
942: if ((isr & sc->sc_imr) == 0)
943: break;
944:
945: handled = 1;
946:
947: if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) {
948: /* Grab any new packets. */
949: sip_rxintr(sc);
950:
951: if (isr & ISR_RXORN) {
952: printf("%s: receive FIFO overrun\n",
953: sc->sc_dev.dv_xname);
954:
955: /* XXX adjust rx_drain_thresh? */
956: }
957:
958: if (isr & ISR_RXIDLE) {
959: printf("%s: receive ring overrun\n",
960: sc->sc_dev.dv_xname);
961:
962: /* Get the receive process going again. */
963: bus_space_write_4(sc->sc_st, sc->sc_sh,
964: SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr));
965: bus_space_write_4(sc->sc_st, sc->sc_sh,
966: SIP_CR, CR_RXE);
967: }
968: }
969:
970: if (isr & (ISR_TXURN|ISR_TXDESC)) {
971: /* Sweep up transmit descriptors. */
972: sip_txintr(sc);
973:
974: if (isr & ISR_TXURN) {
975: u_int32_t thresh;
976:
977: printf("%s: transmit FIFO underrun",
978: sc->sc_dev.dv_xname);
979:
980: thresh = sc->sc_tx_drain_thresh + 1;
981: if (thresh <= TXCFG_DRTH &&
982: (thresh * 32) <= (SIP_TXFIFO_SIZE -
983: (sc->sc_tx_fill_thresh * 32))) {
984: printf("; increasing Tx drain "
985: "threshold to %u bytes\n",
986: thresh * 32);
987: sc->sc_tx_drain_thresh = thresh;
1.17 ! thorpej 988: (void) sip_init(ifp);
1.1 thorpej 989: } else {
1.17 ! thorpej 990: (void) sip_init(ifp);
1.1 thorpej 991: printf("\n");
992: }
993: }
994: }
995:
996: if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) {
997: if (isr & ISR_PAUSE_ST) {
998: sc->sc_flags |= SIPF_PAUSED;
999: ifp->if_flags |= IFF_OACTIVE;
1000: }
1001: if (isr & ISR_PAUSE_END) {
1002: sc->sc_flags &= ~SIPF_PAUSED;
1003: ifp->if_flags &= ~IFF_OACTIVE;
1004: }
1005: }
1006:
1007: if (isr & ISR_HIBERR) {
1008: #define PRINTERR(bit, str) \
1009: if (isr & (bit)) \
1010: printf("%s: %s\n", sc->sc_dev.dv_xname, str)
1011: PRINTERR(ISR_DPERR, "parity error");
1012: PRINTERR(ISR_SSERR, "system error");
1013: PRINTERR(ISR_RMABT, "master abort");
1014: PRINTERR(ISR_RTABT, "target abort");
1015: PRINTERR(ISR_RXSOVR, "receive status FIFO overrun");
1.17 ! thorpej 1016: (void) sip_init(ifp);
1.1 thorpej 1017: #undef PRINTERR
1018: }
1019: }
1020:
1021: /* Try to get more packets going. */
1022: sip_start(ifp);
1023:
1024: return (handled);
1025: }
1026:
1027: /*
1028: * sip_txintr:
1029: *
1030: * Helper; handle transmit interrupts.
1031: */
1032: void
1033: sip_txintr(sc)
1034: struct sip_softc *sc;
1035: {
1036: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1037: struct sip_txsoft *txs;
1038: u_int32_t cmdsts;
1039:
1040: if ((sc->sc_flags & SIPF_PAUSED) == 0)
1041: ifp->if_flags &= ~IFF_OACTIVE;
1042:
1043: /*
1044: * Go through our Tx list and free mbufs for those
1045: * frames which have been transmitted.
1046: */
1047: while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1048: SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs,
1049: BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1050:
1.14 tsutsui 1051: cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts);
1.1 thorpej 1052: if (cmdsts & CMDSTS_OWN)
1053: break;
1054:
1055: SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q);
1056:
1057: sc->sc_txfree += txs->txs_dmamap->dm_nsegs;
1058:
1059: bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
1060: 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1061: bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
1062: m_freem(txs->txs_mbuf);
1063: txs->txs_mbuf = NULL;
1064:
1065: SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1066:
1067: /*
1068: * Check for errors and collisions.
1069: */
1070: if (cmdsts &
1071: (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) {
1072: if (ifp->if_flags & IFF_DEBUG) {
1073: if (CMDSTS_Tx_ED)
1074: printf("%s: excessive deferral\n",
1075: sc->sc_dev.dv_xname);
1076: if (CMDSTS_Tx_EC) {
1077: printf("%s: excessive collisions\n",
1078: sc->sc_dev.dv_xname);
1079: ifp->if_collisions += 16;
1080: }
1081: }
1082: } else {
1083: /* Packet was transmitted successfully. */
1084: ifp->if_opackets++;
1085: ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts);
1086: }
1087: }
1088:
1089: /*
1090: * If there are no more pending transmissions, cancel the watchdog
1091: * timer.
1092: */
1093: if (txs == NULL)
1094: ifp->if_timer = 0;
1095: }
1096:
1097: /*
1098: * sip_rxintr:
1099: *
1100: * Helper; handle receive interrupts.
1101: */
1102: void
1103: sip_rxintr(sc)
1104: struct sip_softc *sc;
1105: {
1106: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1107: struct sip_rxsoft *rxs;
1108: struct mbuf *m;
1109: u_int32_t cmdsts;
1110: int i, len;
1111:
1112: for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) {
1113: rxs = &sc->sc_rxsoft[i];
1114:
1115: SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1116:
1.14 tsutsui 1117: cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts);
1.1 thorpej 1118:
1119: /*
1120: * NOTE: OWN is set if owned by _consumer_. We're the
1121: * consumer of the receive ring, so if the bit is clear,
1122: * we have processed all of the packets.
1123: */
1124: if ((cmdsts & CMDSTS_OWN) == 0) {
1125: /*
1126: * We have processed all of the receive buffers.
1127: */
1128: break;
1129: }
1130:
1131: /*
1132: * If any collisions were seen on the wire, count one.
1133: */
1134: if (cmdsts & CMDSTS_Rx_COL)
1135: ifp->if_collisions++;
1136:
1137: /*
1138: * If an error occurred, update stats, clear the status
1139: * word, and leave the packet buffer in place. It will
1140: * simply be reused the next time the ring comes around.
1141: */
1142: if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT|
1143: CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) {
1144: ifp->if_ierrors++;
1145: if ((cmdsts & CMDSTS_Rx_RXA) != 0 &&
1146: (cmdsts & CMDSTS_Rx_RXO) == 0) {
1147: /* Receive overrun handled elsewhere. */
1148: printf("%s: receive descriptor error\n",
1149: sc->sc_dev.dv_xname);
1150: }
1151: #define PRINTERR(bit, str) \
1152: if (cmdsts & (bit)) \
1153: printf("%s: %s\n", sc->sc_dev.dv_xname, str)
1154: PRINTERR(CMDSTS_Rx_LONG, "packet too long");
1155: PRINTERR(CMDSTS_Rx_RUNT, "runt packet");
1156: PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error");
1157: PRINTERR(CMDSTS_Rx_CRCE, "CRC error");
1158: PRINTERR(CMDSTS_Rx_FAE, "frame alignment error");
1159: #undef PRINTERR
1160: SIP_INIT_RXDESC(sc, i);
1161: continue;
1162: }
1163:
1164: bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1165: rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1166:
1167: /*
1168: * No errors; receive the packet. Note, the SiS 900
1169: * includes the CRC with every packet; trim it.
1170: */
1171: len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN;
1172:
1173: #ifdef __NO_STRICT_ALIGNMENT
1174: /*
1.2 thorpej 1175: * If the packet is small enough to fit in a
1176: * single header mbuf, allocate one and copy
1177: * the data into it. This greatly reduces
1178: * memory consumption when we receive lots
1179: * of small packets.
1180: *
1181: * Otherwise, we add a new buffer to the receive
1182: * chain. If this fails, we drop the packet and
1183: * recycle the old buffer.
1.1 thorpej 1184: */
1.2 thorpej 1185: if (sip_copy_small != 0 && len <= MHLEN) {
1186: MGETHDR(m, M_DONTWAIT, MT_DATA);
1187: if (m == NULL)
1188: goto dropit;
1189: memcpy(mtod(m, caddr_t),
1190: mtod(rxs->rxs_mbuf, caddr_t), len);
1.1 thorpej 1191: SIP_INIT_RXDESC(sc, i);
1192: bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1.2 thorpej 1193: rxs->rxs_dmamap->dm_mapsize,
1194: BUS_DMASYNC_PREREAD);
1195: } else {
1196: m = rxs->rxs_mbuf;
1197: if (sip_add_rxbuf(sc, i) != 0) {
1198: dropit:
1199: ifp->if_ierrors++;
1200: SIP_INIT_RXDESC(sc, i);
1201: bus_dmamap_sync(sc->sc_dmat,
1202: rxs->rxs_dmamap, 0,
1203: rxs->rxs_dmamap->dm_mapsize,
1204: BUS_DMASYNC_PREREAD);
1205: continue;
1206: }
1.1 thorpej 1207: }
1208: #else
1209: /*
1210: * The SiS 900's receive buffers must be 4-byte aligned.
1211: * But this means that the data after the Ethernet header
1212: * is misaligned. We must allocate a new buffer and
1213: * copy the data, shifted forward 2 bytes.
1214: */
1215: MGETHDR(m, M_DONTWAIT, MT_DATA);
1216: if (m == NULL) {
1217: dropit:
1218: ifp->if_ierrors++;
1219: SIP_INIT_RXDESC(sc, i);
1220: bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1221: rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1222: continue;
1223: }
1224: if (len > (MHLEN - 2)) {
1225: MCLGET(m, M_DONTWAIT);
1226: if ((m->m_flags & M_EXT) == 0) {
1227: m_freem(m);
1228: goto dropit;
1229: }
1230: }
1231: m->m_data += 2;
1232:
1233: /*
1234: * Note that we use clusters for incoming frames, so the
1235: * buffer is virtually contiguous.
1236: */
1237: memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len);
1238:
1239: /* Allow the receive descriptor to continue using its mbuf. */
1240: SIP_INIT_RXDESC(sc, i);
1241: bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1242: rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1243: #endif /* __NO_STRICT_ALIGNMENT */
1244:
1245: ifp->if_ipackets++;
1246: m->m_pkthdr.rcvif = ifp;
1247: m->m_pkthdr.len = m->m_len = len;
1248:
1249: #if NBPFILTER > 0
1250: /*
1251: * Pass this up to any BPF listeners, but only
1252: * pass if up the stack if it's for us.
1253: */
1.16 thorpej 1254: if (ifp->if_bpf)
1.1 thorpej 1255: bpf_mtap(ifp->if_bpf, m);
1256: #endif /* NBPFILTER > 0 */
1257:
1258: /* Pass it on. */
1259: (*ifp->if_input)(ifp, m);
1260: }
1261:
1262: /* Update the receive pointer. */
1263: sc->sc_rxptr = i;
1264: }
1265:
1266: /*
1267: * sip_tick:
1268: *
1269: * One second timer, used to tick the MII.
1270: */
1271: void
1272: sip_tick(arg)
1273: void *arg;
1274: {
1275: struct sip_softc *sc = arg;
1276: int s;
1277:
1278: s = splnet();
1279: mii_tick(&sc->sc_mii);
1280: splx(s);
1281:
1.9 thorpej 1282: callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc);
1.1 thorpej 1283: }
1284:
1285: /*
1286: * sip_reset:
1287: *
1288: * Perform a soft reset on the SiS 900.
1289: */
1290: void
1291: sip_reset(sc)
1292: struct sip_softc *sc;
1293: {
1294: bus_space_tag_t st = sc->sc_st;
1295: bus_space_handle_t sh = sc->sc_sh;
1296: int i;
1297:
1298: bus_space_write_4(st, sh, SIP_CR, CR_RST);
1299:
1.14 tsutsui 1300: for (i = 0; i < SIP_TIMEOUT; i++) {
1301: if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0)
1302: break;
1.1 thorpej 1303: delay(2);
1304: }
1305:
1.14 tsutsui 1306: if (i == SIP_TIMEOUT)
1307: printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
1308:
1309: delay(1000);
1.1 thorpej 1310: }
1311:
1312: /*
1.17 ! thorpej 1313: * sip_init: [ ifnet interface function ]
1.1 thorpej 1314: *
1315: * Initialize the interface. Must be called at splnet().
1316: */
1.2 thorpej 1317: int
1.17 ! thorpej 1318: sip_init(ifp)
! 1319: struct ifnet *ifp;
1.1 thorpej 1320: {
1.17 ! thorpej 1321: struct sip_softc *sc = ifp->if_softc;
1.1 thorpej 1322: bus_space_tag_t st = sc->sc_st;
1323: bus_space_handle_t sh = sc->sc_sh;
1324: struct sip_txsoft *txs;
1.2 thorpej 1325: struct sip_rxsoft *rxs;
1.1 thorpej 1326: struct sip_desc *sipd;
1327: u_int32_t cfg;
1.2 thorpej 1328: int i, error = 0;
1.1 thorpej 1329:
1330: /*
1331: * Cancel any pending I/O.
1332: */
1.17 ! thorpej 1333: sip_stop(ifp, 0);
1.1 thorpej 1334:
1335: /*
1336: * Reset the chip to a known state.
1337: */
1338: sip_reset(sc);
1339:
1340: /*
1341: * Initialize the transmit descriptor ring.
1342: */
1343: for (i = 0; i < SIP_NTXDESC; i++) {
1344: sipd = &sc->sc_txdescs[i];
1345: memset(sipd, 0, sizeof(struct sip_desc));
1.14 tsutsui 1346: sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i)));
1.1 thorpej 1347: }
1348: SIP_CDTXSYNC(sc, 0, SIP_NTXDESC,
1349: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1350: sc->sc_txfree = SIP_NTXDESC;
1351: sc->sc_txnext = 0;
1352:
1353: /*
1354: * Initialize the transmit job descriptors.
1355: */
1356: SIMPLEQ_INIT(&sc->sc_txfreeq);
1357: SIMPLEQ_INIT(&sc->sc_txdirtyq);
1358: for (i = 0; i < SIP_TXQUEUELEN; i++) {
1359: txs = &sc->sc_txsoft[i];
1360: txs->txs_mbuf = NULL;
1361: SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1362: }
1363:
1364: /*
1365: * Initialize the receive descriptor and receive job
1.2 thorpej 1366: * descriptor rings.
1.1 thorpej 1367: */
1.2 thorpej 1368: for (i = 0; i < SIP_NRXDESC; i++) {
1369: rxs = &sc->sc_rxsoft[i];
1370: if (rxs->rxs_mbuf == NULL) {
1371: if ((error = sip_add_rxbuf(sc, i)) != 0) {
1372: printf("%s: unable to allocate or map rx "
1373: "buffer %d, error = %d\n",
1374: sc->sc_dev.dv_xname, i, error);
1375: /*
1376: * XXX Should attempt to run with fewer receive
1377: * XXX buffers instead of just failing.
1378: */
1379: sip_rxdrain(sc);
1380: goto out;
1381: }
1382: }
1383: }
1.1 thorpej 1384: sc->sc_rxptr = 0;
1385:
1386: /*
1387: * Initialize the configuration register: aggressive PCI
1388: * bus request algorithm, default backoff, default OW timer,
1389: * default parity error detection.
1390: */
1391: cfg = 0;
1392: #if BYTE_ORDER == BIG_ENDIAN
1393: /*
1394: * ...descriptors in big-endian mode.
1395: */
1.14 tsutsui 1396: #if 0
1397: /* "Big endian mode" does not work properly. */
1.1 thorpej 1398: cfg |= CFG_BEM;
1399: #endif
1.14 tsutsui 1400: #endif
1.1 thorpej 1401: bus_space_write_4(st, sh, SIP_CFG, cfg);
1402:
1403: /*
1404: * Initialize the transmit fill and drain thresholds if
1405: * we have never done so.
1406: */
1407: if (sc->sc_tx_fill_thresh == 0) {
1408: /*
1409: * XXX This value should be tuned. This is the
1410: * minimum (32 bytes), and we may be able to
1411: * improve performance by increasing it.
1412: */
1413: sc->sc_tx_fill_thresh = 1;
1414: }
1415: if (sc->sc_tx_drain_thresh == 0) {
1416: /*
1417: * Start at a drain threshold of 128 bytes. We will
1418: * increase it if a DMA underrun occurs.
1419: *
1420: * XXX The minimum value of this variable should be
1421: * tuned. We may be able to improve performance
1422: * by starting with a lower value. That, however,
1423: * may trash the first few outgoing packets if the
1424: * PCI bus is saturated.
1425: */
1426: sc->sc_tx_drain_thresh = 4;
1427: }
1428:
1429: /*
1430: * Initialize the prototype TXCFG register.
1431: */
1432: sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 |
1433: (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) |
1434: sc->sc_tx_drain_thresh;
1435: bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg);
1436:
1437: /*
1438: * Initialize the receive drain threshold if we have never
1439: * done so.
1440: */
1441: if (sc->sc_rx_drain_thresh == 0) {
1442: /*
1443: * XXX This value should be tuned. This is set to the
1444: * maximum of 248 bytes, and we may be able to improve
1445: * performance by decreasing it (although we should never
1446: * set this value lower than 2; 14 bytes are required to
1447: * filter the packet).
1448: */
1449: sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT;
1450: }
1451:
1452: /*
1453: * Initialize the prototype RXCFG register.
1454: */
1455: sc->sc_rxcfg = RXCFG_MXDMA_512 |
1456: (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT);
1457: bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg);
1458:
1459: /* Set up the receive filter. */
1.15 thorpej 1460: (*sc->sc_model->sip_variant->sipv_set_filter)(sc);
1.1 thorpej 1461:
1462: /*
1463: * Give the transmit and receive rings to the chip.
1464: */
1465: bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext));
1466: bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr));
1467:
1468: /*
1469: * Initialize the interrupt mask.
1470: */
1471: sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR|
1472: ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC;
1473: bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr);
1474:
1475: /*
1476: * Set the current media. Do this after initializing the prototype
1477: * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow
1478: * control.
1479: */
1480: mii_mediachg(&sc->sc_mii);
1481:
1482: /*
1483: * Enable interrupts.
1484: */
1485: bus_space_write_4(st, sh, SIP_IER, IER_IE);
1486:
1487: /*
1488: * Start the transmit and receive processes.
1489: */
1490: bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE);
1491:
1492: /*
1493: * Start the one second MII clock.
1494: */
1.9 thorpej 1495: callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc);
1.1 thorpej 1496:
1497: /*
1498: * ...all done!
1499: */
1500: ifp->if_flags |= IFF_RUNNING;
1501: ifp->if_flags &= ~IFF_OACTIVE;
1.2 thorpej 1502:
1503: out:
1504: if (error)
1505: printf("%s: interface not running\n", sc->sc_dev.dv_xname);
1506: return (error);
1507: }
1508:
1509: /*
1510: * sip_drain:
1511: *
1512: * Drain the receive queue.
1513: */
1514: void
1515: sip_rxdrain(sc)
1516: struct sip_softc *sc;
1517: {
1518: struct sip_rxsoft *rxs;
1519: int i;
1520:
1521: for (i = 0; i < SIP_NRXDESC; i++) {
1522: rxs = &sc->sc_rxsoft[i];
1523: if (rxs->rxs_mbuf != NULL) {
1524: bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1525: m_freem(rxs->rxs_mbuf);
1526: rxs->rxs_mbuf = NULL;
1527: }
1528: }
1.1 thorpej 1529: }
1530:
1531: /*
1.17 ! thorpej 1532: * sip_stop: [ ifnet interface function ]
1.1 thorpej 1533: *
1534: * Stop transmission on the interface.
1535: */
1536: void
1.17 ! thorpej 1537: sip_stop(ifp, disable)
! 1538: struct ifnet *ifp;
! 1539: int disable;
1.1 thorpej 1540: {
1.17 ! thorpej 1541: struct sip_softc *sc = ifp->if_softc;
1.1 thorpej 1542: bus_space_tag_t st = sc->sc_st;
1543: bus_space_handle_t sh = sc->sc_sh;
1544: struct sip_txsoft *txs;
1545: u_int32_t cmdsts = 0; /* DEBUG */
1546:
1547: /*
1548: * Stop the one second clock.
1549: */
1.9 thorpej 1550: callout_stop(&sc->sc_tick_ch);
1.4 thorpej 1551:
1552: /* Down the MII. */
1553: mii_down(&sc->sc_mii);
1.1 thorpej 1554:
1555: /*
1556: * Disable interrupts.
1557: */
1558: bus_space_write_4(st, sh, SIP_IER, 0);
1559:
1560: /*
1561: * Stop receiver and transmitter.
1562: */
1563: bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD);
1564:
1565: /*
1566: * Release any queued transmit buffers.
1567: */
1568: while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1569: if ((ifp->if_flags & IFF_DEBUG) != 0 &&
1570: SIMPLEQ_NEXT(txs, txs_q) == NULL &&
1.14 tsutsui 1571: (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) &
1.1 thorpej 1572: CMDSTS_INTR) == 0)
1573: printf("%s: sip_stop: last descriptor does not "
1574: "have INTR bit set\n", sc->sc_dev.dv_xname);
1575: SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q);
1576: #ifdef DIAGNOSTIC
1577: if (txs->txs_mbuf == NULL) {
1578: printf("%s: dirty txsoft with no mbuf chain\n",
1579: sc->sc_dev.dv_xname);
1580: panic("sip_stop");
1581: }
1582: #endif
1583: cmdsts |= /* DEBUG */
1.14 tsutsui 1584: le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts);
1.1 thorpej 1585: bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
1586: m_freem(txs->txs_mbuf);
1587: txs->txs_mbuf = NULL;
1588: SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1.2 thorpej 1589: }
1590:
1.17 ! thorpej 1591: if (disable)
1.2 thorpej 1592: sip_rxdrain(sc);
1.1 thorpej 1593:
1594: /*
1595: * Mark the interface down and cancel the watchdog timer.
1596: */
1597: ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1598: ifp->if_timer = 0;
1599:
1600: if ((ifp->if_flags & IFF_DEBUG) != 0 &&
1601: (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC)
1602: printf("%s: sip_stop: no INTR bits set in dirty tx "
1603: "descriptors\n", sc->sc_dev.dv_xname);
1604: }
1605:
1606: /*
1607: * sip_read_eeprom:
1608: *
1609: * Read data from the serial EEPROM.
1610: */
1611: void
1612: sip_read_eeprom(sc, word, wordcnt, data)
1613: struct sip_softc *sc;
1614: int word, wordcnt;
1615: u_int16_t *data;
1616: {
1617: bus_space_tag_t st = sc->sc_st;
1618: bus_space_handle_t sh = sc->sc_sh;
1619: u_int16_t reg;
1620: int i, x;
1621:
1622: for (i = 0; i < wordcnt; i++) {
1623: /* Send CHIP SELECT. */
1624: reg = EROMAR_EECS;
1625: bus_space_write_4(st, sh, SIP_EROMAR, reg);
1626:
1627: /* Shift in the READ opcode. */
1628: for (x = 3; x > 0; x--) {
1629: if (SIP_EEPROM_OPC_READ & (1 << (x - 1)))
1630: reg |= EROMAR_EEDI;
1631: else
1632: reg &= ~EROMAR_EEDI;
1633: bus_space_write_4(st, sh, SIP_EROMAR, reg);
1634: bus_space_write_4(st, sh, SIP_EROMAR,
1635: reg | EROMAR_EESK);
1636: delay(4);
1637: bus_space_write_4(st, sh, SIP_EROMAR, reg);
1638: delay(4);
1639: }
1640:
1641: /* Shift in address. */
1642: for (x = 6; x > 0; x--) {
1643: if ((word + i) & (1 << (x - 1)))
1644: reg |= EROMAR_EEDI;
1645: else
1646: reg &= ~EROMAR_EEDI;
1647: bus_space_write_4(st, sh, SIP_EROMAR, reg);
1648: bus_space_write_4(st, sh, SIP_EROMAR,
1649: reg | EROMAR_EESK);
1650: delay(4);
1651: bus_space_write_4(st, sh, SIP_EROMAR, reg);
1652: delay(4);
1653: }
1654:
1655: /* Shift out data. */
1656: reg = EROMAR_EECS;
1657: data[i] = 0;
1658: for (x = 16; x > 0; x--) {
1659: bus_space_write_4(st, sh, SIP_EROMAR,
1660: reg | EROMAR_EESK);
1661: delay(4);
1662: if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO)
1663: data[i] |= (1 << (x - 1));
1664: bus_space_write_4(st, sh, SIP_EROMAR, reg);
1.13 tsutsui 1665: delay(4);
1.1 thorpej 1666: }
1667:
1668: /* Clear CHIP SELECT. */
1669: bus_space_write_4(st, sh, SIP_EROMAR, 0);
1670: delay(4);
1671: }
1672: }
1673:
1674: /*
1675: * sip_add_rxbuf:
1676: *
1677: * Add a receive buffer to the indicated descriptor.
1678: */
1679: int
1680: sip_add_rxbuf(sc, idx)
1681: struct sip_softc *sc;
1682: int idx;
1683: {
1684: struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx];
1685: struct mbuf *m;
1686: int error;
1687:
1688: MGETHDR(m, M_DONTWAIT, MT_DATA);
1689: if (m == NULL)
1690: return (ENOBUFS);
1691:
1692: MCLGET(m, M_DONTWAIT);
1693: if ((m->m_flags & M_EXT) == 0) {
1694: m_freem(m);
1695: return (ENOBUFS);
1696: }
1697:
1698: if (rxs->rxs_mbuf != NULL)
1699: bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1700:
1701: rxs->rxs_mbuf = m;
1702:
1703: error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
1704: m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
1705: if (error) {
1706: printf("%s: can't load rx DMA map %d, error = %d\n",
1707: sc->sc_dev.dv_xname, idx, error);
1708: panic("sip_add_rxbuf"); /* XXX */
1709: }
1710:
1711: bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
1712: rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1713:
1714: SIP_INIT_RXDESC(sc, idx);
1715:
1716: return (0);
1717: }
1718:
1719: /*
1.15 thorpej 1720: * sip_sis900_set_filter:
1.1 thorpej 1721: *
1722: * Set up the receive filter.
1723: */
1724: void
1.15 thorpej 1725: sip_sis900_set_filter(sc)
1.1 thorpej 1726: struct sip_softc *sc;
1727: {
1728: bus_space_tag_t st = sc->sc_st;
1729: bus_space_handle_t sh = sc->sc_sh;
1730: struct ethercom *ec = &sc->sc_ethercom;
1731: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1732: struct ether_multi *enm;
1.11 thorpej 1733: u_int8_t *cp;
1.1 thorpej 1734: struct ether_multistep step;
1735: u_int32_t crc, mchash[8];
1736:
1737: /*
1738: * Initialize the prototype RFCR.
1739: */
1740: sc->sc_rfcr = RFCR_RFEN;
1741: if (ifp->if_flags & IFF_BROADCAST)
1742: sc->sc_rfcr |= RFCR_AAB;
1743: if (ifp->if_flags & IFF_PROMISC) {
1744: sc->sc_rfcr |= RFCR_AAP;
1745: goto allmulti;
1746: }
1747:
1748: /*
1749: * Set up the multicast address filter by passing all multicast
1750: * addresses through a CRC generator, and then using the high-order
1751: * 6 bits as an index into the 128 bit multicast hash table (only
1752: * the lower 16 bits of each 32 bit multicast hash register are
1753: * valid). The high order bits select the register, while the
1754: * rest of the bits select the bit within the register.
1755: */
1756:
1757: memset(mchash, 0, sizeof(mchash));
1758:
1759: ETHER_FIRST_MULTI(step, ec, enm);
1760: while (enm != NULL) {
1761: if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1762: /*
1763: * We must listen to a range of multicast addresses.
1764: * For now, just accept all multicasts, rather than
1765: * trying to set only those filter bits needed to match
1766: * the range. (At this time, the only use of address
1767: * ranges is for IP multicast routing, for which the
1768: * range is big enough to require all bits set.)
1769: */
1770: goto allmulti;
1771: }
1772:
1.11 thorpej 1773: crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1774:
1.1 thorpej 1775: /* Just want the 7 most significant bits. */
1776: crc >>= 25;
1777:
1778: /* Set the corresponding bit in the hash table. */
1779: mchash[crc >> 4] |= 1 << (crc & 0xf);
1780:
1781: ETHER_NEXT_MULTI(step, enm);
1782: }
1783:
1784: ifp->if_flags &= ~IFF_ALLMULTI;
1785: goto setit;
1786:
1787: allmulti:
1788: ifp->if_flags |= IFF_ALLMULTI;
1789: sc->sc_rfcr |= RFCR_AAM;
1790:
1791: setit:
1792: #define FILTER_EMIT(addr, data) \
1793: bus_space_write_4(st, sh, SIP_RFCR, (addr)); \
1.14 tsutsui 1794: delay(1); \
1795: bus_space_write_4(st, sh, SIP_RFDR, (data)); \
1796: delay(1)
1.1 thorpej 1797:
1798: /*
1799: * Disable receive filter, and program the node address.
1800: */
1801: cp = LLADDR(ifp->if_sadl);
1802: FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]);
1803: FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]);
1804: FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]);
1805:
1806: if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1807: /*
1808: * Program the multicast hash table.
1809: */
1810: FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]);
1811: FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]);
1812: FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]);
1813: FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]);
1814: FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]);
1815: FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]);
1816: FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]);
1817: FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]);
1818: }
1819: #undef FILTER_EMIT
1820:
1821: /*
1822: * Re-enable the receiver filter.
1823: */
1824: bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr);
1825: }
1826:
1827: /*
1.15 thorpej 1828: * sip_dp83815_set_filter:
1829: *
1830: * Set up the receive filter.
1831: */
1832: void
1833: sip_dp83815_set_filter(sc)
1834: struct sip_softc *sc;
1835: {
1836: bus_space_tag_t st = sc->sc_st;
1837: bus_space_handle_t sh = sc->sc_sh;
1838: struct ethercom *ec = &sc->sc_ethercom;
1839: struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1840: struct ether_multi *enm;
1841: u_int8_t *cp;
1842: struct ether_multistep step;
1843: u_int32_t crc, mchash[16];
1844: int i;
1845:
1846: /*
1847: * Initialize the prototype RFCR.
1848: */
1849: sc->sc_rfcr = RFCR_RFEN | RFCR_AARP | RFCR_APM;
1850: if (ifp->if_flags & IFF_BROADCAST)
1851: sc->sc_rfcr |= RFCR_AAB;
1852: if (ifp->if_flags & IFF_PROMISC) {
1853: sc->sc_rfcr |= RFCR_AAP;
1854: goto allmulti;
1855: }
1856:
1857: /*
1858: * Set up the multicast address filter by passing all multicast
1859: * addresses through a CRC generator, and then using the high-order
1860: * 9 bits as an index into the 512 bit multicast hash table. The
1861: * high-order bits select the slot, while the rest of the bits
1862: * select the bit within the slot. Note that only the low 16-bits
1863: * of each filter word are used, and there are 64 filter words.
1864: */
1865:
1866: memset(mchash, 0, sizeof(mchash));
1867:
1868: ETHER_FIRST_MULTI(step, ec, enm);
1869: while (enm != NULL) {
1870: if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1871: /*
1872: * We must listen to a range of multicast addresses.
1873: * For now, just accept all multicasts, rather than
1874: * trying to set only those filter bits needed to match
1875: * the range. (At this time, the only use of address
1876: * ranges is for IP multicast routing, for which the
1877: * range is big enough to require all bits set.)
1878: */
1879: goto allmulti;
1880: }
1881:
1882: crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1883:
1884: /* Just want the 9 most significant bits. */
1885: crc >>= 23;
1886:
1887: /* Set the corresponding bit in the hash table. */
1888: mchash[crc >> 5] |= 1 << (crc & 0x1f);
1889:
1890: ETHER_NEXT_MULTI(step, enm);
1891: }
1892:
1893: ifp->if_flags |= ~IFF_ALLMULTI;
1894: sc->sc_rfcr |= RFCR_MHEN;
1895: goto setit;
1896:
1897: allmulti:
1898: ifp->if_flags |= IFF_ALLMULTI;
1899: sc->sc_rfcr |= RFCR_AAM;
1900:
1901: setit:
1902: #define FILTER_EMIT(addr, data) \
1903: bus_space_write_4(st, sh, SIP_RFCR, (addr)); \
1904: delay(1); \
1905: bus_space_write_4(st, sh, SIP_RFDR, (data)); \
1906: delay(1);
1907:
1908: /*
1909: * Disable receive filter, and program the node address.
1910: */
1911: cp = LLADDR(ifp->if_sadl);
1912: FILTER_EMIT(RFCR_NS_RFADDR_PMATCH, (cp[1] << 8) | cp[0]);
1913: FILTER_EMIT(RFCR_NS_RFADDR_PMATCH, (cp[3] << 8) | cp[2]);
1914: FILTER_EMIT(RFCR_NS_RFADDR_PMATCH, (cp[5] << 8) | cp[4]);
1915:
1916: if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1917: /*
1918: * Program the multicast hash table.
1919: */
1920: for (i = 0; i < 16; i++) {
1921: FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2),
1922: mchash[i] & 0xffff);
1923: FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2) + 2,
1924: (mchash[i] >> 16) & 0xffff);
1925: }
1926: }
1927: #undef FILTER_EMIT
1928:
1929: /*
1930: * Re-enable the receiver filter.
1931: */
1932: bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr);
1933: }
1934:
1935: /*
1936: * sip_sis900_mii_readreg: [mii interface function]
1.1 thorpej 1937: *
1938: * Read a PHY register on the MII.
1939: */
1940: int
1.15 thorpej 1941: sip_sis900_mii_readreg(self, phy, reg)
1.1 thorpej 1942: struct device *self;
1943: int phy, reg;
1944: {
1945: struct sip_softc *sc = (struct sip_softc *) self;
1946: u_int32_t enphy;
1947:
1948: /*
1949: * The SiS 900 has only an internal PHY on the MII. Only allow
1950: * MII address 0.
1951: */
1.15 thorpej 1952: if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0)
1.1 thorpej 1953: return (0);
1954:
1955: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY,
1.5 thorpej 1956: (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) |
1957: ENPHY_RWCMD | ENPHY_ACCESS);
1.1 thorpej 1958: do {
1959: enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY);
1960: } while (enphy & ENPHY_ACCESS);
1961: return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT);
1962: }
1963:
1964: /*
1.15 thorpej 1965: * sip_sis900_mii_writereg: [mii interface function]
1.1 thorpej 1966: *
1967: * Write a PHY register on the MII.
1968: */
1969: void
1.15 thorpej 1970: sip_sis900_mii_writereg(self, phy, reg, val)
1.1 thorpej 1971: struct device *self;
1972: int phy, reg, val;
1973: {
1974: struct sip_softc *sc = (struct sip_softc *) self;
1975: u_int32_t enphy;
1976:
1977: /*
1978: * The SiS 900 has only an internal PHY on the MII. Only allow
1979: * MII address 0.
1980: */
1.15 thorpej 1981: if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0)
1.1 thorpej 1982: return;
1983:
1984: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY,
1.5 thorpej 1985: (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) |
1986: (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS);
1.1 thorpej 1987: do {
1988: enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY);
1989: } while (enphy & ENPHY_ACCESS);
1990: }
1991:
1992: /*
1.15 thorpej 1993: * sip_sis900_mii_statchg: [mii interface function]
1.1 thorpej 1994: *
1995: * Callback from MII layer when media changes.
1996: */
1997: void
1.15 thorpej 1998: sip_sis900_mii_statchg(self)
1.1 thorpej 1999: struct device *self;
2000: {
2001: struct sip_softc *sc = (struct sip_softc *) self;
2002: u_int32_t flowctl;
2003:
2004: /*
2005: * Update TXCFG for full-duplex operation.
2006: */
2007: if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0)
2008: sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
2009: else
2010: sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
2011:
2012: /*
2013: * Update RXCFG for full-duplex or loopback.
2014: */
2015: if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 ||
2016: IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP)
2017: sc->sc_rxcfg |= RXCFG_ATX;
2018: else
2019: sc->sc_rxcfg &= ~RXCFG_ATX;
2020:
2021: /*
2022: * Update IMR for use of 802.3x flow control.
2023: */
2024: if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) {
2025: sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST);
2026: flowctl = FLOWCTL_FLOWEN;
2027: } else {
2028: sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST);
2029: flowctl = 0;
2030: }
2031:
2032: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg);
2033: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg);
2034: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr);
2035: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl);
1.15 thorpej 2036: }
2037:
2038: /*
2039: * sip_dp83815_mii_readreg: [mii interface function]
2040: *
2041: * Read a PHY register on the MII.
2042: */
2043: int
2044: sip_dp83815_mii_readreg(self, phy, reg)
2045: struct device *self;
2046: int phy, reg;
2047: {
2048: struct sip_softc *sc = (struct sip_softc *) self;
2049: u_int32_t val;
2050:
2051: /*
2052: * The DP83815 only has an internal PHY. Only allow
2053: * MII address 0.
2054: */
2055: if (phy != 0)
2056: return (0);
2057:
2058: /*
2059: * Apparently, after a reset, the DP83815 can take a while
2060: * to respond. During this recovery period, the BMSR returns
2061: * a value of 0. Catch this -- it's not supposed to happen
2062: * (the BMSR has some hardcoded-to-1 bits), and wait for the
2063: * PHY to come back to life.
2064: *
2065: * This works out because the BMSR is the first register
2066: * read during the PHY probe process.
2067: */
2068: do {
2069: val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg));
2070: } while (reg == MII_BMSR && val == 0);
2071:
2072: return (val & 0xffff);
2073: }
2074:
2075: /*
2076: * sip_dp83815_mii_writereg: [mii interface function]
2077: *
2078: * Write a PHY register to the MII.
2079: */
2080: void
2081: sip_dp83815_mii_writereg(self, phy, reg, val)
2082: struct device *self;
2083: int phy, reg, val;
2084: {
2085: struct sip_softc *sc = (struct sip_softc *) self;
2086:
2087: /*
2088: * The DP83815 only has an internal PHY. Only allow
2089: * MII address 0.
2090: */
2091: if (phy != 0)
2092: return;
2093:
2094: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val);
2095: }
2096:
2097: /*
2098: * sip_dp83815_mii_statchg: [mii interface function]
2099: *
2100: * Callback from MII layer when media changes.
2101: */
2102: void
2103: sip_dp83815_mii_statchg(self)
2104: struct device *self;
2105: {
2106: struct sip_softc *sc = (struct sip_softc *) self;
2107:
2108: /*
2109: * Update TXCFG for full-duplex operation.
2110: */
2111: if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0)
2112: sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
2113: else
2114: sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
2115:
2116: /*
2117: * Update RXCFG for full-duplex or loopback.
2118: */
2119: if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 ||
2120: IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP)
2121: sc->sc_rxcfg |= RXCFG_ATX;
2122: else
2123: sc->sc_rxcfg &= ~RXCFG_ATX;
2124:
2125: /*
2126: * XXX 802.3x flow control.
2127: */
2128:
2129: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg);
2130: bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg);
1.1 thorpej 2131: }
2132:
2133: /*
2134: * sip_mediastatus: [ifmedia interface function]
2135: *
2136: * Get the current interface media status.
2137: */
2138: void
2139: sip_mediastatus(ifp, ifmr)
2140: struct ifnet *ifp;
2141: struct ifmediareq *ifmr;
2142: {
2143: struct sip_softc *sc = ifp->if_softc;
2144:
2145: mii_pollstat(&sc->sc_mii);
2146: ifmr->ifm_status = sc->sc_mii.mii_media_status;
2147: ifmr->ifm_active = sc->sc_mii.mii_media_active;
2148: }
2149:
2150: /*
2151: * sip_mediachange: [ifmedia interface function]
2152: *
2153: * Set hardware to newly-selected media.
2154: */
2155: int
2156: sip_mediachange(ifp)
2157: struct ifnet *ifp;
2158: {
2159: struct sip_softc *sc = ifp->if_softc;
2160:
2161: if (ifp->if_flags & IFF_UP)
2162: mii_mediachg(&sc->sc_mii);
2163: return (0);
2164: }
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