version 1.45, 2019/12/12 12:00:06 |
version 1.46, 2019/12/14 04:12:49 |
Line 91 __KERNEL_RCSID(0, "$NetBSD$"); |
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Line 91 __KERNEL_RCSID(0, "$NetBSD$"); |
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#define MARH 0x204 /* MAC address high */ |
#define MARH 0x204 /* MAC address high */ |
#define GRR 0x216 /* global reset */ |
#define GRR 0x216 /* global reset */ |
#define SIDER 0x400 /* switch ID and function enable */ |
#define SIDER 0x400 /* switch ID and function enable */ |
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#define SGCR3 0x406 /* switch function control 3 */ |
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#define CR3_USEHDX (1U<<6) /* use half-duplex 8842 host port */ |
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#define CR3_USEFC (1U<<5) /* use flowcontrol 8842 host port */ |
#define IACR 0x4a0 /* indirect access control */ |
#define IACR 0x4a0 /* indirect access control */ |
#define IADR1 0x4a2 /* indirect access data 66:63 */ |
#define IADR1 0x4a2 /* indirect access data 66:63 */ |
#define IADR2 0x4a4 /* indirect access data 47:32 */ |
#define IADR2 0x4a4 /* indirect access data 47:32 */ |
Line 145 __KERNEL_RCSID(0, "$NetBSD$"); |
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Line 148 __KERNEL_RCSID(0, "$NetBSD$"); |
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#define INT_DMTS (1U<<30) /* sending desc. has posted Tx done */ |
#define INT_DMTS (1U<<30) /* sending desc. has posted Tx done */ |
#define INT_DMRS (1U<<29) /* frame was received */ |
#define INT_DMRS (1U<<29) /* frame was received */ |
#define INT_DMRBUS (1U<<27) /* Rx descriptor pool is full */ |
#define INT_DMRBUS (1U<<27) /* Rx descriptor pool is full */ |
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#define INT_DMxPSS (3U<<25) /* 26:25 DMA Tx/Rx have stopped */ |
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#define T0_OWN (1U<<31) /* desc is ready to Tx */ |
#define T0_OWN (1U<<31) /* desc is ready to Tx */ |
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Line 825 kse_init(struct ifnet *ifp) |
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Line 829 kse_init(struct ifnet *ifp) |
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if (sc->sc_chip == 0x8842) { |
if (sc->sc_chip == 0x8842) { |
sc->sc_txc |= TXC_FCE; |
sc->sc_txc |= TXC_FCE; |
sc->sc_rxc |= RXC_FCE; |
sc->sc_rxc |= RXC_FCE; |
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CSR_WRITE_2(sc, SGCR3, |
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CSR_READ_2(sc, SGCR3) | CR3_USEFC); |
} |
} |
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/* build multicast hash filter if necessary */ |
/* build multicast hash filter if necessary */ |