version 1.253.2.2, 2014/05/18 17:45:40 |
version 1.254, 2013/07/03 05:49:36 |
Line 671 static const struct bge_product { |
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Line 671 static const struct bge_product { |
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NULL }, |
NULL }, |
}; |
}; |
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#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE) |
#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) |
#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY) |
#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) |
#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS) |
#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) |
#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY) |
#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) |
#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS) |
#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) |
#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS) |
#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) |
#define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY) |
#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) |
#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS) |
#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) |
#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS) |
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static const struct bge_revision { |
static const struct bge_revision { |
uint32_t br_chipid; |
uint32_t br_chipid; |
Line 1447 bge_miibus_statchg(struct ifnet *ifp) |
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Line 1446 bge_miibus_statchg(struct ifnet *ifp) |
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* Get flow control negotiation result. |
* Get flow control negotiation result. |
*/ |
*/ |
if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && |
if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && |
(mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) |
(mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { |
sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; |
sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; |
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mii->mii_media_active &= ~IFM_ETH_FMASK; |
if (!BGE_STS_BIT(sc, BGE_STS_LINK) && |
} |
mii->mii_media_status & IFM_ACTIVE && |
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IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) |
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BGE_STS_SETBIT(sc, BGE_STS_LINK); |
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else if (BGE_STS_BIT(sc, BGE_STS_LINK) && |
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(!(mii->mii_media_status & IFM_ACTIVE) || |
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IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) |
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BGE_STS_CLRBIT(sc, BGE_STS_LINK); |
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if (!BGE_STS_BIT(sc, BGE_STS_LINK)) |
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return; |
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/* Set the port mode (MII/GMII) to match the link speed. */ |
/* Set the port mode (MII/GMII) to match the link speed. */ |
mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & |
mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & |
Line 1475 bge_miibus_statchg(struct ifnet *ifp) |
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Line 1464 bge_miibus_statchg(struct ifnet *ifp) |
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tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; |
tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; |
rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; |
rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; |
if ((mii->mii_media_active & IFM_FDX) != 0) { |
if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { |
if (sc->bge_flowflags & IFM_ETH_TXPAUSE) |
if (sc->bge_flowflags & IFM_ETH_TXPAUSE) |
tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; |
tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; |
if (sc->bge_flowflags & IFM_ETH_RXPAUSE) |
if (sc->bge_flowflags & IFM_ETH_RXPAUSE) |
Line 1741 bge_newbuf_std(struct bge_softc *sc, int |
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Line 1730 bge_newbuf_std(struct bge_softc *sc, int |
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m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; |
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; |
m_new->m_data = m_new->m_ext.ext_buf; |
m_new->m_data = m_new->m_ext.ext_buf; |
} |
} |
if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) |
if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) |
m_adj(m_new, ETHER_ALIGN); |
m_adj(m_new, ETHER_ALIGN); |
if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, |
if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, |
BUS_DMA_READ|BUS_DMA_NOWAIT)) |
BUS_DMA_READ|BUS_DMA_NOWAIT)) |
Line 1802 bge_newbuf_jumbo(struct bge_softc *sc, i |
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Line 1791 bge_newbuf_jumbo(struct bge_softc *sc, i |
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buf = m_new->m_data = m_new->m_ext.ext_buf; |
buf = m_new->m_data = m_new->m_ext.ext_buf; |
m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; |
m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; |
} |
} |
if (!(sc->bge_flags & BGEF_RX_ALIGNBUG)) |
if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) |
m_adj(m_new, ETHER_ALIGN); |
m_adj(m_new, ETHER_ALIGN); |
bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, |
bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, |
mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, |
mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, |
Line 1835 bge_init_rx_ring_std(struct bge_softc *s |
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Line 1824 bge_init_rx_ring_std(struct bge_softc *s |
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{ |
{ |
int i; |
int i; |
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if (sc->bge_flags & BGEF_RXRING_VALID) |
if (sc->bge_flags & BGE_RXRING_VALID) |
return 0; |
return 0; |
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for (i = 0; i < BGE_SSLOTS; i++) { |
for (i = 0; i < BGE_SSLOTS; i++) { |
Line 1846 bge_init_rx_ring_std(struct bge_softc *s |
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Line 1835 bge_init_rx_ring_std(struct bge_softc *s |
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sc->bge_std = i - 1; |
sc->bge_std = i - 1; |
bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); |
bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); |
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sc->bge_flags |= BGEF_RXRING_VALID; |
sc->bge_flags |= BGE_RXRING_VALID; |
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return 0; |
return 0; |
} |
} |
Line 1856 bge_free_rx_ring_std(struct bge_softc *s |
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Line 1845 bge_free_rx_ring_std(struct bge_softc *s |
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{ |
{ |
int i; |
int i; |
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if (!(sc->bge_flags & BGEF_RXRING_VALID)) |
if (!(sc->bge_flags & BGE_RXRING_VALID)) |
return; |
return; |
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for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { |
for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { |
Line 1870 bge_free_rx_ring_std(struct bge_softc *s |
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Line 1859 bge_free_rx_ring_std(struct bge_softc *s |
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sizeof(struct bge_rx_bd)); |
sizeof(struct bge_rx_bd)); |
} |
} |
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sc->bge_flags &= ~BGEF_RXRING_VALID; |
sc->bge_flags &= ~BGE_RXRING_VALID; |
} |
} |
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static int |
static int |
Line 1879 bge_init_rx_ring_jumbo(struct bge_softc |
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Line 1868 bge_init_rx_ring_jumbo(struct bge_softc |
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int i; |
int i; |
volatile struct bge_rcb *rcb; |
volatile struct bge_rcb *rcb; |
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if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID) |
if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) |
return 0; |
return 0; |
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for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { |
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { |
Line 1888 bge_init_rx_ring_jumbo(struct bge_softc |
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Line 1877 bge_init_rx_ring_jumbo(struct bge_softc |
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} |
} |
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sc->bge_jumbo = i - 1; |
sc->bge_jumbo = i - 1; |
sc->bge_flags |= BGEF_JUMBO_RXRING_VALID; |
sc->bge_flags |= BGE_JUMBO_RXRING_VALID; |
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rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; |
rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; |
rcb->bge_maxlen_flags = 0; |
rcb->bge_maxlen_flags = 0; |
Line 1904 bge_free_rx_ring_jumbo(struct bge_softc |
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Line 1893 bge_free_rx_ring_jumbo(struct bge_softc |
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{ |
{ |
int i; |
int i; |
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if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID)) |
if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) |
return; |
return; |
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for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { |
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { |
Line 1916 bge_free_rx_ring_jumbo(struct bge_softc |
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Line 1905 bge_free_rx_ring_jumbo(struct bge_softc |
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sizeof(struct bge_rx_bd)); |
sizeof(struct bge_rx_bd)); |
} |
} |
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sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID; |
sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; |
} |
} |
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static void |
static void |
Line 1925 bge_free_tx_ring(struct bge_softc *sc) |
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Line 1914 bge_free_tx_ring(struct bge_softc *sc) |
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int i; |
int i; |
struct txdmamap_pool_entry *dma; |
struct txdmamap_pool_entry *dma; |
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if (!(sc->bge_flags & BGEF_TXRING_VALID)) |
if (!(sc->bge_flags & BGE_TXRING_VALID)) |
return; |
return; |
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for (i = 0; i < BGE_TX_RING_CNT; i++) { |
for (i = 0; i < BGE_TX_RING_CNT; i++) { |
Line 1946 bge_free_tx_ring(struct bge_softc *sc) |
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Line 1935 bge_free_tx_ring(struct bge_softc *sc) |
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free(dma, M_DEVBUF); |
free(dma, M_DEVBUF); |
} |
} |
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sc->bge_flags &= ~BGEF_TXRING_VALID; |
sc->bge_flags &= ~BGE_TXRING_VALID; |
} |
} |
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static int |
static int |
bge_init_tx_ring(struct bge_softc *sc) |
bge_init_tx_ring(struct bge_softc *sc) |
{ |
{ |
struct ifnet *ifp = &sc->ethercom.ec_if; |
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int i; |
int i; |
bus_dmamap_t dmamap; |
bus_dmamap_t dmamap; |
bus_size_t maxsegsz; |
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struct txdmamap_pool_entry *dma; |
struct txdmamap_pool_entry *dma; |
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if (sc->bge_flags & BGEF_TXRING_VALID) |
if (sc->bge_flags & BGE_TXRING_VALID) |
return 0; |
return 0; |
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sc->bge_txcnt = 0; |
sc->bge_txcnt = 0; |
Line 1977 bge_init_tx_ring(struct bge_softc *sc) |
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Line 1964 bge_init_tx_ring(struct bge_softc *sc) |
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if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) |
if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) |
bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); |
bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); |
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/* Limit DMA segment size for some chips */ |
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if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) && |
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(ifp->if_mtu <= ETHERMTU)) |
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maxsegsz = 2048; |
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else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) |
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maxsegsz = 4096; |
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else |
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maxsegsz = ETHER_MAX_LEN_JUMBO; |
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SLIST_INIT(&sc->txdma_list); |
SLIST_INIT(&sc->txdma_list); |
for (i = 0; i < BGE_TX_RING_CNT; i++) { |
for (i = 0; i < BGE_TX_RING_CNT; i++) { |
if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, |
if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, |
BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT, |
BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, |
&dmamap)) |
&dmamap)) |
return ENOBUFS; |
return ENOBUFS; |
if (dmamap == NULL) |
if (dmamap == NULL) |
Line 2004 bge_init_tx_ring(struct bge_softc *sc) |
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Line 1983 bge_init_tx_ring(struct bge_softc *sc) |
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SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); |
SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); |
} |
} |
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sc->bge_flags |= BGEF_TXRING_VALID; |
sc->bge_flags |= BGE_TXRING_VALID; |
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return 0; |
return 0; |
} |
} |
Line 2176 bge_poll_fw(struct bge_softc *sc) |
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Line 2155 bge_poll_fw(struct bge_softc *sc) |
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aprint_error_dev(sc->bge_dev, "reset timed out\n"); |
aprint_error_dev(sc->bge_dev, "reset timed out\n"); |
return -1; |
return -1; |
} |
} |
} else if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) { |
} else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { |
/* |
/* |
* Poll the value location we just wrote until |
* Poll the value location we just wrote until |
* we see the 1's complement of the magic number. |
* we see the 1's complement of the magic number. |
Line 2296 bge_chipinit(struct bge_softc *sc) |
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Line 2275 bge_chipinit(struct bge_softc *sc) |
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CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); |
CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); |
} |
} |
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if (BGE_IS_57765_FAMILY(sc)) { |
/* XXX Should we use 57765_FAMILY? */ |
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if (BGE_IS_57765_PLUS(sc)) { |
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { |
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) { |
/* Save */ |
/* Save */ |
mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); |
mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL); |
Line 2347 bge_chipinit(struct bge_softc *sc) |
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Line 2327 bge_chipinit(struct bge_softc *sc) |
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/* Set up the PCI DMA control register. */ |
/* Set up the PCI DMA control register. */ |
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; |
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; |
if (sc->bge_flags & BGEF_PCIE) { |
if (sc->bge_flags & BGE_PCIE) { |
/* Read watermark not used, 128 bytes for write. */ |
/* Read watermark not used, 128 bytes for write. */ |
DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", |
DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", |
device_xname(sc->bge_dev))); |
device_xname(sc->bge_dev))); |
Line 2355 bge_chipinit(struct bge_softc *sc) |
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Line 2335 bge_chipinit(struct bge_softc *sc) |
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dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); |
dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); |
else |
else |
dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); |
dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); |
} else if (sc->bge_flags & BGEF_PCIX) { |
} else if (sc->bge_flags & BGE_PCIX) { |
DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", |
DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", |
device_xname(sc->bge_dev))); |
device_xname(sc->bge_dev))); |
/* PCI-X bus */ |
/* PCI-X bus */ |
Line 2413 bge_chipinit(struct bge_softc *sc) |
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Line 2393 bge_chipinit(struct bge_softc *sc) |
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BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) |
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; |
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; |
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if (BGE_IS_57765_PLUS(sc)) { |
if (BGE_IS_5717_PLUS(sc)) { |
dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; |
dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; |
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) |
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) |
dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; |
dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; |
Line 2423 bge_chipinit(struct bge_softc *sc) |
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Line 2403 bge_chipinit(struct bge_softc *sc) |
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* a status tag update and leave interrupts permanently |
* a status tag update and leave interrupts permanently |
* disabled. |
* disabled. |
*/ |
*/ |
if (!BGE_IS_57765_FAMILY(sc) && |
if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717) |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) |
dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; |
dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; |
} |
} |
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Line 2645 bge_blockinit(struct bge_softc *sc) |
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Line 2625 bge_blockinit(struct bge_softc *sc) |
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rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; |
rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; |
BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); |
BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); |
/* 5718 step 16 */ |
/* 5718 step 16 */ |
if (BGE_IS_57765_PLUS(sc)) { |
if (BGE_IS_5717_PLUS(sc)) { |
/* |
/* |
* Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) |
* Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) |
* Bits 15-2 : Maximum RX frame size |
* Bits 15-2 : Maximum RX frame size |
Line 2779 bge_blockinit(struct bge_softc *sc) |
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Line 2759 bge_blockinit(struct bge_softc *sc) |
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if (BGE_IS_5700_FAMILY(sc)) { |
if (BGE_IS_5700_FAMILY(sc)) { |
/* 5700 to 5704 had 16 send rings. */ |
/* 5700 to 5704 had 16 send rings. */ |
limit = BGE_TX_RINGS_EXTSSRAM_MAX; |
limit = BGE_TX_RINGS_EXTSSRAM_MAX; |
} else if (BGE_IS_5717_PLUS(sc)) { |
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limit = BGE_TX_RINGS_5717_MAX; |
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} else if (BGE_IS_57765_FAMILY(sc)) { |
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limit = BGE_TX_RINGS_57765_MAX; |
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} else |
} else |
limit = 1; |
limit = 1; |
rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; |
rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; |
Line 2815 bge_blockinit(struct bge_softc *sc) |
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Line 2791 bge_blockinit(struct bge_softc *sc) |
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* 'ring diabled' bit in the flags field of all the receive |
* 'ring diabled' bit in the flags field of all the receive |
* return ring control blocks, located in NIC memory. |
* return ring control blocks, located in NIC memory. |
*/ |
*/ |
if (BGE_IS_5717_PLUS(sc)) { |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || |
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BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || |
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BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { |
/* Should be 17, use 16 until we get an SRAM map. */ |
/* Should be 17, use 16 until we get an SRAM map. */ |
limit = 16; |
limit = 16; |
} else if (BGE_IS_5700_FAMILY(sc)) |
} else if (BGE_IS_5700_FAMILY(sc)) |
limit = BGE_RX_RINGS_MAX; |
limit = BGE_RX_RINGS_MAX; |
else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || |
else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || |
BGE_IS_57765_FAMILY(sc)) |
BGE_IS_57765_PLUS(sc)) |
limit = 4; |
limit = 4; |
else |
else |
limit = 1; |
limit = 1; |
Line 2977 bge_blockinit(struct bge_softc *sc) |
|
Line 2955 bge_blockinit(struct bge_softc *sc) |
|
BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | |
BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | |
BGE_MACMODE_FRMHDR_DMA_ENB; |
BGE_MACMODE_FRMHDR_DMA_ENB; |
|
|
if (sc->bge_flags & BGEF_FIBER_TBI) |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) |
val |= BGE_PORTMODE_TBI; |
val |= BGE_PORTMODE_TBI; |
else if (sc->bge_flags & BGEF_FIBER_MII) |
else if (sc->bge_flags & BGE_PHY_FIBER_MII) |
val |= BGE_PORTMODE_GMII; |
val |= BGE_PORTMODE_GMII; |
else |
else |
val |= BGE_PORTMODE_MII; |
val |= BGE_PORTMODE_MII; |
Line 3036 bge_blockinit(struct bge_softc *sc) |
|
Line 3014 bge_blockinit(struct bge_softc *sc) |
|
BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | |
BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | |
BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; |
BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; |
|
|
if (sc->bge_flags & BGEF_PCIE) |
if (sc->bge_flags & BGE_PCIE) |
val |= BGE_RDMAMODE_FIFO_LONG_BURST; |
val |= BGE_RDMAMODE_FIFO_LONG_BURST; |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { |
if (sc->bge_flags & BGE_TSO) |
if (ifp->if_mtu <= ETHERMTU) |
|
val |= BGE_RDMAMODE_JMB_2K_MMRR; |
|
} |
|
if (sc->bge_flags & BGEF_TSO) |
|
val |= BGE_RDMAMODE_TSO4_ENABLE; |
val |= BGE_RDMAMODE_TSO4_ENABLE; |
|
|
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { |
Line 3059 bge_blockinit(struct bge_softc *sc) |
|
Line 3033 bge_blockinit(struct bge_softc *sc) |
|
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || |
BGE_IS_57765_PLUS(sc)) { |
BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */ |
dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); |
dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); |
/* |
/* |
* Adjust tx margin to prevent TX data corruption and |
* Adjust tx margin to prevent TX data corruption and |
Line 3132 bge_blockinit(struct bge_softc *sc) |
|
Line 3106 bge_blockinit(struct bge_softc *sc) |
|
|
|
/* 5718 step 60, 57XX step 90 */ |
/* 5718 step 60, 57XX step 90 */ |
/* Turn on send data initiator state machine */ |
/* Turn on send data initiator state machine */ |
if (sc->bge_flags & BGEF_TSO) { |
if (sc->bge_flags & BGE_TSO) { |
/* XXX: magic value from Linux driver */ |
/* XXX: magic value from Linux driver */ |
CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | |
CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | |
BGE_SDIMODE_HW_LSO_PRE_DMA); |
BGE_SDIMODE_HW_LSO_PRE_DMA); |
Line 3163 bge_blockinit(struct bge_softc *sc) |
|
Line 3137 bge_blockinit(struct bge_softc *sc) |
|
* Enable attention when the link has changed state for |
* Enable attention when the link has changed state for |
* devices that use auto polling. |
* devices that use auto polling. |
*/ |
*/ |
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); |
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); |
} else { |
} else { |
/* 5718 step 68 */ |
/* 5718 step 68 */ |
Line 3304 bge_attach(device_t parent, device_t sel |
|
Line 3278 bge_attach(device_t parent, device_t sel |
|
uint32_t pm_ctl; |
uint32_t pm_ctl; |
bool no_seeprom; |
bool no_seeprom; |
int capmask; |
int capmask; |
char intrbuf[PCI_INTRSTR_LEN]; |
|
|
|
bp = bge_lookup(pa); |
bp = bge_lookup(pa); |
KASSERT(bp != NULL); |
KASSERT(bp != NULL); |
Line 3356 bge_attach(device_t parent, device_t sel |
|
Line 3329 bge_attach(device_t parent, device_t sel |
|
} |
} |
|
|
DPRINTFN(5, ("pci_intr_string\n")); |
DPRINTFN(5, ("pci_intr_string\n")); |
intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); |
intrstr = pci_intr_string(pc, ih); |
|
|
DPRINTFN(5, ("pci_intr_establish\n")); |
DPRINTFN(5, ("pci_intr_establish\n")); |
sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); |
sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); |
Line 3377 bge_attach(device_t parent, device_t sel |
|
Line 3350 bge_attach(device_t parent, device_t sel |
|
&sc->bge_pciecap, NULL) != 0) |
&sc->bge_pciecap, NULL) != 0) |
|| (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { |
|| (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { |
/* PCIe */ |
/* PCIe */ |
sc->bge_flags |= BGEF_PCIE; |
sc->bge_flags |= BGE_PCIE; |
/* Extract supported maximum payload size. */ |
/* Extract supported maximum payload size. */ |
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, |
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, |
sc->bge_pciecap + PCIE_DCAP); |
sc->bge_pciecap + PCIE_DCAP); |
Line 3391 bge_attach(device_t parent, device_t sel |
|
Line 3364 bge_attach(device_t parent, device_t sel |
|
} else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & |
} else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & |
BGE_PCISTATE_PCI_BUSMODE) == 0) { |
BGE_PCISTATE_PCI_BUSMODE) == 0) { |
/* PCI-X */ |
/* PCI-X */ |
sc->bge_flags |= BGEF_PCIX; |
sc->bge_flags |= BGE_PCIX; |
if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, |
if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, |
&sc->bge_pcixcap, NULL) == 0) |
&sc->bge_pcixcap, NULL) == 0) |
aprint_error_dev(sc->bge_dev, |
aprint_error_dev(sc->bge_dev, |
Line 3415 bge_attach(device_t parent, device_t sel |
|
Line 3388 bge_attach(device_t parent, device_t sel |
|
|
|
/* Save chipset family. */ |
/* Save chipset family. */ |
switch (BGE_ASICREV(sc->bge_chipid)) { |
switch (BGE_ASICREV(sc->bge_chipid)) { |
|
case BGE_ASICREV_BCM57765: |
|
case BGE_ASICREV_BCM57766: |
|
sc->bge_flags |= BGE_57765_PLUS; |
|
/* FALLTHROUGH */ |
case BGE_ASICREV_BCM5717: |
case BGE_ASICREV_BCM5717: |
case BGE_ASICREV_BCM5719: |
case BGE_ASICREV_BCM5719: |
case BGE_ASICREV_BCM5720: |
case BGE_ASICREV_BCM5720: |
sc->bge_flags |= BGEF_5717_PLUS; |
sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | |
/* FALLTHROUGH */ |
BGE_575X_PLUS | BGE_5705_PLUS | BGE_JUMBO_CAPABLE; |
case BGE_ASICREV_BCM57765: |
|
case BGE_ASICREV_BCM57766: |
|
if (!BGE_IS_5717_PLUS(sc)) |
|
sc->bge_flags |= BGEF_57765_FAMILY; |
|
sc->bge_flags |= BGEF_57765_PLUS | BGEF_5755_PLUS | |
|
BGEF_575X_PLUS | BGEF_5705_PLUS | BGEF_JUMBO_CAPABLE; |
|
/* Jumbo frame on BCM5719 A0 does not work. */ |
/* Jumbo frame on BCM5719 A0 does not work. */ |
if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && |
if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) && |
(sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) |
(sc->bge_chipid == BGE_CHIPID_BCM5719_A0)) |
sc->bge_flags &= ~BGEF_JUMBO_CAPABLE; |
sc->bge_flags |= ~BGE_JUMBO_CAPABLE; |
break; |
break; |
case BGE_ASICREV_BCM5755: |
case BGE_ASICREV_BCM5755: |
case BGE_ASICREV_BCM5761: |
case BGE_ASICREV_BCM5761: |
Line 3437 bge_attach(device_t parent, device_t sel |
|
Line 3408 bge_attach(device_t parent, device_t sel |
|
case BGE_ASICREV_BCM5785: |
case BGE_ASICREV_BCM5785: |
case BGE_ASICREV_BCM5787: |
case BGE_ASICREV_BCM5787: |
case BGE_ASICREV_BCM57780: |
case BGE_ASICREV_BCM57780: |
sc->bge_flags |= BGEF_5755_PLUS | BGEF_575X_PLUS | BGEF_5705_PLUS; |
sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; |
break; |
break; |
case BGE_ASICREV_BCM5700: |
case BGE_ASICREV_BCM5700: |
case BGE_ASICREV_BCM5701: |
case BGE_ASICREV_BCM5701: |
case BGE_ASICREV_BCM5703: |
case BGE_ASICREV_BCM5703: |
case BGE_ASICREV_BCM5704: |
case BGE_ASICREV_BCM5704: |
sc->bge_flags |= BGEF_5700_FAMILY | BGEF_JUMBO_CAPABLE; |
sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE; |
break; |
break; |
case BGE_ASICREV_BCM5714_A0: |
case BGE_ASICREV_BCM5714_A0: |
case BGE_ASICREV_BCM5780: |
case BGE_ASICREV_BCM5780: |
case BGE_ASICREV_BCM5714: |
case BGE_ASICREV_BCM5714: |
sc->bge_flags |= BGEF_5714_FAMILY | BGEF_JUMBO_CAPABLE; |
sc->bge_flags |= BGE_5714_FAMILY | BGE_JUMBO_CAPABLE; |
/* FALLTHROUGH */ |
/* FALLTHROUGH */ |
case BGE_ASICREV_BCM5750: |
case BGE_ASICREV_BCM5750: |
case BGE_ASICREV_BCM5752: |
case BGE_ASICREV_BCM5752: |
case BGE_ASICREV_BCM5906: |
case BGE_ASICREV_BCM5906: |
sc->bge_flags |= BGEF_575X_PLUS; |
sc->bge_flags |= BGE_575X_PLUS; |
/* FALLTHROUGH */ |
/* FALLTHROUGH */ |
case BGE_ASICREV_BCM5705: |
case BGE_ASICREV_BCM5705: |
sc->bge_flags |= BGEF_5705_PLUS; |
sc->bge_flags |= BGE_5705_PLUS; |
break; |
break; |
} |
} |
|
|
Line 3466 bge_attach(device_t parent, device_t sel |
|
Line 3437 bge_attach(device_t parent, device_t sel |
|
case BGE_ASICREV_BCM5719: |
case BGE_ASICREV_BCM5719: |
case BGE_ASICREV_BCM5720: |
case BGE_ASICREV_BCM5720: |
case BGE_ASICREV_BCM5761: |
case BGE_ASICREV_BCM5761: |
sc->bge_flags |= BGEF_APE; |
sc->bge_flags |= BGE_APE; |
break; |
break; |
} |
} |
|
|
/* |
|
* The 40bit DMA bug applies to the 5714/5715 controllers and is |
|
* not actually a MAC controller bug but an issue with the embedded |
|
* PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. |
|
*/ |
|
if (BGE_IS_5714_FAMILY(sc) && ((sc->bge_flags & BGEF_PCIX) != 0)) |
|
sc->bge_flags |= BGEF_40BIT_BUG; |
|
|
|
/* Chips with APE need BAR2 access for APE registers/memory. */ |
/* Chips with APE need BAR2 access for APE registers/memory. */ |
if ((sc->bge_flags & BGEF_APE) != 0) { |
if ((sc->bge_flags & BGE_APE) != 0) { |
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); |
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); |
if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, |
if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, |
&sc->bge_apetag, &sc->bge_apehandle, NULL, |
&sc->bge_apetag, &sc->bge_apehandle, NULL, |
Line 3506 bge_attach(device_t parent, device_t sel |
|
Line 3469 bge_attach(device_t parent, device_t sel |
|
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) |
sc->bge_flags |= BGEF_CPMU_PRESENT; |
sc->bge_flags |= BGE_CPMU_PRESENT; |
|
|
/* Set MI_MODE */ |
/* Set MI_MODE */ |
mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); |
mimode = BGE_MIMODE_PHYADDR(sc->bge_phy_addr); |
if ((sc->bge_flags & BGEF_CPMU_PRESENT) != 0) |
if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) |
mimode |= BGE_MIMODE_500KHZ_CONST; |
mimode |= BGE_MIMODE_500KHZ_CONST; |
else |
else |
mimode |= BGE_MIMODE_BASE; |
mimode |= BGE_MIMODE_BASE; |
Line 3525 bge_attach(device_t parent, device_t sel |
|
Line 3488 bge_attach(device_t parent, device_t sel |
|
* payloads by copying the received packets. |
* payloads by copying the received packets. |
*/ |
*/ |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && |
sc->bge_flags & BGEF_PCIX) |
sc->bge_flags & BGE_PCIX) |
sc->bge_flags |= BGEF_RX_ALIGNBUG; |
sc->bge_flags |= BGE_RX_ALIGNBUG; |
|
|
if (BGE_IS_5700_FAMILY(sc)) |
if (BGE_IS_5700_FAMILY(sc)) |
sc->bge_flags |= BGEF_JUMBO_CAPABLE; |
sc->bge_flags |= BGE_JUMBO_CAPABLE; |
|
|
misccfg = CSR_READ_4(sc, BGE_MISC_CFG); |
misccfg = CSR_READ_4(sc, BGE_MISC_CFG); |
misccfg &= BGE_MISCCFG_BOARD_ID_MASK; |
misccfg &= BGE_MISCCFG_BOARD_ID_MASK; |
Line 3537 bge_attach(device_t parent, device_t sel |
|
Line 3500 bge_attach(device_t parent, device_t sel |
|
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && |
(misccfg == BGE_MISCCFG_BOARD_ID_5788 || |
(misccfg == BGE_MISCCFG_BOARD_ID_5788 || |
misccfg == BGE_MISCCFG_BOARD_ID_5788M)) |
misccfg == BGE_MISCCFG_BOARD_ID_5788M)) |
sc->bge_flags |= BGEF_IS_5788; |
sc->bge_flags |= BGE_IS_5788; |
|
|
/* |
/* |
* Some controllers seem to require a special firmware to use |
* Some controllers seem to require a special firmware to use |
Line 3558 bge_attach(device_t parent, device_t sel |
|
Line 3521 bge_attach(device_t parent, device_t sel |
|
*/ |
*/ |
if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && |
if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && |
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) |
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) |
sc->bge_flags |= BGEF_TSO; |
sc->bge_flags |= BGE_TSO; |
} |
} |
|
|
capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ |
capmask = 0xffffffff; /* XXX BMSR_DEFCAPMASK */ |
Line 3578 bge_attach(device_t parent, device_t sel |
|
Line 3541 bge_attach(device_t parent, device_t sel |
|
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || |
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { |
capmask &= ~BMSR_EXTSTAT; |
capmask &= ~BMSR_EXTSTAT; |
sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; |
sc->bge_flags |= BGE_PHY_NO_WIRESPEED; |
} |
} |
|
|
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || |
(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && |
(BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && |
(sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && |
(sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && |
sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) |
sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) |
sc->bge_phy_flags |= BGEPHYF_NO_WIRESPEED; |
sc->bge_flags |= BGE_PHY_NO_WIRESPEED; |
|
|
/* Set various PHY bug flags. */ |
/* Set various PHY bug flags. */ |
if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || |
if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || |
sc->bge_chipid == BGE_CHIPID_BCM5701_B0) |
sc->bge_chipid == BGE_CHIPID_BCM5701_B0) |
sc->bge_phy_flags |= BGEPHYF_CRC_BUG; |
sc->bge_flags |= BGE_PHY_CRC_BUG; |
if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || |
if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || |
BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) |
BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) |
sc->bge_phy_flags |= BGEPHYF_ADC_BUG; |
sc->bge_flags |= BGE_PHY_ADC_BUG; |
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) |
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) |
sc->bge_phy_flags |= BGEPHYF_5704_A0_BUG; |
sc->bge_flags |= BGE_PHY_5704_A0_BUG; |
if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || |
if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && |
PCI_VENDOR(subid) == PCI_VENDOR_DELL) |
PCI_VENDOR(subid) == PCI_VENDOR_DELL) |
sc->bge_phy_flags |= BGEPHYF_NO_3LED; |
sc->bge_flags |= BGE_PHY_NO_3LED; |
if (BGE_IS_5705_PLUS(sc) && |
if (BGE_IS_5705_PLUS(sc) && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && |
!BGE_IS_57765_PLUS(sc)) { |
!BGE_IS_5717_PLUS(sc)) { |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { |
if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && |
if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && |
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) |
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) |
sc->bge_phy_flags |= BGEPHYF_JITTER_BUG; |
sc->bge_flags |= BGE_PHY_JITTER_BUG; |
if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) |
if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) |
sc->bge_phy_flags |= BGEPHYF_ADJUST_TRIM; |
sc->bge_flags |= BGE_PHY_ADJUST_TRIM; |
} else |
} else |
sc->bge_phy_flags |= BGEPHYF_BER_BUG; |
sc->bge_flags |= BGE_PHY_BER_BUG; |
} |
} |
|
|
/* |
/* |
Line 3624 bge_attach(device_t parent, device_t sel |
|
Line 3587 bge_attach(device_t parent, device_t sel |
|
*/ |
*/ |
if (prop_dictionary_get_bool(device_properties(self), |
if (prop_dictionary_get_bool(device_properties(self), |
"without-seeprom", &no_seeprom) && no_seeprom) |
"without-seeprom", &no_seeprom) && no_seeprom) |
sc->bge_flags |= BGEF_NO_EEPROM; |
sc->bge_flags |= BGE_NO_EEPROM; |
|
|
else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) |
else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) |
sc->bge_flags |= BGEF_NO_EEPROM; |
sc->bge_flags |= BGE_NO_EEPROM; |
|
|
/* Now check the 'ROM failed' bit on the RX CPU */ |
/* Now check the 'ROM failed' bit on the RX CPU */ |
else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) |
else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) |
sc->bge_flags |= BGEF_NO_EEPROM; |
sc->bge_flags |= BGE_NO_EEPROM; |
|
|
sc->bge_asf_mode = 0; |
sc->bge_asf_mode = 0; |
/* No ASF if APE present. */ |
/* No ASF if APE present. */ |
if ((sc->bge_flags & BGEF_APE) == 0) { |
if ((sc->bge_flags & BGE_APE) == 0) { |
if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == |
if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == |
BGE_SRAM_DATA_SIG_MAGIC)) { |
BGE_SRAM_DATA_SIG_MAGIC)) { |
if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & |
if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & |
Line 3677 bge_attach(device_t parent, device_t sel |
|
Line 3640 bge_attach(device_t parent, device_t sel |
|
BGE_SRAM_DATA_VER_SHIFT; |
BGE_SRAM_DATA_VER_SHIFT; |
if ((0 < tmp) && (tmp < 0x100)) |
if ((0 < tmp) && (tmp < 0x100)) |
hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); |
hwcfg2 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_2); |
if (sc->bge_flags & BGEF_PCIE) |
if (sc->bge_flags & BGE_PCIE) |
hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); |
hwcfg3 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_3); |
if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) |
if (BGE_ASICREV(sc->bge_chipid == BGE_ASICREV_BCM5785)) |
hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); |
hwcfg4 = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG_4); |
} else if (!(sc->bge_flags & BGEF_NO_EEPROM)) { |
} else if (!(sc->bge_flags & BGE_NO_EEPROM)) { |
bge_read_eeprom(sc, (void *)&hwcfg, |
bge_read_eeprom(sc, (void *)&hwcfg, |
BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); |
BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); |
hwcfg = be32toh(hwcfg); |
hwcfg = be32toh(hwcfg); |
Line 3724 bge_attach(device_t parent, device_t sel |
|
Line 3687 bge_attach(device_t parent, device_t sel |
|
sc->bge_dmatag = pa->pa_dmat64; |
sc->bge_dmatag = pa->pa_dmat64; |
else |
else |
sc->bge_dmatag = pa->pa_dmat; |
sc->bge_dmatag = pa->pa_dmat; |
|
|
/* 40bit DMA workaround */ |
|
if (sizeof(bus_addr_t) > 4) { |
|
if ((sc->bge_flags & BGEF_40BIT_BUG) != 0) { |
|
bus_dma_tag_t olddmatag = sc->bge_dmatag; /* save */ |
|
|
|
if (bus_dmatag_subregion(olddmatag, 0, |
|
(bus_addr_t)(1ULL << 40), &(sc->bge_dmatag), |
|
BUS_DMA_NOWAIT) != 0) { |
|
aprint_error_dev(self, |
|
"WARNING: failed to restrict dma range," |
|
" falling back to parent bus dma range\n"); |
|
sc->bge_dmatag = olddmatag; |
|
} |
|
} |
|
} |
|
DPRINTFN(5, ("bus_dmamem_alloc\n")); |
DPRINTFN(5, ("bus_dmamem_alloc\n")); |
if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), |
if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), |
PAGE_SIZE, 0, &sc->bge_ring_seg, 1, |
PAGE_SIZE, 0, &sc->bge_ring_seg, 1, |
Line 3840 bge_attach(device_t parent, device_t sel |
|
Line 3787 bge_attach(device_t parent, device_t sel |
|
sc->ethercom.ec_capabilities |= |
sc->ethercom.ec_capabilities |= |
ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; |
ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; |
|
|
if (sc->bge_flags & BGEF_TSO) |
if (sc->bge_flags & BGE_TSO) |
sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; |
sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; |
|
|
/* |
/* |
Line 3862 bge_attach(device_t parent, device_t sel |
|
Line 3809 bge_attach(device_t parent, device_t sel |
|
if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || |
if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || |
(hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { |
(hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { |
if (BGE_IS_5714_FAMILY(sc)) |
if (BGE_IS_5714_FAMILY(sc)) |
sc->bge_flags |= BGEF_FIBER_MII; |
sc->bge_flags |= BGE_PHY_FIBER_MII; |
else |
else |
sc->bge_flags |= BGEF_FIBER_TBI; |
sc->bge_flags |= BGE_PHY_FIBER_TBI; |
} |
} |
|
|
/* Set bge_phy_flags before prop_dictionary_set_uint32() */ |
|
if (BGE_IS_JUMBO_CAPABLE(sc)) |
|
sc->bge_phy_flags |= BGEPHYF_JUMBO_CAPABLE; |
|
|
|
/* set phyflags and chipid before mii_attach() */ |
/* set phyflags and chipid before mii_attach() */ |
dict = device_properties(self); |
dict = device_properties(self); |
prop_dictionary_set_uint32(dict, "phyflags", sc->bge_phy_flags); |
prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); |
prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); |
prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); |
|
|
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, |
ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, |
bge_ifmedia_sts); |
bge_ifmedia_sts); |
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); |
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); |
Line 4043 bge_reset(struct bge_softc *sc) |
|
Line 3986 bge_reset(struct bge_softc *sc) |
|
|
|
if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && |
if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && |
(BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { |
(BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { |
if (sc->bge_flags & BGEF_PCIE) |
if (sc->bge_flags & BGE_PCIE) |
write_op = bge_writemem_direct; |
write_op = bge_writemem_direct; |
else |
else |
write_op = bge_writemem_ind; |
write_op = bge_writemem_ind; |
Line 4052 bge_reset(struct bge_softc *sc) |
|
Line 3995 bge_reset(struct bge_softc *sc) |
|
|
|
/* 57XX step 4 */ |
/* 57XX step 4 */ |
/* Acquire the NVM lock */ |
/* Acquire the NVM lock */ |
if ((sc->bge_flags & BGEF_NO_EEPROM) == 0 && |
if ((sc->bge_flags & BGE_NO_EEPROM) == 0 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { |
CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); |
CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); |
Line 4100 bge_reset(struct bge_softc *sc) |
|
Line 4043 bge_reset(struct bge_softc *sc) |
|
/* |
/* |
* XXX: from FreeBSD/Linux; no documentation |
* XXX: from FreeBSD/Linux; no documentation |
*/ |
*/ |
if (sc->bge_flags & BGEF_PCIE) { |
if (sc->bge_flags & BGE_PCIE) { |
if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && |
if (BGE_ASICREV(sc->bge_chipid != BGE_ASICREV_BCM5785) && |
!BGE_IS_57765_PLUS(sc) && |
!BGE_IS_57765_PLUS(sc) && |
(CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == |
(CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) == |
Line 4133 bge_reset(struct bge_softc *sc) |
|
Line 4076 bge_reset(struct bge_softc *sc) |
|
* powered up in D0 uninitialized. |
* powered up in D0 uninitialized. |
*/ |
*/ |
if (BGE_IS_5705_PLUS(sc) && |
if (BGE_IS_5705_PLUS(sc) && |
(sc->bge_flags & BGEF_CPMU_PRESENT) == 0) |
(sc->bge_flags & BGE_CPMU_PRESENT) == 0) |
reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; |
reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; |
|
|
/* Issue global reset */ |
/* Issue global reset */ |
write_op(sc, BGE_MISC_CFG, reset); |
write_op(sc, BGE_MISC_CFG, reset); |
|
|
/* 5718 reset step 7, 57XX step 8 */ |
/* 5718 reset step 7, 57XX step 8 */ |
if (sc->bge_flags & BGEF_PCIE) |
if (sc->bge_flags & BGE_PCIE) |
delay(100*1000); /* too big */ |
delay(100*1000); /* too big */ |
else |
else |
delay(1000); |
delay(1000); |
|
|
if (sc->bge_flags & BGEF_PCIE) { |
if (sc->bge_flags & BGE_PCIE) { |
if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { |
if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { |
DELAY(500000); |
DELAY(500000); |
/* XXX: Magic Numbers */ |
/* XXX: Magic Numbers */ |
Line 4162 bge_reset(struct bge_softc *sc) |
|
Line 4105 bge_reset(struct bge_softc *sc) |
|
PCIE_DCSR_ENA_NO_SNOOP); |
PCIE_DCSR_ENA_NO_SNOOP); |
|
|
/* Set PCIE max payload size to 128 for older PCIe devices */ |
/* Set PCIE max payload size to 128 for older PCIe devices */ |
if ((sc->bge_flags & BGEF_CPMU_PRESENT) == 0) |
if ((sc->bge_flags & BGE_CPMU_PRESENT) == 0) |
devctl &= ~(0x00e0); |
devctl &= ~(0x00e0); |
/* Clear device status register. Write 1b to clear */ |
/* Clear device status register. Write 1b to clear */ |
devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED |
devctl |= PCIE_DCSR_URD | PCIE_DCSR_FED |
Line 4185 bge_reset(struct bge_softc *sc) |
|
Line 4128 bge_reset(struct bge_softc *sc) |
|
BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); |
BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); |
val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; |
val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; |
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && |
if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && |
(sc->bge_flags & BGEF_PCIX) != 0) |
(sc->bge_flags & BGE_PCIX) != 0) |
val |= BGE_PCISTATE_RETRY_SAME_DMA; |
val |= BGE_PCISTATE_RETRY_SAME_DMA; |
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) |
if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) |
val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | |
val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | |
Line 4195 bge_reset(struct bge_softc *sc) |
|
Line 4138 bge_reset(struct bge_softc *sc) |
|
pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); |
pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); |
pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); |
pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); |
|
|
/* 57xx step 11: disable PCI-X Relaxed Ordering. */ |
/* Step 11: disable PCI-X Relaxed Ordering. */ |
if (sc->bge_flags & BGEF_PCIX) { |
if (sc->bge_flags & BGE_PCIX) { |
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap |
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap |
+ PCIX_CMD); |
+ PCIX_CMD); |
/* Set max memory read byte count to 2K */ |
|
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { |
|
reg &= ~PCIX_CMD_BYTECNT_MASK; |
|
reg |= PCIX_CMD_BCNT_2048; |
|
} else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704){ |
|
/* |
|
* For 5704, set max outstanding split transaction |
|
* field to 0 (0 means it supports 1 request) |
|
*/ |
|
reg &= ~(PCIX_CMD_SPLTRANS_MASK |
|
| PCIX_CMD_BYTECNT_MASK); |
|
reg |= PCIX_CMD_BCNT_2048; |
|
} |
|
pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap |
pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap |
+ PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); |
+ PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER); |
} |
} |
Line 4266 bge_reset(struct bge_softc *sc) |
|
Line 4196 bge_reset(struct bge_softc *sc) |
|
* adjustment to insure the SERDES drive level is set |
* adjustment to insure the SERDES drive level is set |
* to 1.2V. |
* to 1.2V. |
*/ |
*/ |
if (sc->bge_flags & BGEF_FIBER_TBI && |
if (sc->bge_flags & BGE_PHY_FIBER_TBI && |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { |
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { |
uint32_t serdescfg; |
uint32_t serdescfg; |
|
|
Line 4275 bge_reset(struct bge_softc *sc) |
|
Line 4205 bge_reset(struct bge_softc *sc) |
|
CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); |
CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); |
} |
} |
|
|
if (sc->bge_flags & BGEF_PCIE && |
if (sc->bge_flags & BGE_PCIE && |
!BGE_IS_57765_PLUS(sc) && |
!BGE_IS_57765_PLUS(sc) && |
sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && |
sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { |
BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { |
Line 4414 bge_rxeof(struct bge_softc *sc) |
|
Line 4344 bge_rxeof(struct bge_softc *sc) |
|
* the Rx buffer has the layer-2 header unaligned. |
* the Rx buffer has the layer-2 header unaligned. |
* If our CPU requires alignment, re-align by copying. |
* If our CPU requires alignment, re-align by copying. |
*/ |
*/ |
if (sc->bge_flags & BGEF_RX_ALIGNBUG) { |
if (sc->bge_flags & BGE_RX_ALIGNBUG) { |
memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, |
memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, |
cur_rx->bge_len); |
cur_rx->bge_len); |
m->m_data += ETHER_ALIGN; |
m->m_data += ETHER_ALIGN; |
|
|
bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) |
bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) |
{ |
{ |
|
|
if (BGE_IS_57765_PLUS(sc)) { |
if (BGE_IS_5717_PLUS(sc)) { |
if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { |
if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { |
if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) |
if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) != 0) |
m->m_pkthdr.csum_flags = M_CSUM_IPv4; |
m->m_pkthdr.csum_flags = M_CSUM_IPv4; |
Line 4617 bge_intr(void *xsc) |
|
Line 4547 bge_intr(void *xsc) |
|
if (sc->bge_pending_rxintr_change) { |
if (sc->bge_pending_rxintr_change) { |
uint32_t rx_ticks = sc->bge_rx_coal_ticks; |
uint32_t rx_ticks = sc->bge_rx_coal_ticks; |
uint32_t rx_bds = sc->bge_rx_max_coal_bds; |
uint32_t rx_bds = sc->bge_rx_max_coal_bds; |
|
uint32_t junk; |
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); |
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); |
DELAY(10); |
DELAY(10); |
(void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); |
junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); |
|
|
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); |
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); |
DELAY(10); |
DELAY(10); |
(void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); |
junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); |
|
|
sc->bge_pending_rxintr_change = 0; |
sc->bge_pending_rxintr_change = 0; |
} |
} |
Line 4679 bge_tick(void *xsc) |
|
Line 4610 bge_tick(void *xsc) |
|
else |
else |
bge_stats_update(sc); |
bge_stats_update(sc); |
|
|
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
/* |
/* |
* Since in TBI mode auto-polling can't be used we should poll |
* Since in TBI mode auto-polling can't be used we should poll |
* link status manually. Here we register pending link event |
* link status manually. Here we register pending link event |
Line 4820 static inline int |
|
Line 4751 static inline int |
|
bge_compact_dma_runt(struct mbuf *pkt) |
bge_compact_dma_runt(struct mbuf *pkt) |
{ |
{ |
struct mbuf *m, *prev; |
struct mbuf *m, *prev; |
int totlen; |
int totlen, prevlen; |
|
|
prev = NULL; |
prev = NULL; |
totlen = 0; |
totlen = 0; |
|
prevlen = -1; |
|
|
for (m = pkt; m != NULL; prev = m,m = m->m_next) { |
for (m = pkt; m != NULL; prev = m,m = m->m_next) { |
int mlen = m->m_len; |
int mlen = m->m_len; |
Line 4920 bge_compact_dma_runt(struct mbuf *pkt) |
|
Line 4852 bge_compact_dma_runt(struct mbuf *pkt) |
|
m = n; /* for continuing loop */ |
m = n; /* for continuing loop */ |
} |
} |
} |
} |
|
prevlen = m->m_len; |
} |
} |
return 0; |
return 0; |
} |
} |
Line 5301 bge_init(struct ifnet *ifp) |
|
Line 5234 bge_init(struct ifnet *ifp) |
|
{ |
{ |
struct bge_softc *sc = ifp->if_softc; |
struct bge_softc *sc = ifp->if_softc; |
const uint16_t *m; |
const uint16_t *m; |
uint32_t mode, reg; |
uint32_t mode; |
int s, error = 0; |
int s, error = 0; |
|
|
s = splnet(); |
s = splnet(); |
Line 5410 bge_init(struct ifnet *ifp) |
|
Line 5343 bge_init(struct ifnet *ifp) |
|
/* 5718 step 66 */ |
/* 5718 step 66 */ |
DELAY(10); |
DELAY(10); |
|
|
/* 5718 step 12, 57XX step 37 */ |
/* 5718 step 12 */ |
/* |
CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); |
* XXX Doucments of 5718 series and 577xx say the recommended value |
|
* is 1, but tg3 set 1 only on 57765 series. |
|
*/ |
|
if (BGE_IS_57765_PLUS(sc)) |
|
reg = 1; |
|
else |
|
reg = 2; |
|
CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg); |
|
|
|
/* Tell firmware we're alive. */ |
/* Tell firmware we're alive. */ |
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); |
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); |
Line 5456 bge_ifmedia_upd(struct ifnet *ifp) |
|
Line 5381 bge_ifmedia_upd(struct ifnet *ifp) |
|
int rc; |
int rc; |
|
|
/* If this is a 1000baseX NIC, enable the TBI port. */ |
/* If this is a 1000baseX NIC, enable the TBI port. */ |
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) |
if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) |
return EINVAL; |
return EINVAL; |
switch (IFM_SUBTYPE(ifm->ifm_media)) { |
switch (IFM_SUBTYPE(ifm->ifm_media)) { |
Line 5513 bge_ifmedia_upd(struct ifnet *ifp) |
|
Line 5438 bge_ifmedia_upd(struct ifnet *ifp) |
|
* things working was to receive a packet and get a RX intr. |
* things working was to receive a packet and get a RX intr. |
*/ |
*/ |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || |
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || |
sc->bge_flags & BGEF_IS_5788) |
sc->bge_flags & BGE_IS_5788) |
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); |
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); |
else |
else |
BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); |
BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); |
Line 5530 bge_ifmedia_sts(struct ifnet *ifp, struc |
|
Line 5455 bge_ifmedia_sts(struct ifnet *ifp, struc |
|
struct bge_softc *sc = ifp->if_softc; |
struct bge_softc *sc = ifp->if_softc; |
struct mii_data *mii = &sc->bge_mii; |
struct mii_data *mii = &sc->bge_mii; |
|
|
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
ifmr->ifm_status = IFM_AVALID; |
ifmr->ifm_status = IFM_AVALID; |
ifmr->ifm_active = IFM_ETHER; |
ifmr->ifm_active = IFM_ETHER; |
if (CSR_READ_4(sc, BGE_MAC_STS) & |
if (CSR_READ_4(sc, BGE_MAC_STS) & |
Line 5586 bge_ioctl(struct ifnet *ifp, u_long comm |
|
Line 5511 bge_ioctl(struct ifnet *ifp, u_long comm |
|
switch (command) { |
switch (command) { |
case SIOCSIFMEDIA: |
case SIOCSIFMEDIA: |
/* XXX Flow control is not supported for 1000BASE-SX */ |
/* XXX Flow control is not supported for 1000BASE-SX */ |
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
ifr->ifr_media &= ~IFM_ETH_FMASK; |
ifr->ifr_media &= ~IFM_ETH_FMASK; |
sc->bge_flowflags = 0; |
sc->bge_flowflags = 0; |
} |
} |
Line 5606 bge_ioctl(struct ifnet *ifp, u_long comm |
|
Line 5531 bge_ioctl(struct ifnet *ifp, u_long comm |
|
} |
} |
/* FALLTHROUGH */ |
/* FALLTHROUGH */ |
case SIOCGIFMEDIA: |
case SIOCGIFMEDIA: |
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, |
error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, |
command); |
command); |
} else { |
} else { |
Line 5765 bge_stop(struct ifnet *ifp, int disable) |
|
Line 5690 bge_stop(struct ifnet *ifp, int disable) |
|
/* |
/* |
* Isolate/power down the PHY. |
* Isolate/power down the PHY. |
*/ |
*/ |
if (!(sc->bge_flags & BGEF_FIBER_TBI)) |
if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) |
mii_down(&sc->bge_mii); |
mii_down(&sc->bge_mii); |
|
|
sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; |
sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; |
Line 5824 bge_link_upd(struct bge_softc *sc) |
|
Line 5749 bge_link_upd(struct bge_softc *sc) |
|
return; |
return; |
} |
} |
|
|
if (sc->bge_flags & BGEF_FIBER_TBI) { |
if (sc->bge_flags & BGE_PHY_FIBER_TBI) { |
status = CSR_READ_4(sc, BGE_MAC_STS); |
status = CSR_READ_4(sc, BGE_MAC_STS); |
if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { |
if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { |
if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { |
if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { |
Line 5842 bge_link_upd(struct bge_softc *sc) |
|
Line 5767 bge_link_upd(struct bge_softc *sc) |
|
BGE_STS_CLRBIT(sc, BGE_STS_LINK); |
BGE_STS_CLRBIT(sc, BGE_STS_LINK); |
if_link_state_change(ifp, LINK_STATE_DOWN); |
if_link_state_change(ifp, LINK_STATE_DOWN); |
} |
} |
|
/* |
|
* Discard link events for MII/GMII cards if MI auto-polling disabled. |
|
* This should not happen since mii callouts are locked now, but |
|
* we keep this check for debug. |
|
*/ |
} else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { |
} else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { |
/* |
/* |
* Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED |
* Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED |
Line 5863 bge_link_upd(struct bge_softc *sc) |
|
Line 5793 bge_link_upd(struct bge_softc *sc) |
|
IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) |
IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) |
BGE_STS_CLRBIT(sc, BGE_STS_LINK); |
BGE_STS_CLRBIT(sc, BGE_STS_LINK); |
} |
} |
} else { |
|
/* |
|
* For controllers that call mii_tick, we have to poll |
|
* link status. |
|
*/ |
|
mii_pollstat(mii); |
|
} |
} |
|
|
/* Clear the attention */ |
/* Clear the attention */ |
Line 5916 bge_sysctl_init(struct bge_softc *sc) |
|
Line 5840 bge_sysctl_init(struct bge_softc *sc) |
|
int rc, bge_root_num; |
int rc, bge_root_num; |
const struct sysctlnode *node; |
const struct sysctlnode *node; |
|
|
|
if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, |
|
CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, |
|
NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { |
|
goto out; |
|
} |
|
|
if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, |
if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, |
0, CTLTYPE_NODE, "bge", |
0, CTLTYPE_NODE, "bge", |
SYSCTL_DESCR("BGE interface controls"), |
SYSCTL_DESCR("BGE interface controls"), |
Line 5965 bge_debug_info(struct bge_softc *sc) |
|
Line 5895 bge_debug_info(struct bge_softc *sc) |
|
printf(" - 5714 Family\n"); |
printf(" - 5714 Family\n"); |
if (BGE_IS_5700_FAMILY(sc)) |
if (BGE_IS_5700_FAMILY(sc)) |
printf(" - 5700 Family\n"); |
printf(" - 5700 Family\n"); |
if (sc->bge_flags & BGEF_IS_5788) |
if (sc->bge_flags & BGE_IS_5788) |
printf(" - 5788\n"); |
printf(" - 5788\n"); |
if (sc->bge_flags & BGEF_JUMBO_CAPABLE) |
if (sc->bge_flags & BGE_JUMBO_CAPABLE) |
printf(" - Supports Jumbo Frames\n"); |
printf(" - Supports Jumbo Frames\n"); |
if (sc->bge_flags & BGEF_NO_EEPROM) |
if (sc->bge_flags & BGE_NO_EEPROM) |
printf(" - No EEPROM\n"); |
printf(" - No EEPROM\n"); |
if (sc->bge_flags & BGEF_PCIX) |
if (sc->bge_flags & BGE_PCIX) |
printf(" - PCI-X Bus\n"); |
printf(" - PCI-X Bus\n"); |
if (sc->bge_flags & BGEF_PCIE) |
if (sc->bge_flags & BGE_PCIE) |
printf(" - PCI Express Bus\n"); |
printf(" - PCI Express Bus\n"); |
if (sc->bge_flags & BGEF_RX_ALIGNBUG) |
if (sc->bge_flags & BGE_RX_ALIGNBUG) |
printf(" - RX Alignment Bug\n"); |
printf(" - RX Alignment Bug\n"); |
if (sc->bge_flags & BGEF_APE) |
if (sc->bge_flags & BGE_APE) |
printf(" - APE\n"); |
printf(" - APE\n"); |
if (sc->bge_flags & BGEF_CPMU_PRESENT) |
if (sc->bge_flags & BGE_CPMU_PRESENT) |
printf(" - CPMU\n"); |
printf(" - CPMU\n"); |
if (sc->bge_flags & BGEF_TSO) |
if (sc->bge_flags & BGE_TSO) |
printf(" - TSO\n"); |
printf(" - TSO\n"); |
|
|
if (sc->bge_phy_flags & BGEPHYF_NO_3LED) |
if (sc->bge_flags & BGE_PHY_NO_3LED) |
printf(" - No 3 LEDs\n"); |
printf(" - No 3 LEDs\n"); |
if (sc->bge_phy_flags & BGEPHYF_CRC_BUG) |
if (sc->bge_flags & BGE_PHY_CRC_BUG) |
printf(" - CRC bug\n"); |
printf(" - CRC bug\n"); |
if (sc->bge_phy_flags & BGEPHYF_ADC_BUG) |
if (sc->bge_flags & BGE_PHY_ADC_BUG) |
printf(" - ADC bug\n"); |
printf(" - ADC bug\n"); |
if (sc->bge_phy_flags & BGEPHYF_5704_A0_BUG) |
if (sc->bge_flags & BGE_PHY_5704_A0_BUG) |
printf(" - 5704 A0 bug\n"); |
printf(" - 5704 A0 bug\n"); |
if (sc->bge_phy_flags & BGEPHYF_JITTER_BUG) |
if (sc->bge_flags & BGE_PHY_JITTER_BUG) |
printf(" - jitter bug\n"); |
printf(" - jitter bug\n"); |
if (sc->bge_phy_flags & BGEPHYF_BER_BUG) |
if (sc->bge_flags & BGE_PHY_BER_BUG) |
printf(" - BER bug\n"); |
printf(" - BER bug\n"); |
if (sc->bge_phy_flags & BGEPHYF_ADJUST_TRIM) |
if (sc->bge_flags & BGE_PHY_ADJUST_TRIM) |
printf(" - adjust trim\n"); |
printf(" - adjust trim\n"); |
if (sc->bge_phy_flags & BGEPHYF_NO_WIRESPEED) |
if (sc->bge_flags & BGE_PHY_NO_WIRESPEED) |
printf(" - no wirespeed\n"); |
printf(" - no wirespeed\n"); |
} |
} |
#endif /* BGE_DEBUG */ |
#endif /* BGE_DEBUG */ |
Line 6009 bge_get_eaddr_fw(struct bge_softc *sc, u |
|
Line 5939 bge_get_eaddr_fw(struct bge_softc *sc, u |
|
prop_dictionary_t dict; |
prop_dictionary_t dict; |
prop_data_t ea; |
prop_data_t ea; |
|
|
if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) |
if ((sc->bge_flags & BGE_NO_EEPROM) == 0) |
return 1; |
return 1; |
|
|
dict = device_properties(sc->bge_dev); |
dict = device_properties(sc->bge_dev); |